Integrated circuit (IC) die including galvanically isolated capacitors

Abstract

The present specification generally relates to a capacitor (124) on an integrated circuit (IC) die. In an example, a package (100) includes a first IC die (102) and a second IC die (104). The first IC die (102) includes a first circuit (126), a capacitor (124), and a polyimide layer. The first circuit (126) is located on a substrate (120). The capacitor (124) includes a bottom plate (124a) positioned above the substrate (120) and a top plate (124b) positioned above the bottom plate (124a). The polyimide layer is located at least partially above the top plate (124b). The distance from the top surface of the top plate (124b) to the bottom surface of the polyimide layer is at least 30% of the distance from the top surface of the bottom plate (124a) to the bottom surface of the top plate (124b). Comprising the capacitor (124) is electrically coupled between the first circuit (126) and a second circuit (136) in the second IC die (104) that does not comprise a galvanically isolated capacitor in the signal path.

Description

Background Art

[0001] Galvanic isolation generally involves isolating functional parts of a circuit or system to prevent direct current (DC) current from flowing between these functional parts. Alternating current (AC) signals can still be exchanged between parts of a circuit or system by other means (such as capacitors, inductors, etc.). Galvanic isolation can be used when two or more circuits are configured to communicate with each other. However, it may be desirable to prevent DC current loops between two or more circuits, for example, when the circuits have ground nodes at different potentials. Galvanic isolation can be an effective method to disconnect ground loops by preventing unwanted DC currents from flowing between circuits. Summary of the invention

[0002] An example described herein is an integrated circuit (IC) package. The IC package includes a first IC die and a second IC die. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is disposed on a first semiconductor substrate. The capacitor includes a bottom plate and a top plate. The bottom plate is disposed above the first semiconductor substrate, and the top plate is disposed above the bottom plate. The first distance is from the top surface of the bottom plate to the bottom surface of the top plate. The polyimide layer is at least partially disposed above the top plate of the capacitor. The second distance is from the top surface of the top plate to the bottom surface of the polyimide layer. The second distance is equal to or greater than 30% of the first distance. The second IC die includes a second circuit, which is disposed on a second semiconductor substrate. A signal path is electrically coupled between the first circuit and the second circuit. The signal path includes the capacitor, and the second IC die does not include a current isolation capacitor in the signal path.

[0003] Another example described herein is a semiconductor processing method. A first capacitor plate is formed on a first interlayer dielectric (ILD). The first ILD is disposed over a semiconductor substrate. A second capacitor plate is formed on a second ILD. The second ILD is disposed over the first capacitor plate and the first ILD. A first distance is a distance from a top surface of the first capacitor plate to a bottom surface of the second capacitor plate. The first distance is equal to or greater than 15 μm. A polyimide layer is formed over the second capacitor plate and the second ILD. A second distance is from a top surface of the second capacitor plate to a bottom surface of the polyimide layer. The second distance is equal to or greater than 30% of the first distance.

[0004] Another example described herein is an IC die. The IC die includes a current isolation capacitor and a polyimide layer. The current isolation capacitor includes a bottom plate located above a semiconductor substrate and a top plate located above the bottom plate. A first distance is from a top surface of the bottom plate to a bottom surface of the top plate. The first distance is equal to or greater than 15 μm. The polyimide layer is located above the top plate of the current isolation capacitor. A second distance is from a top surface of the top plate to a bottom surface of the polyimide layer. The second distance is equal to or greater than 30% of the first distance.

[0005] The foregoing summary of the invention has generally outlined the various features of the examples of the specification described in detail below. Additional features and advantages of such examples will be described below. The described examples can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order that the manner in which the features set forth above may be described in detail, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

[0007] Figure 1 is a partial cross-sectional view of an integrated circuit (IC) package according to some examples.

[0008] Figure 2 Based on some examples Figure 1 A cross-sectional portion of an IC die within an IC package.

[0009] Figure 3 is a partial cross-sectional view of an IC die including a buffer dielectric layer according to some examples.

[0010] Figure 4 is a partial cross-sectional view of an IC die including a buffer dielectric layer according to some examples.

[0011] Figure 5 and 6 2 is a table showing the results of modeling and simulating an example embodiment compared to an application without a buffer dielectric layer.

[0012] Figures 7 to 17 According to some embodiments, semiconductor processing is performed to form Figure 1 Cross-sectional view of an IC die and IC packaging during the process.

[0013] The drawings and the accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples shown in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Wherever possible, the same reference numerals can be used to refer to the same elements that are common to the drawings. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0014] The various features are described below with reference to the accompanying drawings. An example may not have all the aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example, and may be practiced in any other example, even if not so described or not so explicitly described. Further, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with more or fewer operations in various other orders (e.g., including performing various operations sequentially or in parallel).

[0015] The present specification relates to a capacitor located on an integrated circuit (IC) die, and more specifically, to a current isolation capacitor located on an IC die. An IC die having a capacitor can be packaged in an IC package together with another IC die. The IC die having a capacitor includes an outer polyimide layer. In some instances, the distance between the capacitor plates of the capacitor is equal to or greater than 15 μm, and the distance from the top surface of the capacitor top plate to the bottom surface of the polyimide layer is equal to or greater than 30% (or more specifically, equal to or greater than 32% and / or 37%) of the distance between the capacitor plates of the capacitor. In some instances, the capacitor top plate is located in the uppermost metal level in the IC die. Further, the capacitor top plate can be a bonding pad for wire bonding.

[0016] In cases where current isolation capacitors are implemented in IC die, specifically high voltage (HV) applications, failure modes have been observed in which the system may fail due to relatively high electric fields. In some instances, having a distance from the top surface of the capacitor top plate to the bottom surface of the polyimide layer as previously mentioned can reduce the electric field peaks in the system. This can reduce the likelihood of failures and early life failures. Other variations that can reduce the likelihood of system failures, etc. are also described. Other advantages or benefits can be achieved using the various aspects described herein.

[0017] The specific examples described are then described in the context of IC packages using leadframes and wire bonding, such as quad flat packages (QFP), small outline packages (SOP), etc. It will be apparent to one of ordinary skill in the art that current isolation capacitors implemented consistent with the present specification may be implemented in other types of IC packages, such as ball grid array (BGA) packages, chip scale packages (CSP), etc.

[0018] Figure 1 1 is a partial cross-sectional view of an IC package 100 according to some examples. The IC package 100 includes a first IC die 102 and a second IC die 104. The first IC die 102 and the second IC die 104 are attached to a lead frame 106. The first IC die 102 and the second IC die 104 can be attached to the lead frame 106 by an adhesive. A molding compound 110 encapsulates the first IC die 102 and the second IC die 104 on the lead frame 106.

[0019] The first IC die 102 includes a semiconductor substrate 120 and a metallization structure 122 located above the semiconductor substrate 120. The semiconductor substrate 120 can be any semiconductor material, and can include bulk materials (e.g., bulk silicon) and one or more epitaxial semiconductor material layers. The metallization structure 122 can include multiple interlayer dielectrics (ILDs) and metal levels (METs). The metallization structure 122 of the first IC die 102 includes a capacitor 124, which can be a current isolation capacitor. The capacitor 124 includes a capacitor bottom plate 124a disposed in the MET and a capacitor top plate 124b disposed in another MET. The capacitor bottom plate 124a is electrically connected to a circuit 126 located in the first IC die 102. The circuit 126 is located on the semiconductor substrate 120. The circuit 126 can include one or more devices disposed in, above, and / or on the semiconductor substrate 120, and can include electrical connections, such as electrical connections made by metal contacts, metal lines, and / or metal vias in the metallization structure 122. The cross-sectional portion 128 of the first IC die 102 is Figure 1 is roughly identified in Figure 2 Described in detail.

[0020] Similarly, the second IC die 104 includes a semiconductor substrate 130 and a metallization structure 132 located above the semiconductor substrate 130. The semiconductor substrate 130 can be any semiconductor material, and can include bulk materials (e.g., bulk silicon) and one or more epitaxial semiconductor material layers. The metallization structure 132 can include multiple ILDs and METs. The metallization structure 132 includes a bonding pad 134 located in the uppermost MET. The second IC die 104 includes a circuit 136 located on the semiconductor substrate 130. The bonding pad 134 is electrically connected to the circuit 136. The circuit 136 may include one or more devices disposed in, above, and / or on the semiconductor substrate 130, and may include electrical connections, such as electrical connections made by metal contacts, metal lines, and / or metal vias in the metallization structure 132.

[0021] The capacitor top plate 124b of the first IC die 102 is bonded to the wire 140, and therefore, the capacitor top plate 124b can be further a bonding pad. The wire 140 is further bonded to the bonding pad 134 of the second IC die 104. Therefore, the capacitor 124 is electrically coupled between the circuit 126 in the first IC die 102 and the circuit 136 in the second IC die 104 (through the wire 140 and the bonding pad 134). The capacitor 124 can be a direct current (DC) current stopper between the circuit 126 in the first IC die 102 and the circuit 136 in the second IC die 104. Therefore, the capacitor 124 can provide a certain level of isolation between the circuit 126 in the first IC die 102 and the circuit 136 in the second IC die 104.

[0022] Typically, a signal path is disposed between the circuit 126 in the first IC die 102 and the circuit 136 in the second IC die 104. The signal path includes the capacitor 124, the wire 140, and the bonding pad 134. In some instances, the second IC die 104 does not include a capacitor in the signal path between the circuits 126, 136. The second IC die 104 does not include a current isolation capacitor between the circuits 126, 136. As shown and as in some instances, in the IC package 100, the first IC die 102 is the only IC die for providing current isolation capacitance (e.g., through the capacitor 124) between the circuit 126 in the first IC die 102 and the circuit 136 in the second IC die 104.

[0023] The first IC die 102 and the second IC die 104 may include other bonding pads (e.g., bonding pads 150, 152) to which wires (e.g., wires 154, 156) are bonded. Although not specifically shown, some of the wires may be further bonded to wires of the lead frame 106, which may provide external electrical connectors outside the IC package 100.

[0024] Figure 2 1 is a cross-sectional portion 128 of a first IC die 102 in an IC package 100 according to some examples. The first IC die 102 includes a semiconductor substrate 120 in, on, and / or over which one or more semiconductor devices (e.g., transistors 204) are formed. The semiconductor substrate 120 may be or include a bulk semiconductor substrate (e.g., a silicon substrate), a semiconductor on insulator (SOI) substrate, or the like, and may include one or more epitaxial semiconductor material layers. The first IC die 102 includes a pre-metal dielectric (PMD) located over the semiconductor substrate 120. The PMD includes a conformal dielectric layer 206 (e.g., an etch stop layer) located over (e.g., possibly over) the semiconductor substrate 120 and a dielectric layer 208 located over the conformal dielectric layer 206. In some examples, the conformal dielectric layer 206 is or includes silicon nitride, silicon oxynitride, or the like, or a combination thereof, and the dielectric layer 208 is or includes phosphosilicate glass (PSG), or the like, or a combination thereof.

[0025] The first IC die 102 further includes a first interlayer dielectric (ILD1), a second ILD (ILD2), a third ILD (ILD3), and a fourth ILD (ILD4). ILD1 is located above the PMD. ILD2 is located above ILD1, and ILD3 is located above ILD2. ILD4 is located above ILD3. ILD1 includes a first dielectric sublayer 210 located above the PMD and a second dielectric sublayer 212 located above the first dielectric sublayer 210. ILD2 includes a first dielectric sublayer 214 located above the second dielectric sublayer 212 and a second dielectric sublayer 216 located above the first dielectric sublayer 214. ILD3 includes a first dielectric sublayer 218 located above the second dielectric sublayer 216, a second dielectric sublayer 220 located above the first dielectric sublayer 218, and a third dielectric sublayer 222 located above the second dielectric sublayer 220. ILD4 includes a first dielectric sublayer 224 located above the third dielectric sublayer 222, a second dielectric sublayer 226 located above the first dielectric sublayer 224, a third dielectric sublayer 228 located above the second dielectric sublayer 226, a fourth dielectric sublayer 230 located above the third dielectric sublayer 228, and a fifth dielectric sublayer 232 located above the fourth dielectric sublayer 230. In some examples, each of the first dielectric sublayers 210, 214, 218, 224 is or includes high density plasma (HDP) silicon oxide (SiO x ), etc., and the second dielectric sublayers 212, 216, 220, 226 and the third dielectric sublayers 222, 228 are each or include tetraethyl orthosilicate (TEOS), etc. In some examples, the fourth dielectric sublayer 230 is or includes silicon oxynitride, etc., and the fifth dielectric sublayer 232 is or includes silicon nitride, etc.

[0026] The first IC bare die 102 includes a first metal level (MET1), a second metal level (MET2), a third metal level (MET3), a fourth metal level (MET4), and a fifth metal level (MET5). MET1 includes metal lines 240, 241. Metal lines 240, 241 are disposed above (e.g., possibly on) the dielectric layer 208 of the PMD, or in other examples, are disposed in the dielectric layer. The first dielectric sublayer 210 of ILD1 is disposed above the metal lines 240, 241 of MET1.

[0027] MET2 includes metal lines 242, 243 and a capacitor bottom plate 124a. The metal lines 242, 243 and the capacitor bottom plate 124a are disposed over the second dielectric sublayer 212 of ILD1, or in the second dielectric sublayer in other examples. The first dielectric sublayer 214 of ILD2 is disposed over the metal lines 242, 243 and the capacitor bottom plate 124a of MET2. In other examples, the capacitor bottom plate 124a can be located in another metal level.

[0028] MET3 includes metal lines 245, 246. Metal lines 245, 246 are disposed over the second dielectric sublayer 216 of ILD2, or in the second dielectric sublayer in other examples. The first dielectric sublayer 218 of ILD3 is disposed over the metal lines 245, 246 of MET3. MET4 includes metal lines 247, 248. Metal lines 247, 248 are disposed over the third dielectric sublayer 222 of ILD3, or in the third dielectric sublayer in other examples. The first dielectric sublayer 224 of ILD4 is disposed over the metal lines 247, 248 of MET4.

[0029] MET5 includes metal lines 249, 250 and capacitor top plate 124b. Metal lines 249, 250 and capacitor top plate 124b are disposed above the fifth dielectric sublayer 232 and / or another dielectric sublayer of ILD4, or in other examples, in the fifth dielectric sublayer and / or another dielectric sublayer. MET5 and therefore capacitor top plate 124b have a thickness 280, which in some examples may be in the range of 0.5 μm to 4.0 μm, and more specifically 1.5 μm to 3.0 μm. In the example shown, MET5 is the uppermost metal level away from semiconductor substrate 120, but in other examples, additional or fewer metal levels may be included, for example, above MET5. Capacitor top plate 124b is in a metal level located above capacitor bottom plate 124a. In other examples, capacitor top plate 124b may be located in another metal level. Capacitor bottom plate 124a and capacitor top plate 124b form a capacitor, such as a galvanic isolation capacitor.

[0030] A trench 251 is located in the ILD4. The trench 251 laterally circumscribes the capacitor top plate 124b. In the illustrated example, the trench 251 extends from the top surface of the ILD4 (e.g., the top surface of the fifth dielectric sub-layer 232), through the fifth dielectric sub-layer 232, and into the fourth dielectric sub-layer 230. As shown, the trench 251 extends to a depth that is approximately midway through the thickness of the fourth dielectric sub-layer 230. In other examples, the trench 251 may extend to other depths. In some examples, the lateral width of the trench 251 may be in the range of 5 μm to 50 μm.

[0031] The first IC die 102 includes metal contacts 252-254 and metal vias 255-267 that electrically connect various components or metal lines. The metal contacts 252, 253 extend through the PMD (e.g., conformal dielectric layer 206 and dielectric layer 208) and contact the semiconductor substrate 120 and the metal line 240. The metal contact 254 extends through the PMD (e.g., conformal dielectric layer 206 and dielectric layer 208) and contacts the gate electrode of the transistor 204 and the metal line 241. The metal vias 255, 256 extend through the ILD1 (e.g., dielectric sub-layers 210, 212) and contact the metal lines 240, 242. The metal via 257 extends through the ILD1 (e.g., dielectric sub-layers 210, 212) and contacts the metal lines 241, 243. Metal vias 258 extend through ILD2 (eg, dielectric sub-layers 214, 216) and contact metal lines 242, 245. Metal vias 259 extend through ILD2 (eg, dielectric sub-layers 214, 216) and contact metal lines 243, 246.

[0032] Metal via 260 extends through the first dielectric sub-layer 218 and the second dielectric sub-layer 220 of ILD3 and contacts metal line 245 and metal via 262. Metal via 261 extends through the first dielectric sub-layer 218 and the second dielectric sub-layer 220 of ILD3 and contacts metal line 246 and metal via 263. Metal via 262 extends through the third dielectric sub-layer 222 of ILD3 and contacts metal line 247 and metal via 260. Metal via 263 extends through the third dielectric sub-layer 222 of ILD3 and contacts metal line 248 and metal via 261. Metal via 264 extends through the first dielectric sub-layer 224 and the second dielectric sub-layer 226 of ILD4 and contacts metal line 247 and metal via 266. Metal via 265 extends through the first dielectric sub-layer 224 and the second dielectric sub-layer 226 of ILD4 and contacts metal line 248 and metal via 267. Metal via 266 extends through third dielectric sub-layer 228, fourth dielectric sub-layer 230, and fifth dielectric sub-layer 232 of ILD4 and contacts metal line 249 and metal via 264. Metal via 267 extends through third dielectric sub-layer 228, fourth dielectric sub-layer 230, and fifth dielectric sub-layer 232 of ILD4 and contacts metal line 250 and metal via 265.

[0033] Metal lines 240-243, 245-250, capacitor plates 124a, 124b, metal contacts 252-254, and metal vias 255-267 are each or include a metal. For example, each may be or include aluminum (Al), copper (Cu), tungsten (W), combinations thereof, etc. Further, each may include a barrier and / or adhesion layer, such as titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof.

[0034] Figure 2 The metal lines and metal vias shown in the figure are shown as examples and can be configured in any arrangement, including more or fewer metal lines and / or metal vias. Metal lines 241, 243, 246, 248, 250, metal vias 257, 259, 261, 263, 265, 267, and metal contact 254 illustrate an arrangement of metal lines and metal vias electrically connected, for example, between the gate electrode of transistor 204 and MET5. Metal lines 240, 242, 245, 247, 249, metal vias 255, 256, 258, 260, 262, 264, 266, and metal contacts 252, 253 can form a ground ring that laterally surrounds at least a portion of capacitor 124 formed by capacitor bottom plate 124a and capacitor top plate 124b. The ground ring can be connected to an electrical ground node and can be electrically connected to semiconductor substrate 120 and MET5.

[0035] The first IC die 102 includes an overlying dielectric disposed over the MET5 and the ILD4. The overlying dielectric includes a first dielectric sublayer 270 and a second dielectric sublayer 272. The first dielectric sublayer 270 is disposed over the MET5 (e.g., metal lines 249, 250 and capacitor top plate 124b) and the ILD4 (e.g., the fifth dielectric sublayer 232). The first dielectric sublayer 270 fills the trench 251 in the ILD4. The second dielectric sublayer 272 is at least partially disposed over the first dielectric sublayer 270. The respective top surfaces of the first dielectric sublayer 270 and the second dielectric sublayer 272 may be coplanar. The overlying dielectric has a thickness 281 from the top surface of the MET5 (e.g., the capacitor top plate 124b) to the top surface of the overlying dielectric. The thickness 281 may be in the range of 0.5 μm to 3.0 μm, and more specifically 1.1 μm to 1.7 μm. In some examples, the first dielectric sublayer 270 is or includes HDP SiO x etc., and the second dielectric sublayer 272 is or includes TEOS or the like.

[0036] The first IC die 102 includes one or more buffer dielectric layers 274, a passivation dielectric layer 276, and a polyimide layer 278. The buffer dielectric layer 274 is disposed over the overlying dielectric (e.g., the first dielectric sublayer 270 and / or the second dielectric sublayer 272). The buffer dielectric layer 274 is described in detail with respect to the subsequent figures. The buffer dielectric layer 274 has a thickness 282, which in some examples can be in the range of 3.0 μm to 5.0 μm, and more specifically 3.2 μm to 3.8 μm. The passivation dielectric layer 276 is disposed over the buffer dielectric layer 274. The passivation dielectric layer 276 has a thickness 283, which in some examples can be in the range of 0.5 μm to 3.0 μm, and more specifically 0.7 μm to 0.9 μm. In some examples, the passivation dielectric layer 276 is or includes a nitrogen-containing dielectric layer, such as silicon oxynitride, silicon nitride, etc. Polyimide layer 278 is disposed over passivation dielectric layer 276. Polyimide layer 278 has a thickness 284, which in some examples may be in a range of 5 μm to 30 μm, and more specifically 16 μm to 24 μm.

[0037] The openings extend through the polyimide layer 278, the passivation dielectric layer 276, the buffer dielectric layer 274, and the overlying dielectric layer (e.g., the first dielectric sublayer 270 and / or the second dielectric sublayer 272) to reach the capacitor top plate 124b. The wire 140 is bonded to the capacitor top plate 124b through the openings. The molding compound 110 encapsulates the first IC die 102 (and the second IC die 104) and the wire 140.

[0038] Distance 290 is from the top surface of capacitor bottom plate 124a to the bottom surface of capacitor top plate 124b. Distance 290 is generally normal to the top surface of capacitor bottom plate 124a and the bottom surface of capacitor top plate 124b, respectively. Distance 290 is also generally the thickness of the dielectric layer stack between capacitor bottom plate 124a and capacitor top plate 124b. In some instances, distance 290 is equal to or greater than 15 μm. In some cases, making distance 290 at least 15 μm can allow capacitor 124 to be implemented for HV applications, such as when providing current isolation capacitance between circuits on an IC die.

[0039] Distance 291 is from the top surface of capacitor top plate 124b to the bottom surface of polyimide layer 278. In some examples, distance 291 is generally normal to the top surface of capacitor top plate 124b and the bottom surface of polyimide layer 278, respectively. In some examples, distance 291 is equal to or greater than 30% of distance 290, and more specifically, equal to or greater than 32% of distance 290, and even further, equal to or greater than 37% of distance 290. In some examples, distance 291 is in the range of 30% to 38% of distance 290, and more specifically, in the range of 32% to 34% of distance 290. Additionally, distance 292 (e.g., parallel to distance 291) is from the bottom surface of capacitor top plate 124b to the bottom surface of polyimide layer 278.

[0040] Figure 3 A partial cross-sectional view of the first IC die 102 including the buffer dielectric layer 274 is shown according to some examples. In the example shown, the buffer dielectric layer 274 includes a first dielectric layer 302, a second dielectric layer 304, and a third dielectric layer 306. The first dielectric layer 302 is disposed over an overlying dielectric (e.g., the first dielectric sub-layer 270 and / or the second dielectric sub-layer 272). The second dielectric layer 304 is disposed over the first dielectric layer 302, and the third dielectric layer 306 is disposed over the second dielectric layer 304.

[0041] For illustration purposes, the thickness of the various layers are shown. The first dielectric sublayer 270 of the overlying dielectric has a thickness 310, and the second dielectric sublayer 272 of the overlying dielectric has a thickness 312. The first dielectric layer 302 of the buffer dielectric layer 274 has a thickness 322. The second dielectric layer 304 of the buffer dielectric layer 274 has a thickness 324. The third dielectric layer 306 of the buffer dielectric layer 274 has a thickness 326.

[0042] In some examples, the materials and thicknesses of the various layers are as shown in Table 1. These materials and thicknesses are merely examples, and other materials and / or thicknesses may be implemented in other examples.

[0043]

[0044]

[0045] Figure 4 A partial cross-sectional view of the first IC die 102 including the buffer dielectric layer 274 is shown according to some examples. In the example shown, the buffer dielectric layer 274 includes a first dielectric layer 402, a second dielectric layer 404, and a third dielectric layer 406. The first dielectric layer 402 is disposed over an overlying dielectric (e.g., the first dielectric sub-layer 270 and / or the second dielectric sub-layer 272). The second dielectric layer 404 is disposed over the first dielectric layer 402, and the third dielectric layer 406 is disposed over the second dielectric layer 404.

[0046] For illustration purposes, the thickness of the various layers are shown. The first dielectric layer 402 of the buffer dielectric layer 274 has a thickness 422. The second dielectric layer 404 of the buffer dielectric layer 274 has a thickness 424. The third dielectric layer 406 of the buffer dielectric layer 274 has a thickness 426.

[0047] In some examples, the materials and thicknesses of the various layers are as shown in Table 2. These materials and thicknesses are merely examples, and other materials and / or thicknesses may be implemented in other examples.

[0048]

[0049] In some applications of current isolation capacitors, particularly in HV applications, failure modes due to electric field peaks in the system have been observed. In such applications, in the absence of buffer dielectric layer 274, the electric field achieved in the system can be relatively high. This high electric field can cause system failures that can cause undesirable currents to flow through portions of the system to a ground node, such as on an IC die. Such failures can negatively impact the isolation capabilities of the IC die.

[0050] By incorporating one or more buffer dielectric layers 274 as previously described, the polyimide layer 278 can be at a greater distance from the capacitor top plate 124b, which can result in a reduction in the electric field. A reduction in the electric field can result in a lower likelihood of system failure.

[0051] When designing an IC die having such a current isolation capacitor with a target voltage rating, the distance 291 between the capacitor top plate 124b and the polyimide layer 278 can be determined relative to the distance 290 between the capacitor plates 124a, 124b. The distance 291 can be a certain percentage relative to the distance 290 such that the distance 291 is large enough to make the probability of failure of the dielectric layer between the capacitor plates 124a, 124b higher than the probability of failure of the polyimide layer 278. For example, in reference to Figure 1 , 2In the HV application described in Figures 4 and 2 and Table 2, distance 290 may be 20.5 μm, and distance 291 may be 6.9 μm, which is approximately 33.7% of distance 290. In some examples, distance 291 is equal to or greater than 30% of distance 290, equal to or greater than 32% of the distance, and / or equal to or greater than 37% of the distance. In some examples, distance 291 is in the range of 30% to 38% of distance 290.

[0052] Figure 5 and 6 The results are shown in Figure 2 compared to an application without a buffer dielectric layer. Figure 1 , 2 and 4 and Table 2 are tables of modeling and simulation results for the embodiments described in Table 2. Figure 1 , 2 In the embodiments of FIG. 4 and Table 2, the electric field quantities 511, 521, 531, 541, 651, 661 are obtained by simulation at positions L1, L2, L3, L4, L5, and L6. Positions L1, L2, L3, L4, L5, and L6 are shown in FIG. Figure 2 . Typically, positions L1, L2 are located at the interface between the passivation dielectric layer 276 and the polyimide layer 278, and are vertically aligned with the relative vertical sidewalls of the capacitor top plate 124b. Positions L3, L4 are located at the interface between the polyimide layer 278 and the molding compound 110, and are vertically aligned with the relative vertical sidewalls of the capacitor top plate 124b. Positions L5, L6 are located at the overlying dielectric (e.g., the first dielectric sublayer 270) at the relative vertical sidewalls of the capacitor top plate 124b. Similarly, in an embodiment having only a dielectric layer (thickness of 2 μm) composed of silicon oxynitride disposed between the overlying dielectric and the passivation dielectric layer, electric field quantities 512, 522, 532, 542, 652, 662 were obtained by simulating at similar corresponding positions L1, L2, L3, L4, L5, L6.

[0053] like Figure 5 and 6 As shown, according to Figure 1 , 2 4 and the embodiments of Table 2 achieve reduced electric field magnitudes 511, 521, 531, 541, 651, 661 relative to the electric field magnitudes 512, 522, 532, 542, 652, 662 at locations L1, L2, L3, L4, L5, L6. Thus, implementations of the buffer dielectric layer 274 as described herein can achieve lower electric fields at such locations. In general, increasing the thickness of the buffer dielectric layer 274 can reduce the peak electric fields at various locations in the first IC die 102 and the IC package 100.

[0054] In some examples, one or more dielectric layers of the buffer dielectric layer 274 can have a low dielectric constant (k) value, such as 3.9 or less. Adding a low-k value dielectric layer to the buffer dielectric layer 274 can change (e.g., reduce) the effective k value of the buffer dielectric layer 274. Dielectric layers with low k values ​​and / or buffer dielectric layers 274 with lower effective k values ​​can be less susceptible to failure. This can improve the isolation capability of the buffer dielectric layer 274, and thus can reduce the likelihood of system failure. Example dielectric materials with a K value of 3.9 or less include TEOS.

[0055] In some examples, the thickness 280 of the capacitor top plate 124b can be increased. Increasing the thickness 280 can increase the distance 292 between the bottom surface of the capacitor top plate 124b (e.g., the bottom corner of the capacitor top plate 124b) and the bottom surface of the polyimide layer 278. This can reduce the electric field at the interface between the polyimide layer 278 and the passivation dielectric layer 276, which can reduce system failures. Further, increasing the thickness 280 can reduce the system electric field, which can reduce early life failures.

[0056] Additionally, in some examples, the thickness 284 of the polyimide layer 278 can be increased. Increasing the thickness 284 can increase the distance between (a) the interface between (i) the polyimide layer 278 and (ii) the molding compound 110 and (b) the capacitor top plate 124b. This can reduce the electric field peaks at portions of the system. In some examples, the thickness 284 can be equal to or greater than 110% of the distance 290, and more specifically, equal to or greater than 113% of the distance 290.

[0057] Figures 7 to 17 Semiconductor processing is performed to form Figure 1 A cross-sectional view of a first IC die 102 and IC package 100 during the method. Figure 7, front-end-of-line (FEOL) processing (e.g., to form transistor 204) is performed on semiconductor substrate 120 until MET1 is formed. FEOL may include forming semiconductor devices (e.g., transistor 204) in, on, and / or over semiconductor substrate 120. Then, a PMD is formed over semiconductor substrate 120. A conformal dielectric layer 206 of the PMD is deposited over the semiconductor substrate, such as by using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc. A dielectric layer 208 of the PMD is deposited over conformal dielectric layer 206, such as by using PECVD, spin-on, etc. Metal contacts 252-254 may then be formed through the PMD, such as by using a process similar to that described subsequently with respect to the formation of metal vias. A MET1 including metal lines 240, 241 is formed over the PMD, such as by using a process similar to that described subsequently with respect to the formation of other metal levels.

[0058] Then, ILD1 is formed over PMD and MET1. Forming ILD1 includes depositing a first dielectric sublayer 210 over PMD (e.g., dielectric layer 208) and MET1 (e.g., metal lines 240, 241), and depositing a second dielectric sublayer 212 over the first dielectric sublayer 210. The first dielectric sublayer 210 may be deposited by HDP-CVD, etc., and the second dielectric sublayer 212 may be deposited by PECVD, etc. The top surface of the second dielectric sublayer 212 of ILD1 may be planarized, such as by chemical mechanical polishing (CMP).

[0059] refer to Figure 8 , openings 801, 802, 803 are formed through ILD1 (e.g., second dielectric sublayer 212 and first dielectric sublayer 210). Openings 801-803 may be formed using a photolithography process and an etching process such as reactive ion etching (RIE). Openings 801, 802 expose metal line 240, and opening 803 exposes metal line 241.

[0060] refer to Fig. 9, metal vias 255, 256, 257 are formed through ILD1 in openings 801, 802, 803, respectively, and metal lines 242, 243 and capacitor bottom plate 124a are formed over ILD1. Adhesion and / or barrier layers may be conformally deposited on the surfaces of openings 801-803 and the top surface of ILD1 (e.g., second dielectric sublayer 212), such as by CVD, ALD, etc., and metal may be deposited on the adhesion and / or barrier layers, such as by CVD, physical vapor deposition (PVD), etc. Excess metal located above the top surface of ILD1 may be removed, such as by CMP, etc., to form metal vias 255-257. Then, metal is deposited on the top surface of ILD1, such as by CVD, PVD, etc. The metal may be patterned using a photolithography process and an etching process to have a pattern that forms metal lines 242, 243 and capacitor bottom plate 124a. In various examples, adhesion and / or barrier layers may be included in metal lines 242, 243 and capacitor bottom plate 124a, and / or may be omitted in metal vias 255-257 and / or metal lines 242, 243 and capacitor bottom plate 124a. In other examples, metal lines and / or metal vias may be formed using other processes, such as a dual damascene process.

[0061] refer to Fig.10 , forming ILD2 (including the first dielectric sub-layer 214 and the second dielectric sub-layer 216) and MET3 (including metal lines 245, 246) and metal vias 258, 259 located thereunder. Figure 7 MET3 and metal vias 258, 259 are formed as described in the above with respect to the formation of ILD1. Figure 8 and 9 The metal vias 255 - 257 are formed as described in relation to the formation of MET2 and metal vias 255 - 257 .

[0062] refer to Fig.11 , forming ILD3 (including the first dielectric sub-layer 218, the second dielectric sub-layer 220 and the third dielectric sub-layer 222) and MET4 (including metal lines 247, 248) and metal vias 260-263 located thereunder. The first dielectric sub-layer 218 and the second dielectric sub-layer 220 of ILD3 are as shown in FIG. Figure 7 Then, as described in the foregoing for the formation of ILD1. Figure 8Openings (not shown) are formed through first dielectric sub-layer 218 and second dielectric sub-layer 220 corresponding to where metal vias 260, 261 are to be formed as described above with respect to the formation of openings 801-803. An adhesion and / or barrier layer may be conformally deposited on the surfaces of the openings (not shown) and on the top surface of second dielectric sub-layer 220 of ILD3, such as by PVD, CVD, ALD, etc., and metal may be deposited on the adhesion and / or barrier layer, such as by CVD, PVD, etc. Excess metal and the adhesion and / or barrier layer located above the top surface of second dielectric sub-layer 220 are removed, such as by CMP, etc. As before, the adhesion and / or barrier layer may be omitted.

[0063] Then, a third dielectric sublayer 222 is formed over the second dielectric sublayer 220 and the metal vias 260, 261. The third dielectric sublayer 222 may be deposited by PECVD or the like. The top surface of the third dielectric sublayer 222 of the ILD3 may be planarized, such as by CMP or the like. Figure 8 and 9 The metal vias 255 - 257 are formed as described in relation to the formation of MET2 and metal vias 255 - 257 .

[0064] refer to Fig.12 , forming ILD4 (including dielectric sub-layers 224, 226, 228, 230, 232) and MET5 (including metal lines 249, 250 and capacitor top plate 124b) and metal vias 264-267 located thereunder. The first dielectric sub-layer 224 and the second dielectric sub-layer 226 of ILD4 are as shown in FIG. Figure 7 Then, as described in the foregoing for the formation of ILD1. Figure 8 Openings (not shown) are formed through first dielectric sub-layer 224 and second dielectric sub-layer 226 corresponding to where metal vias 264, 265 are to be formed as described above with respect to the formation of openings 801-803. An adhesion and / or barrier layer may be conformally deposited on the surfaces of the openings (not shown) and on the top surface of second dielectric sub-layer 226 of ILD4, such as by PVD, CVD, ALD, etc., and metal may be deposited on the adhesion and / or barrier layer, such as by CVD, PVD, etc. Excess metal and the adhesion and / or barrier layer located above the top surface of second dielectric sub-layer 226 are removed, such as by CMP, etc. As before, the adhesion and / or barrier layer may be omitted.

[0065] Then, a third dielectric sublayer 228, a fourth dielectric sublayer 230, and a fifth dielectric sublayer 232 are formed over the second dielectric sublayer 226 and the metal vias 264, 265. The third dielectric sublayer 228, the fourth dielectric sublayer 230, and the fifth dielectric sublayer 232 are sequentially deposited. The third dielectric sublayer 228, the fourth dielectric sublayer 230, and the fifth dielectric sublayer 232 can each be deposited by PECVD or the like. Figure 8 and 9 The trench 251 is then formed in ILD4 (eg, extending through the fifth dielectric sub-layer 232 and into the fourth dielectric sub-layer 230 ), such as by photolithography and etching processes.

[0066] refer to Fig.13 , an overlying dielectric (including a first dielectric sublayer 270 and a second dielectric sublayer 272) is formed over MET5 and ILD4. Forming the overlying dielectric includes depositing the first dielectric sublayer 270 over ILD4 (e.g., the fifth dielectric sublayer 232) and MET5 (e.g., metal lines 249, 250 and capacitor top plate 124b), and depositing the second dielectric sublayer 272 over the first dielectric sublayer 270. The first dielectric sublayer 270 fills the trench 251. The first dielectric sublayer 270 can be deposited by HDP-CVD, etc., and the second dielectric sublayer 272 can be deposited by CVD, PECVD, etc. The top surface of the second dielectric sublayer 272 of the overlying dielectric can be planarized, such as by CMP, etc. In some examples, due to planarization (e.g., removing the second dielectric sublayer 272 from directly over the capacitor top plate 124b), the top surface of the first dielectric sublayer 270 is exposed over the capacitor top plate 124b. In some examples, a portion of second dielectric sublayer 272 can remain directly above capacitor top plate 124b after planarization.

[0067] refer to Fig.14 , forming one or more buffer dielectric layers 274 over the overlying dielectric layer, and forming a passivation dielectric layer 276 over the buffer dielectric layer 274. In some examples, the buffer dielectric layer 274 includes Figure 3 The first dielectric layer 302, the second dielectric layer 304 and the third dielectric layer 306 are shown. In some examples, the buffer dielectric layer 274 includes Figure 44. A first dielectric layer 402, a second dielectric layer 404, and a third dielectric layer 406 are shown. In these examples, the first dielectric layer 302, 402 is deposited over an overlying dielectric (e.g., the first dielectric sublayer 270 and / or the second dielectric sublayer 272); the second dielectric layer 304, 404 is deposited over the first dielectric layer 302, 402; and the third dielectric layer 306, 406 is deposited over the second dielectric layer 304, 404. The dielectric layers 302-306, 402-406 can be deposited by PECVD or the like. In other examples, different dielectric layers and / or different numbers of dielectric layers can be implemented as the buffer dielectric layer 274. The passivation dielectric layer 276 is deposited over the buffer dielectric layer 274 (e.g., the third dielectric layer 306, 406), such as by PECVD or the like.

[0068] refer to Fig.15 An opening 1501 is formed through the passivation dielectric layer 276, the buffer dielectric layer 274, and the overlying dielectric (eg, the first dielectric sublayer 270 and / or the second dielectric sublayer 272) to the capacitor top plate 124b. The opening 1501 may be formed using a photolithography process and an etching process.

[0069] refer to Fig.16 , a polyimide layer 278 is formed over the passivation dielectric layer 276. In some examples, the polyimide layer 278 can be a photosensitive material deposited by spin coating or the like, and is patterned using photolithography to have an opening 1601. In some examples, such as when the polyimide layer 278 is a thick layer, a multi-pass process can be implemented. For example, a first sublayer composed of polyimide can be deposited, exposed, and developed by spin coating, and then a second sublayer composed of polyimide can be deposited, exposed, and developed by spin coating. The opening 1601 through the polyimide layer 278 corresponds to the opening 1501, and in the case of the opening 1501, the opening 1601 exposes the capacitor top plate 124b.

[0070] refer to Fig.17, the first IC die 102 is separated from other IC die that may be formed on the same semiconductor substrate 120 (e.g., a wafer). The separation may be performed by using sawing or cutting. The separated first IC die 102 is attached to the lead frame 106 using an adhesive. Similarly, the second IC die 104 is attached to the lead frame 106 using an adhesive. A wire bonding process is performed, the process including wire bonding the wire 140 to the capacitor top plate 124b through the openings 1501, 1601. The wire 140 has another end that is wire bonded to the bonding pad 134 of the second IC die 104. Other wires may be wire bonded to the leads on the lead frame 106 from the first IC die 102 and / or the second IC die 104. Subsequently, the first IC die 102 and the second IC die 104 attached to the lead frame 106 are encapsulated by the molding compound 110, as Figure 2 shown.

[0071] Although various examples have been described in detail, various changes, substitutions and alterations can be made herein without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit (IC) package, comprising: A first IC die, the first IC die comprising: a first circuit disposed on a first semiconductor substrate; A capacitor, the capacitor comprising: A base plate disposed above the first semiconductor substrate ； as well as a top plate disposed above the bottom plate, the first distance being from a top surface of the bottom plate to a bottom surface of the top plate; as well as a polyimide layer disposed at least partially over the top plate of the capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance; as well as A second IC die includes a second circuit disposed on a second semiconductor substrate, a signal path electrically coupled between the first circuit and the second circuit, the signal path including the capacitor, the second IC die not including a galvanic isolation capacitor in the signal path. 2 . The IC package of claim 1 , wherein the first distance is equal to or greater than 15 μm.

3. The IC package of claim 1 , wherein the first IC die further comprises: an overlying dielectric disposed at least partially above the top plate of the capacitor, the top plate of the capacitor disposed in an uppermost metal level distal from the first semiconductor substrate; one or more buffer dielectric layers disposed over the overlying dielectric layer; as well as A passivation dielectric layer is disposed over the one or more buffer dielectric layers, and the polyimide layer is disposed over the passivation dielectric layer. 4 . The IC package according to claim 3 , wherein a dielectric constant value of a buffer dielectric layer in the one or more buffer dielectric layers is 3.9 or less.

5. The IC package of claim 3, wherein the one or more buffer dielectric layers comprise: a first dielectric layer disposed over the overlying dielectric; a second dielectric layer disposed over the first dielectric layer; and A third dielectric layer is disposed over the second dielectric layer, and the passivation dielectric layer is disposed over the third dielectric layer.

6. The IC package according to claim 5, in: The first dielectric layer is a first layer composed of tetraethyl orthosilicate (TEOS); The second dielectric layer is a second layer composed of TEOS; and The third dielectric layer is a layer made of silicon oxynitride.

7. The IC package according to claim 5, in: The first dielectric layer is a first layer composed of tetraethyl orthosilicate (TEOS); The second dielectric layer is a second layer composed of TEOS; and The third dielectric layer is a third layer made of TEOS.

8. The IC package of claim 1, further comprising wires bonded to the first IC die and the second IC die, the wires passing through the polyimide layer and bonded to the top plate of the capacitor, the signal path including the wires.

9. A method of semiconductor processing, the method comprising: forming a first capacitor plate on a first interlayer dielectric (ILD), the first ILD disposed over a semiconductor substrate; forming a second capacitor plate on a second ILD, the second ILD being disposed over the first capacitor plate and the first ILD, a first distance being from a top surface of the first capacitor plate to a bottom surface of the second capacitor plate, the first distance being equal to or greater than 15 μm; and A polyimide layer is formed over the second capacitor plate and the second ILD, a second distance is from a top surface of the second capacitor plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance.

10. The method according to claim 9, further comprising: forming an overlying dielectric over the second ILD and at least partially over the second capacitor plate, the second capacitor plate disposed in an uppermost metal level remote from the semiconductor substrate; forming one or more buffer dielectric layers over the overlying dielectric layer; as well as A passivation dielectric layer is formed over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.

11. The method of claim 10, wherein forming the one or more buffer dielectric layers comprises: forming a first dielectric layer over the overlying dielectric layer; forming a second dielectric layer over the first dielectric layer; and A third dielectric layer is formed over the second dielectric layer, and the passivation dielectric layer is disposed over the third dielectric layer. 12 . The method of claim 9 , wherein the second distance is equal to or greater than 32% of the first distance.

13. The method of claim 9, wherein the second distance is in a range of 30% to 38% of the first distance.

14. The method of claim 9, further comprising bonding a wire to the second capacitor plate through an opening through the polyimide layer.

15. An integrated circuit (IC) bare die, comprising: A current isolation capacitor, the current isolation capacitor comprising: A base plate located above the semiconductor substrate ； as well as A top plate, the top plate is located above the bottom plate, a first distance is from a top surface of the bottom plate to a bottom surface of the top plate, and the first distance is equal to or greater than 15 μm; as well as A polyimide layer is located above the top plate of the current isolation capacitor, and a second distance is from the top surface of the top plate to the bottom surface of the polyimide layer, and the second distance is equal to or greater than 30% of the first distance.

16. The IC die of claim 15, further comprising: a first interlayer dielectric (ILD), the first ILD being disposed above the semiconductor substrate, the base plate being disposed on the first ILD; a second ILD, the second ILD being disposed above the bottom plate and the first ILD, the top plate being disposed on the second ILD, the top plate being disposed in an uppermost metal level; an overlying dielectric disposed over the second ILD and at least partially over the top plate; one or more buffer dielectric layers disposed over the overlying dielectric layer; as well as A passivation dielectric layer is disposed over the one or more buffer dielectric layers, and the polyimide layer is disposed over the passivation dielectric layer.

17. The IC die of claim 15, wherein the second distance is equal to or greater than 32% of the first distance.

18. The IC die of claim 15, wherein the second distance is equal to or greater than 37% of the first distance.

19. The IC die of claim 15, wherein the second distance is in the range of 30% to 38% of the first distance.

20. The IC die of claim 15, wherein a thickness of the polyimide layer is equal to or greater than 110% of the first distance.

Images