Chemical mechanical polishing method

Abstract

A chemical mechanical polishing method comprises the steps that a semiconductor device is provided, the semiconductor device comprises a substrate, a dielectric layer with a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; performing a first polishing process on the semiconductor device on the first polishing pad to remove a part of thickness of the metal layer; performing a second polishing process on the semiconductor device on the second polishing pad to remove the metal layer and the barrier layer above the trench; wherein in the second grinding process, before the semiconductor device is ground through the second grinding pad, a step of carrying out first finishing on the second grinding pad is included, and when the semiconductor device is ground through the second grinding pad, a step of carrying out second finishing on the second grinding pad is included. According to the method, the defects of reduction of the grinding rate and scratching caused by accumulation and agglomeration of grinding byproducts in the grinding process can be effectively reduced, the grinding rate is more stable, and the thickness between wafers is controlled through the more stable grinding rate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chemical mechanical polishing method. Background Art

[0002] In the integrated circuit manufacturing process, copper metal deposition usually requires a chemical mechanical polishing process for planarization. During the process of polishing and planarizing the metal copper, the polishing time is generally long. The copper surface temperature will rise rapidly due to the polishing time, causing the copper metal layer to soften, seriously affecting subsequent processes and the final performance and yield of the product.

[0003] In the related technology, copper chemical mechanical polishing usually adopts in-situ condition (In-situ condition, which refers to the dressing of the polishing pad during the grinding process). Although it can achieve real-time repair of the polishing pad, it cannot effectively cover the entire grinding process during the main grinding process. In the later stage of grinding, grinding by-products are prone to accumulate and agglomerate on the polishing pad, resulting in scratch defects. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, the present application provides a chemical mechanical polishing method, which comprises: A semiconductor device is provided, the semiconductor device comprising a substrate, a dielectric layer having a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; Performing a first grinding process on the semiconductor device on a first grinding pad to remove a portion of the thickness of the metal layer; performing a second polishing process on the semiconductor device on a second polishing pad to remove the metal layer and the barrier layer above the trench; Among them, in the second grinding process, before grinding the semiconductor device with the second grinding pad, it includes the step of performing a first trimming step on the second grinding pad, and when grinding the semiconductor device with the second grinding pad, it includes the step of performing a second trimming step on the second grinding pad.

[0006] In some embodiments of the present application, the second grinding process includes a plurality of sub-processes, and in each of the sub-processes, the semiconductor device is ground by a second grinding pad; wherein, Before each second polishing pad polishes the semiconductor device, the step of performing a first trimming step on the second polishing pad is included; When each second polishing pad polishes the semiconductor device, the method includes performing a second dressing step on the second polishing pad.

[0007] In some embodiments of the present application, the plurality of sub-processes include a first sub-process and a second sub-process. In the first sub-process, the metal layer above the barrier layer is removed; In the second sub-process, the barrier layer on the dielectric layer is removed.

[0008] In some embodiments of the present application, the step of removing a portion of the dielectric layer outside the groove by grinding with a third grinding pad is also included; Before the third grinding pad is used for grinding, the third grinding pad is first trimmed.

[0009] In some embodiments of the present application, the first dressing is performed on the second polishing pad for a first preset time.

[0010] In some embodiments of the present application, the second dressing includes real-time dressing of the polishing pad during polishing.

[0011] In some embodiments of the present application, in the first grinding process, the first grinding pad is trimmed for a second preset time.

[0012] In some embodiments of the present application, when the portion of the dielectric layer outside the groove is removed by grinding with the third grinding pad, a grinding critical endpoint is determined based on eddy currents.

[0013] In some embodiments of the present application, before the first grinding process is performed on the semiconductor device, the thickness of the metal layer is 4500-5000 nm; After the first grinding process is performed on the semiconductor device, the thickness of the metal layer is 3800nm-4000nm; After the second grinding process is performed on the semiconductor device, the thickness of the metal layer is 3000nm-3500nm.

[0014] In some embodiments of the present application, the metal layer includes copper.

[0015] According to the chemical mechanical polishing method of the embodiment of the present application, by performing a first trimming on the second polishing pad before polishing the semiconductor device with the second polishing pad in the second polishing process, and performing a second trimming on the second polishing pad when polishing the semiconductor device with the second polishing pad, the reduction in polishing rate and scratch defects caused by the accumulation and agglomeration of polishing by-products during the polishing process can be effectively reduced, and by combining the first trimming and the second trimming, the entire second polishing process can be evenly covered in real time, so that the polishing rate is more stable, and the thickness control between wafers can be achieved through a more stable polishing rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0017] Figure 1 The figure shows a schematic structural diagram of a chemical mechanical polishing machine in the related art.

[0018] Figure 2 A flow chart of a chemical mechanical polishing method according to a specific embodiment of the present invention is shown.

[0019] FIG. 3A to FIG. 3C A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown.

[0020] Figure 4A A polishing defect image of a chemical mechanical polishing method in the related art is shown.

[0021] Figure 4B A polishing defect image of a chemical mechanical polishing method according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0023] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0024] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part.

[0025] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0026] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0027] The chemical mechanical polishing machine of the related art can be as follows Figure 1As shown, the machine comprises a grinding table 101, a grinding pad 102 and a grinding head 103. The grinding table 101 carries the grinding pad 102. When grinding, the wafer to be ground is first adsorbed on the grinding head 103, so that the surface to be ground of the wafer is opposite to the rotating grinding pad 102. At this time, a grinding liquid composed of abrasive grains and chemical additives can be provided on the grinding pad 102 through a grinding liquid nozzle 104; then, the grinding head 103 provides a controllable load such as pressure to the wafer, and the surface to be ground of the wafer is pressed tightly against the grinding pad 102. With the relative movement between the wafer and the grinding pad, and the spraying of the grinding liquid on the grinding pad, the wafer is ground to form a flat surface of the wafer.

[0028] In the related art, copper chemical mechanical polishing usually adopts in-situ condition (In-situ condition, which means that the polishing pad is trimmed by the trimming disc 105 during the polishing process). Although it can achieve real-time polishing pad repair, it cannot effectively cover the entire polishing process during the main polishing process. In the later stage of polishing, the polishing pad is prone to accumulation and agglomeration of polishing byproducts, resulting in scratch defects (polishing defect images such as Figure 4A ), and cannot meet the requirements of thickness fluctuation and defect control between wafers.

[0029] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a chemical mechanical polishing method, such as Figure 2 As shown, the chemical mechanical polishing method includes: Step S1, providing a semiconductor device, wherein the semiconductor device comprises a substrate, a dielectric layer having a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; Step S2, performing a first grinding process on the semiconductor device on a first grinding pad to remove a portion of the thickness of the metal layer; Step S3, performing a second polishing process on the semiconductor device on a second polishing pad to remove the metal layer and the barrier layer above the trench; Among them, in the second grinding process, before grinding the semiconductor device with the second grinding pad, it includes the step of performing a first trimming step on the second grinding pad, and when grinding the semiconductor device with the second grinding pad, it includes the step of performing a second trimming step on the second grinding pad.

[0030] The chemical mechanical polishing method of the present application can effectively reduce the reduction in polishing rate and scratch defects caused by the accumulation and agglomeration of polishing by-products during the polishing process by performing a first trimming on the second polishing pad before polishing the semiconductor device with the second polishing pad in the second polishing process, and performing a second trimming on the second polishing pad when polishing the semiconductor device with the second polishing pad. Moreover, by combining the first trimming and the second trimming, the entire second polishing process can be evenly covered in real time, making the polishing rate more stable, and achieving thickness control between wafers through a more stable polishing rate.

[0031] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0032] Below, reference FIG. 3A to FIG. 3C The chemical mechanical polishing method of the present invention is described in detail, wherein: FIG. 3A to FIG. 3C A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a chemical mechanical polishing method according to a specific embodiment of the present invention is shown.

[0033] Exemplarily, the chemical mechanical polishing method of the present invention comprises the following steps: First, perform step 1, such as Figure 3A As shown, a semiconductor device is provided. The semiconductor device includes a substrate. A dielectric layer 301 having a groove is formed on the substrate. A barrier layer 302 and a metal layer 303 are sequentially formed on the dielectric layer 301 .

[0034] The method for forming a semiconductor device may be as follows: first, a substrate is provided, and then a dielectric layer 301 is deposited on the substrate. Then, a photoresist layer is coated on the dielectric layer 301, and the photoresist layer is exposed and developed. The opening of the patterned photoresist layer is used to define the position of the groove; the patterned photoresist layer is used as a mask to etch the dielectric layer 301 to form a groove. Then, a barrier layer 302 and a metal layer 303 are deposited in sequence to form a semiconductor device. Figure 3A The semiconductor device shown.

[0035] In some examples, the substrate layer can be any suitable semiconductor substrate, such as a bulk silicon substrate, which can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0036] In some embodiments, the deposited metal layer 303 may be a copper metal layer, an aluminum metal layer, or a metal layer made of any other suitable metal material, which is not limited.

[0037] In some embodiments, the thickness of the deposited metal layer 303 may be 4500-5000 nm.

[0038] Next, execute step 2, such as Figure 3B As shown, a first grinding process is performed on the semiconductor device on the first grinding pad to remove a portion of the thickness of the metal layer 303 .

[0039] Among them, in the first grinding process, the ground surface of the semiconductor device is in contact with the first grinding pad to achieve chemical mechanical grinding, and the grinding of the semiconductor device by the first grinding pad is called the main grinding. In the main grinding process, the metal layer 303 can be ground at a relatively high grinding rate to remove most of the thickness of the metal layer 303 above the barrier layer 302. The execution of the first process, for example, can adopt the optical interferometry endpoint detection technology, and determine the grinding thickness by using the interference formed by the reflection of the first surface and the second surface. After the first process is completed, the metal layer 303 above the barrier layer 302 is required to have a certain thickness value.

[0040] In some embodiments, in the first grinding process, a fixed grinding time can be set to remove most of the thickness of the metal layer 303. Exemplarily, in the first grinding process, the first grinding pad can be trimmed with a second preset time, wherein the second preset time can be set according to actual conditions and is not limited thereto.

[0041] In the first grinding process, the number of the first grinding pads is not limited and can be set according to actual conditions. For example, three first grinding pads can be set, and in the first grinding process, the three first grinding pads are trimmed respectively.

[0042] In some embodiments, after the first grinding process is performed on the semiconductor device, the thickness of the metal layer 303 is 3800 nm-4000 nm.

[0043] Next, execute step 3, such as Figure 3C As shown, a second polishing process is performed on the semiconductor device on the second polishing pad to remove the metal layer 303 and the barrier layer 302 above the trench.

[0044] In the second polishing step, the polished surface of the semiconductor device contacts the second polishing pad to achieve chemical mechanical polishing. The polishing of the semiconductor device by the second polishing pad can also be called main polishing.

[0045] In the present embodiment, by making the chemical mechanical polishing method include a first polishing process and a second polishing process, two-step independent polishing of the semiconductor device is achieved. Compared with the one-step polishing method in the related art, the polishing time of the semiconductor device is reduced, thereby avoiding the softening problem of the metal layer 303 caused by long-term polishing, reducing the number of defects on the surface of the semiconductor device after polishing and improving the flatness of the semiconductor device after polishing.

[0046] In some embodiments, the second polishing process includes a first trimming step of the second polishing pad before polishing the semiconductor device with the second polishing pad, and includes a second trimming step of the second polishing pad when polishing the semiconductor device with the second polishing pad.

[0047] Among them, in the second grinding process, before grinding the semiconductor device with the second grinding pad, the first trimming of the second grinding pad can also be called post-grinding trimming (Ex-situ condition), and its purpose is to remove impurities before grinding the semiconductor device with the second grinding pad to increase the grinding rate. When grinding the semiconductor device with the second grinding pad, the second trimming of the second grinding pad can also be called in-situ condition, and its purpose is to remove the grinding by-products generated in the grinding process to prevent the grinding by-products from agglomerating. In this embodiment, by arranging post-grinding trimming and in-situ trimming in the second grinding process, the reduction in grinding rate and scratch defects caused by the accumulation and agglomeration of grinding by-products during the grinding process can be effectively reduced (grinding defect image as shown in FIG. 1 ). Figure 4B As shown, it can be seen that compared with Figure 4A The chemical mechanical polishing method of the present application can significantly improve the polishing defects), and by combining post-grinding dressing and in-grinding dressing, it can evenly cover the entire second polishing process in real time, making the polishing rate more stable, and achieving thickness control between wafers through a more stable polishing rate.

[0048] In some embodiments, the first dressing and the second dressing may be performed on the second polishing pad by a dressing disc.

[0049] In some embodiments, the second grinding process may include multiple sub-processes, in each of which the semiconductor device is ground by a second grinding pad; wherein, before each second grinding pad grinds the semiconductor device, a first trimming step of the second grinding pad is included; and when each second grinding pad grinds the semiconductor device, a second trimming step of the second grinding pad is included.

[0050] In this embodiment, the second grinding process is divided into multiple sub-processes, and in each sub-process, there is a corresponding second grinding pad and a dressing disc. The dressing disc in each sub-process can perform post-grinding dressing and in-grinding dressing on the second grinding pad in the sub-process, and the workload of the dressing disc can be well balanced, thereby stabilizing the grinding rate while reducing scratch defects caused by the accumulation of grinding by-products.

[0051] In some embodiments, the plurality of sub-processes may include a first sub-process for removing the metal layer 303 above the barrier layer 302 and a second sub-process for removing the barrier layer 302 above the dielectric layer 301 .

[0052] Specifically, in the first sub-process, the semiconductor device can be ground by a second grinding pad to remove the metal layer 303 on the barrier layer 302; in the second sub-process, the semiconductor device can be ground by another second grinding pad to remove the barrier layer 302 above the dielectric layer 301 (including removing the metal layer 303 located in the barrier layer 302). In both the first sub-process and the second sub-process, post-grinding trimming and in-grinding trimming are provided, which can effectively reduce the reduction in grinding rate and scratch defects caused by the accumulation and agglomeration of grinding byproducts during the grinding process, and meet the thickness fluctuation and defect control between wafers.

[0053] In some embodiments, after the second grinding process is performed on the semiconductor device, the thickness of the metal layer 303 is 3000 nm-3500 nm.

[0054] In some embodiments, the step of removing a portion of the dielectric layer 301 outside the groove by grinding with a third grinding pad is also included; wherein, before grinding with the third grinding pad, the third grinding pad is first trimmed.

[0055] Specifically, after the dielectric layer 301 outside the groove is removed by grinding with the third grinding pad (and the metal layer 303 in the groove is removed at the same time), the surface of the metal layer 303 in the groove may have a concave structure. Figure 3C shown.

[0056] When the third polishing pad is used to polish and remove the portion of the dielectric layer outside the groove, the polishing critical end point can be determined based on the eddy current, and when the polishing critical end point is detected, the removal of the dielectric layer 301 outside the groove is stopped. The principle of the polishing critical end point detection method is: in the process of polishing and removing the portion of the dielectric layer 301 outside the groove by the third polishing pad, eddy current data is collected in real time by an eddy current sensor, and when the eddy current data meets the set conditions, it is determined that the polishing critical end point has been reached, thereby stopping the polishing operation.

[0057] In some embodiments, the first trimming of the second polishing pad is performed for a first preset time, wherein the first preset time can be set according to actual conditions, such as 9s, 10s, 11s, etc., and is not limited thereto.

[0058] In some embodiments, the second conditioning includes conditioning the polishing pad in real time during polishing to remove polishing by-products generated during the polishing process in real time to prevent the polishing by-products from agglomerating.

[0059] In summary, according to the chemical mechanical polishing method of the embodiment of the present application, by performing a first trimming on the second polishing pad before polishing the semiconductor device with the second polishing pad in the second polishing process, and performing a second trimming on the second polishing pad when polishing the semiconductor device with the second polishing pad, the reduction in polishing rate and scratch defects caused by the accumulation and agglomeration of polishing by-products during the polishing process can be effectively reduced, and by combining the first trimming and the second trimming, the entire second polishing process can be evenly covered in real time, so that the polishing rate is more stable, and the thickness control between wafers is achieved through a more stable polishing rate.

[0060] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0061] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various application aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the application point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0062] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0063] It should be noted that the above embodiments illustrate rather than limit the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be construed as a limitation to the claims. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A chemical mechanical polishing method, characterized in that: The chemical mechanical polishing method comprises: A semiconductor device is provided, the semiconductor device comprising a substrate, a dielectric layer having a groove is formed on the substrate, and a barrier layer and a metal layer are sequentially formed on the dielectric layer; Performing a first grinding process on the semiconductor device on a first grinding pad to remove a portion of the thickness of the metal layer; performing a second polishing process on the semiconductor device on a second polishing pad to remove the metal layer and the barrier layer above the trench; Among them, in the second grinding process, before grinding the semiconductor device with the second grinding pad, it includes the step of performing a first trimming step on the second grinding pad, and when grinding the semiconductor device with the second grinding pad, it includes the step of performing a second trimming step on the second grinding pad.

2. The chemical mechanical polishing method according to claim 1, wherein: The second grinding process includes a plurality of sub-processes, and in each of the sub-processes, the semiconductor device is ground by a second grinding pad; wherein, Before each second polishing pad polishes the semiconductor device, the step of performing a first trimming step on the second polishing pad is included; When each second polishing pad polishes the semiconductor device, the method includes performing a second dressing step on the second polishing pad.

3. The chemical mechanical polishing method according to claim 2, wherein: The plurality of sub-processes include a first sub-process and a second sub-process, In the first sub-process, the metal layer above the barrier layer is removed; In the second sub-process, the barrier layer on the dielectric layer is removed.

4. The chemical mechanical polishing method according to claim 1, wherein: The step also includes the step of removing a portion of the dielectric layer outside the groove by grinding with a third grinding pad; Before the third grinding pad is used for grinding, the third grinding pad is first trimmed.

5. The chemical mechanical polishing method according to any one of claims 1 to 3, characterized in that: The first dressing is performed on the second polishing pad for a first preset time.

6. The chemical mechanical polishing method according to any one of claims 1 to 4, characterized in that: The second dressing includes real-time dressing of the polishing pad during polishing.

7. The chemical mechanical polishing method according to claim 1, wherein: In the first grinding process, the first grinding pad is dressed for a second preset time.

8. The chemical mechanical polishing method according to claim 4, wherein: When the portion of the dielectric layer outside the groove is removed by grinding with the third grinding pad, a grinding critical end point is determined based on the eddy current.

9. The chemical mechanical polishing method according to claim 1, wherein: Before the first grinding process is performed on the semiconductor device, the thickness of the metal layer is 4500-5000 nm; After the first grinding process is performed on the semiconductor device, the thickness of the metal layer is 3800nm-4000nm; After the second grinding process is performed on the semiconductor device, the thickness of the metal layer is 3000nm-3500nm.

10. The chemical mechanical polishing method according to claim 1, wherein: The metal layer includes copper.

Images