SOC synchronization control method, device, equipment and storage medium

Abstract

The present application discloses a SOC synchronous control method, device, equipment and storage medium. The state of charge can be quickly determined by using the echo control current. Then, on the basis of the state of charge, the output adjustment parameters of each output channel module can be confirmed by further using the echo control voltage, the charge internal resistance correspondence table, and the charge voltage correspondence table. Then, the first enable line and the second enable line can be used to complete the synchronous trigger control of the output adjustment of each output channel module, thereby improving the synchronization of the cascaded operation of multiple output channel modules. In addition, the present application cleverly uses the full-duplex working mode of the Ethernet switch device to reduce the waiting time required for data transmission and improve communication efficiency. Moreover, the communication efficiency of the Ethernet switch device itself is higher than that of communication methods such as CAN, thereby realizing communication synchronization control in scenarios with a large number of battery simulators in parallel.

Description

Technical Field

[0001] The present application relates to the field of battery simulators, and in particular to a SOC synchronization control method, device, equipment and storage medium. Background Art

[0002] After multiple battery simulators in a multi-channel battery simulator are connected in parallel or series, it is necessary to perform soc (State of Charge) control operations to obtain the output voltage and output current of multiple output channels connected to each battery simulator to complete the synchronous control of multiple output channels. However, in the existing synchronous control process, due to the inconsistency of the time when each channel receives the set parameters and the time when the output is adjusted according to the set parameters, it often leads to large output synchronization errors, which in turn causes output abnormalities and makes it impossible to complete the test in conjunction with external equipment. Summary of the invention

[0003] The present application aims to propose a SOC synchronous control method, device, equipment and storage medium, which improves the synchronization during the cascade control of multiple battery simulators.

[0004] According to the SOC synchronization control method of the first aspect of the present application, it is used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; the multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; the multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0005] The SOC synchronization control method, applied to the control module of the first simulator, comprises:

[0006] Acquire an echo control current, wherein, when a plurality of the battery simulators are connected in series, the echo control current is the echo current of one of the output channel modules of any of the battery simulators, and when a plurality of the battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the plurality of battery simulators;

[0007] Acquire an echo control voltage, where the echo control voltage is an echo voltage of an external device to which a plurality of the battery simulators are connected after being cascaded;

[0008] Determining the state of charge according to the echo control current;

[0009] Determine the output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of internal resistance information, and the charge voltage correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of voltage information;

[0010] Transmitting the output adjustment parameter to each of the output channel modules;

[0011] The first enable line and each of the second enable lines are controlled to output a first trigger level, so that each of the output channel modules performs an output operation according to the received output adjustment parameter.

[0012] According to the second aspect of the present application, the SOC synchronization control device is used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; the multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; the multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of the multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators;

[0013] The SOC synchronization control device, applied to the control module of the first simulator, comprises:

[0014] A current acquisition module, used to acquire an echo control current, wherein, when a plurality of the battery simulators are connected in series, the echo control current is the echo current of one of the output channel modules of any of the battery simulators, and when a plurality of the battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the plurality of battery simulators;

[0015] A voltage acquisition module, used for acquiring an echo control voltage, wherein the echo control voltage is an echo voltage of an external device connected to a plurality of the battery simulators after cascading;

[0016] A state of charge acquisition module, used to determine the state of charge according to the echo control current;

[0017] an adjustment parameter determination module, configured to determine an output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates a correspondence between a plurality of the states of charge and a plurality of internal resistance information, and the charge voltage correspondence table indicates a correspondence between a plurality of the states of charge and a plurality of voltage information;

[0018] A data transmission module, used for transmitting the output adjustment parameter to each of the output channel modules;

[0019] The synchronous output control module is used to control the first enable line and each of the second enable lines to output a first trigger level, so that each of the output channel modules performs an output operation according to the received output adjustment parameter.

[0020] According to an electronic device of a third aspect of the present application, the device includes: a processor and a memory storing computer program instructions;

[0021] When the processor executes computer program instructions, it implements the SOC synchronization control method as described in the first aspect.

[0022] According to the computer-readable storage medium of the fourth aspect embodiment of the present application, computer executable instructions are stored, and the computer executable instructions are used to execute the SOC synchronization control method as described in the first aspect embodiment above.

[0023] The SOC synchronous control method, device, equipment and storage medium of the present application can quickly determine the state of charge by using the echo control current, and then on the basis of obtaining the state of charge, the echo control voltage, the charge internal resistance correspondence table, and the charge voltage correspondence table can be further used to complete the confirmation of the output adjustment parameters of each output channel module, and then the first enable line and the second enable line can be used to complete the synchronous trigger control of the output adjustment of each output channel module, thereby improving the synchronization of the cascaded operation of multiple output channel modules. In addition, the present application cleverly uses the full-duplex working mode of the Ethernet switch device to reduce the waiting time required for data transmission and improve communication efficiency. Moreover, the communication efficiency of the Ethernet switch device itself is higher than that of communication methods such as CAN, thereby realizing communication synchronization control in scenarios with a large number of battery simulators in parallel.

[0024] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0026] Figure 1 A schematic diagram of the structure of a multi-channel battery simulator platform provided in one embodiment of the present application;

[0027] Figure 2 A flowchart of a soc synchronization control method provided by an embodiment of the present application;

[0028] Figure 3 A schematic diagram of the structure of a soc synchronization control device provided in one embodiment of the present application.

[0029] Reference numerals:

[0030] Control module 110 , FPGA module 120 , and output channel module 130 . DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0033] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0034] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0035] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments.

[0036] In order to better describe the SOC synchronization control method, device, equipment and storage medium of the embodiment of the present invention, a multi-channel battery simulator platform is proposed here, such as Figure 1 As shown, the multi-channel battery simulator platform includes multiple battery simulators, each of which includes a control module 110, an FPGA (Field Programmable Gate Array) module 120, and multiple output channel modules 130. The control module 110 is connected to the FPGA module 120 for communication, and a serial communication line, a first enable line, and a first clock line are connected between the FPGA module 120 and each output channel module 130; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules 120 of two adjacent battery simulators; multiple FPGA modules 120 output synchronized clock signals to the corresponding output channel modules 130 through the first clock line and the second clock line; the control modules 110 of multiple battery simulators are connected through an Ethernet switch device;

[0037] The control module 110 and the FPGA module 120 are connected via a fsmc (Flexible Static Memory Controller) bus.

[0038] The control modules 110 of the above-mentioned multiple battery simulators are connected through an Ethernet switch device, which can realize full-duplex communication between multiple battery simulators. Specifically, in the embodiment of the present application, full-duplex communication is mainly realized between the first simulator and multiple second simulators, and because of the particularity of the Ethernet switch device, there will be no data conflicts leading to packet loss, thereby greatly reducing the delay waiting time due to fear of data transmission conflicts.

[0039] The above-mentioned multiple battery simulators are set in sequence, and the battery simulator in the first position is set as the first simulator, which can be understood as a host device, and the remaining battery simulators are set as the second simulator, which can be understood as slave devices.

[0040] After being started, the FPGA module 120 in the first simulator can continue to send clock signals through the first clock line and the second clock line. When the FPGA module 120 in each second simulator detects the clock signal sent by the second clock line, it will also output a clock signal synchronized with the clock signal output by the FPGA module 120 in the first simulator to the next second simulator through the second clock line, until the FPGA modules 120 in all battery simulators can output synchronized clock signals.

[0041] The above serial communication line can realize data transmission between the FPGA module 120 and the output channel.

[0042] The output channel module 130 has a built-in controller, which is used to implement data interaction with the FPGA module 120 and to implement control of the output of the output channel module 130 .

[0043] Based on the above power supply system, the power supply parallel synchronous output control method, device and storage medium according to the embodiment of the present invention are described below.

[0044] See also Figure 2 As shown, Figure 2 1 is a flow chart of a SOC synchronization control method provided by an embodiment of the present application. The SOC synchronization control method is applied to the control module 110 of the first simulator. The SOC synchronization control method includes:

[0045] Obtaining an echo control current, wherein, when multiple battery simulators are connected in series, the echo control current is the echo current of an output channel module 130 of any battery simulator, and when multiple battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the multiple battery simulators;

[0046] Acquire an echo control voltage, where the echo control voltage is an echo voltage of an external device to which multiple battery simulators are connected after cascading;

[0047] Determine the state of charge based on the echo control current;

[0048] Determine the output adjustment parameter according to the state of charge, the echo control voltage, a pre-built charge internal resistance correspondence table, and a pre-built charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates the correspondence between multiple charge states and multiple internal resistance information, and the charge voltage correspondence table indicates the correspondence between multiple charge states and multiple voltage information;

[0049] Transmitting output adjustment parameters to each output channel module 130;

[0050] The first enable line and each second enable line are controlled to output a first trigger level, so that each output channel module 130 performs an output operation according to the received output adjustment parameter.

[0051] In the embodiment of the present application, the state of charge can be quickly determined by using the echo control current, and then, on the basis of the obtained state of charge, the output adjustment parameters of each output channel module 130 can be confirmed by further using the echo control voltage, the charge internal resistance correspondence table, and the charge voltage correspondence table, and then the first enable line and the second enable line can be used to complete the synchronous trigger control of the output adjustment of each output channel module 130, thereby improving the synchronization of the cascaded operation of multiple output channel modules 130. In addition, the present application cleverly utilizes the full-duplex working mode of the Ethernet switch device, greatly reducing the waiting time required for data transmission, which can effectively improve the communication efficiency, and the communication efficiency of the Ethernet switch device itself is higher than that of communication methods such as CAN, so that the communication synchronization control in the scenario with a large number of battery simulators in parallel can be realized.

[0052] The echo current of each output channel module 130 of each battery simulator may be collected periodically.

[0053] When the multiple output channel modules 130 of the above-mentioned multiple battery simulators are connected in series, the current in the loop is equal everywhere, and the echo control current can be directly obtained by using the echo current of any output channel module 130 in the first simulator. Compared with using the data in the second simulator, directly using the echo current of any output channel module 130 in the first simulator, the data acquisition process is simpler and the data transmission time can be reduced.

[0054] When the multiple output channel modules 130 of the above-mentioned multiple battery simulators are connected in parallel, the current in the loop is obtained by superposition of the multiple output channel modules 130, that is, the echo control current can be directly obtained by accumulating and calculating the echo currents of the multiple output channel modules 130.

[0055] The above-mentioned echo control voltage is determined by an external device. After the multiple output channel modules 130 of the multiple battery simulators are cascaded, a unified output port will be retained. The output port will be connected to the external device to detect the external device. At this time, the output voltage of the battery simulator depends on the state of the external device. Therefore, the echo control voltage can be obtained by obtaining the output voltage of the external device, or by directly detecting the voltage at the electrical connection between the cascaded multiple battery simulators and the external device to obtain the echo control voltage.

[0056] The charge-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information, that is, after a charge state is determined, the corresponding voltage information can be obtained by looking up the table.

[0057] Specifically, the charged internal resistance correspondence table displays the relationship between the charged state and the corresponding voltage information with a certain proportional value, as shown in Table 1. The data in Table 1 can be expanded according to actual needs, and the specific number of rows is not limited.

[0058] Table 1

[0059]

[0060] Soc1 in Table 1 can be understood as the state of charge amplified by 100 times, and the corresponding voltage ratio in Table 1 can be understood as voltage information, that is, the ratio value required for the subsequent calculation of the set voltage using the open circuit voltage. For example, if the state of charge is 0.6080318193, the calculated Soc1 is 60.80318193, and the corresponding voltage ratio is 0.972853458. Assuming the open circuit voltage is 10 volts, the set voltage calculated using the voltage ratio is 9.72853458 volts.

[0061] The above open circuit voltage can be obtained by the user through the human-computer interaction interface.

[0062] The above-mentioned charge-internal resistance correspondence table can indicate the correspondence between multiple charge states and multiple internal resistance information, that is, after determining a charge state, the corresponding internal resistance information can be obtained by looking up the table.

[0063] Specifically, the charge-to-internal resistance correspondence table can display the relationship between the charge state and the corresponding internal resistance information with a certain proportional value, as shown in Table 2. The data in Table 2 can be expanded according to actual needs, and the specific number of rows is not limited.

[0064] Table 2

[0065]

[0066] Soc2 in Table 2 can be understood as the state of charge magnified 100 times, and the corresponding internal resistance ratio in Table 2 can be understood as the internal resistance information, that is, the ratio required for the subsequent calculation of the current internal resistance using the maximum internal resistance. For example, if the state of charge is 0.6080318193, the calculated Soc2 is 60.80318193. If the value cannot be found at this time, the closest Soc2 is selected for confirmation, that is, Soc2 is confirmed as 60.58506543, and the corresponding voltage ratio is 0.671063479. Assuming that the maximum internal resistance is 1 ohm, the current internal resistance calculated using the internal resistance ratio is 0.671063479 ohm.

[0067] The above maximum internal resistance can be input by the user through the human-computer interaction interface.

[0068] After the above-mentioned state of charge, echo control current, and echo control voltage are obtained, the output voltage and output current that each output channel needs to bear after the cascade can be quickly confirmed according to the type of cascade, and then the output adjustment parameters can be obtained.

[0069] The above-mentioned transmission of the output adjustment parameter to each output channel module 130 may be performed by the control module 110 of the first simulator transmitting the output adjustment parameter to the FPGA module 120 of the first simulator and the control module 110 of each second simulator, and then the output adjustment parameter received by each FPGA module 120 is transmitted to the multiple connected output channel modules 130;

[0070] The above-mentioned control of the first enable line and each second enable line outputting the first trigger level is executed after each output channel module 130 receives the output adjustment parameter. At this time, the first trigger level can be used as a synchronization trigger signal. Each output channel module 130 will perform an output operation according to the output adjustment parameter only when the first trigger level is detected, thereby avoiding the situation where the output channel adjustment module that receives the output adjustment parameter first performs output adjustment first.

[0071] In some embodiments, determining the state of charge according to the echo control current includes:

[0072] The echo control current is integrated using a preset sampling period to obtain the state of charge;

[0073] The sampling period is the time period for acquiring the echo current and the echo voltage, and the echo current and the echo voltage are acquired synchronously.

[0074] The above-mentioned echo current and echo voltage are obtained by periodic sampling, and are sampled synchronously to improve the accuracy of the output adjustment parameters determined subsequently.

[0075] After sampling, the echo current and the echo voltage are transmitted to the first simulator for storage. A special data buffer area may be set in the first simulator to cache these data.

[0076] The upload time of the above-mentioned echo current and echo voltage data will be staggered with the time when the first simulator transmits the output setting parameters to avoid communication conflicts and data loss. In the actual communication process, data conflicts can be avoided by setting the transmission period of uplink data and downlink data.

[0077] The above-mentioned method of integrating the echo control current using a preset sampling period to obtain the charge state can be understood as the charge state corresponding to this sampling period can be obtained by multiplying the corresponding duration of the sampling period with the echo control current. This method of determining the charge state is relatively simple. By setting a suitable sampling period, the difficulty of calculation can be effectively reduced while meeting the control accuracy requirements, and the real-time performance of the control can also be improved.

[0078] In some implementations, determining the output adjustment parameter according to the state of charge, the echo control voltage, a pre-built charge internal resistance correspondence table, and a pre-built charge voltage correspondence table includes:

[0079] According to the state of charge and charge voltage correspondence table, a first output setting voltage is obtained;

[0080] According to the corresponding relationship table between state of charge and charged internal resistance, the real-time internal resistance is obtained;

[0081] Obtaining a first output setting current according to the real-time internal resistance and the echo control voltage;

[0082] An output adjustment parameter is determined according to the first output setting voltage and the first output setting current.

[0083] The first output setting voltage is obtained according to the charge state and charge voltage correspondence table, that is, the charge state is used to look up the charge voltage correspondence table to obtain the corresponding voltage ratio, and then the first output setting voltage is obtained by multiplying the open circuit voltage and the obtained voltage ratio.

[0084] The real-time internal resistance is obtained according to the charge state and charge internal resistance correspondence table, that is, the charge state is used to look up the charge internal resistance correspondence table to obtain the corresponding internal resistance ratio, and then the maximum internal resistance and the obtained internal resistance ratio are multiplied to obtain the real-time internal resistance.

[0085] The first output setting current can be obtained by performing an ohmic operation using the real-time internal resistance and the echo control voltage after the real-time internal resistance is obtained.

[0086] The output adjustment parameter can be understood as a voltage control parameter and a current control parameter. After the first output setting voltage and the first output setting current are obtained, the voltage and current control parameters of the output channel module 130 can be confirmed.

[0087] In some implementations, determining the output adjustment parameter according to the first output setting voltage and the first output setting current includes:

[0088] In the case where a plurality of battery simulators are connected in parallel, the first output setting voltage is determined as the second output setting voltage, and the second output setting current is determined according to the first output setting current and the number of battery simulators connected in parallel;

[0089] In the case where a plurality of battery simulators are connected in series, the first output setting current is determined as the second output setting current, and the second output setting voltage is determined according to the first output setting voltage and the number of battery simulators connected in parallel;

[0090] An output adjustment parameter is obtained according to the second output setting current and the second output setting voltage.

[0091] The calculation method of the above-mentioned second output setting current is affected by the cascade method. In the parallel mode, the first output setting current needs to be evenly distributed to each battery simulator to obtain the second output setting current. In the series case, the current of each battery simulator is equal, and the first output setting current can be directly determined as the second output setting current.

[0092] The calculation method of the above-mentioned second output setting voltage is affected by the cascade method. In the series mode, the first output setting voltage needs to be evenly distributed to each battery simulator to obtain the second output setting voltage. In the parallel case, the voltage of each battery simulator is equal, and the first output setting voltage can be directly determined as the second output setting voltage.

[0093] In some embodiments, transmitting the output adjustment parameter to each output channel module 130 includes:

[0094] Transmitting the output adjustment parameters to the FPGA module 120 in the first simulator;

[0095] Generate a slave control data frame according to the output adjustment parameter;

[0096] The slave control data frame is broadcasted and transmitted to the control module 110 of each second simulator, wherein after receiving the corresponding slave control data frame, the control module 110 of each second simulator outputs the adjustment parameter in the slave control data frame and transmits it to the FPGA module 120, and feeds back the slave response signal to the control module 110 of the first simulator after the transmission of the output adjustment parameter is completed;

[0097] Upon receiving the feedback slave response signal fed back by each second simulator, the first enable line and each second enable line are adjusted to a second trigger level to control each battery simulator to transmit the output adjustment parameters in the FPGA module 120 to each output channel module 130, wherein the first trigger level and the second trigger level are different, wherein each output channel module 130 feeds back a channel response signal to the corresponding control module 110 upon receiving the output adjustment parameters.

[0098] After obtaining the output adjustment parameters, the control module 110 in the first simulator may first transmit the output adjustment parameters to the FPGA module 120 in the first simulator via the Fsmc bus, and the FPGA module 120 may temporarily store the output adjustment parameters.

[0099] After obtaining the output adjustment parameters, the control module 110 in the above-mentioned first simulator can use the output adjustment parameters to generate a slave control data frame, and then transmit the slave control data frame to each control module 110 in the second simulator through the Ethernet switch device, and then each control module 110 in the second simulator further transmits it to the FPGA module 120 for temporary storage.

[0100] After the control module 110 in each of the above-mentioned second simulators transmits the output adjustment parameters to the FPGA module 120 for temporary storage, it will generate a slave response signal, and transmit the slave response signal back to the first simulator through the Ethernet switch device. In the embodiment of the present application, full-duplex communication is performed based on the Ethernet switch device, and there is no need to worry about data transmission conflicts. It only needs to be determined that the output adjustment parameters are transmitted to the FPGA module 120 for temporary storage, and the slave response signal can be immediately fed back. It does not need to be executed according to a strict timing like the CAN bus transmission to avoid data conflicts.

[0101] After receiving the slave response signal returned by each second simulator, the first simulator can determine that the FPGA module 120 in each second simulator has completed the temporary storage of the output adjustment parameters. At this time, the first enable line and each second enable line can be adjusted to the second trigger level. When each battery simulator detects the second trigger level signal, it can transmit the output adjustment parameters temporarily stored in the FPGA module 120 to the corresponding output channel module 130. In this way, the synchronization of data transmission can be improved when transmitting the output adjustment parameters, the timing can be more strictly controlled, the control of uplink and downlink data transmission is convenient, and the possibility of data conflicts can be reduced.

[0102] The second trigger level and the first trigger level are different level signals. For example, the second trigger level can be set to a high level and the first trigger level can be set to a low level, or the second trigger level can be set to a low level and the first trigger level can be set to a high level. In the embodiment of the present application, the second trigger level can be set to a high level and the first trigger level can be set to a low level.

[0103] In some implementations, controlling the first enable line and each second enable line to output a first trigger level so that each output channel module 130 performs an output operation according to the received output adjustment parameter includes:

[0104] After confirming that each output channel transmission in each battery simulator has returned a channel response signal, the first enable line and the second enable line are adjusted to the first trigger level, so that each output channel module 130, upon detecting the first transition edge signal in the corresponding first enable line or the second enable line, responds to the trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

[0105] After receiving the output adjustment parameters, each of the above-mentioned output channel modules 130 transmits the feedback channel response signal to the corresponding control module 110. The control module 110 can determine whether there is data omission or mistransmission based on the feedback channel response signal. For example, if there is an output channel module 130 that does not feedback the channel response signal to the corresponding control module 110, it can be determined that there is a data omission. At this time, it is meaningless to perform synchronous control output, and an alarm can be generated to inform the operator.

[0106] After receiving the channel response signals fed back by the multiple output channel modules 130 corresponding to each battery simulator, the above-mentioned first simulator can adjust the first enable line and each second enable line to the first trigger level. When each battery simulator detects the first trigger level, each output channel module 130 can wait for the jump of the clock signal in the first clock line or the second clock line, for example, wait for the rising edge. When the rising edge of the clock signal is identified, the output can be completed according to the received output adjustment parameters.

[0107] It should be noted that the clock signals in the first clock line or the second clock line are synchronous, so that the multiple output channel modules 130 can complete synchronous output control.

[0108] It should also be noted that multiple battery simulators usually use the same model. Although there may be slight differences in data transmission time between the internal control modules 110, FPGA modules 120, and output channel modules 130 of the two battery simulators due to manufacturing process problems, the first simulator still needs to adjust the level of the first enable line and each second enable line after the channel response signal. This short period of time is sufficient to make up for the aforementioned time error, and there will be no situation in which the output channel module 130 in the second simulator is about to output but the channel response signal has not yet been fed back.

[0109] In some implementations, adjusting the first enable line and each second enable line to a second trigger level includes:

[0110] Sending a write enable signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enable line to the second trigger level and adjusts the second enable line connected to the adjacent FPGA module 120 to the second trigger level;

[0111] The FPGA module 120 in each second simulator synchronously adjusts the second enable line connected to the next FPGA module 120 to the second trigger level.

[0112] When receiving the slave response signal returned by each second simulator, the first simulator sends a write enable signal to the FPGA module 120 in the first simulator, and the FPGA module 120 can adjust the first enable line to the second trigger level, and synchronously adjust the second enable line connected to the adjacent FPGA module 120 to the second trigger level. The FPGA module 120 in each second simulator can synchronously adjust the enable line connected to the next FPGA module 120 to the second trigger level.

[0113] In this implementation, the characteristics of the FPGA module 120 are utilized to achieve synchronous transmission of the corresponding enable signal.

[0114] In some embodiments, controlling each battery simulator to transmit the output adjustment parameters in the FPGA module 120 to each output channel module 130 includes:

[0115] When the FPGA module 120 adjusts the first enable line to the second trigger level in the first simulator, the output adjustment parameter is sent to the corresponding output channel module 130;

[0116] When the FPGA module 120 in each second simulator detects the second transition edge signal in the second enable line, the FPGA module 120 in each second simulator sends the output adjustment parameter to the corresponding output channel module 130; the second transition edge signal and the first transition edge signal have different directions;

[0117] After receiving the corresponding output adjustment parameter, each output channel module 130 returns a channel response signal to the corresponding control module 110 through the corresponding FPGA module 120 .

[0118] In this embodiment, the second trigger level output by the FPGA module 120 in the first simulator through the second enable line can synchronously reach all second simulators. Based on this, each second simulator can synchronously send the corresponding output adjustment parameters to the corresponding output channel module 130 when detecting the second jump edge signal in the second enable line. In addition, the FPGA module 120 in the first simulator can also send the corresponding output adjustment parameters to the corresponding output channel module 130 when adjusting the first enable line to the second trigger level, thereby realizing synchronous control of all output channel modules 130 receiving the output adjustment parameters.

[0119] The first transition edge signal and the second transition edge signal are in opposite directions. For example, when the second trigger level is set to a high level and the first trigger level is set to a low level, the first transition edge signal can be understood as a falling edge signal and the second transition edge signal can be understood as a rising edge signal.

[0120] In some embodiments, the following steps are performed to confirm that each output channel transmission in each battery simulator has returned a channel response signal:

[0121] When receiving the signal indicating that each output channel transmission in the FPGA module 120 in the first simulator has returned a channel response signal, it is confirmed that each output channel transmission in each battery simulator has returned a channel response signal.

[0122] In the embodiment of the present application, the FPGA modules 120 in multiple battery simulators send output adjustment data to the output channels based on the second trigger level signal of the enable line. Therefore, the output adjustment data is transmitted simultaneously. Therefore, it is only necessary to determine that each output channel transmission in the FPGA module 120 in the first simulator has returned a channel response signal, so that it can be determined that all the FPGA modules 120 in the second simulator can complete the writing of the output adjustment parameters to the output channel before the next output enable signal arrives.

[0123] In some implementations, after any slave control data frame is sent to the control module 110 corresponding to the second simulator, the SOC synchronization control method further includes:

[0124] If no slave response signal returned by any second simulator is received within the first preset time length, a slave control data frame corresponding to any second simulator is resent.

[0125] In this embodiment, considering that the slave control data frame may not be sent to the corresponding second simulator, when it is detected that any second simulator does not return a slave response signal, a retransmission method will be adopted to ensure that each second simulator can receive the slave control data frame as much as possible.

[0126] In some implementations, the SOC synchronization control method further includes:

[0127] When a slave response signal returned by any second simulator is not received for N consecutive times, a first alarm message is generated, where N is a positive integer greater than or equal to 2.

[0128] In this embodiment, taking into account the possibility that the second simulator may be off-grid, at this time, the first simulator cannot obtain a slave response signal when sending multiple slave control data frames to the second simulator continuously. At this time, it is necessary to issue a first alarm message in time so that the operator can know the situation in time and conduct an alarm investigation.

[0129] In some implementations, the SOC synchronization control method further includes:

[0130] Each second simulator generates a second alarm message if it fails to receive the slave control data frame within the second preset time length.

[0131] In this embodiment, if any second simulator does not receive the slave control data frame within the second preset time length, it can be said that a communication failure has occurred between the second simulator and the first simulator. At this time, a second alarm message needs to be issued in time so that the operator can know the situation in time and conduct alarm investigation.

[0132] In some implementations, adjusting the first enable line and the second enable line to a first trigger level includes:

[0133] Sending an output enable signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enable line corresponding to the output channel module 130 to the first trigger level, and adjusts the second enable line connected to the adjacent FPGA module 120 to the first trigger level;

[0134] The FPGA module 120 in each second simulator adjusts the second enable line connected to the next FPGA module 120 to the first trigger level.

[0135] In this embodiment, the first trigger level output by the FPGA module 120 in the first simulator through the second enable line can synchronously reach all the second simulators, and then synchronously reach the output channel module 130 of each battery simulator, so that all the output channel modules 130 can synchronously detect the change of the level from the second trigger level to the first trigger level, and then the rising edge of the subsequently detected clock signal can be the same rising edge, thereby achieving high synchronization.

[0136] The SOC synchronization control method provided in the embodiment of the present application can be executed by a SOC synchronization control device. In the embodiment of the present application, the SOC synchronization control device executing the SOC synchronization control method is taken as an example to illustrate the SOC synchronization control device provided in the embodiment of the present application.

[0137] refer to Figure 3 The embodiment of the present application further provides a SOC synchronization control device, the SOC synchronization control device comprising:

[0138] A current acquisition module, used to acquire an echo control current, wherein, when multiple battery simulators are connected in series, the echo control current is the echo current of an output channel module 130 of any battery simulator, and when multiple battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of multiple battery simulators;

[0139] A voltage acquisition module, used to acquire an echo control voltage, where the echo control voltage is an echo voltage of an external device to which multiple battery simulators are connected after cascading;

[0140] A state of charge acquisition module, used to determine the state of charge according to the echo control current;

[0141] An adjustment parameter determination module, used to determine the output adjustment parameter according to the state of charge, the echo control voltage and a pre-constructed charge internal resistance correspondence table and a pre-constructed charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates the correspondence between multiple charge states and multiple internal resistance information, and the charge voltage correspondence table indicates the correspondence between multiple charge states and multiple voltage information;

[0142] A data transmission module, used for transmitting the output adjustment parameters to each output channel module 130;

[0143] The synchronous output control module is used to control the first enable line and each second enable line to output a first trigger level, so that each output channel module 130 performs an output operation according to the received output adjustment parameter.

[0144] The SOC synchronization control device in the embodiment of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (Ultra-mobile per Sonal Computer, UMPC), a netbook or a personal digital assistant (per Sonal digital asSiStant, PDA), etc. It can also be a server, a network attached storage (Network AttaChed Storage, NAS), a personal computer (per Sonal Computer, PC), a television (teleViSion, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0145] The embodiment of the present application also provides an electronic device, including: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the SOC synchronization control method as described above is implemented. The source table provided in the embodiment of the present application can implement each process implemented in the embodiment of the SOC synchronization control method described above, and achieve the same beneficial effects. To avoid repetition, it will not be repeated here.

[0146] An embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or a control module, so that the above-mentioned processor can execute the SOC synchronization control method in the above-mentioned embodiment, for example, execute the method described above.

[0147] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0148] The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0149] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0150] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0151] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A soc synchronization control method, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The SOC synchronization control method, applied to the control module of the first simulator, comprises: Acquire an echo control current, wherein, when a plurality of the battery simulators are connected in series, the echo control current is the echo current of one of the output channel modules of any of the battery simulators, and when a plurality of the battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the plurality of battery simulators; Acquire an echo control voltage, where the echo control voltage is an echo voltage of an external device to which a plurality of the battery simulators are connected after being cascaded; Determining the state of charge according to the echo control current; Determine the output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of internal resistance information, and the charge voltage correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of voltage information; Transmitting the output adjustment parameter to each of the output channel modules; Controlling the first enable line and each of the second enable lines to output a first trigger level, so that each of the output channel modules performs an output operation according to the received output adjustment parameter; The step of transmitting the output adjustment parameter to each of the output channel modules comprises: Transmitting the output adjustment parameter to the FPGA module in the first simulator; generating a slave control data frame according to the output adjustment parameter; The slave control data frame is broadcasted and transmitted to each control module of the second simulator, wherein, after receiving the corresponding slave control data frame, each control module of the second simulator transmits the output adjustment parameter in the slave control data frame to the FPGA module, and feeds back a slave response signal to the control module of the first simulator after completing the transmission of the output adjustment parameter; Upon receiving a feedback slave response signal fed back by each of the second simulators, adjusting the first enable line and each of the second enable lines to a second trigger level, so as to control each of the battery simulators to transmit the output adjustment parameters in the FPGA module to each of the output channel modules, wherein the first trigger level and the second trigger level are different, wherein each of the output channel modules feeds back a channel response signal to the corresponding control module upon receiving the output adjustment parameters; The controlling the first enable line and each of the second enable lines to output a first trigger level so that each of the output channel modules performs an output operation according to the received output adjustment parameter comprises: After confirming that each of the output channel transmissions in each of the battery simulators has returned the channel response signal, the first enable line and the second enable line are adjusted to a first trigger level so that each of the output channel modules, upon detecting a first transition edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

2. The soc synchronization control method according to claim 1, characterized in that: The determining the state of charge according to the echo control current includes: Integrating the echo control current using a preset sampling period to obtain the charge state; The sampling period is a time period for acquiring the echo current and the echo voltage, and the echo current and the echo voltage are acquired synchronously.

3. The soc synchronization control method according to claim 1, characterized in that: The step of determining the output adjustment parameter according to the state of charge, the echo control voltage, a pre-built charge internal resistance correspondence table, and a pre-built charge voltage correspondence table includes: Obtaining a first output setting voltage according to the charge state and the charge voltage correspondence table; Obtaining real-time internal resistance according to the charge state and the charge internal resistance correspondence table; Obtaining a first output setting current according to the real-time internal resistance and the echo control voltage; The output adjustment parameter is determined according to the first output setting voltage and the first output setting current.

4. The soc synchronization control method according to claim 3, characterized in that: The step of determining the output adjustment parameter according to the first output setting voltage and the first output setting current includes: In the case where a plurality of the battery simulators are connected in parallel, the first output setting voltage is determined as a second output setting voltage, and a second output setting current is determined according to the first output setting current and the number of the battery simulators connected in parallel; When a plurality of the battery simulators are connected in series, the first output setting current is determined as the second output setting current, and the second output setting voltage is determined according to the first output setting voltage and the number of the battery simulators connected in parallel; The output adjustment parameter is obtained according to the second output setting current and the second output setting voltage.

5. The soc synchronization control method according to claim 1, characterized in that: The step of adjusting the first enable line and each of the second enable lines to a second trigger level includes: Sending a write enable signal to the FPGA module in the first simulator, so that the FPGA module in the first simulator adjusts the first enable line to a second trigger level and adjusts the second enable line connected to the adjacent FPGA module to a second trigger level; Among them, the FPGA module in each of the second simulators synchronously adjusts the second enable line connected to the next FPGA module to the second trigger level.

6. A soc synchronous control device, characterized in that: Used to synchronize multiple battery simulators in a multi-channel battery simulator platform, each of the battery simulators includes a control module, an FPGA module, and multiple output channel modules, the control module is communicatively connected to the FPGA module, a serial communication line, a first enable line, and a first clock line are connected between the FPGA module and each of the output channel modules; multiple battery simulators are arranged in sequence, and a second enable line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators; multiple FPGA modules output synchronized clock signals to the corresponding output channel modules through the first clock line and the second clock line; the control modules of multiple battery simulators are connected through an Ethernet switch device; the battery simulator in the first position is the first simulator, and the remaining battery simulators are the second simulators; The SOC synchronization control device, applied to the control module of the first simulator, comprises: A current acquisition module, used to acquire an echo control current, wherein, when a plurality of the battery simulators are connected in series, the echo control current is the echo current of one of the output channel modules of any of the battery simulators, and when a plurality of the battery simulators are connected in parallel, the echo control current is the accumulation of the echo currents of the plurality of battery simulators; A voltage acquisition module, used for acquiring an echo control voltage, wherein the echo control voltage is an echo voltage of an external device connected to a plurality of the battery simulators after cascading; A state of charge acquisition module, used to determine the state of charge according to the echo control current; an adjustment parameter determination module, configured to determine an output adjustment parameter according to the state of charge, the echo control voltage, a pre-constructed charge internal resistance correspondence table, and a pre-constructed charge voltage correspondence table, wherein the charge internal resistance correspondence table indicates a correspondence between a plurality of the states of charge and a plurality of internal resistance information, and the charge voltage correspondence table indicates a correspondence between a plurality of the states of charge and a plurality of voltage information; A data transmission module, used for transmitting the output adjustment parameter to each of the output channel modules; a synchronous output control module, used for controlling the first enable line and each of the second enable lines to output a first trigger level, so that each of the output channel modules performs an output operation according to the received output adjustment parameter; The step of transmitting the output adjustment parameter to each of the output channel modules comprises: Transmitting the output adjustment parameter to the FPGA module in the first simulator; generating a slave control data frame according to the output adjustment parameter; The slave control data frame is broadcasted and transmitted to each control module of the second simulator, wherein, after receiving the corresponding slave control data frame, each control module of the second simulator transmits the output adjustment parameter in the slave control data frame to the FPGA module, and feeds back a slave response signal to the control module of the first simulator after completing the transmission of the output adjustment parameter; Upon receiving a feedback slave response signal fed back by each of the second simulators, adjusting the first enable line and each of the second enable lines to a second trigger level, so as to control each of the battery simulators to transmit the output adjustment parameters in the FPGA module to each of the output channel modules, wherein the first trigger level and the second trigger level are different, wherein each of the output channel modules feeds back a channel response signal to the corresponding control module upon receiving the output adjustment parameters; The controlling the first enable line and each of the second enable lines to output a first trigger level so that each of the output channel modules performs an output operation according to the received output adjustment parameter comprises: After confirming that each of the output channel transmissions in each of the battery simulators has returned the channel response signal, the first enable line and the second enable line are adjusted to a first trigger level so that each of the output channel modules, upon detecting a first transition edge signal in the corresponding first enable line or the second enable line, responds to a trigger edge signal in the corresponding first clock line or the second clock line and performs an output operation according to the received output adjustment parameters.

7. An electronic device, characterized in that: The electronic device comprises a processor and a memory storing computer program instructions; When the processor executes the computer program, the SOC synchronization control method as described in any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the SOC synchronization control method as described in any one of claims 1 to 5.

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