Electronic device related to detection of internal voltage

Abstract

An electronic device includes a test control circuit configured to generate a test code, configured to generate a reference voltage of which a voltage level is adjusted in response to the test code, and configured to generate a test current of which an amount is adjusted in response to the reference voltage; and an internal voltage detection circuit configured to generate a detection signal for controlling driving of the internal voltage by detecting the internal voltage in response to the test current.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Application No. 10-2023-0077072 filed in the Korean Intellectual Property Office on June 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device related to detection of internal voltage. Background Art

[0004] Generally, an electronic device such as a semiconductor device generates an internal voltage required for internal operation by receiving a power supply voltage VDD and a ground voltage VSS from the outside, and uses the generated internal voltage. The voltage required for the internal operation of the semiconductor device includes a core voltage VCORE supplied to a core region of a memory, a boost voltage VPP used when driving a word line or when overdriving, and a reverse bias voltage VBB supplied as a body voltage of an NMOS transistor in the core region.

[0005] In this case, the power supply voltage VDD received from the outside only needs to be stepped down to a predetermined level and supplied as the core voltage VCORE. However, the boost voltage VPP has a higher level than the power supply voltage VDD received from the outside, and the reverse bias voltage VBB maintains a lower level than the ground voltage VSS received from the outside. Therefore, a charge pumping circuit is required to supply charge for the boost voltage VPP and the reverse bias voltage VBB. Summary of the invention

[0006] In one embodiment, an electronic device may include a test control circuit configured to generate a test code, the test code being selected or generated or "configured to" generate a reference voltage, the magnitude of which is adjusted based on (i.e., in response to) the test code. The test control circuit is additionally configured to generate a test current, the amount of which is adjusted based on the reference voltage, and the internal voltage detection circuit is configured to generate a detection signal for controlling the driving of an internal voltage by detecting the internal voltage based on the test current. In one embodiment of the present disclosure, preferably, the voltage level of the internal voltage detected by the internal voltage detection circuit is adjusted based on the amount of the test current.

[0007] In one embodiment, an electronic device may include: a test code generation circuit, which is configured to generate a first test code and a second test code when entering a test mode; a reference voltage selection circuit, which is configured to generate a first reference voltage and a second reference voltage, and the voltage level of the first reference voltage and the voltage level of the second reference voltage are adjusted based on the first test code and the second test code, respectively; a test current generation circuit, which is configured to generate a test current, the amount of which is adjusted based on the first reference voltage and the second reference voltage; and an internal voltage detection circuit, which is configured to generate a detection signal for an internal voltage by detecting the internal voltage based on the test current. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a configuration of an electronic device according to one example of the present disclosure.

[0009] Figure 2 is based on a Figure 1 A circuit diagram of an example of a reference voltage selection circuit in an electronic device is shown.

[0010] Figure 3 is based on a Figure 1 A circuit diagram of an example of a test current generating circuit in an electronic device is shown.

[0011] Figure 4 is based on a Figure 1 A circuit diagram of an example of an internal voltage detection circuit in an electronic device shown.

[0012] Figure 5 It is used to describe the execution being performed and to adjust the Figure 1 FIG. 1 is a flow chart of an operation of a test mode for detecting a voltage level of an internal voltage in an electronic device.

[0013] Figures 6 to 9 is a view for showing operations in the test mode being executed. DETAILED DESCRIPTION

[0014] In the description of the following embodiments, the term "preset" means that the value of the parameter is predetermined when the parameter is used in a process or algorithm. According to one embodiment, the value of the parameter can be set when starting the process or algorithm or when executing the process or algorithm.

[0015] Terms such as "first" and "second" are used to distinguish between components, but are not limited to these components. For example, a first component may be referred to as a second component, and vice versa.

[0016] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be coupled or connected directly to each other or to each other through another component interposed therebetween. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without additional components interposed therebetween.

[0017] "Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is distinguished from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to one embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to one embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

[0018] "Logical bit set" may mean a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal is changed, the logic bit set of the signal may be set differently. For example, if two bits are included in the signal, when the logic levels of the two bits included in the signal are "logic low level" and "logic low level", the logic bit set of the signal may be set to a first logic bit set, and when the logic levels of the two bits included in the signal are "logic low level" and "logic high level", the logic bit set of the signal may be set to a second logic bit set.

[0019] Hereinafter, the present disclosure will be described in more detail by way of examples. These examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0020] Figure 1 is a block diagram showing an electronic device 1 according to an example of the present disclosure. The electronic device may include a test control circuit 11 , an internal voltage detection circuit (VBB DET) 13 , and an internal voltage generation circuit (VBB GEN) 15 .

[0021] When the test control circuit 11 enters the test mode, the test control circuit can generate test codes TM_CD1, TM_CD2 and TM_CD3. It can also generate reference voltages VREF1, VREF2 and VREF3, whose voltage amplitudes are adjusted based on the test codes TM_CD1, TM_CD2 and TM_CD3.

[0022] The test control circuit 11 may generate a test current TI whose amperage is determined by and adjusted based on (in response to) the reference voltages VREF1 , VREF2 , and VREF3 . The test control circuit 11 may supply the test current TI to the internal voltage detection circuit 13 .

[0023] The test codes TM_CD1, TM_CD2, and TM_CD3 may include a first test code TM_CD1, a second test code TM_CD2, and a third test code TM_CD3. The reference voltages VREF1, VREF2, and VREF3 may include a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF3.

[0024] The test control circuit 11 may include a test code generation circuit (TM_CD GEN) 111 , a reference voltage selection circuit (VREF SEL) 113 , and a test current generation circuit (TI GEN) 115 .

[0025] The test code generation circuit 111 may generate a first test code TM_CD1, a second test code TM_CD2, and a third test code TM_CD3 by receiving a test mode enable signal TM_EN generated when entering a test mode. The first test code TM_CD1 may include a plurality of binary digits, also referred to as "bits". The values ​​of the respective bits of a group of bits included (i.e., contained) in the first test code TM_CD1 may be set to adjust the voltage level of the first reference voltage VREF1. For example, the test code generation circuit 111 may generate a first test code TM_CD1 including bits that have been set to a first logic level (logic 0 or logic 1) so as to set the voltage level of the first reference voltage VREF1 to the first logic level, and generate a first test code TM_CD1 including bits that have been set to a second logic bit group so as to set the voltage level of the first reference voltage VREF1 to the second voltage level. A group of bits included in the second test code TM_CD2 may be set to adjust the voltage level of the second reference voltage VREF2. A group of bits included in the third test code TM_CD3 may be set to adjust the voltage level of the third reference voltage VREF3. The test code generation circuit 111 may be connected to the reference voltage selection circuit 113 , and may provide the first test code TM_CD1 , the second test code TM_CD2 , and the third test code TM_CD3 to the reference voltage selection circuit 113 .

[0026] "Sequentially" is an adverb that is often used to describe things that are arranged in order. "Sequence" usually refers to a group of elements that are arranged in an orderly manner.

[0027] When used in this article to describe voltage and current, "adjusting in sequence" should not be interpreted as meaning that different voltage or current levels are set or arranged or fixed in a specific order or sequence so that each voltage and successive voltage or current levels differ from adjacent levels by the same incremental difference, where "increment" refers to the amount by which something changes. On the contrary, "adjusting in sequence" should be interpreted as including changing or adjusting the voltage or current with one or more step amounts (step) or increments, and the step amounts may be equal or different in size. If the step amount or increment between the levels is fixed and equal, the voltage or current adjusted in sequence can therefore be changed in increments of the same size. If the step amount size or increment between the levels is unequal, the voltage or current adjusted in sequence may also change nonlinearly.

[0028] In the test mode, the test code generation circuit 111 may generate a first test code TM_CD1 for sequentially adjusting the voltage level of the first reference voltage VREF1 in a state where the logic bit group of the bits included in the second test code TM_CD2 and the logic bit group of the bits included in the third test code TM_CD3 are constantly maintained. The first test code TM_CD1 may include bits having the logic bit group adjusted sequentially. For example, the test code generation circuit 111 may generate the first test code TM_CD1 for sequentially adjusting the voltage level of the first reference voltage VREF1 from the first voltage level to the Nth voltage level in a state where the voltage level of the second reference voltage VREF2 and the voltage level of the third reference voltage VREF3 have been fixed. The first test code TM_CD1 may include bits having the logic bit group adjusted sequentially.

[0029] In the test mode, the test code generation circuit 111 may generate a second test code TM_CD2 for sequentially adjusting the voltage level of the second reference voltage VREF2 in a state where the logic bit group of the bits included in the first test code TM_CD1 and the logic bit group of the bits included in the third test code TM_CD3 are constantly maintained. The second test code TM_CD2 may include bits having the logic bit group adjusted sequentially. For example, the test code generation circuit 111 may generate a second test code TM_CD2 for sequentially adjusting the voltage level of the second reference voltage VREF2 from the first voltage level to the Nth voltage level in a state where the voltage level of the first reference voltage VREF1 and the voltage level of the third reference voltage VREF3 have been fixed. The second test code TM_CD2 may include bits having the logic bit group adjusted sequentially.

[0030] In the test mode, the test code generation circuit 111 may generate a third test code TM_CD3 for sequentially adjusting the voltage level of the third reference voltage VREF3 in a state where the logic bit group of the bits included in the first test code TM_CD1 and the logic bit group of the bits included in the second test code TM_CD2 are constantly maintained. The third test code TM_CD3 may include bits having the logic bit group adjusted sequentially. For example, the test code generation circuit 111 may generate the third test code TM_CD3 for sequentially adjusting the voltage level of the third reference voltage VREF3 from the first voltage level to the Nth voltage level in a state where the voltage level of the first reference voltage VREF1 and the voltage level of the second reference voltage VREF2 have been fixed. The third test code TM_CD3 may include bits having the logic bit group adjusted sequentially.

[0031] The reference voltage selection circuit 113 may generate a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF3, the voltage levels of which are adjusted based on (i.e., in response to) the first test code TM_CD1, the second test code TM_CD2, and the third test code TM_CD3, respectively. The reference voltage selection circuit 113 may generate a first reference voltage VREF1, the voltage level of which is adjusted based on (i.e., in response to) the first test code TM_CD1. The reference voltage selection circuit 113 may generate a second reference voltage VREF2, the voltage level of which is adjusted in response to the second test code TM_CD2. The reference voltage selection circuit 113 may generate a third reference voltage VREF3, the voltage level of which is adjusted in response to the third test code TM_CD3.

[0032] The reference voltage selection circuit 113 can generate a plurality of “divided voltages” (eg, Figure 2 VDIV<1:N> in the figure), the voltage amplitudes or levels of these divided voltages have been set differently through a voltage division operation, which can use a traditional resistor divider network, which includes resistors connected in series, and the resistance value of each resistor may be equal in one embodiment or different from each other in different embodiments.

[0033] The reference voltage selection circuit 113 may output a plurality of divided voltages (eg, Figure 2 The reference voltage selection circuit 113 can output a plurality of divided voltages (eg, VDIV<1:N>) by selecting a divided voltage as the second reference voltage VREF2 in response to a logical bit group of bits included in the second test code TM_CD2. Figure 2 The reference voltage selection circuit 113 can output a plurality of divided voltages (eg, VDIV<1:N>) by selecting a divided voltage as the third reference voltage VREF3 in response to a logic bit group of bits included in the third test code TM_CD3. Figure 2 The reference voltage selection circuit 113 may be connected to the test current generation circuit 115 and may supply the first reference voltage VREF1, the second reference voltage VREF2, and the third reference voltage VREF3 to the test current generation circuit 115.

[0034] The reference voltage selection circuit 113 may sequentially adjust (incrementally adjust or step-change) the voltage level of the first reference voltage VREF1 in response to the first test code TM_CD1 in a state where the voltage level of the second reference voltage VREF2 has been fixed in response to the second test code TM_CD2 and the voltage level of the third reference voltage VREF3 has been fixed in response to the third test code TM_CD3. For example, the reference voltage selection circuit 113 may generate the first reference voltage VREF1, which is sequentially adjusted from the first voltage level to the Nth voltage level in a state where the voltage level of the second reference voltage VREF2 and the voltage level of the third reference voltage VREF3 have been fixed.

[0035] The reference voltage selection circuit 113 may sequentially adjust the voltage level of the second reference voltage VREF2 in response to the second test code TM_CD2 in a state where the voltage level of the first reference voltage VREF1 has been fixed in response to the first test code TM_CD1 and the voltage level of the third reference voltage VREF3 has been fixed in response to the third test code TM_CD3. For example, the reference voltage selection circuit 113 may generate the second reference voltage VREF2, which is sequentially adjusted from the first voltage level to the Nth voltage level in a state where the voltage levels of the first reference voltage VREF1 and the third reference voltage VREF3 have been fixed.

[0036] The reference voltage selection circuit 113 may sequentially adjust the voltage level of the third reference voltage VREF3 in response to the third test code TM_CD3 in a state where the voltage level of the first reference voltage VREF1 has been fixed in response to the first test code TM_CD1 and the voltage level of the second reference voltage VREF2 has been fixed in response to the second test code TM_CD2. For example, the reference voltage selection circuit 113 may generate the third reference voltage VREF3, which is sequentially adjusted from the first voltage level to the Nth voltage level in a state where the voltage level of the first reference voltage VREF1 and the voltage level of the second reference voltage VREF2 have been fixed.

[0037] The test current generating circuit 115 may generate a test current TI whose amount is adjusted in response to the first reference voltage VREF1, the second reference voltage VREF2, and the third reference voltage VREF3. The test current generating circuit 115 may set a first voltage (eg, Figure 3 The test current generating circuit 115 may set the first current (eg, Figure 3 The test current generating circuit 115 may set the second current (eg, Figure 3 The test current generating circuit 115 may be responsive to the first current (eg, Figure 3 I1 in) and a second current (e.g., Figure 3 The amount of the test current TI may be set to a first current (eg, Figure 3 I1 in the figure and the amount of the second current (e.g., Figure 3 The sum of the quantities I2) in .

[0038] The internal voltage detection circuit 13 can generate a detection signal DET, which determines whether the internal voltage VBB needs to be driven or changed by detecting the voltage level (i.e., amplitude) of the internal voltage VBB. The internal voltage detection circuit 13 can generate a detection signal DET, which is enabled when the voltage level of the internal voltage VBB is higher than the target level. According to an embodiment, the target level can be set to a variety of different voltage levels. The internal voltage detection circuit 13 can: adjust the voltage level of the detected internal voltage VBB by receiving the test current TI supplied by the test control circuit 11, thereby performing a "fine-tuning" voltage level adjustment operation, that is, adjusting the voltage level by a small increment or step amount. For example, the internal voltage detection circuit 13 can: when the target level has been set to -0.6V, when the amount of the test current TI generated in the test mode is sequentially increased and supplied, perform a fine-tuning operation of sequentially adjusting the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13, such as -0.61V, -0.62V and -0.63V. The internal voltage detection circuit 13 may be implemented to detect that the internal voltage VBB has a lower voltage level when the amount of the test current TI supplied by the test control circuit 11 is increased, but this is only an embodiment and the present disclosure is not limited thereto. The internal voltage detection circuit 13 may be connected to the internal voltage generation circuit 15 and may provide a detection signal DET to the internal voltage generation circuit 15.

[0039] As used herein, the verb "drive" should be interpreted as meaning or referring to setting or imposing or providing a signal with a particular level or amplitude. For example, "driving" a node to three volts means that the node is provided with or imposed with a voltage of 3 volts.

[0040] The internal voltage generating circuit 15 may generate the internal voltage VBB in response to the detection signal DET. The internal voltage generating circuit 15 may reduce the voltage level of the internal voltage VBB by driving the internal voltage VBB when receiving the detection signal DET that has been enabled. The internal voltage generating circuit 15 may stop driving the internal voltage VBB when receiving the detection signal DET that has been disabled.

[0041] Figure 2 1 is a circuit diagram of a reference voltage selection circuit 113A according to an example of the reference voltage selection circuit 113. Figure 2 As shown, the reference voltage selection circuit 113A may include a voltage division generation circuit 121 , a first reference voltage output circuit 123 , a second reference voltage output circuit 125 and a third reference voltage output circuit 127 .

[0042] The divided voltage generating circuit 121 may generate divided voltages VDIV<1:N> having different voltage levels in the test mode. The divided voltages VDIV<1:N> may include first to Nth divided voltages VDIV <1> 、VDIV <2> To VDIV <n>The first voltage divider VDIV <1> The second divided voltage VDIV may have the first voltage level already set to the highest. <2> The Nth divided voltage VDIV may have a second voltage level. <n>The Nth voltage level may have been set to be the lowest, but this is only an embodiment and the present disclosure is not limited thereto. The voltage division generating circuit 121 may include a comparison driving circuit 131 and a voltage division circuit 133 .

[0043] The comparison driving circuit 131 can set the voltage level of the internal node nd144 to a preset voltage level in response to the test reference voltage TVREF and the test bias voltage TVBIAS. The voltage level of the test reference voltage TVREF can be set to a voltage level that is half of the voltage level of the internal node nd144 in the test mode, but this is only an embodiment and the present disclosure is not limited thereto. The voltage level of the test bias voltage TVBIAS can be set to the same level as the preset voltage level in the test mode.

[0044] The comparison driving circuit 131 may include PMOS transistors 141_1, 141_2, and 141_3 and NMOS transistors 143_1, 143_2, 143_3, 143_4, and 143_5. The PMOS transistors 141_1 and 141_2 may be connected between a terminal for a power supply voltage VDD and nodes nd141 and nd143, and may operate as constant current sources that supply current to nodes nd141 and nd143, respectively. The NMOS transistors 143_1 and 143_2 may be connected between nodes nd141 and nd143 and a node nd142, and may adjust the amount of current discharged by nodes nd141 and nd143 accordingly in response to a comparison result between a node nd145 and a test reference voltage TVREF.

[0045] As used herein and when referring to a field effect transistor (FET), whether it is PMOS or NMOS, "on" should be interpreted to mean that the channel is not "pinched off."

[0046] When the voltage of the node nd145 has a voltage level lower than the test reference voltage TVREF, the amount of current discharged by the NMOS transistor 143_1 becomes larger than the amount of current discharged by the NMOS transistor 143_2, so that the node nd141 can be set to have a logic low level. The NMOS transistor 143_2 can be turned on by the test bias TVBIAS in the test mode, and the current of the node nd142 can be discharged to the terminal for the ground voltage VSS. The PMOS transistor 141_3 can be turned on by the voltage of the node nd141, and the voltage level of the node nd144 can be driven to the voltage level of the power supply voltage VDD. The NMOS transistors 143_4 and 143_5 can each operate as a resistance element, and the voltage level of the node nd144 can be divided. If the NMOS transistors 143_4 and 143_5 are set to have the same size, the resistance values ​​of the NMOS transistors 143_4 and 143_5 are set equally. Accordingly, the voltage level of the node nd145 may be set to half the voltage level of the node nd144 .

[0047] The voltage divider circuit 133 may include a plurality of resistor elements connected in series between the node nd144 and a terminal for the ground voltage VSS. The voltage divider circuit 133 may generate the first to Nth divided voltages VDIV<1:N> by dividing the voltage level of the node nd144. Among the first to Nth divided voltages VDIV<1:N>, the first divided voltage VDIV <1> can be set to have the maximum voltage level, and the Nth voltage divider VDIV <n>Can be set to have a minimum voltage level. However, this is only an embodiment, and the present disclosure is not limited thereto. The structure of the voltage divider circuit 133 can be modified in various ways to generate a plurality of divided voltages with different voltage levels.

[0048] As used herein, a "transmission gate" is an electronic component that will selectively block a signal from an input to an output or pass a signal from an input to an output. Such a gate is typically formed by a pMOS transistor and an nMOS transistor whose control gates are biased in a complementary manner so that both transistors are turned on or off.

[0049] The first reference voltage output circuit 123 may output one of the first to N-th divided voltages VDIV<1:N> by selecting a divided voltage as the first reference voltage VREF1 in response to the first to N-th bits TM_CD1<1:N> of the first test code. The first reference voltage output circuit 123 may include inverters 151_1, 151_2 to 151_N and transmission gates 153_1, 153_2 to 153_N. The inverters 151_1, 151_2 to 151_N may respectively output the first to N-th bits TM_CD1<1:N> of the first test code by inverting and buffering the first to N-th bits TM_CD1<1:N> of the first test code. When each of the first to N-th bits TM_CD1<1:N> of the first test code is set to have a logic high level, each of the transmission gates 153_1, 153_2 to 153_N may be turned on. For example, when the first bit TM_CD1 of the first test code <1> When the second bit to the Nth bit TM_CD1<2:N> of the first test code have a logic high level and the second bit to the Nth bit TM_CD1<2:N> of the first test code have a logic low level, the transmission gate 153_1 may be turned on. Accordingly, the first reference voltage output circuit 123 may select the first divided voltage VDIV <1> The first divided voltage VDIV is output as the first reference voltage VREF1 <1> As another example, when the Nth bit TM_CD1 of the first test code <n>When the first bit to the N-1th bit TM_CD1<1:N-1> of the first test code have a logic high level and the first bit to the N-1th bit TM_CD1<1:N-1> have a logic low level, the transmission gate 153_N may be turned on. Accordingly, the first reference voltage output circuit 123 may select the Nth divided voltage VDIV <n>The Nth divided voltage VDIV is output as the first reference voltage VREF1 <n>.

[0050] The second reference voltage output circuit 125 may output one of the first to Nth divided voltages VDIV<1:N> by selecting a divided voltage as the second reference voltage VREF2 in response to the first to Nth bits TM_CD2<1:N> of the second test code. The second reference voltage output circuit 125 may include inverters 161_1, 161_2 to 161_N and transmission gates 163_1, 163_2 to 163_N. The inverters 161_1, 161_2 to 161_N may output the first to Nth bits TM_CD2<1:N> of the second test code accordingly by inverting and buffering the first to Nth bits TM_CD2<1:N> of the second test code. When each of the first to Nth bits TM_CD2<1:N> of the second test code is set to have a logic high level, each of the transmission gates 163_1, 163_2 to 163_N may be turned on. For example, when the first bit TM_CD2 of the second test code <1> When the second bit to the Nth bit TM_CD2<2:N> of the second test code have a logic high level and the second bit to the Nth bit TM_CD2<2:N> of the second test code have a logic low level, the transmission gate 163_1 may be turned on. Accordingly, the second reference voltage output circuit 125 may select the first divided voltage VDIV <1> The first divided voltage VDIV is output as the second reference voltage VREF2 <1> As another example, when the Nth bit TM_CD2 of the second test code <n>When the first bit to the N-1th bit TM_CD2<1:N-1> of the second test code have a logic high level and the first bit to the N-1th bit TM_CD2<1:N-1> have a logic low level, the transmission gate 163_N may be turned on. Accordingly, the second reference voltage output circuit 125 may select the Nth divided voltage VDIV <n>The Nth divided voltage VDIV is output as the second reference voltage VREF2 <n>.

[0051] The third reference voltage output circuit 127 may output one of the first to Nth divided voltages VDIV<1:N> by selecting one divided voltage as the third reference voltage VREF3 in response to the first to Nth bits TM_CD3<1:N> of the third test code. The third reference voltage output circuit 127 may include inverters 171_1, 171_2 to 171_N and transmission gates 173_1, 173_2 to 173_N. The inverters 171_1, 171_2 to 171_N may respectively output the first to Nth bits TM_CD3<1:N> of the third test code by inverting and buffering the first to Nth bits TM_CD3<1:N>. When each of the first to Nth bits TM_CD3<1:N> of the third test code is set to have a logic high level, each of the transmission gates 173_1, 173_2 to 173_N may be turned on. For example, when the first bit TM_CD3 of the third test code is <1> When the second bit to the Nth bit TM_CD3<2:N> of the third test code have a logic high level and the second bit to the Nth bit TM_CD3<2:N> of the third test code have a logic low level, the transmission gate 173_1 may be turned on. Accordingly, the third reference voltage output circuit 127 may select the first divided voltage VDIV <1> The first divided voltage VDIV is output as the third reference voltage VREF3 <1> As another example, when the Nth bit TM_CD3 of the third test code <n>When the first bit to the N-1th bit TM_CD3<1:N-1> of the third test code have a logic high level and the first bit to the N-1th bit TM_CD3<1:N-1> have a logic low level, the transmission gate 173_N may be turned on. Accordingly, the third reference voltage output circuit 127 may select the Nth divided voltage VDIV <n>The Nth divided voltage VDIV is output as the third reference voltage VREF3 <n>.

[0052] Figure 3 FIG. 1 is a circuit diagram of a test current generating circuit 115A according to an example of the test current generating circuit 115. Figure 3 As shown, the test current generating circuit 115A may include a voltage setting circuit 201 , a first current setting circuit 203 , and a second current setting circuit 205 .

[0053] As used herein, a comparator is an electronic device that compares two input voltages and outputs a binary signal, which is a signal that can be only one of two different values ​​when output from the device, and a particular output signal indicates which input signal is larger. In most comparator embodiments, if the non-inverting (+) input is greater than the inverting (-) input, the output goes high. If the inverting input is greater than the non-inverting input, the output goes low.

[0054] The voltage setting circuit 201 may set the first voltage V1 in response to the first reference voltage VREF1. The voltage setting circuit 201 may adjust the voltage level of the first voltage V1 by comparing the first reference voltage VREF1 and the first voltage V1. The voltage setting circuit 201 may include a first comparator 211 and a PMOS transistor 213. The first comparator 211 may generate a first comparison signal AP1 by comparing the first voltage V1 and the first reference voltage VREF1. When the first voltage V1 has a voltage level lower than the first reference voltage VREF1, the first comparator 211 may generate a first comparison signal AP1 set to a logic low level. The PMOS transistor 213 may be turned on when receiving the first comparison signal AP1 set to a logic low level due to the voltage level of the first voltage V1 being lower than the voltage level of the first reference voltage VREF1, and may drive the first voltage V1 output by the node nd211. The voltage setting circuit 201 may be implemented to set the voltage level of the first voltage V1 to a higher voltage level as the voltage level of the first reference voltage VREF1 increases, but this is only an embodiment and the present disclosure is not limited thereto.

[0055] The first current setting circuit 203 may set the first current I1 in response to the second reference voltage VREF2. The first current setting circuit 203 may include a first resistance element 220, a second comparator 221, and an NMOS transistor 223. The second comparator 221 may generate a second comparison signal AP2 by comparing the second reference voltage VREF2 with the second voltage V2. When the second voltage V2 has a voltage level lower than the second reference voltage VREF2, the second comparator 221 may generate a second comparison signal AP2 set to have a logic high level. The NMOS transistor 223 may be turned on when receiving the second comparison signal AP2 set to have a logic high level because the voltage level of the second voltage V2 is lower than the voltage level of the second reference voltage VREF2, and may transmit the first current I1 as a test current TI. The first current setting circuit 203 may be implemented as follows: as the voltage level of the second reference voltage VREF2 increases, the voltage level of the second voltage V2 is set to a higher voltage level, and the amount of the first current I1 is set to be larger, but this is only an embodiment, and the present disclosure is not limited thereto.

[0056] The second current setting circuit 205 may set the second current I2 in response to the third reference voltage VREF3. The second current setting circuit 205 may include a second resistance element 230, a third comparator 231, and an NMOS transistor 233. The third comparator 231 may generate a third comparison signal AP3 by comparing the third reference voltage VREF3 and the third voltage V3. When the third voltage V3 has a voltage level higher than the third reference voltage VREF3, the third comparator 231 may generate a third comparison signal AP3 set to have a logic high level. The NMOS transistor 233 may be turned on when receiving the third comparison signal AP3 set to have a logic high level when the voltage level of the third voltage V3 is higher than the voltage level of the third reference voltage VREF3, and may transmit the second current I2 as a test current TI. The second current setting circuit 205 may be implemented as follows: as the voltage level of the second reference voltage VREF2 decreases, the voltage level of the third voltage V3 is set to a higher voltage level, and the amount of the second current I2 is set to be larger, but this is only an embodiment, and the present disclosure is not limited thereto.

[0057] Figure 4 1 is a circuit diagram of an internal voltage detection circuit 13A according to an example of the internal voltage detection circuit 13. Figure 4 As shown, the internal voltage detection circuit 13A may include: PMOS transistors 251_1, 251_2, 251_3, 251_4 and 251_5, NMOS transistors 253_1, 253_2, 253_3, 253_4 and 253_5, resistor elements 255_1 and 255_2, and an inverter 257. The PMOS transistors 251_1 and 251_2 may be operated as constant current sources that supply current to nodes nd251 and nd252, respectively. The PMOS transistors 251_3 and 251_4 may be turned on by the first bias voltage VBIAS1, and may be operated as constant current sources that supply current to nodes nd253 and nd255, respectively. The conduction degree of NMOS transistors 253_1, 253_2, 253_3 and 253_4 can be determined in response to the voltages of nodes nd251, nd252, nd253, nd254 and nd255. The voltages of nodes nd254 and nd255 can be set equally by NMOS transistors 253_1, 253_2, 253_3 and 253_4. PMOS transistor 251_5 can be turned on in response to the voltage level of node nd252, and the voltage level of node nd256 can be pulled up and driven to the voltage level of power supply voltage VDD. NMOS transistor 253_5 can be turned on by second bias voltage VBIAS2, and the voltage level of node nd256 can be pulled down and driven to the voltage level of ground voltage VSS. Resistor element 255_1 can be connected between node nd254 and the terminal for internal voltage VBB. The inverter 257 can output the detection signal DET by inverting and buffering the signal of the node nd256. The node nd254 can be supplied with the test current TI supplied by the test current generating circuit 115. The resistance element 255_2 can be connected between the node nd255 and the terminal for the ground voltage VSS. In a state where the voltages of the nodes nd254 and nd255 have been set to have the same voltage level, when the test current TI is supplied via the node nd254, the voltage level of the detected internal voltage VBB can be reduced according to the amount of the supplied test current TI. In the test mode, when the amount of the test current TI is sequentially changed and supplied, the internal voltage detection circuit 13A can perform a fine-tuning operation of sequentially adjusting the voltage level of the detected internal voltage VBB.

[0058] Figure 5 1 is a flowchart for describing the operation of the test mode being performed for adjusting the voltage level of the internal voltage VBB detected in the electronic device 1 . Figures 6 to 9 is a view for showing operations in the test mode being executed.

[0059] like Figure 5 As shown, the operation in the test mode may be performed in the order that the operation S101 of entering the test mode, the first fine adjustment operation S103, the second fine adjustment operation S105, the third fine adjustment operation S107, and the operation S109 of exiting the test mode are sequentially performed, and the operation is performed to adjust the voltage level of the detected internal voltage VBB. Figures 5 to 9 The first fine-tuning operation S103 , the second fine-tuning operation S105 , and the third fine-tuning operation S107 are described in detail.

[0060] like Figure 5 and Figure 6 As shown, the first fine-tuning operation S103 may be performed in the following manner: the voltage level of the second reference voltage VREF2 has been fixed to the first divided voltage VDIV <1> , and the voltage level of the third reference voltage VREF3 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the first reference voltage VREF1 is sequentially increased from the first divided voltage VDIV <1> Change to the Nth voltage divider VDIV <n>The test current TI is generated at the same time, and the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A is adjusted in response to the test current TI (S111 to S117). More specifically, the first fine-tuning operation S103 can be performed in a manner of repeating the following operations: when the voltage level of the second reference voltage VREF2 has been fixed to the first divided voltage VDIV <1> , and the voltage level of the third reference voltage VREF3 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the first reference voltage VREF1 is set (S111) to the first divided voltage VDIV <1> , thereby generating a test current TI, adjusting (S113) the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A in response to the test current TI, and then, the voltage level of the first reference voltage VREF1 is sequentially increased from the second divided voltage VDIV through operations S115 and S117. <2> Change to the Nth voltage divider VDIV <n>At the same time, the voltage level of the detected internal voltage VBB is adjusted (S113). The amount of the test current TI generated at this time can be adjusted by the first voltage V1, the second voltage V2, and the third voltage V3 set by the first reference voltage VREF1, the second reference voltage VREF2, and the third reference voltage VREF3 when the resistance elements 220 and 230 are equally set to have the resistance value R1. That is, because the first current I1 is generated as The second current I2 is generated as And TI = I1 + I2, so the test current TI can be generated as

[0061] like Figure 5 and Figure 7 As shown, when the test current TI is supplied to the node nd254 of the internal voltage detection circuit 13A, the voltage drops through the resistance value R2 of the resistance element 255_1. Accordingly, the change in the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A is proportional to the voltage level of the voltage dropped through the resistance element 255_1 (i.e., the product of the test current TI and the resistance value R2 of the resistance element 255_1). A first fine-tuning operation S103 of sequentially adjusting the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A can be performed in response to the test current TI, wherein the amount of the test current TI is sequentially changed from the first divided voltage VDIV to the first reference voltage VREF1. <1> Change to the Nth voltage divider VDIV <n>are changed sequentially.

[0062] like Figure 5 and Figure 8 As shown, the second fine-tuning operation S105 may be performed in the following manner: the voltage level of the first reference voltage VREF1 has been fixed to the first divided voltage VDIV <1> , and the voltage level of the third reference voltage VREF3 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the second reference voltage VREF2 is sequentially increased from the second divided voltage VDIV <2> Change to the Nth voltage divider VDIV <n>The test current TI is generated at the same time, and the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A is adjusted in response to the test current TI (S121 to S127). More specifically, the second fine-tuning operation S105 can be performed in a manner of repeating the following operations: when the voltage level of the first reference voltage VREF1 has been fixed to the first divided voltage VDIV <1> And the voltage level of the third reference voltage VREF3 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the second reference voltage VREF2 is set (S121) to the second divided voltage VDIV <2> , thereby generating a test current TI, adjusting (S123) the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A in response to the test current TI, and then, the voltage level of the second reference voltage VREF2 is sequentially increased from the third divided voltage VDIV through operations S125 and S127. <3> Change to the Nth voltage divider VDIV <n>At the same time, the voltage level of the detected internal voltage VBB is adjusted (S123). The test current TI generated at this time can be generated as

[0063] like Figure 5 and Fig. 9 As shown, the third fine-tuning operation S107 may be performed in the following manner: the voltage level of the first reference voltage VREF1 has been fixed to the first divided voltage VDIV <1> , and the voltage level of the second reference voltage VREF2 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the third reference voltage VREF3 is sequentially increased from the second divided voltage VDIV <2> Change to the Nth voltage divider VDIV <n>The test current TI is generated at the same time, and the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A is adjusted in response to the test current TI (S131 to S137). More specifically, the third fine-tuning operation S107 can be performed in a manner of repeating the following operations: when the voltage level of the first reference voltage VREF1 has been fixed to the first divided voltage VDIV <1> , and the voltage level of the second reference voltage VREF2 has been fixed to the first divided voltage VDIV <1> In the state, the voltage level of the third reference voltage VREF3 is set (S131) ​​to the second divided voltage VDIV <2> , generating a test current TI, adjusting (S133) the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13A in response to the test current TI, and then, the voltage level of the third reference voltage VREF3 is sequentially increased from the third divided voltage VDIV through operations S135 and S137 <3> Change to the Nth voltage divider VDIV <n>At the same time, the voltage level of the detected internal voltage VBB is adjusted (S133). The test current TI generated at this time can be set and generated as

[0064] By generating reference voltages VREF1, VREF2, and VREF3 (the voltage level of each of which can be adjusted to a variety of voltage levels), and supplying a test current TI (the amount of which is adjusted in response to the reference voltages VREF1, VREF2, and VREF3) to the internal voltage detection circuit 13, the above-mentioned electronic device 1 can easily adjust the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13. In addition, by adjusting the amount of the test current TI, the voltage level of the internal voltage VBB detected by the internal voltage detection circuit 13 is adjusted, and the electronic device 1 can also adjust the voltage level of the fine-tuning internal voltage VBB at a desired voltage level interval without adding a special circuit. The electronic device 1 has been described as generating the internal voltage VBB, but according to an embodiment, it can be applied to generate a variety of internal voltages, such as various core voltages VCORE and various boost voltages VPP.

[0065] A number of embodiments of the present disclosure have been described so far. It will be appreciated by those skilled in the art that the present invention may be implemented in a modified form without departing from the essential features of the present disclosure. Accordingly, the disclosed embodiments should be considered from a descriptive perspective rather than a restrictive perspective. The scope of the present disclosure is described in the claims rather than in the foregoing description, and all differences within the equivalent range thereof should be interpreted as being included in the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An electronic device, include: a test control circuit that generates test codes, each of which includes a plurality of binary digits, each of which causes the test control circuit to generate a corresponding reference voltage, the level of which is determined by the binary digits of the test code, and further generates a test current, the amount of which is determined by the reference voltage; and an internal voltage detection circuit, the internal voltage detection circuit generating a detection signal, the internal voltage detection circuit controlling the internal voltage in response to the test current and in response to detecting the internal voltage, Wherein, a voltage level of the internal voltage detected by the internal voltage detection circuit is adjusted in response to the test current.

2. The electronic device according to claim 1, in, The test control circuit receives a test mode enable signal and generates a test code when the test control circuit enters a test mode.

3. The electronic device according to claim 1, in: The test code includes a first test code and a second test code; The reference voltage includes a first reference voltage and a second reference voltage; and The test control circuit includes a test code generation circuit, which generates the first test code including binary digits, at least one of which has a value set to provide the first reference voltage; the test control circuit also generates the second test code including binary digits, at least one of which has a value set to adjust the second reference voltage.

4. The electronic device according to claim 3, in, The test code generation circuit sequentially adjusts the binary digits including the first test code to maintain values ​​of the binary digits including the second test code.

5. The electronic device according to claim 4, in, The test pattern generation circuit sequentially adjusts binary digits of the second test pattern to maintain the first test pattern.

6. The electronic device according to claim 1, in: The test code includes a first test code and a second test code; The reference voltage includes a first reference voltage and a second reference voltage; and The test control circuit includes a reference voltage selection circuit, and the reference voltage selection circuit adjusts the voltage level of the first reference voltage by receiving the first test code. The test control circuit also adjusts the voltage level of the second reference voltage by receiving the second test code.

7. The electronic device according to claim 6, in, The reference voltage selection circuit sequentially adjusts the voltage level of the first reference voltage in response to the first test code in a state in which the voltage level of the second reference voltage is maintained in response to the second test code.

8. The electronic device according to claim 7, in, The reference voltage selection circuit adjusts the voltage level of the second reference voltage in response to the second test code in a state in which the voltage level of the first reference voltage is maintained by the first test code.

9. The electronic device according to claim 6, in, The reference voltage selection circuit comprises: A voltage divider circuit, wherein the voltage divider circuit provides different “divided voltages” by dividing the voltage of an internal node; a first reference voltage output circuit, the first reference voltage output circuit: outputting the first divided voltage by selecting the first divided voltage as the first reference voltage in response to the first test code; and The second reference voltage output circuit outputs the second divided voltage by selecting the second divided voltage as the second reference voltage in response to the second test code.

10. The electronic device according to claim 1, in: The reference voltages include a first reference voltage, a second reference voltage and a third reference voltage; as well as The test control circuit includes a test current generating circuit that generates a test current corresponding to the first reference voltage, the second reference voltage, and the third reference voltage.

11. The electronic device according to claim 10, in, The test current generating circuit further includes: a voltage setting circuit that sets a first voltage in response to the first reference voltage; a first current setting circuit that adjusts a first current flowing through a first resistance element in response to the second reference voltage, the first resistance element being connected to an internal node and having the first voltage set in the internal node; and A second current setting circuit is provided for adjusting a second current flowing through a second resistance element in response to the third reference voltage, the second resistance element being connected to the internal node.

12. The electronic device according to claim 11, in, The test current generating circuit generates the test current whose current amount is a sum of an amount of the first current and an amount of the second current.

13. The electronic device according to claim 11, in, The voltage setting circuit comprises: a comparator that generates a comparison signal by comparing the voltage of the internal node with the first reference voltage; and A MOS transistor is configured to be conductive in response to the comparison signal and to set the first voltage.

14. The electronic device according to claim 11, in, The first current setting circuit comprises: a comparator that generates a comparison signal by comparing a second voltage determined by the first current with the second reference voltage; and A MOS transistor is turned on in response to the comparison signal and adjusts the first current.

15. The electronic device according to claim 11, in, The second current setting circuit comprises: a comparator that generates a comparison signal by comparing a third voltage with the third reference voltage, the voltage level of the third voltage being set in response to the second current; and A MOS transistor is turned on in response to the comparison signal and adjusts a current amount of the second current.

16. An electronic device, include: a test code generation circuit, wherein the test code generation circuit generates a first test code and a second test code when entering a test mode; a reference voltage selection circuit that generates a first reference voltage and a second reference voltage, the level of the first reference voltage and the level of the second reference voltage being adjusted in response to the first test code and the second test code, respectively; a test current generating circuit that generates a test current whose amount is adjusted in response to the first reference voltage and the second reference voltage; as well as An internal voltage detection circuit generates a detection signal for controlling an internal voltage in response to the test current.

17. The electronic device according to claim 16, in, A voltage level of the internal voltage detected by the internal voltage detection circuit is adjusted in response to the test current.

18. The electronic device according to claim 16, in, The test code generating circuit: adjusting the binary digits in the first test code; and Adjust the binary digits in the second test pattern.

19. The electronic device according to claim 16, in, The reference voltage selection circuit: adjusting a voltage level of the first reference voltage in response to a first test code, by which the voltage level of the second reference voltage is maintained; as well as The voltage level of the second reference voltage is adjusted in response to a second test code through which the first reference voltage is maintained.

20. The electronic device according to claim 16, in, The test current generating circuit comprises: a voltage setting circuit that sets a first voltage in response to the first reference voltage; and A current setting circuit adjusts the amount of a first current flowing through a first resistance element in response to the second reference voltage, the first resistance element being connected to an internal node in which the first voltage has been set.

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