Electronic device

Abstract

An electronic device is disclosed. The electronic device includes a first electronic component, a second electronic component, and a circuit structure. The circuit structure is supported by the first electronic component and the second electronic component. The circuit structure electrically connects the first electronic component to the second electronic component and is configured to provide power to the first electronic component and the second electronic component.

Description

Technical Field

[0001] The present disclosure generally relates to an electronic device. Background Art

[0002] For high performance computing (HPC) systems of electronic devices, power supply units with low power consumption and high heat dissipation are required. The power delivery path for transmitting power signals is usually provided by a system board on which several dies are mounted. The layout design may be limited by the need to minimize electromagnetic interference between power signals and non-power signals (e.g., electrical signals), which can limit the ability to miniaturize the system board.

[0003] The voltage and power requirements of the die vary, and the rapid increase in the total number and variety of dies has led to a corresponding increase in the number of power delivery paths. One approach to providing a more stable power delivery path is to provide power through an interconnect structure or power conditioning components on the interconnect die. However, this may increase the size of the electronic device and place further constraints on the level of miniaturization of the electronic device that can be achieved. Summary of the invention

[0004] In some embodiments, an electronic device includes a first electronic component, a second electronic component, and a circuit structure. The circuit structure is supported by the first electronic component and the second electronic component. The circuit structure electrically connects the first electronic component to the second electronic component and is configured to provide power to the first electronic component and the second electronic component.

[0005] In some embodiments, the electronic device includes a first electronic component, an interconnection circuit, and a second electronic component. The interconnection circuit is adjacent to the first electronic component. The second electronic component has a front surface for transmitting a non-power signal and a back surface for receiving a first power signal. The second electronic component is electrically connected to the first electronic component through the back surface of the second electronic component and the interconnection circuit.

[0006] In some embodiments, an electronic device includes a first electronic component and an integrated circuit. The first electronic component has a front surface and a back surface opposite to the front surface. The integrated circuit is configured to provide a power signal to the first electronic component through the back surface of the first electronic component, and is configured to bridge a non-power signal between the first electronic component and a second electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that the various structures may not be drawn to scale, and the sizes of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A A top view of an example electronic device is shown in accordance with some embodiments of the present disclosure.

[0009] Figure 1B The following are some examples according to the present disclosure: Figure 1A A cross-sectional view of the electronic device shown.

[0010] Figure 2 A cross-sectional view of an electronic assembly according to some embodiments of the present disclosure is shown.

[0011] Figure 3 A cross-sectional view of an electronic assembly according to some embodiments of the present disclosure is shown.

[0012] Figure 4 A cross-sectional view of an electronic device according to some embodiments of the present disclosure is shown.

[0013] Figure 5 A cross-sectional view of an electronic device according to some embodiments of the present disclosure is shown.

[0014] Figure 6 A top view of an example electronic device is shown in accordance with some embodiments of the present disclosure.

[0015] Figure 7 A cross-sectional view of an electronic device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0016] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components.The arrangements of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0017] The following disclosure provides many different arrangements or examples of different features of the provided themes. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. Of course, these components and arrangements are examples only and are not intended to be restrictive. For example, in the following description, a first feature is formed above or on a second feature, and an arrangement in which the first feature and the second feature are directly contacted or arranged may be included, and an arrangement in which an additional feature may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be directly contacted may also be included. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various arrangements and / or configurations discussed.

[0018] Figure 1A and Figure 1B An example electronic device 1a according to some embodiments of the present disclosure is shown, wherein Figure 1A is a top view, and Figure 1B It is along Figure 1A. In some embodiments, the electronic device 1a may include a computer system or may be part of a computer system. Depending on the intended use of the computer system, the electronic device 1a may be provided to meet different requirements. For example, the electronic device 1a may be implemented for data transmission, data processing, data management and maintenance, sensors, and other functions. In some embodiments, the electronic device 1a may include a carrier 10, electronic components 20-1, 20-2, 20-3, 20-3, 20-4, 20-5, and 20-6, a semiconductor die 30, and an encapsulation 40.

[0019] like Figure 1A As shown, semiconductor die 30 may include active components, such as ICs. In some embodiments, semiconductor die 30 may include power regulating circuits 32a-1, 32a-2, 32a-3, 32a-4, 32a-5, 32a-6, 32a-7, 32a-8, 32a-9, and 32a-10, and interconnection circuits 32b-1, 32b-2, 32b-3, 32b-4, 32b-5, 32b-6, and 32b-7. In some embodiments, power regulating circuits 32a-1, 32a-2, and 32a-3 and interconnection circuits 32b-1 and 32b-2 may be arranged alternately. For example, interconnection circuit 32b-1 may be disposed between power regulating circuits 32a-1 and 32a-2. In some embodiments, some of power regulating circuits 32a-1 to 32a-10 may cover only one of the chips. For example, the power conditioning circuit 32a-1 may cover the electronic component 20-1 and not overlap vertically with other electronic components 20-2 to 20-6. In some embodiments, some of the power conditioning circuits 32a-1 to 32a-10 may not overlap with the chip. For example, the power conditioning circuit 32a-9 may not overlap with the electronic components 20-1 to 20-6. In some embodiments, some of the power conditioning circuits 32a-1 to 32a-10 may be located in a relatively peripheral area or closer to the corner (or edge) of the semiconductor die 30. For example, the power conditioning circuits 32a-1, 32a-3, 32a-4, 32a-6, 32a-7 and 32a-8 are closer to the edge (or side) of the semiconductor die 30. In some embodiments, the power conditioning circuits 32a-1 to 32a-10 may have different sizes (e.g., areas). For example, the area of ​​the power conditioning circuit 32a-2 may be smaller than the area of ​​the power conditioning circuit 32a-1. The present disclosure does not limit the number of power conditioning circuits 32a-1 to 32a-10. In some embodiments, the number and size of power conditioning circuits 32a-1 to 32a-10 may be modified and / or controlled depending on design requirements.

[0020] Each of the interconnection circuits 32b-1 to 32b-7 may be spaced apart from the power conditioning circuits 32a-1 to 32a-10. In some embodiments, some of the interconnection circuits 32b-1 to 32b-7 may cover at least two electronic components (or chips). For example, the interconnection circuit 32b-1 may cover the electronic components 20-1 and 20-2; the interconnection circuit 32b-3 may cover the electronic components 20-1 and 20-4. In some embodiments, some of the interconnection circuits 32b-1 to 32b-7 may be positioned or disposed across a gap defined by two adjacent electronic components (or chips). For example, the interconnection circuit 32b-1 may be positioned across the gap G1 between the electronic components 20-1 and 20-2. In some embodiments, some of the interconnection circuits 32b-1 to 32b-7 may be located at a corner (or edge) of the semiconductor die 30 relative to the center area or further away. In some embodiments, each of the interconnection circuits 32b-1 to 32b-7 may be arranged between two or three or more power conditioning circuits 32a-1 to 32a-10. In some embodiments, some of the power conditioning circuits 32a-1 to 32a-10 may be surrounded by some of the interconnection circuits 32b-1 to 32b-7. For example, the power conditioning circuit 32a-9 may be surrounded by interconnection circuits 32b-1, 32b-3, 32b-4, and 32b-6. In some embodiments, the interconnection circuits 32b-1 to 32b-7 may have different sizes (e.g., areas). For example, the area of ​​the interconnection circuit 32b-1 may be smaller than the area of ​​the interconnection circuit 32b-3. The present disclosure does not limit the number of interconnection circuits. In some embodiments, the number and size of the interconnection circuits 32b-1 to 32b-7 may be modified and / or controlled depending on design requirements.

[0021] like Figure 1BAs shown, the carrier 10 may be configured to support electronic components (or chips) 20-1, 20-2 and 20-3 and a semiconductor die 30. The carrier 10 may include a system board, a main board, a main printed circuit board (PCB) or other suitable carriers. The carrier 10 may include an interconnect structure, such as a redistribution layer (RDL), a circuit layer, a conductive trace, a conductive via, etc. The interconnect structure may provide a signal path for other components electrically connected to the carrier 10. For example, the carrier 10 may facilitate and allow communication between components mounted thereon. In some embodiments, the carrier 10 may receive and / or transmit non-power signals (e.g., I / O signals) from the electronic components 20-1, 20-2 and / or 20-3. In some embodiments, the carrier 10 may receive and / or transmit power signals toward the electronic components 20-1, 20-2 and / or 20-3. The carrier 10 may have a surface 10s1 (or a lower surface) and a surface 10s2 (or an upper surface) opposite to the surface 10s1. In some embodiments, the carrier 10 may include a circuit (not shown) configured to provide a power path and transmit power through the surface 10s2. In the present disclosure, the power path may refer to a physical structure through which a signal passes, or may refer to the direction of a signal flow.

[0022] The electronic device 1a may include an electrical connector 12. The electrical connector 12 may be disposed on or below the surface 10s1 of the carrier 10. The electrical connector 12 may be electrically connected to an external device (not shown). The electrical connector 12 may include solder balls, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGA), land grid arrays (LGA), etc. The electrical connector 12 may include a solder material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials.

[0023] Each of the electronic components 20-1, 20-2 and 20-3 may be disposed on or above the surface 10s2 of the carrier 10. Each of the electronic components 20-1, 20-2 and 20-3 may include a chip. In some arrangements, each of the electronic components 20-1, 20-2 and 20-3 may include an active component that relies on an external power supply to control, output or modify an electrical signal. For example, the electronic components 20-1, 20-2 and 20-3 may each include a processor, a controller, a memory or an input / output (I / O) buffer, etc. Each of the electronic components 20-1, 20-2 and 20-3 may include a system on chip (SoC), a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), a microcontroller unit (MCU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or another type of integrated circuit. Each of the electronic components 20-1, 20-2, and 20-3 may include a lower surface and an upper surface. For example, the electronic component 20-1 may include a surface 20-1s1 (or a lower surface or a front surface) and a surface 20-1s2 (or an upper surface or a backside surface). The electronic component 20-2 may include a surface 20-2s1 (or a lower surface or a front surface) and a surface 20-2s2 (or an upper surface or a backside surface). In some embodiments, the front surfaces of the electronic components 20-1, 20-2, and 20-3 may be configured to transmit input / output (I / O) signals, which may include or include alternating current (AC). In some embodiments, the backside surfaces of the electronic components 20-1, 20-2, and 20-3 may be configured to receive power, which may include or include direct current (DC). In some embodiments, the backside surfaces of electronic components 20-1, 20-2, and 20-3 may be configured to transmit and / or receive signals in communications between and / or among chips, which signals may include or include AC. Figure 1BAlthough not shown and described in the drawings, the positions, structures and functions of the electronic components 20-4, 20-5 and 20-6 may be the same or similar to those of the electronic component 20-1. Each of the electronic components 20-1, 20-2 and 20-3 may have terminals on the front surface and the back surface, which will be Figure 2 and Figure 3 Detailed description in.

[0024] In some embodiments, the semiconductor die 30 may be disposed on or above the backside surface of the electronic components 20-1, 20-2, and 20-3. For example, the semiconductor die 30 may be disposed on or above the surface 20-1s2 of the electronic component 20-1. In some embodiments, the semiconductor die 30 may be connected to the electronic components 20-1 to 20-3 by solder bonding, conductive pillars (e.g., copper pillars), or a combination thereof. In some embodiments, the semiconductor die 30 may include a circuit structure configured to transmit and / or receive power signals and / or non-power signals. In some embodiments, the semiconductor die 30 may serve as an insert included in a signal path or a power path. In some embodiments, the semiconductor die 30 may be configured to provide power to the electronic components 20-1, 20-2, and 20-3. In some embodiments, the semiconductor die 30 may be configured to electrically connect the electronic components 20-1, 20-2, and / or 20-3. The semiconductor die 30 may include a surface 30s1 (or a lower surface or a front surface), a surface 30s2 (or an upper surface of the backside surface) opposite to the surface 30s1, and a surface 30s3 (or a lateral surface) extending between the surface 30s1 and the surface 30s2. In some embodiments, the surface 30s1 of the semiconductor die 30 may be configured to transmit power to the electronic components 20-1, 20-2, and 20-3. In some embodiments, the surface 30s1 of the semiconductor die 30 may be configured to transmit signals in communication between or among the electronic components 20-1, 20-2, and / or 20-3.

[0025] In some embodiments, the semiconductor die 30 may include a semiconductor substrate, which may include silicon, germanium or other suitable materials. In some embodiments, the semiconductor die 30 may include a circuit region 32 and a rigid region 34. In some embodiments, the circuit region 32 is closer to the surface 30s1 of the semiconductor die 30 than the rigid region 34. The circuit region 32 may include power conditioning circuits 32a-1, 32a-2 and 32a-3. Each of the power conditioning circuits 32a-1, 32a-2 and 32a-3 may be configured to transmit regulated power to the electronic components 20-1, 20-2 and / or 20-3. In some embodiments, the power conditioning circuits 32a-1, 32a-2 and 32a-3 may include passive devices, such as capacitor structures (e.g., deep trench capacitors), inductors, resistors, filters or combinations thereof. The power conditioning circuits 32a-1, 32a-2 and 32a-3 may be circuits or circuit elements that do not provide electrical gain. In some embodiments, the power conditioning circuit 32a-1 may be located directly above the electronic component 20-1, which may reduce the transmission path of the power. Therefore, the voltage drop or power loss of the power path may be reduced. Figure 1B Although not shown and described, the structures and functions of the power conditioning circuits 32a-4 to 32a-10 may be the same as or similar to those of the power conditioning circuit 32a-1.

[0026] Circuit area 32 may include interconnect circuits 32b-1 and 32b-2. Each of interconnect circuits 32b-1 and 32b-2 may be configured to transmit a signal from one electronic component (or chip) to another electronic component (or chip). For example, interconnect circuit 32b-1 may receive a signal from electronic component 20-1 and transmit the signal to electronic component 20-2. For example, interconnect circuit 32b-1 may bridge a signal (non-power signal) between electronic components 20-1 and 20-2. Although Figure 1B Although not shown and described, the structures and functions of the interconnection circuits 32b-3 to 32b-7 may be the same as or similar to those of the interconnection circuit 32b-1.

[0027] In some embodiments, the rigid region 34 is closer to the surface 30s2 than the circuit region 32. In some embodiments, the rigid region 34 may be configured to support the circuit region 32. In some embodiments, the rigid region 34 may be more robust than the circuit region 32 because the structure of the semiconductor substrate of the rigid region 34 is less damaged than the circuit region 32. In some embodiments, the rigidity of the rigid region 34 may be greater than the rigidity of the circuit region 32. In some embodiments, the ratio of silicon (or components of the semiconductor substrate of the semiconductor die 30, such as semiconductor materials) of the rigid region 34 may be greater than the ratio of silicon of the circuit region 32. In some embodiments, the density of conductive elements (e.g., conductive layers, conductive traces, conductive pads, and / or conductive vias) of the rigid region 34 is less than the density of conductive elements (e.g., conductive layers, conductive traces, conductive pads, and / or conductive vias) of the circuit region 32. In some embodiments, no conductive elements (e.g., conductive layers, conductive traces, conductive pads, and / or conductive vias) are formed in the rigid region 34. In some embodiments, the thickness of the rigid region 34 may be greater than, equal to, or less than the thickness of the circuit region 32.

[0028] In some embodiments, the encapsulant 40 may be disposed on or above the surface 10s2 of the carrier 10. In some embodiments, the encapsulant 40 may encapsulate the electronic components 20-1, 20-2, and 20-3. In some embodiments, the encapsulant 40 may encapsulate the semiconductor die 30. In some embodiments, the encapsulant 40 may contact the surface 30s3 of the semiconductor die 30. The encapsulant 40 may have a surface 40s1 (or upper surface) spaced apart from the carrier 10. In some embodiments, the surface 40s1 of the encapsulant 40 may be substantially coplanar or aligned with the surface 30s2 of the semiconductor die 30. The encapsulant 40 may include an insulating material or a dielectric material. In some embodiments, the encapsulant 40 may be made of a molding material or molding compound, which may include, for example, a phenolic resin, an epoxy resin, a silicon-based resin, or another suitable encapsulant. A suitable filler may also be included, such as powdered SiO2.

[0029] like Figure 1B As shown, semiconductor die 30 may be configured to provide path P1. Path P1 may be a non-power path. In some embodiments, path P1 may pass through the backside surfaces of electronic components 20-1 to 20-6 and interconnect circuits 32b-1 to 32b-7. For example, path P1 may pass through surface 20-1s2 of electronic component 20-1, interconnect circuit 32b-1, and surface 20-2s2 of electronic component 20-2.

[0030] The semiconductor die 30 may be configured to provide a path P2. Path P2 may be a power path. In some embodiments, path P2 may pass through the backside surface of the electronic components 20-1 to 20-6 and the power conditioning circuits 32a-1 to 32a-10. For example, path P2 may pass through the power conditioning circuit 32a-1, the surface 30s1 of the semiconductor die 30, and the surface 20-1s2 of the electronic component 20-1. The semiconductor die 30 may be configured to provide a path P2'. Path P2' may be a power path. In some embodiments, path P2' may pass through the backside surface of the electronic components 20-1 to 20-6 and the power conditioning circuits 32a-1 to 32a-10. For example, path P2' may pass through the power conditioning circuit 32a-2, the surface 30s1 of the semiconductor die 30, and the surface 20-2s2 of the electronic component 20-2. In some embodiments, the power of path P2 may be the same as the power of path P2'. In some embodiments, the power of path P2 may be different from the power of path P2'.

[0031] Each of the electronic components 20 - 1 , 20 - 2 , and 20 - 3 may be configured to provide a path P3 . The path P3 may include a non-power path, such as an I / O signal path . For example, the path P3 may pass through the surface 20 - 1 s1 of the electronic component 20 - 1 and the surface 10 s2 of the carrier 10 .

[0032] In a comparative example, the power conditioning circuit (or component) is mounted on a power board or on an interconnection die. Such a design may increase the size (e.g., thickness) of the electronic device and increase the transmission path of the power path. In this embodiment, the power conditioning circuit and the interconnection circuit are integrated in the semiconductor die, which may reduce the size (e.g., thickness) of the electronic device. In addition, the power path may also be reduced to reduce voltage drop and / or power loss.

[0033] Figure 2 20 - 1 according to some embodiments of the present disclosure. Figure 2 The electronic assembly 20-1 shown in FIG. 1 can be applied to Figure 1A and 1B Electronic components 20-1 to 20-6 are shown.

[0034] In some embodiments, the electronic component 20-1 may have an integrated circuit layer 22 (or IC layer) within the substrate of the electronic component 20-1. In some embodiments, the IC layer 22 may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. For example, the IC layer 22 may include an application specific IC (ASIC), a radio frequency integrated circuit (RFIC), a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a field programmable gate array (FPGA), or another type of IC. In some embodiments, the IC layer 22 may be configured to receive power through the path P2, such as Figure 1B In some embodiments, IC layer 22 may be configured to receive and / or transmit signals passing through path P1, such as Figure 1B In some embodiments, IC layer 22 may be configured to receive and / or transmit I / O signals passing through path P3, such as Figure 1B shown.

[0035] In some embodiments, electronic component 20-1 may include redistribution structures 24a, 24b, and 24c. Each of redistribution structures 24a, 24b, and 24c includes conductive traces, conductive pads, and / or conductive vias embedded in or disposed on a dielectric layer.

[0036] The redistribution structure 24a may be disposed between the surface 20-1s1 and the IC layer 22. The redistribution structure 24a may be adjacent to the surface 20-1s1 of the electronic component 20-1. The redistribution structure 24a may be configured to receive and / or transmit I / O signals passing through the path P3, such as Figure 1B As shown. The redistribution structure 24b may be disposed between the surface 20-1s2 and the IC layer 22. The redistribution structure 24b may be adjacent to the surface 20-1s2 of the electronic component 20-1. The redistribution structure 24b may be configured to receive power passing through the path P2, such as Figure 1B As shown. The redistribution structure 24c may be disposed between the surface 20-1s2 and the IC layer 22. The redistribution structure 24c may be adjacent to the surface 20-1s2 of the electronic component 20-1. The redistribution structure 24c may be configured to receive and / or transmit a signal (eg, a non-power signal) passing through the path P1, such as Figure 1B As shown. Figure 2 Although not shown, the electronic component 20 - 1 may include redistribution structures between the IC layer 22 and the redistribution structure 24 a and between the IC layer 22 and the redistribution structure 24 b .

[0037] In some embodiments, the redistribution structures 24a, 24b, and 24c may have different sizes. In some embodiments, the line width / line space (L / S) of the redistribution structure 24c may be smaller than the line width / line space of the redistribution structure 24a. For example, the size (e.g., width, diameter, and / or surface area) of the conductive layer, conductive trace, conductive pad, and / or conductive via of the redistribution structure 24c may be smaller than the size of the conductive layer, conductive trace, conductive pad, and / or conductive via of the redistribution structure 24a. In some embodiments, the L / S of the redistribution structure 24a may be smaller than the L / S of the redistribution structure 24b. For example, the size (e.g., width, diameter, and / or surface area) of the conductive layer, conductive trace, conductive pad, and / or conductive via of the redistribution structure 24a may be smaller than the size of the conductive layer, conductive trace, conductive pad, and / or conductive via of the redistribution structure 24b.

[0038] In some embodiments, redistribution structures 24a, 24b, and 24c may have different densities (e.g., the number of conductive elements per unit area). In some embodiments, the density of redistribution structure 24c may be greater than the density of redistribution structure 24a. For example, the conductive layers, conductive traces, conductive pads, and / or conductive vias of redistribution structure 24c may have a density greater than the density of the conductive layers, conductive traces, conductive pads, and / or conductive vias of redistribution structure 24a. In some embodiments, the density of redistribution structure 24a may be greater than the density of redistribution structure 24b. For example, the conductive layers, conductive traces, conductive pads, and / or conductive vias of redistribution structure 24a may have a density greater than the density of the conductive layers, conductive traces, conductive pads, and / or conductive vias of redistribution structure 24b.

[0039] In some embodiments, the electronic component 20-1 may include terminals 26a, 26b, and 26c. In some embodiments, the terminal 26a may be disposed on or below the surface 20-1s1 of the electronic component 20-1 and electrically connected to the redistribution structure 24a. The terminal 26a may be electrically connected to the carrier 10, such as Figure 1B In some embodiments, the terminal 26b may be disposed on or above the surface 20-1s2 of the electronic component 20-1 and electrically connected to the redistribution structure 24b. The terminal 26b may be electrically connected to, for example, Figure 1B In some embodiments, the terminal 26c may be disposed on or above the surface 20-1s2 of the electronic component 20-1 and electrically connected to the redistribution structure 24c. The terminal 26c may be electrically connected to, for example, Figure 1B The interconnection circuit 32b-1 is shown. In some embodiments, the terminals 26a, 26b, and 26c may have the same size. In other embodiments, based on design requirements, the terminals 26a, 26b, and 26c may have different sizes.

[0040] In some embodiments, the density of terminals 26a, 26b and 26c may be proportional to the density of redistribution structures 24, 24b and 24c, respectively. In some embodiments, terminals 26a, 26b and 26c may have different densities. In some embodiments, the density of terminal 26c may be greater than the density of terminal 26a. In some embodiments, the density of terminal 26a may be greater than the density of terminal 26b. In some embodiments, the density of terminal 26c may be greater than the density of terminal 26b. In some embodiments, terminals 26a, 26b and 26c may have different spacings. In some embodiments, the spacing of terminal 26c may be less than the spacing of terminal 26a. In some embodiments, the spacing of terminal 26a may be less than the spacing of terminal 26b.

[0041] Since power transmission and signal transmission have different requirements in terms of electrical properties (eg, capacitance, data transmission speed, etc.), such a design can optimize the transmission efficiency of power and signals, thereby improving the performance of the electronic device 1a.

[0042] Figure 3 A cross-sectional view of an electronic component 20 - 1 ′ according to some embodiments of the present disclosure is shown. The electronic component 20 - 1 ′ may be similar to the electronic component 20 - 1 , with the following differences therebetween.

[0043] In some embodiments, the electronic component 20-1' may include a redistribution structure 24b'. The redistribution structure 24b' may be disposed between the surface 20-1s2 and the IC layer 22. The redistribution structure 24b' may be adjacent to the surface 20-1s2 of the electronic component 20-1'. The redistribution structure 24b' may be configured to receive power passing through the path P2, such as Figure 1B shown.

[0044] In some embodiments, the L / S of the redistribution structure 24b' may be substantially equal to the L / S of the redistribution structure 24c. For example, the dimensions (e.g., width, diameter, and / or surface area) of the conductive layers, conductive traces, conductive pads, and / or conductive vias of the redistribution structure 24b' may be substantially equal to the dimensions of the conductive layers, conductive traces, conductive pads, and / or conductive vias of the redistribution structure 24c. In some embodiments, the L / S of the redistribution structure 24b' may be smaller than the L / S of the redistribution structure 24a. For example, the dimensions (e.g., width, diameter, and / or surface area) of the conductive layers, conductive traces, conductive pads, and / or conductive vias of the redistribution structure 24b' may be smaller than the dimensions of the conductive layers, conductive traces, conductive pads, and / or conductive vias of the redistribution structure 24a.

[0045] In some embodiments, the electronic component 20-1' may include a terminal 26b'. In some embodiments, the terminal 26b' may be disposed on or above the surface 20-1s2 of the electronic component 20-1' and electrically connected to the redistribution structure 24b'. The terminal 26b' may be electrically connected to, for example, Figure 1B The power conditioning circuit 32a-1 shown. In some embodiments, the density of terminals 26b' may be substantially equal to the density of terminals 26c. In some embodiments, the density of terminals 26b' may be greater than the density of terminals 26a. In some embodiments, the spacing of terminals 26b' may be substantially equal to the spacing of terminals 26c. In some embodiments, the spacing of terminals 26b' may be less than the spacing of terminals 26a.

[0046] Such a design may improve the yield of manufacturing electronic component 20 - 1 (and electronic components 20 - 2 through 20 - 5 ) and reduce manufacturing costs.

[0047] Figure 4 A cross-sectional view of an electronic device 1b according to some embodiments of the present disclosure is shown. The electronic device 1b may be similar to the electronic device 1a, with the following differences therebetween.

[0048] In some embodiments, the electronic device 1 b may include an electrical connector 52 , a cable 54 , a power conditioning element 56 , and a heat dissipation element 60 .

[0049] The electrical connector 52 may be disposed on or above the surface 30s2 of the semiconductor die 30. In some embodiments, a power supply unit (not shown) such as an alternating current (AC) to direct current (DC) (AC / DC) converter and a DC to DC (DC / DC) converter may be configured to provide power to the electrical connector 52 via the cable 54.

[0050] The cable 54 may include an Ethernet cable, a flexible flat cable (FFC), an insulated wire with a protective housing, or another suitable wired connection. In some embodiments, a flexible printed circuit (FPC) may be used instead of the cable 54 to provide power. The cable 54 may have one end connected to the power supply unit and the other end connected to the electrical connector 52. In other embodiments, the cable 54 may be replaced by other suitable elements, such as wires (e.g., bonding wires).

[0051] In some embodiments, the power conditioning element 56 may be disposed on or above the surface 30s2 of the semiconductor die 30. The power conditioning element 56 may be electrically connected to the semiconductor die 30 using flip chip or wire bonding technology. In some embodiments, the power conditioning element 56 may include a power management integrated circuit (PMIC). In some embodiments, the power conditioning element 56 may include a voltage regulator, such as a linear regulator (which is configured to maintain a constant output voltage) or a switching regulator (which is configured to generate an output voltage higher or lower than the input voltage). In some embodiments, the power conditioning element 56 may include a step-down (buck) converter, a step-up (boost) converter, an analog / digital converter, a digital / analog converter, an AC / DC converter, a DC / DC converter, other types of converters, or a combination thereof. In some embodiments, the power conditioning element 56 may receive input power from the electrical connector 52, regulate the input power, and in turn provide the regulated power (which may range between about 0.6 and 1.0 volts) to the electronic components 20-1, 20-2, and 20-3 through the power conditioning circuits 32a-1, 32a-2, and 32a-3.

[0052] In some embodiments, semiconductor die 30 may include conductive structures 36. In some embodiments, conductive structures 36 may extend between power conditioning element 56 and power conditioning circuit 32a-1 (or 32a-2 or 32a-3). In some embodiments, conductive structures 36 may be configured to electrically connect power conditioning element 56 and power conditioning circuit 32a-1 (or 32a-2 or 32a-3). In some embodiments, conductive structures 36 may be disposed within rigid region 34, such as Figure 1B In some embodiments, conductive structure 36 may be configured to receive and / or transmit power regulated by power conditioning element 56. In some embodiments, conductive structure 36 may include at least one conductive via, a redistribution structure, or other suitable element.

[0053] In some embodiments, the power conditioning element 56 may partially overlap vertically with the power conditioning circuit 32a-1 (or 32a-2 or 32a-3), thereby reducing the transmission path of the power. In some embodiments, the power conditioning element 56 may partially overlap vertically with the electronic component 20-1 (or 20-2 or 20-3), thereby reducing the transmission path of the power.

[0054] In some embodiments, path P4 (e.g., power path) may pass through cable 54, electrical connector 52, power conditioning element 56, conductive structure 36, power conditioning circuit 32a-1 (or 32a-2 or 32a-3), and electronic component 20-1 (or 20-2 or 20-3). In some embodiments, regulated power regulated by power conditioning element 56 may enter semiconductor die 30 from surface 30s2. Such an arrangement may facilitate power transmission, and communication between chips (e.g., electronic components 20-1 and 20-2) may not be disturbed by power transmission.

[0055] In some embodiments, the heat dissipation element 60 may be disposed on or above the surface 30s2 of the semiconductor die 30. The heat dissipation element 60 may at least partially overlap with the electronic component 20-1 (or 20-2 or 20-3) in a direction substantially perpendicular to the surface 30s2 of the semiconductor die 30. The heat dissipation element 60 may include a heat sink extending from a base portion along a direction substantially perpendicular to the surface 30s2 of the semiconductor die 30, such as a heat dissipation fin as shown. The heat dissipation element 60 may be configured to facilitate heat dissipation from at least one of the electronic components 20-1 to 20-3 to an external space of the electronic device 1b.

[0056] Figure 5 A cross-sectional view of an electronic device 1c according to some embodiments of the present disclosure is shown. The electronic device 1c may be similar to the electronic device 1b, with the following differences therebetween.

[0057] In some embodiments, the electronic device 1c may include a power conditioning element 62 and a conductive structure 64. In some embodiments, the power conditioning element 62 may be disposed on or above the surface 10s2 of the carrier 10. In some embodiments, the power conditioning element 62 may be encapsulated by an encapsulant 40. The power conditioning element 62 may be electrically connected to the carrier 10 using a flip chip or wire bonding technique. In some embodiments, the power conditioning element 62 may include a PMIC. In some embodiments, the power conditioning element 62 may include a voltage regulator, such as a linear regulator (which is configured to maintain a constant output voltage) or a switching regulator (which is configured to generate an output voltage higher or lower than an input voltage). In some embodiments, the power conditioning element 62 may include a step-down (buck) converter, a step-up (boost) converter, an analog / digital converter, a digital / analog converter, an AC / DC converter, a DC / DC converter, other types of converters, or a combination thereof. In some embodiments, the power conditioning element 62 may receive input power from the carrier 10, condition the input power, and provide the regulated power (which may range between about 0.6 and 1.0 volts) to the electronic components 20-1, 20-2, and 20-3 through the power conditioning circuits 32a-1, 32a-2, and 32a-3. In this embodiment, the semiconductor die 30 is located above the electronic component 20-1 and has an edge (e.g., surface 30s3) that exceeds the lateral surface of the electronic component 20-1. Therefore, the carrier 10 may provide space for arranging additional power conditioning elements (e.g., 62) below the semiconductor die 30. In addition, the additional power conditioning elements (e.g., 62) may be stacked along the Z direction defined as the direction from the surface 10s1 toward the surface 10s2. Therefore, the size of the electronic device 1c along the XY plane defined as a plane parallel to the surface 10s2 may be reduced.

[0058] In some embodiments, the conductive structure 64 may extend between the surface 30s1 of the semiconductor die 30 and the surface 10s2 of the carrier 10. In some embodiments, the conductive structure 64 may be encapsulated by the encapsulation 40. The conductive structure 64 may be electrically connected to the power conditioning element 62. The conductive structure 64 may be electrically connected to the power conditioning circuit 32a-1 (or 32a-2 or 32a-3). In some embodiments, the conductive structure 64 may include a conductive pillar or other suitable component.

[0059] In some embodiments, path P5 (e.g., power path) may pass through power conditioning element 62, conductive structure 64, power conditioning circuit 32a-1 (or 32a-2 or 32a-3), and electronic component 20-1 (or 20-2 or 20-3). In some embodiments, regulated power regulated by power conditioning element 62 may enter semiconductor die 30 from surface 30s1. This arrangement may utilize the remaining space not occupied by electronic components 20-1, 20-2, and 20-3, which may reduce the size (e.g., thickness) of electronic device 1c.

[0060] Figure 6 A top view of an example electronic device 1d according to some embodiments of the present disclosure is shown. The electronic device 1d may be similar to the electronic device 1a, with the following differences.

[0061] In some embodiments, the semiconductor die 30 may include a data storage circuit 38. The data storage circuit 38 may include a non-temporary memory or a non-volatile memory (e.g., a flash memory and a read-only memory (ROM)) or a volatile memory (e.g., a dynamic random access memory (DRAM)). In some embodiments, the data storage circuit 38 may include a high bandwidth memory (HBM). In some embodiments, the data storage circuit 38 may be configured to be accessed by the electronic components 20-1 to 20-6. In some embodiments, the data storage circuit 38 may be electrically connected to the electronic components 20-1 to 20-6. The data storage circuit 38 may be configured to support data storage and retrieval operations on the electronic components 20-1 to 20-6. The number of data storage circuits 38 may be determined based on budgets such as power, cost, heat, and / or capacity. In some embodiments, the data storage circuit 38 may also include a memory controller to manage access to the memory IC and provide memory management and maintenance. In such embodiments, the data storage circuit 38 may be integrated within the semiconductor die 30, thereby reducing the size of the electronic device 1d.

[0062] Figure 7 A cross-sectional view of an electronic device 1e according to some embodiments of the present disclosure is shown. The electronic device 1e may be similar to the electronic device 1a, with the following differences therebetween.

[0063] In some embodiments, the electronic device 1e may include electronic components 72-1, 72-2, and 72-3 and electronic components 74-1 and 74-2. Each of the electronic components 72-1, 72-2, and 72-3 may be disposed above the electronic components 20-1, 20-2, and / or 20-3. In some embodiments, the electronic components 72-1, 72-2, and 72-3 may be connected to the electronic components 20-1 to 20-3 by surface mount technology (SMT). In some embodiments, the electronic components 72-1, 72-2, and 72-3 may be connected to the electronic components 20-1 to 20-3 by solder bonding, hybrid bonding involving bonding between metals (e.g., copper to copper). Each of the electronic components 72-1, 72-2, and 72-3 may include a semiconductor die including a circuit structure. Each of the electronic components 72-1, 72-2, and 72-3 may include a power conditioning circuit, a capacitor, an inductor, or other suitable circuits. Each of the electronic components 72-1, 72-2, and 72-3 may act as an insert included in the power path. In some embodiments, the electronic components 72-1, 72-2, and 72-3 may be configured to provide regulated power to the electronic components 20-1, 20-2, and 20-3. In some embodiments, the electronic components 72-1, 72-2, and 72-3 may be configured to electrically connect the electronic components 20-1, 20-2, and / or 20-3. The electronic component 72-1 may include a surface 72-1s1 (or a lower surface or a front surface). In some embodiments, the surface 72-1s1 of the electronic component 72-1 may be configured to transmit power (or a power signal) to the electronic component 20-1.

[0064] Each of the electronic components 74-1 and 74-2 may be disposed above the electronic components 20-1, 20-2, and / or 20-3. Each of the electronic components 74-1 and 74-2 may include a semiconductor die. Each of the electronic components 74-1 and 74-2 may act as an insert included in a signal path. Each of the electronic components 74-1 and 74-2 may include a bridge die or an interconnect circuit. In some embodiments, the electronic components 74-1 and 74-2 may be configured to provide non-power signals to the electronic components 20-1, 20-2, and 20-3. In some embodiments, the electronic components 74-1 and 74-2 may be configured to electrically connect the electronic components 20-1, 20-2, and / or 20-3. The electronic component 74-1 may include a surface 74-1s1 (or a lower surface or a front surface). In some embodiments, the surface 74-1s1 of the electronic component 74-1 may be configured to transmit non-power signals between the electronic components 20-1 and 20-2.

[0065] In some embodiments, the electronic device 1e may include an encapsulation 80. The encapsulation 80 may encapsulate the electronic components 72-1, 72-2, and 72-3 and the electronic components 74-1 and 74-2. For example, the upper surfaces and lateral surfaces (not labeled) of the electronic components 72-1, 72-2, and 72-3 and the electronic components 74-1 and 74-2 may be covered by the encapsulation 80. The encapsulation 80 may include a surface 80s1 (or a lower surface), a surface 80s2 (or an upper surface), and a surface 80s3 (or a lateral surface). The surface 80s1 of the encapsulation 80 may be covered by the encapsulation 40. The surface 80s3 of the encapsulation 80 may be covered by the encapsulation 40. The surface 80s2 of the encapsulation 80 may be substantially aligned with the surface 40s1 of the encapsulation 40. The encapsulation 80 may include an insulating material or a dielectric material. In some embodiments, the encapsulant 80 may be made of a molding material that may include, for example, a phenolic resin, an epoxy resin, a silicone resin, or another suitable encapsulant. A suitable filler, such as powdered SiO2, may also be included. In this embodiment, the encapsulant 80 above the electronic components 72-1 to 72-3 and the electronic components 74-1 and 74-2 may serve as a rigid region configured to support the electronic components 72-1 to 72-3 and the electronic components 74-1 and 74-2.

[0066] Electronic component 74-1 (or 74-2) may be configured to provide path P6. Path P6 may be a non-power path. In some embodiments, path P6 may pass through the backside surface of electronic components 20-1 to 20-6. In some embodiments, path P6 may pass through the front surface of electronic components 74-1 and 74-2. For example, path P6 may pass through surface 74-1s1 of electronic component 74-1.

[0067] Electronic components 72-1, 72-2, and 72-3 may be configured to provide path P7. Path P7 may be a power path. In some embodiments, path P7 may pass through the backside surface of electronic components 20-1 to 20-6. In some embodiments, path P7 may pass through the front surface of electronic components 72-1, 72-2, and 72-3. For example, path P7 may pass through surface 72-1s1 of electronic component 72-1.

[0068] Unless otherwise specified, spatial descriptions such as "above", "below", "upper", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the arrangements disclosed herein are not deviated by such arrangements.

[0069] As used herein, the terms "substantially," "substantially," and "approximately" are used to describe and take into account minor variations. When used in conjunction with an event or situation, the terms may refer to situations in which the event or situation clearly occurs as well as situations in which the event or situation is very close to occurring. For example, when used in conjunction with a numerical value, the term may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average value of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​may be considered to be "substantially" the same or equal.

[0070] Two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0071] As used herein, the singular terms "a," "an," and "the" may include plural references unless the context clearly dictates otherwise.

[0072] As used herein, the terms "conductive", "electrically conductive" and "conductivity" refer to the ability to transmit an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Generally, conductive materials are materials having a conductivity greater than about 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6 The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0073] In addition, sometimes amounts, ratios and other numerical values ​​are presented in range format herein. It should be understood that such range format is for convenience and brevity, and should be flexibly understood to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0074] Although the present disclosure has been described and illustrated with reference to a specific arrangement of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other arrangements of the present disclosure that are not specifically described. This specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. An electronic device comprising: a first electronic component; a second electronic component; as well as A circuit structure is supported by the first electronic component and the second electronic component, wherein the circuit structure electrically connects the first electronic component to the second electronic component and is configured to provide power to the first electronic component and the second electronic component. 2 . The electronic device according to claim 1 , wherein the power passes through a backside surface of the first electronic component. 3 . The electronic device of claim 1 , wherein the circuit structure comprises a first power conditioning circuit configured to provide a first power to the first electronic component. 4 . The electronic device of claim 3 , wherein the circuit structure includes an interconnect circuit different from the first power conditioning circuit, wherein the interconnect circuit electrically connects the first electronic component to the second electronic component. 5 . The electronic device of claim 4 , wherein the circuit structure comprises a second power regulating circuit separated from the first power regulating circuit by the interconnect circuit, wherein the second power regulating circuit is configured to provide a second power to the second electronic component. The electronic device of claim 4 , wherein the interconnect circuit is not connected to the first power conditioning circuit. 7 . The electronic device of claim 3 , wherein the circuit structure comprises a rigid region supporting the first power conditioning circuit, and the first power conditioning circuit is disposed between the first electronic component and the rigid region. 8 . The electronic device of claim 7 , wherein the circuit structure includes an interconnect circuit that is closer to the first electronic component than the rigid region, and the interconnect circuit electrically connects the first electronic component to the second electronic component.

9. The electronic device of claim 7, wherein the circuit structure includes a power path passing through the rigid region and the first power conditioning circuit.

10. The electronic device according to claim 7, further comprising: A heat dissipation element is supported by the circuit structure.

11. An electronic device comprising: a first electronic component; an interconnect circuit adjacent to the first electronic component; as well as A second electronic component has a front surface for transmitting non-power signals and a back surface for receiving first power signals, wherein the second electronic component is electrically connected to the first electronic component through the back surface of the second electronic component and the interconnection circuit.

12. The electronic device according to claim 11, further comprising: A die includes the interconnect circuit and is configured to stabilize a second power signal transmitted to the first electronic component.

13. The electronic device according to claim 11, further comprising: A bare die includes a circuit area and a rigid area supporting the circuit area, wherein the circuit area is closer to the first electronic component than the rigid area.

14. The electronic device according to claim 11, further comprising: A carrier supports the first electronic component, wherein the carrier is configured to receive input / output signals from the first electronic component.

15. The electronic device of claim 11, wherein the interconnect circuit spans a gap between the first electronic component and the second electronic component.

16. An electronic device comprising: a first electronic component having a front surface and a back surface opposite the front surface; as well as An integrated circuit is configured to provide a power signal to the first electronic component through a backside surface of the first electronic component and is configured to bridge non-power signals between the first electronic component and a second electronic component.

17. The electronic device of claim 16, wherein the integrated circuit comprises a data storage circuit electrically connected to the first electronic component.

18. The electronic device of claim 16, wherein the integrated circuit comprises a power regulation circuit, and the power regulation circuit comprises a first portion that does not overlap with at least one of the first electronic component and the second electronic component.

19. The electronic device of claim 18, wherein the integrated circuit includes an interconnect circuit adjacent to the power conditioning circuit, and the power conditioning circuit includes a second portion adjacent to at least two sides of the interconnect circuit when viewed from a top view.

20. An electronic device according to claim 16, wherein the integrated circuit includes an interconnect circuit adjacent to the power regulation circuit, the interconnect circuit is configured to bridge the first electronic component and the second electronic component, the first electronic component includes a first terminal and a second terminal adjacent to the back surface of the first electronic component, the first terminal is disposed under the power regulation circuit and has a first density, and the second terminal is disposed under the interconnect circuit and has a second density greater than the first density.

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