Instruction control circuit and instruction control method, processor and chip

Abstract

The present disclosure relates to an instruction control circuit and an instruction control method, a processor and a chip. The instruction control circuit is used for responding to an execution unit writing result data of a first instruction into a corresponding data buffer, a first scoreboard updating a first state of the first instruction to a first release-dependency state, and a second scoreboard updating a second state of the first instruction to a second release-dependency state; responding to the data buffer writing the result data of the first instruction into a storage unit, the second scoreboard updates the second state of the first instruction to a second release-dependency state. The embodiment of the present disclosure can record the first instruction that has generated result data but has not yet been written into the storage unit through the coordinated use of the first scoreboard and the second scoreboard, thereby deceiving the instruction control circuit to release the dependency relationship between the current first instruction and the next second instruction, so as to wake up the second instruction in advance, reduce the delay time between mutually dependent instructions, and improve the efficiency of instruction execution.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an instruction control circuit and instruction control method, a processor and a chip. Background Art

[0002] In architectures such as Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT), multiple instructions can be grouped together, and multiple groups can be scheduled to increase parallelism. Because there are dependencies between instructions, such as one instruction depending on the execution result of another instruction, execution delays are hidden. For example, when the execution result of an instruction becomes the input of subsequent instructions, this dependency prevents the processor from executing independent parallel instructions. In this case, the processor may need to suspend the execution of dependent instructions and wait for the previous instruction to complete, which will affect the data processing efficiency of the processor. Summary of the invention

[0003] The present disclosure proposes a command control technical solution.

[0004] According to one aspect of the present disclosure, an instruction control circuit is provided, the instruction control circuit comprising: a storage unit, a first scoreboard, a second scoreboard, N execution units, and a data buffer corresponding to each execution unit, where N is an integer greater than or equal to 1; the instruction control circuit is used to: when the second instruction depends on the result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to a first release-of-dependence state, and the second scoreboard updates the second state of the first instruction to a second release-of-dependence state; in response to the first scoreboard updating the first state of the first instruction to the first release-of-dependence state, the execution unit receives the second instruction; in response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to a second release-of-dependence state; when the execution unit detects that the second scoreboard updates the second state of the first instruction to the second release-of-dependence state, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction.

[0005] In a possible implementation, the execution unit is connected to the corresponding data buffer, N data buffers are respectively connected to the storage unit and the second score board, N execution units are respectively connected to the first score board and the second score board, and the storage unit is connected to the second score board.

[0006] In a possible implementation, when detecting that the second scoreboard does not update the second state of the first instruction to the second release dependency state, the execution unit waits for the data buffer to write the result data of the first instruction into the storage unit.

[0007] In a possible implementation, the instruction control circuit is further used for: when the first instruction depends on result data of a third instruction, and the second instruction depends on the result data of the first instruction, in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state; in response to the first scoreboard updating the first state of the first instruction to the first dependent state, and the second scoreboard updating the second state of the third instruction to the second de-dependence state, the execution unit initiates an access request to the storage unit to read the result data of the third instruction according to the first instruction; the execution unit generates the result data of the first instruction according to the result data of the third instruction; in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to the first de-dependence state, the second scoreboard updates the second state of the first instruction to the second dependent state, and records the write address of the result data of the first instruction.

[0008] In a possible implementation, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction, including: the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction and the write address of the result data of the first instruction recorded by the second scoreboard.

[0009] In a possible implementation, the instruction control circuit also includes a scheduling port, which is connected to N execution units and a first scoreboard. The scheduling port is used to select a first instruction from multiple instructions and send the first instruction to the execution unit, and the first instruction does not depend on any instruction of the multiple instructions; in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state, including: in response to the execution unit receiving the first instruction, the scheduling port instructs the first scoreboard to update the first state of the first instruction to the first dependent state.

[0010] In a possible implementation, the instruction control circuit further includes an arbitrator, and N data buffers are connected to the storage unit via the arbitrator. The arbitrator is used to arbitrate the instruction result data from the N data buffers and write the instruction result data to the storage unit in an arbitration order.

[0011] According to one aspect of the present disclosure, there is provided an instruction control method, which is applied to an instruction control circuit, wherein the instruction control circuit comprises: a storage unit, a first scoreboard, a second scoreboard, N execution units, and a data buffer corresponding to each execution unit, wherein N is an integer greater than or equal to 1; the instruction control method comprises: in a case where the second instruction depends on result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to a first release-of-dependence state, and the second scoreboard updates the second state of the first instruction to a second release-of-dependence state; in response to the first scoreboard updating the first state of the first instruction to the first release-of-dependence state, the execution unit receives the second instruction; in response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to a second release-of-dependence state; in a case where the execution unit detects that the second scoreboard updates the second state of the first instruction to the second release-of-dependence state, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction.

[0012] In a possible implementation, the execution unit is connected to the corresponding data buffer, N data buffers are respectively connected to the storage unit and the second score board, N execution units are respectively connected to the first score board and the second score board, and the storage unit is connected to the second score board.

[0013] In a possible implementation, the instruction control method further includes: when the execution unit detects that the second scoreboard has not updated the second state of the first instruction to the second release dependency state, waiting for the data buffer to write the result data of the first instruction into the storage unit.

[0014] In a possible implementation, the instruction control method further includes: when the first instruction depends on result data of a third instruction, and the second instruction depends on the result data of the first instruction, in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state; in response to the first scoreboard updating the first state of the first instruction to the first dependent state, and the second scoreboard updating the second state of the third instruction to the second de-dependence state, the execution unit initiates an access request to the storage unit to read the result data of the third instruction according to the first instruction; the execution unit generates the result data of the first instruction according to the result data of the third instruction; in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to the first de-dependence state, the second scoreboard updates the second state of the first instruction to the second dependent state, and records the write address of the result data of the first instruction.

[0015] In a possible implementation, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction, including: the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction and the write address of the result data of the first instruction recorded by the second scoreboard.

[0016] In a possible implementation, the instruction control circuit also includes a scheduling port, which is connected to N execution units and a first scoreboard. The scheduling port is used to select a first instruction from multiple instructions and send the first instruction to the execution unit, and the first instruction does not depend on any instruction of the multiple instructions; in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state, including: in response to the execution unit receiving the first instruction, the scheduling port instructs the first scoreboard to update the first state of the first instruction to the first dependent state.

[0017] In a possible implementation, the instruction control circuit further includes an arbitrator, and N data buffers are connected to the storage unit via the arbitrator. The arbitrator is used to arbitrate the instruction result data from the N data buffers and write the instruction result data to the storage unit in an arbitration order.

[0018] According to one aspect of the present disclosure, a processor is provided, the processor comprising the instruction control circuit as described above.

[0019] According to one aspect of the present disclosure, a chip is provided, wherein the chip includes the processor as described above.

[0020] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a storage unit for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the storage unit to execute the above method.

[0021] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0022] In the instruction control circuit of the embodiment of the present disclosure, when the second instruction depends on the result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to the first release state, and the second scoreboard updates the second state of the first instruction to the second dependency state; in response to the first scoreboard updating the first state of the first instruction to the first release state, the execution unit receives the second instruction; in response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to the second release state; when the execution unit detects that the second scoreboard updates the second state of the first instruction to the second release state, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction. In this way, through the coordinated use of the first scoreboard and the second scoreboard, the first instruction that has generated the result data but has not been written into the storage unit can be recorded, thereby deceiving the instruction control circuit to release the dependency relationship between the current first instruction and the next second instruction, so as to wake up the second instruction in advance, which can reduce the delay time between mutually dependent instructions and improve the efficiency of instruction execution.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0025] Figure 1 A block diagram of an instruction control circuit according to an embodiment of the present disclosure is shown.

[0026] Figure 2 A schematic diagram showing a command control circuit in the related art.

[0027] Figure 3 A schematic diagram of a command control circuit according to an embodiment of the present disclosure is shown.

[0028] Figure 4 A comparative schematic diagram showing the effect of the instruction control circuit according to an embodiment of the present disclosure

[0029] Figure 5 A flow chart of an instruction control method according to an embodiment of the present disclosure is shown.

[0030] Figure 6 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, specifications and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0033] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0034] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0035] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0036] Figure 1 A block diagram of an instruction control circuit according to an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the instruction control circuit includes: a storage unit 1, a first scoring board 2, a second scoring board 3, N execution units 4, and a data buffer 5 corresponding to each execution unit 4, where N is an integer greater than or equal to 1. Each execution unit 4 can be connected to a corresponding data buffer 5, the N data buffers 5 are respectively connected to the storage unit 1 and the second scoring board 3, the N execution unit connections 4 are respectively connected to the first scoring board 2 and the second scoring board 3, and the storage unit 1 is connected to the second scoring board 3.

[0037] For example, the instruction control circuit may include a storage unit 1, a first scoreboard 2, a second scoreboard 3, execution units 4_1 to 4_N, and data buffers 5_1 to 5_N. Among them, the execution unit 4_1 may be connected to the corresponding data buffer 5_1, the execution unit 4_2 may be connected to the corresponding data buffer 5_2, and so on, the execution unit 4_N may be connected to the corresponding data buffer 5_N. The data buffers 5_1 to 5_N may be connected to the same storage unit 1, and the data buffers 5_1 to 5_N may also be connected to the same second scoreboard 3. The execution units 4_1 to 4_N may be connected to the same first scoreboard 2, and the execution units 4_1 to 4_N may also be connected to the same second scoreboard 3.

[0038] In one possible implementation, the instruction control circuit is used to reduce the time delay between interdependent instructions. For example, if the second instruction depends on the result data of the first instruction, the instruction control circuit can reduce the time delay between the first instruction and the second instruction, thereby improving the efficiency of instruction execution.

[0039] In one possible implementation, Figure 1 As shown, the instruction control circuit is used for:

[0040] In the case where the second instruction depends on the result data of the first instruction, in response to the execution unit 4 writing the result data of the first instruction into the corresponding data buffer 5, the first scoreboard 2 updates the first state of the first instruction to the first release state, and the second scoreboard 3 updates the second state of the first instruction to the second dependency state. The first release state is used to deceive the instruction control circuit to release the dependency between the first instruction and the second instruction so as to wake up the second instruction in advance. However, since the result data of the first instruction has not been written into the storage unit 1 at this time, the execution unit 4 cannot respond to the second instruction to read the result data of the first instruction from the storage unit 1, and the dependency between the first instruction and the second instruction has not been truly released. The second dependency state is used to record that there is a dependency between the first instruction and the second instruction, and the dependency between the two has not been truly released, and the second instruction will depend on the result data of the first instruction.

[0041] In response to the first scoreboard 2 updating the first state of the first instruction to the first de-dependence state, the execution unit 4 receives a second instruction, which depends on the result data of the first instruction.

[0042] In response to the data buffer 5 writing the result data of the first instruction into the storage unit 1, the second scoreboard 3 updates the second state of the first instruction to a second release of dependency state; wherein the second release of dependency state represents that the dependency relationship between the first instruction and the second instruction is released, and the execution unit 4 can read the result data of the first instruction from the storage unit 1 according to the second instruction.

[0043] When the execution unit 4 detects that the second scoreboard 3 updates the second state of the first instruction to the second release dependency state, the execution unit 4 initiates an access request to the storage unit 1 to read the result data of the first instruction according to the second instruction.

[0044] The instruction control circuit of the disclosed embodiment can record the first instruction that has currently generated result data but has not yet been written into the storage unit 1 through the coordinated use of the first scoreboard 2 and the second scoreboard 3, thereby deceiving the instruction control circuit into releasing the dependency between the current first instruction and the next second instruction so as to wake up the second instruction in advance, thereby reducing the delay time between mutually dependent instructions and improving the efficiency of instruction execution.

[0045] In a possible implementation, the instruction control circuit can be set in a processor. The processor can be a newly designed one or an improved one of an existing processor chip. The types of processor chips may include but are not limited to: central processing unit (CPU), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), etc.

[0046] In one possible implementation, the execution unit 4 may be a component in a processor for executing instructions, and may include a multi-stage pipeline, wherein the types of instructions executable by the execution unit 4 include data transmission instructions, arithmetic operation instructions, bit operation instructions, program flow control instructions, string operation instructions, interrupt instructions, etc., which are not limited in this embodiment of the present disclosure.

[0047] In a possible implementation, the data buffer 5 may be a multi-level buffer (Buffer), which may be composed of a plurality of electronic components with a temporary storage function. By introducing the data buffer 5 between each execution unit 4 and the storage unit 1, data caching may be performed between the execution unit 4 and the storage unit 1, and the difference in transmission speed between the execution unit 4 and the storage unit 1 may be coordinated to improve data processing efficiency. Among them, each level of the data buffer 5 may have different capacities to meet data requirements at different levels. The embodiments of the present disclosure do not limit the number of levels of the data buffer 5 and the capacity of each level of the buffer, and may be set according to the actual application scenario.

[0048] In a possible implementation, the storage unit 1 may be a sequential logic circuit for storing data and programs, so that the execution unit 4 can quickly access and process the data via the corresponding data buffer 5. The storage unit 1 may include a random access memory (DRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), etc. The embodiments of the present disclosure do not limit the type of the storage unit 1.

[0049] In a possible implementation, the first scoring board 2 and the second scoring board 3 may be multi-bit register circuits. The embodiments of the present disclosure do not limit the number of bits of the register circuits, and they may be set according to actual application scenarios.

[0050] In a possible implementation, the first scoreboard 2 includes a first array and a second array with the same number of bits, the same bits in the first array and the second array correspond to the same instruction, the first array is used to record the dependency order between instructions, and the second array is used to record the first state of each instruction, the first state includes a first release dependency state or a first dependency state;

[0051] For example, assuming that the second instruction depends on the result data of the first instruction, the first array may include two bits, the low bit on the right is used to indicate the first instruction, and the high bit on the left is used to indicate the second instruction. The first array is used to record the dependency order between the first instructions, that is, the high-order second instruction depends on the low-order first instruction. The second array may also include two bits, the low bit on the right is used to indicate the first instruction, and the high bit on the left is used to indicate the second instruction. In the second array, taking the low-order first instruction as an example, if the low bit in the second array is marked as a first identifier (for example, 0), it means that the first state of the first instruction is a first release dependency state, and the first release dependency state is used to deceive the instruction control circuit to release the dependency relationship between the current first instruction and the high-order second instruction, so as to wake up the high-order second instruction in advance; if the low bit in the second array is marked as a second identifier (for example, 1), it means that the first state of the first instruction is a first dependency state, indicating that there is a dependency relationship between the low-order first instruction and the high-order second instruction, and the high-order second instruction cannot be woken up in advance.

[0052] The second scoreboard 3 includes a third array and a fourth array with the same number of bits, the same bits in the third array and the fourth array correspond to the same instruction, the third array is used to record the dependency order between instructions, and the fourth array is used to record the second state of each instruction, and the second state includes a second release dependency state or a second dependency state.

[0053] For example, assuming that the second instruction depends on the result data of the first instruction, the third array may include two bits, the low bit on the right is used to indicate the first instruction, the high bit on the left is used to indicate the second instruction, and the third array is used to record the dependency order between the first instructions, that is, the high-order second instruction depends on the low-order first instruction. The fourth array may also include two bits, the low bit on the right is used to indicate the first instruction, and the high bit on the left is used to indicate the second instruction. In the fourth array, taking the low-order first instruction as an example, if the low bit in the fourth array is marked as the first identifier (for example, 0), it means that the second state of the first instruction is the second release dependency state, indicating that the current first instruction and the high-order second instruction have released the dependency relationship, and the execution unit can continue to execute the second instruction to initiate an access request to the storage unit to read the result data of the first instruction; if the low bit in the fourth array is marked as the second identifier (for example, 1), it means that the second state of the first instruction is the second dependency state, indicating that there is still a dependency relationship between the low-order first instruction and the high-order second instruction, and the dependency relationship between the two has not been truly released, and the second instruction will rely on the result data of the first instruction.

[0054] It should be understood that the embodiments of the present disclosure do not limit the number of bits of the first to fourth arrays, and they can be set according to actual application scenarios.

[0055] In this way, the first scoring board 2 and the second scoring board 3 can be flexibly arranged, so that the control circuit can be applied to more scenarios.

[0056] Exemplarily, assuming that it is known that there is a dependency relationship between the current first instruction and the next second instruction, and the second instruction depends on the result data of the first instruction, an idle execution unit can be selected from execution units 4_1 to 4_N, for example, the i-th (i can be any integer in the range of 1 to N) execution unit 4_i, and the current first instruction is processed by execution unit 4_i to obtain the result data of the first instruction, and the result data of the first instruction is sent to the corresponding data buffer 5_i.

[0057] In response to the execution unit 4_i writing the result data of the first instruction into the corresponding data buffer 5_i, the execution unit 4_i may instruct the first scoreboard 2 to update the first state of the first instruction to the first de-dependency state.

[0058] For example, the first scoreboard 2 may have a plurality of bits, each of which may be used to indicate the first state information of the corresponding instruction, and the bit corresponding to the first instruction among the plurality of bits may be marked as a first identifier (e.g., 0), indicating that the first state of the first instruction is a first de-dependency state. The first de-dependency state is used to deceive the instruction control circuit to release the dependency between the current first instruction and the next second instruction, so as to wake up the next second instruction in advance. In fact, at this time, the result data of the first instruction has not been written into the storage unit 1 through the data buffer 5_i, and the second instruction cannot read the result data of the first instruction from the storage unit 1, and the dependency between the first instruction and the second instruction has not been truly released.

[0059] In response to the first scoreboard 2 updating the first state of the first instruction to the first release dependency state, an idle execution unit can be selected from the execution units 4_1 to 4_N, for example, the j-th (j can be any integer in the range of 1 to N) execution unit 4_j, and the second instruction can be started to be processed through the execution unit 4_j.

[0060] During the process of the execution unit 4_j processing the second instruction, considering that the second instruction depends on the result data of the first instruction, and according to the first dependency release state of the first instruction recorded in the first scoreboard 2, it is impossible to determine whether the dependency relationship between the first instruction and the second instruction is truly released, that is, it is impossible to determine whether the result data of the first instruction is written into the storage unit 1.

[0061] Therefore, in the process of execution unit 4_j processing the second instruction, the result data of the first instruction will be used. Before the execution unit 4_j initiates an access request to the storage unit 1 to read the result data of the first instruction, it is also necessary to detect the second state information of the first instruction recorded in the second score board 3. When the execution unit 4_j detects that the second score board 3 updates the second state of the first instruction to the second release dependency state, the execution unit 4_j can continue to execute the second instruction to initiate an access request to the storage unit 1 to read the result data of the first instruction.

[0062] Alternatively, to ensure data consistency and correctness, the execution unit 4_j waits for the data buffer 5_i to write the result data of the first instruction into the storage unit 1 when detecting that the second scoreboard 3 has not updated the second state of the first instruction to the second release dependency state.

[0063] In response to the data buffer 5_i writing the result data of the first instruction into the storage unit 1, the second scoreboard 3 updates the second state of the first instruction to the second de-dependence state; for example, the second scoreboard 3 may have a plurality of bits, each of which may be used to indicate the second state information of the corresponding instruction, and the bit corresponding to the first instruction in the plurality of bits may be marked as a first identifier (e.g., 0), indicating that the second state of the first instruction is the second de-dependence state. The second de-dependence state is used to characterize that the dependency relationship between the first instruction and the second instruction is released, so that the execution unit 4_j can read the result data of the first instruction from the storage unit 1 according to the second instruction.

[0064] Alternatively, if the data buffer 5_i has not yet written the result data of the first instruction into the storage unit 1, the second state of the first instruction recorded by the second scoreboard 3 is not the second de-dependence state. For example, among the multiple bits recorded by the second scoreboard 3, the bit corresponding to the first instruction is not the first identifier (for example, 0), indicating that the second state of the first instruction is not the second de-dependence state, and the execution unit 4_j will wait for the data buffer 5_i to write the result data of the first instruction into the storage unit 1.

[0065] The first scoreboard 2 can be used to deceive the instruction control circuit to release the dependency between the current first instruction and the next second instruction, so as to wake up the second instruction in advance. In addition, in the process of executing the second instruction, before reading the result data of the first instruction from the storage unit 1, the second scoreboard 3 will be detected first, because the second scoreboard 3 can record the first instruction that has generated the result data but has not yet been written into the storage unit 1, so that only when the dependency between the first instruction and the second instruction is truly released (that is, the result data of the first instruction has been written into the storage unit 1) will the access request for reading the result data of the first instruction be initiated to the storage unit 1 according to the second instruction. Compared with the related art, the second instruction will be awakened only when the result data of the first instruction is written into the storage unit 1. The instruction control circuit of the embodiment of the present disclosure can wake up the second instruction in advance, which can reduce the delay time between mutually dependent instructions and improve the efficiency of instruction execution.

[0066] In a possible implementation, in order to improve processing efficiency, in addition to having a plurality of bits, each of which can be used to indicate the second state information of the corresponding instruction, the second scoreboard 3 also has a plurality of address bits corresponding to each bit, which are used to record the write address of the result data of the first instruction. The execution unit 4 initiates an access request to the storage unit 1 to read the result data of the first instruction according to the second instruction, including: the execution unit 4 initiates an access request to the storage unit 1 to read the result data of the first instruction according to the second instruction and the write address of the result data of the first instruction recorded by the second scoreboard 3. In this way, the execution unit will compare the access address carried by the second instruction with the write address of the result data of the first instruction recorded by the second scoreboard. If the two match and the second dependency of the first instruction has been released, the second instruction can access the storage unit 1, and the access address is the address compared with the write address in the second scoreboard.

[0067] Since the read and write operations of the result data are performed based on the known records of the second scoreboard 3, the behavior of the instruction control circuit is more predictable, which also facilitates the maintenance and debugging of the instruction control circuit, allowing developers to track and locate problems more easily.

[0068] In a possible implementation, the instruction control circuit further includes an arbitrator ( Figure 1 (not shown), N data buffers 5 are connected to the storage unit 1 via the arbitrator, and the arbitrator is used to arbitrate the instruction result data from the N data buffers 5 and write the instruction result data to the storage unit 1 according to the arbitration order.

[0069] The storage unit 1 is a shared resource of the N data buffers 5 corresponding to the N execution units 4. The arbitrator can be used to manage the competitive access of the N data buffers 5 to the storage unit 1. The arbitrator can arbitrate the multiple result data from the data buffers 5_1 to 5_N to be written into the storage unit 1, and select a target result data of the current round from the N result data to be written into the storage unit 1. The arbitration processing method may include round robin arbitration, fixed priority arbitration, circular arbitration, circular priority arbitration, etc. The implementation of the present disclosure does not limit the arbitration processing method of the arbitrator.

[0070] Exemplarily, in order to improve the parallelism of the processor, N execution units 4 may be used to process multiple independent pending tasks in parallel, each pending task may include multiple instructions with dependencies, and there is no dependency between the instructions of different pending tasks. For example, the execution unit 4_1 may process the first instruction 1 of the pending task 1, the execution unit 4_2 may process the first instruction 2 of the pending task 2, and so on, the execution unit 4_N may process the first instruction N of the pending task N. There may be a data buffer 5_1 receiving the result data 1 of the first instruction 1 from the execution unit 4_1, the data buffer 5_2 receiving the result data 2 of the first instruction 2 from the execution unit 4_2, and so on, the data buffer 5_N receiving the result data N of the first instruction N from the execution unit 4_N.

[0071] In this case, if data buffer 5_1 is to write result data 1 into storage unit 1, data buffer 5_2 is to write result data 2 into storage unit 1, and so on, data buffer 5_N is to write result data N into storage unit 1. That is, N data buffers 5 are to write N result data (e.g., including result data 1 to result data N) into the same storage unit 1. In the case that N data buffers 5 form a competitive access to storage unit 1, the arbitrator can arbitrate the N result data (e.g., including result data 1 to result data N) to be written into storage unit 1 from data buffer 5_1 to data buffer 5_N, and select a target result data of the current round from result data 1 to result data N to write into storage unit 1.

[0072] By setting an arbitrator in the instruction control circuit, data conflicts or confusion caused by multiple data buffers 5 simultaneously trying to write result data to the storage unit 1 can be reduced, the utilization rate of the write bandwidth of the storage unit 1 can be improved, and the writing efficiency of the result data can be improved.

[0073] In order to more clearly describe the instruction control circuit of the embodiment of the present disclosure, the instruction control circuit of the embodiment of the present disclosure is exemplarily illustrated in the following by a comparative introduction method.

[0074] For a first instruction and a second instruction that have a dependency relationship, where the second instruction depends on the result data of the first instruction, for example:

[0075] First instruction: OP R4, R0, R1, R2

[0076] Second instruction: OP R5, R0, R1, R4

[0077] OP stands for operation code, which indicates the type or nature of the operation to be performed by the instruction, such as fetching, adding or outputting data. R0, R1, R2, R4 and R5 represent different address codes, which are used to indicate the content of the operation object or the address of the operation object in storage unit 1.

[0078] For example, the first instruction "OP R4, R0, R1, R2" means performing an OP operation on R0, R1, R2 (for example, OP represents an addition operation), and obtaining the result data R4 of the first instruction (for example, R4=R0+R1+R2). The second instruction "OP R5, R0, R1, R4" means performing an OP operation on R0, R1, R4 (for example, OP represents an addition operation), and obtaining the result data R5 of the second instruction (for example, R5=R0+R1+R4). It can be seen that the second instruction "OP R5, R0, R1, R4" depends on the result data R4 of the first instruction "OP R4, R0, R1, R2", that is, the result data R4 of executing the first instruction "OP R4, R0, R1, R2" is the operation data of the second instruction "OP R5, R0, R1, R4".

[0079] Figure 2 A schematic diagram of a command control circuit in the related art is shown, Figure 2 As shown, in the related art, the thread group 7 can select the first instruction to be executed, and the first instruction is transmitted to the corresponding execution unit 4 via the scheduling port 6. The execution unit 4 initiates the operand read request required to execute the first instruction operation, and after the operand data is returned, the corresponding operation is completed after multiple cycles, and the result data R4 of the first instruction is written back to the storage unit 1. Due to the dependency of data between instructions, the result data R4 of the first instruction written back may be the operation data of the next second instruction. Therefore, the first scoreboard 2 can be designed to record the dependency relationship between instructions. After the current first instruction writes back the result data R4, the first scoreboard 2 can be notified to release the dependency relationship between the first instruction and the next second instruction, and wake up the execution of the next second instruction.

[0080] For example, when the first instruction is sent to the execution unit 4 through the scheduling port 6, the first scoreboard 2 can be updated. After the first instruction enters the execution unit 4, it first initiates an operand read request to the storage unit 1. After the operation data is returned, it is processed through the multi-stage pipeline of pipeline 0 to pipeline K to complete the corresponding operation, and the result data R4 of the first instruction obtained is written back to the storage unit 1. Since the execution unit 4 is far away from the storage unit 1, a multi-stage data buffer 5 can be inserted in the middle. The result data R4 of the first instruction needs to pass through the multi-stage data buffer 5 to reach the port of the storage unit 1, and needs to compete with the write request of other execution units 4 to decide whether it can be written to the storage unit 1. After obtaining the competition arbitration right, the write response can be returned to the corresponding execution unit 4 through the multi-stage data buffer 5. After receiving the response, the execution unit 4 can initiate an update request to the first scoreboard 2, indicating that the first instruction has been executed and its result data R4 is ready, and the second instruction can be sent for execution.

[0081] In the related technical solution, the result data R4 of the first instruction needs to go through the multi-level data buffer 5, the arbitration processing of the arbitrator, and return the write response indicating that the result data R4 has been written into the storage unit 1 before the first scoreboard 2 can be updated, so that the next second instruction can be issued. This results in a long time delay between the two instructions, affecting the efficiency of instruction execution.

[0082] In fact, in order to improve the efficiency of instruction execution, the second instruction can be awakened in advance. As long as the second instruction enters the execution unit 4 and reads the operation data from the storage unit 1, the result data R4 of the previous first instruction can be written into the storage unit 1.

[0083] In view of this, Figure 3 A schematic diagram of an instruction control circuit according to an embodiment of the present disclosure is shown. Figure 3 As shown, the instruction control circuit may include not only a storage unit 1, a first scoreboard 2, a second scoreboard 3, N execution units 4 (e.g., execution unit 4_1 to execution unit 4_N), and a data buffer 5 corresponding to each execution unit 4 (e.g., data buffer 5_1 to data buffer 5_N), but also a thread group 7 and a scheduling port 6. Optionally, the thread group 7 may include multiple thread groups, each thread group may include multiple instructions, and there may be a dependency relationship between the multiple instructions of each thread group. Optionally, the scheduling port 6 connects the N execution units 4 and the first scoreboard 2, and the scheduling port 6 is used to select a first instruction from multiple instructions and send the first instruction to the execution unit 4 (e.g., a preset execution unit 4 among the N execution units 4), and the first instruction does not depend on any instruction among the multiple instructions.

[0084] like Figure 3As shown, assuming that for the same first instruction "OP R4, R0, R1, R2" and second instruction "OP R5, R0, R1, R4", the second instruction "OP R5, R0, R1, R4" will depend on the result data R4 of the first instruction "OP R4, R0, R1, R2".

[0085] When the first instruction is transmitted to a certain execution unit 4 (for example, any idle execution unit 4 among execution units 4_1 to 4_N, or a preset execution unit 4 among execution units 4_1 to 4_N, which can be set according to a specific application scenario) through the dispatch port 6, the first scoreboard 2 is updated, and the first state of the first instruction is updated to the first dependent state. After the first instruction enters the execution unit 4, an operand read request is first initiated to the storage unit 1. After the operand is returned, the corresponding operation is completed after the multi-stage pipeline processing of the execution unit 4 channel 0 to channel K, and the result data R4 of the first instruction is written back to the storage unit 1. When the result data R4 of the first instruction begins to be written into the corresponding data buffer 5, the first scoreboard 2 and the second scoreboard 3 can be updated at the same time, and the first state of the first instruction in the first scoreboard 2 is updated to the first release dependency state, and the second state of the first instruction in the second scoreboard 3 is updated to the second dependent state, and the second scoreboard 3 can also record the information of the current first instruction, such as the write address of the result data R4 of the first instruction.

[0086] Because in the first scoreboard 2, the first state of the first instruction has been updated to the first release-dependency state, the second instruction can be awakened, and the second instruction can be sent to the corresponding execution unit 4 (for example, any idle execution unit 4 among the execution units 4_1 to 4_N, or the preset execution unit 4 among the execution units 4_1 to 4_N, which can be set according to the specific application scenario) through the scheduling port 6. During this process, after the result data R4 of the first instruction passes through the multi-level buffering of the data buffer 5 and obtains the arbitration right after the arbitration processing of the arbitrator and is written into the storage unit 1, the second scoreboard 3 can be updated, and the second state of the first instruction in the second scoreboard 3 is updated to the second release-dependency state. When the second instruction initiates an access request to read the result data R4 of the first instruction to the storage unit 1, the second scoreboard 3 is first checked. If the second state of the first instruction in the second scoreboard 3 has been updated to the second release-dependency state, it indicates that the result data R4 of the previous first instruction has been written into the storage unit 1, and the second instruction can read the result data R4 of the first instruction normally. If the second scoreboard 3 has not been updated, and the second state of the first instruction in the second scoreboard 3 is still the second dependency state, it indicates that the result data R4 of the previous first instruction is still in the data buffer 5 or has not obtained the write arbitration right. At this time, the second instruction can wait for the result data R4 of the first instruction to be written into the storage unit 1 until the second scoreboard 3 is updated to the second release dependency state.

[0087] Figure 4 A comparative schematic diagram showing the effect of the instruction control circuit according to an embodiment of the present disclosure is shown as follows: Figure 4 As shown, in the related technology, the execution unit 4 will wait for the data buffer 5 to cache the result data R4 of the first instruction, the arbitration processing of the arbitrator, and until the return response of writing the result data R4 of the first instruction into the storage unit 1 is received, the first state of the first instruction in the first scoreboard 2 will be updated to the first release dependency state, thereby waking up the second instruction and sending the second instruction to the corresponding execution unit 4 through the scheduling port 6.

[0088] In the instruction control circuit of the embodiment of the present disclosure, the execution unit 4 does not need to wait for the data buffer 5 to perform data caching and arbitration processing of the arbiter on the result data R4 of the first instruction. When the execution unit 4 sends the first result R4 of the first instruction to the data buffer 5, the first state of the first instruction in the first scoreboard 2 can be updated to the first de-dependence state, thereby waking up the second instruction in advance, and sending the second instruction to the corresponding execution unit 4 through the scheduling port 6. In addition, due to the first de-dependence state of the first instruction recorded in the first scoreboard 2, the deception instruction control circuit releases the dependency relationship between the first instruction and the second instruction, so as to wake up the second instruction in advance. The instruction control circuit of the embodiment of the present disclosure is also provided with a second scoreboard 3. In response to detecting that the result data R4 of the first instruction is written into the storage unit 1, the second state of the first instruction in the second scoreboard 3 is updated to the second de-dependence state, so that in the process of executing the second instruction, it can ensure that the result data R4 of the first instruction is written into the storage unit 1 before initiating an access request to read the result data R4 of the first instruction.

[0089] It can be seen that the instruction control circuit of the embodiment of the present disclosure, through the coordinated use of the first scoreboard 2 and the second scoreboard 3, can record the first instruction that has currently generated the result data R4 but has not yet been written into the storage unit 1, thereby deceiving the instruction control circuit to release the dependency between the current first instruction and the next second instruction, so as to wake up the second instruction in advance, which can reduce the delay time between interdependent instructions and improve the efficiency of instruction execution.

[0090] In a possible implementation, if the first instruction depends on the result data of the third instruction, the second instruction depends on the result data of the first instruction. That is, the third instruction is the previous instruction of the first instruction, and the second instruction is the next instruction of the first instruction. According to the dependency relationship between the instructions, the instruction sequence is: third instruction->first instruction->second instruction. When the execution unit 4 sends the result data of the third instruction to the corresponding data buffer 5, the first instruction can be awakened in advance, and the first instruction can be sent to the corresponding execution unit 4 through the scheduling port 6.

[0091] In this scenario, the instruction control circuit is also used for: when the first instruction depends on the result data of the third instruction, and the second instruction depends on the result data of the first instruction, in response to the execution unit 4 receiving the first instruction, the first scoreboard 2 updates the first state of the first instruction to a first dependency state; for example, the first scoreboard 2 may have multiple bits, each bit may be used to indicate the first state information of the corresponding instruction, and in response to the execution unit 4 receiving the first instruction, the bit corresponding to the first instruction among the multiple bits may be marked as a second identifier (for example, 1), indicating that the first state of the first instruction is a first dependency state, and the first dependency state is used to indicate that there is a dependency relationship between the current first instruction and the next second instruction.

[0092] Optionally, in response to the execution unit 4 receiving the first instruction, the first scoreboard 2 updates the first state of the first instruction to the first dependent state, including: in response to the execution unit 4 receiving the first instruction, the scheduling port 6 instructs the first scoreboard 2 to update the first state of the first instruction to the first dependent state. For example, when the scheduling port 6 sends the first instruction to the execution unit 4, the first state of the first instruction in the first scoreboard 2 can be synchronously updated to the first dependent state, thereby improving the processing efficiency of the instruction control circuit.

[0093] In response to the first scoreboard 2 updating the first state of the first instruction to the first dependent state, and the second scoreboard 3 updating the second state of the third instruction to the second released dependent state, indicating that the result data of the third instruction has been written into the storage unit 1, the execution unit 4 initiates an access request to the storage unit 1 to read the result data of the third instruction according to the first instruction, and the first instruction depends on the result data of the third instruction;

[0094] The execution unit 4 generates result data of the first instruction based on the result data of the third instruction; in response to the execution unit 4 writing the result data of the first instruction into the corresponding data buffer 5, the first scoreboard 2 updates the first state of the first instruction to a first release dependency state, and the second scoreboard 3 updates the second state of the first instruction to a second dependency state, and records the write address of the result data of the first instruction.

[0095] For example, the second scoreboard 3 may have multiple bits, each bit can be used to indicate the second state information of the corresponding instruction, and the bit corresponding to the first instruction among the multiple bits can be marked as a second identifier (for example, 1), indicating that the second state of the first instruction is a second dependent state, and the second dependency release state is used to characterize that there is a dependency relationship between the first instruction and the second instruction, and the second instruction depends on the result data of the first instruction.

[0096] In summary, the instruction control circuit of the embodiment of the present disclosure can record the first instruction that has generated result data but has not yet been written into the storage unit 1 through the coordinated use of the first scoreboard 2 and the second scoreboard 3, thereby deceiving the instruction control circuit to release the dependency between the current first instruction and the next second instruction, so as to wake up the second instruction in advance, reduce the delay time between mutually dependent instructions, and improve the efficiency of instruction execution. In addition, the instruction control circuit of the embodiment of the present disclosure is universal for instruction scheduling of processors with architectures such as Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT).

[0097] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned scheme of the specific implementation method, the specific execution order of each circuit module should be determined according to its function and possible internal logic.

[0098] In addition, the present disclosure also provides an instruction control method, which can be applied to the instruction control circuit, processor, and electronic device provided in the embodiments of the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0099] Figure 5 A flowchart of the instruction control method according to an embodiment of the present disclosure is shown. Figure 5 As shown, the instruction control method is applied to an instruction control circuit, the instruction control circuit includes: a storage unit, a first scoreboard, a second scoreboard, N execution units, and a data buffer corresponding to each execution unit, where N is an integer greater than or equal to 1, and the instruction control method includes:

[0100] In step S11, when the second instruction depends on the result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to the first release dependency state, and the second scoreboard updates the second state of the first instruction to the second dependency state;

[0101] In step S12, in response to the first scoreboard updating the first state of the first instruction to a first release dependency state, the execution unit receives a second instruction;

[0102] In step S13, in response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to a second release dependency state;

[0103] In step S14, when the execution unit detects that the second scoreboard updates the second state of the first instruction to the second release dependency state, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction.

[0104] In a possible implementation, the execution unit is connected to the corresponding data buffer, N data buffers are respectively connected to the storage unit and the second score board, N execution units are respectively connected to the first score board and the second score board, and the storage unit is connected to the second score board.

[0105] In a possible implementation, the instruction control method further includes: when the execution unit detects that the second scoreboard has not updated the second state of the first instruction to the second release dependency state, waiting for the data buffer to write the result data of the first instruction into the storage unit.

[0106] In a possible implementation, the instruction control method further includes: when the first instruction depends on result data of a third instruction, and the second instruction depends on the result data of the first instruction, in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state; in response to the first scoreboard updating the first state of the first instruction to the first dependent state, and the second scoreboard updating the second state of the third instruction to the second de-dependence state, the execution unit initiates an access request to the storage unit to read the result data of the third instruction according to the first instruction; the execution unit generates the result data of the first instruction according to the result data of the third instruction; in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to the first de-dependence state, the second scoreboard updates the second state of the first instruction to the second dependent state, and records the write address of the result data of the first instruction.

[0107] In a possible implementation, the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction, including: the execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction and the write address of the result data of the first instruction recorded by the second scoreboard.

[0108] In a possible implementation, the instruction control circuit also includes a scheduling port, which is connected to N execution units and a first scoreboard. The scheduling port is used to select a first instruction from multiple instructions and send the first instruction to the execution unit, and the first instruction does not depend on any instruction of the multiple instructions; in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependent state, including: in response to the execution unit receiving the first instruction, the scheduling port instructs the first scoreboard to update the first state of the first instruction to the first dependent state.

[0109] In a possible implementation, the instruction control circuit further includes an arbitrator, and N data buffers are connected to the storage unit via the arbitrator. The arbitrator is used to arbitrate the instruction result data from the N data buffers and write the instruction result data to the storage unit in an arbitration order.

[0110] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0111] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0112] The embodiment of the present disclosure also provides a processor, which includes the instruction control circuit as described above.

[0113] The embodiment of the present disclosure also provides a chip, which includes the processor as described above.

[0114] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0115] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0116] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0117] Electronic devices can be provided as terminals, servers or other forms of devices, such as user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDA), handheld devices, computing devices, vehicle-mounted devices, wearable devices, etc.

[0118] Figure 6 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 6 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0119] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0120] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0121] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0122] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0123] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0124] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0125] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0126] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0127] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0128] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0129] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0130] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0131] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0132] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, a clear and obvious status is set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he agrees to collect his personal information; or on the device for processing personal information, the personal information processing rules are notified by obvious status / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his personal information by himself; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0133] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A command control circuit, characterized in that: The instruction control circuit includes: a storage unit, a first scoreboard, a second scoreboard, N execution units, and a data buffer corresponding to each execution unit, where N is an integer greater than or equal to 1; The command control circuit is used for: In a case where the second instruction depends on result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to a first release dependency state, and the second scoreboard updates the second state of the first instruction to a second dependency state; In response to the first scoreboard updating the first state of the first instruction to a first de-dependency state, the execution unit receives a second instruction; In response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to a second release dependency state; When the execution unit detects that the second scoreboard updates the second state of the first instruction to a second release-dependency state, the execution unit initiates an access request to the storage unit to read result data of the first instruction according to the second instruction.

2. The command control circuit according to claim 1, characterized in that: The execution unit is connected to the corresponding data buffer, the N data buffers are respectively connected to the storage unit and the second score board, the N execution units are respectively connected to the first score board and the second score board, and the storage unit is connected to the second score board.

3. The command control circuit according to claim 1, characterized in that: When detecting that the second scoreboard does not update the second state of the first instruction to the second de-dependence state, the execution unit waits for the data buffer to write the result data of the first instruction into the storage unit.

4. The command control circuit according to any one of claims 1 to 3, characterized in that: The command control circuit is also used for: In a case where the first instruction depends on result data of a third instruction and the second instruction depends on result data of the first instruction, in response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependency state; In response to the first scoreboard updating the first state of the first instruction to the first dependency state, and the second scoreboard updating the second state of the third instruction to the second release dependency state, the execution unit initiates an access request to the storage unit to read result data of the third instruction according to the first instruction; The execution unit generates result data of the first instruction according to the result data of the third instruction; In response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to a first release dependency state, the second scoreboard updates the second state of the first instruction to a second dependency state, and records the write address of the result data of the first instruction.

5. The command control circuit according to claim 4, characterized in that: The execution unit initiates an access request to the storage unit to read result data of the first instruction according to the second instruction, including: The execution unit initiates an access request to the storage unit to read the result data of the first instruction according to the second instruction and the write address of the result data of the first instruction recorded in the second scoreboard.

6. The command control circuit according to any one of claims 1 to 3, characterized in that: The instruction control circuit further includes a scheduling port, the scheduling port is connected to the N execution units and the first scoreboard, the scheduling port is used to select a first instruction from the multiple instructions and send the first instruction to the execution unit, the first instruction does not depend on any instruction in the multiple instructions; In response to the execution unit receiving the first instruction, the first scoreboard updates the first state of the first instruction to a first dependency state, including: In response to the execution unit receiving the first instruction, the dispatch port instructs the first scoreboard to update a first state of the first instruction to a first dependency state.

7. The command control circuit according to any one of claims 1 to 3, characterized in that: The instruction control circuit also includes an arbitrator, and N data buffers are connected to the storage unit via the arbitrator. The arbitrator is used to arbitrate the instruction result data from the N data buffers and write the instruction result data to the storage unit according to the arbitration order.

8. A command control method, characterized in that: The instruction control method is applied to an instruction control circuit, the instruction control circuit comprising: a storage unit, a first scoreboard, a second scoreboard, N execution units, and a data buffer corresponding to each execution unit, where N is an integer greater than or equal to 1; The instruction control method comprises: In a case where the second instruction depends on result data of the first instruction, in response to the execution unit writing the result data of the first instruction into the corresponding data buffer, the first scoreboard updates the first state of the first instruction to a first release dependency state, and the second scoreboard updates the second state of the first instruction to a second dependency state; In response to the first scoreboard updating the first state of the first instruction to a first de-dependency state, the execution unit receives a second instruction; In response to the data buffer writing the result data of the first instruction into the storage unit, the second scoreboard updates the second state of the first instruction to a second release dependency state; When the execution unit detects that the second scoreboard updates the second state of the first instruction to a second release-dependency state, the execution unit initiates an access request to the storage unit to read result data of the first instruction according to the second instruction.

9. A processor, characterized in that: The processor comprises the instruction control circuit according to any one of claims 1 to 7.

10. A chip, characterized in that: The chip includes the processor of claim 9.

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