Multi-thread concurrent management method and related device

Abstract

The invention discloses a multi-thread concurrent management method and a related device. The method comprises the following steps: dividing a target global variable into a plurality of sub-variable regions; the target global variable is used for controlling multithreading to access target data, and each sub-variable region in the plurality of sub-variable regions comprises one or more flag bits; dividing the plurality of threads into a plurality of thread groups; the multiple threads are used for applying for the permission of reading the target data; authorizing the target thread in the target thread group to modify the flag bit in the target sub-variable region; one thread group in the plurality of thread groups is in one-to-one correspondence with one sub-variable region in the plurality of sub-variable regions; and if the target thread successfully modifies the flag bit, allowing the target thread to read the target data. The embodiment of the invention is applied to a scene of multi-thread concurrent CAS operation, and the success rate of the CAS operation can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-threaded concurrent management method and related devices. Background Art

[0002] A thread is a single sequential control flow in a process and is the smallest unit of program execution. In an operating system that introduces threads, threads are used as the basic unit of independent operation and scheduling. Threads can be executed concurrently, including concurrent execution of multiple threads in a process, concurrent execution of threads in different processes, and concurrent execution of threads on different cores in a multi-core computer system.

[0003] When multiple threads are concurrent, they may need to access the same shared data. That is, the shared data may be shared with different threads. To ensure the integrity of the shared data, atomic operations, such as compare and switch (CAS) operations, are required when multiple threads access the shared data at the same time. As a result, multiple concurrent threads cannot modify the shared data at the same time; a thread cannot read the shared data being modified by other threads; and multiple threads can read the shared data at the same time. A common application scenario for CAS operations is in read-write locks or other functions that implement similar read-write functions (such as pinbuffer / unpinbuffer). Read-write locks have two states: read lock and write lock. When a thread holds a write lock, it can read and write shared data, and other threads cannot hold a write lock or a read lock. When a thread holds a read lock, it can read shared data, and other threads can also hold a read lock. Read-write locks generally use a variable for state control, and consistency can be ensured between multiple threads through CAS operations.

[0004] However, as the number of computer cores continues to increase and the computing power of a single core continues to increase, the concurrency and speed of threads are further improved. In high-concurrency scenarios, the failure rate of CAS operations performed by multiple threads concurrently is high, and the phenomenon of CAS operation retries is serious. The overhead of CAS operations increases exponentially, becoming one of the bottlenecks limiting computer performance.

[0005] Therefore, how to provide a method for improving the success rate of multi-threaded concurrent CAS operations is a problem to be solved urgently. Summary of the invention

[0006] The embodiments of the present application provide a multi-thread concurrent management method and related devices, which are applied in the scenario of multi-thread concurrent CAS operation and can improve the success rate of CAS operation.

[0007] In a first aspect, an embodiment of the present application provides a multi-threaded concurrency management method, which may include: dividing a target global variable into multiple sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each of the multiple sub-variable areas includes one or more flag bits; dividing multiple threads into multiple thread groups; the multiple threads are used to apply for permission to read the target data; authorizing a target thread in a target thread group to modify the flag bit in a target sub-variable area; wherein the target thread group is one of the multiple thread groups, the target sub-variable area is one of the multiple sub-variable areas, and one of the thread groups and one of the multiple sub-variable areas correspond one to one; if the target thread successfully modifies the flag bit, the target thread is allowed to read the target data.

[0008] In the prior art, when multiple threads apply to read shared data and concurrently modify the global variables used to control multi-threaded access to shared data, only one thread can successfully modify the value of the global variable at a time, resulting in a large number of modification operations failing and retrying, a low modification success rate, a large instruction overhead for modification operations, and serious waste of resources. In an embodiment of the present application, by dividing the global variable used to control multi-threaded access to shared data into multiple sub-variable areas, the multiple threads applying to read the shared data are divided into multiple thread groups, so that one thread group corresponds to one sub-variable area, and different thread groups correspond to different sub-variable areas, so that when threads in different thread groups apply to read shared data, they can obtain the permission to read the shared data by modifying the value of the corresponding sub-variable area. Among them, when applying to read shared data, the modification of the values ​​of different sub-variable areas between threads of different thread groups is independent, so that the value of each sub-variable area can be successfully modified by one thread respectively, that is, in one round of concurrent modification, multiple threads can be successfully modified. Therefore, when the above method is applied to the scenario of multi-threaded concurrent CAS operations, if multiple threads apply to read shared data, and concurrent CAS operations modify the values ​​of different sub-variable areas, multiple CAS operations can be successful, thereby improving the success rate of CAS operations and reducing resource waste.

[0009] In a possible implementation, the method further includes: determining the total number of threads that can currently read the target data according to the state of the mark bit in each sub-variable area.

[0010] In the embodiment of the present application, the number of threads that can currently read the shared data represented by each sub-variable area is determined according to the state of the flag bit in each sub-variable area, and the total number of threads that can currently read the shared data is the sum of the number of threads that can be determined in each sub-variable area. In the case where a thread holds a read lock, if another thread applies for a write lock, the lock will fail and the thread will go into hibernation and wait. When the total number of threads holding the read lock is 0, the thread that previously applied for a write lock and temporarily went into hibernation can be awakened.

[0011] In a possible implementation, when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

[0012] In an embodiment of the present application, when multiple threads in the same thread group concurrently apply to read the target data, that is, when concurrently attempting to modify the mark bit of the sub-variable area, only one thread is allowed to successfully modify it, thereby ensuring the consistency of the modification of the mark bit in the sub-variable area and avoiding confusion.

[0013] In a possible implementation, the authorizing a target thread in a target thread group to modify a flag bit in a target subvariable area includes:

[0014] If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

[0015] In an embodiment of the present application, during the process of modifying the mark bit of the sub-variable area by a thread, it can first be determined whether the target data has been exclusively occupied. If no other thread has exclusively occupied the target data, the thread can modify the mark bit through a CAS operation to ensure the consistency of the modification and avoid confusion.

[0016] In a possible implementation, each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; and the method further includes:

[0017] When the first thread of the target thread group applies for exclusive use of the target data, authorizing the first thread to modify the control state bit of each sub-variable area respectively;

[0018] If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively occupy the target data.

[0019] In the embodiment of the present application, each sub-variable area may also have a control status bit, and the control status bit may be used to identify whether the target data has been exclusively occupied by a thread. When a thread applies for exclusive use of the target data, the thread needs to modify the control status bit in each sub-variable area, so that when other threads subsequently apply to read the target data, they only need to determine whether the target data is exclusively occupied by judging the control status bit in the sub-variable area corresponding to their own thread group. If the thread applying for exclusive use of the target data successfully modifies the control status bit, the thread is allowed to exclusively occupy the target data.

[0020] In a possible implementation, the step of authorizing the first thread to modify the control status bit of each sub-variable area includes:

[0021] If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0022] In an embodiment of the present application, during the process of modifying the control status bit of a sub-variable area by a thread, it can be determined whether the target data has been exclusively occupied or read. If no other thread has exclusively occupied or read the target data, the thread can modify the control status bit of each sub-variable area through a CAS operation to ensure the consistency of the modification and avoid confusion when multiple threads apply for exclusive use of the target data at the same time.

[0023] In a possible implementation, the global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

[0024] In the embodiment of the present application, the method of controlling multi-threaded access to shared data can be a read-write lock, then the global variable can be a lock state variable, the mark bit can be a read lock count bit, and the process of multiple threads applying to read the target data and modifying the mark bit is equivalent to the encryption and unencryption lock operation. When the lock state variable is partitioned, the threads are grouped, and multiple threads can modify the read lock count bit of the partition in multiple parallel ways, multiple threads can modify successfully, thereby improving the success rate of encryption and unencryption lock.

[0025] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0026] In the embodiment of the present application, the method of controlling multi-threaded access to shared data can be a read-write lock, then the global variable can be a lock state variable, the control state bit can be a write lock state bit, and the process of multiple threads applying for exclusive use of the target data and modifying the write lock state bit is equivalent to adding and unlocking the write lock operation. When a thread applies for exclusive use of the target data, the thread needs to modify the write lock state bit in each sub-variable area, so that if other threads subsequently apply to read the target data, they only need to judge the write lock state bit in the sub-variable area corresponding to their own thread group to determine whether the target data is exclusive, that is, whether there is a thread holding the write lock.

[0027] In a second aspect, an embodiment of the present application provides a multi-threaded concurrency management device, which may include: a first processing unit, configured to divide a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, each of the plurality of sub-variable areas comprising one or more flag bits;

[0028] A second processing unit is used to divide the multiple threads into multiple thread groups; the multiple threads are used to apply for permission to read the target data;

[0029] Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one;

[0030] The third processing unit is configured to allow the target thread to read the target data if the target thread successfully modifies the mark bit.

[0031] In a possible implementation manner, the device further includes:

[0032] A determination unit is used to determine the total number of threads that can currently read the target data according to the state of the mark bit in each sub-variable area.

[0033] In a possible implementation, when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

[0034] In a possible implementation manner, the second processing unit is specifically configured to:

[0035] If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

[0036] In a possible implementation, each of the sub-variable regions further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the second processing unit is further used to authorize the first thread of the target thread group to modify the control status bit of each sub-variable region respectively when the first thread applies for exclusive use of the target data;

[0037] The third processing unit is further configured to allow the first thread to exclusively occupy the target data if the first thread successfully modifies the control status bit.

[0038] In a possible implementation manner, the second processing unit is specifically configured to:

[0039] If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0040] In a possible implementation, the global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

[0041] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0042] In a third aspect, an embodiment of the present application provides a multi-threaded concurrent management device, including a processor, the processor being configured to support the device to implement the corresponding functions in the multi-threaded concurrent management method provided in the first aspect. The device may also include a memory, the memory is used to couple with the processor, and the memory stores the necessary program instructions and data of the device. The device may also include an interface circuit for the device to communicate with other devices, other equipment or a communication network.

[0043] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer software instructions used by a device apparatus for implementing a multi-threaded concurrent management method provided by one or more of the second aspects above, which includes a program designed for executing the above aspects.

[0044] In a fifth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute a process executed by an apparatus for implementing a multi-threaded concurrent management method provided by one or more of the second aspects above.

[0045] In a sixth aspect, an embodiment of the present application provides an electronic device, the electronic device includes a processor, and the processor is configured to support the electronic device to implement the corresponding functions in the multi-threaded concurrent management method provided in the first aspect. The electronic device may also include a memory, the memory is used to couple with the processor, and the memory stores the necessary program instructions and data of the electronic device. The electronic device may also include a communication interface for enabling the electronic device to communicate with other devices or a communication network.

[0046] In a seventh aspect, an embodiment of the present application provides a chip system, which includes a processor for supporting a device to implement the functions involved in the first aspect, for example, generating or processing the information involved in the multi-threaded concurrent management method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0047] In an eighth aspect, an embodiment of the present application provides a server, comprising a communication interface, a memory and a processor; the communication interface, the memory and the processor are coupled, the communication interface is used for the server to communicate with other devices or a communication network, the memory is used to store computer program code, the computer program code includes computer instructions, and when the processor reads the computer instructions from the memory, the server executes any possible implementation method as in the first aspect.

[0048] In the ninth aspect, an embodiment of the present application provides a vehicle-mounted device, including a communication interface, a memory and a processor; the communication interface, the memory and the processor are coupled, the communication interface is used for the vehicle-mounted device to communicate with other devices or a communication network, the memory is used to store computer program code, the computer program code includes computer instructions, and when the processor reads the computer instructions from the memory, the vehicle-mounted device executes any possible implementation method as in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0050] Figure 1 It is a structural diagram of a lock state variable;

[0051] Figure 2 It is a flowchart of a read-write lock;

[0052] Figure 3 It is a schematic diagram of the result of multiple threads performing CAS operations simultaneously;

[0053] Figure 4It is a system architecture diagram of a multi-threaded concurrent management method application provided in an embodiment of the present application;

[0054] Figure 5 It is a flowchart of a multi-threaded concurrent management method provided in an embodiment of the present application;

[0055] Figure 6 It is a structural diagram of a lock state variable partition provided by an embodiment of the present application;

[0056] Figure 7 This is a schematic diagram of the result of a multi-threaded group performing CAS operations simultaneously provided by an embodiment of the present application;

[0057] Figure 8 It is a performance analysis perf flame graph provided in an embodiment of the present application;

[0058] Fig. 9 It is another performance analysis perf flame graph provided in an embodiment of the present application;

[0059] Fig.10 It is another performance analysis perf flame graph provided in an embodiment of the present application;

[0060] Fig.11 It is a structural diagram of a multi-threaded concurrent management device provided in an embodiment of the present application;

[0061] Fig.12 It is a structural diagram of another multi-threaded concurrency management device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0063] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0064] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in one or more embodiments of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0065] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0066] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0067] (1) Atomic operation refers to one or a series of operations that cannot be interrupted, that is, operations that will not be interrupted by the thread scheduling mechanism, and there will be no context switch during operation. Atomic operations mainly include simple addition and subtraction operations, compare and exchange (CAS) operations, and assignment operations. When multiple threads access shared data at the same time, executing CAS atomic operations to modify the variables of read-write locks or other functions that implement similar read-write functions can ensure the atomicity of the variable value modification in multi-threaded concurrent scenarios to avoid confusion. In an embodiment of the present application, the variable is divided into multiple regions, and multiple threads are grouped. When a thread in the target group reads shared data, the count value of the corresponding target region in the variable can be modified through a CAS operation. That is, by dividing the CAS operations of concurrent threads into multiple regions, the concurrency conflicts of CAS operations are reduced, thereby improving the success rate of CAS operations.

[0068] (2) Read-write locks, including read locks and write locks. Among them, only one thread can occupy the read-write lock in the write lock state at a time, but multiple threads can occupy the read-write lock in the read lock state at the same time. Therefore, when the read-write lock is in the write lock state, all threads attempting to lock the lock (including read lock and write lock) will be blocked before the lock is unlocked. When the read-write lock is in the read lock state, other threads attempting to add the read lock can obtain access rights, but if a thread wants to add the write lock, it must wait until all threads release the lock. The read-write lock generally uses a variable for state control, and the consistency between multiple threads can be guaranteed through CAS operations. In the embodiment of the present application, the variable used to control the state of the read-write lock can be partitioned, and multiple threads with concurrent CAS operations can be grouped. When a thread in the target group applies for a read lock (i.e., when reading shared data), the count value of the corresponding target area in the variable can be modified through the CAS operation, and other areas are used to process concurrent CAS operations of threads in other groups, thereby improving the success rate of CAS.

[0069] (3) The compare and switch (CAS) operation will pass in three values: the address of the target variable to be modified, the original value of the variable, and the new value to be modified. When performing a CAS operation, memory access will be exclusively controlled in certain units (usually within a cache line). If the value of the target variable in the memory (target variable address) is equal to the "original value of the variable" passed in by the CAS operation, the target variable in the memory will be changed to the "new value to be modified" passed in by the CAS operation; if the value of the target variable in the memory is inconsistent with the "original value of the variable" passed in by the CAS operation, the modification fails and the current value of the target variable is transmitted. This ensures the atomicity of the target variable value modification in multi-threaded concurrent scenarios.

[0070] (4) Concurrency means that multiple threads can run part of the logic in a period of time. The current thread can start executing regardless of whether the previous thread has completed, without having to wait for the previous thread to complete.

[0071] (5) In this application, "plurality" means two or more. "and / or" describes the association relationship of related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0072] First, the technical problems to be solved by this application are analyzed and proposed. In the prior art, the common application scenarios of CAS operation are read-write locks or other functions that implement similar read-write functions (such as pinbuffer / unpinbuffer), see the following solutions 1 and 2:

[0073] Solution 1: The common implementation of read-write locks is controlled by a lock state variable, see Figure 1 , Figure 1 It is a structural diagram of a lock state variable. Taking Linux rwlock as an example, Figure 1 The variable shown in indicates that no thread currently holds the write lock, and 3 threads hold the read lock. When the variable is 0, it means that the read-write lock is in an idle state, that is, no thread holds the lock (including the read lock and the write lock). When the highest bit is 1, it means that a thread holds the write lock, and the highest bit is set to 0 when the thread releases the write lock. Each time a thread adds a read lock, the variable is incremented by 1, and when a thread releases the read lock (i.e., reads the lock), the variable is decremented by 1. To ensure the consistency of variable modifications between multiple threads, each thread is synchronized through CAS operation instructions to ensure that only one thread can modify the variable at a time. Of course, the write lock status bit does not have to be in the highest bit, or not all bits in the variable are used for read-write lock counting. Several bits can be used for other customized identification purposes.

[0074] This solution has the following disadvantages:

[0075] When a large number of threads concurrently access a shared resource for read-only access, a large number of read locks will be acquired concurrently, and the failure rate of acquiring read locks is high. Figure 2 , Figure 2 It is a flowchart of locking a read-write lock. In the above scheme 1, when a thread applies for a write lock (such as Figure 2 Method 1 in the above method first determines the lock status to see if it is a read lock or a write lock. If it is already locked, the write lock application fails and needs to be reapplied (you can retry immediately or wait to be awakened by other release processes); if it is not locked, the variable write lock status position needs to be set to 1, and then the variable is subjected to a CAS atomic operation. If the modification is successful, the write lock is added successfully; if the modification fails, it means that other threads have locked and modified the variable value first, and the write lock fails, and the process of retrying, waiting or other processes is entered. When a thread applies for a read lock (such as Figure 2Method 2 in the above method first determines whether the lock state is a write lock. If a write lock has been added, the read lock application fails and needs to be reapplied (you can retry immediately or wait to be awakened by other release processes); if a write lock has not been added, the variable read lock count bit needs to be increased by 1, and then the variable is subjected to a CAS atomic operation. If the modification is successful, the read lock is added successfully; if the modification fails, it means that other threads have modified the variable value during this period, that is, when multiple threads concurrently add read locks, other threads successfully add read locks, resulting in the failure of this thread to add read locks, and enter retry or other processes. Under normal circumstances, the read lock process will be retried immediately according to the latest value of the current lock state variable.

[0076] It can be seen that when two threads simultaneously apply read locks, the CAS operation of one of the threads will fail. After judging the latest lock status, if the write lock is not applied, the read lock will be applied again immediately. Furthermore, when a large number of threads concurrently access a shared resource for read-only access, a large number of read locks will be applied concurrently, the number of read lock failures will increase, and the failure rate will increase sharply. Figure 3 , Figure 3 It is a schematic diagram of the result of multi-threaded simultaneous CAS operations. Taking 4 threads adding read locks at the same time as an example, the current value is read from the memory storing the lock state variable, and the old value and the new value are the input values ​​of the CAS operation. In the four rounds of concurrent CAS operations, there are 4 valid CAS operations (ie OK), and 6 invalid CAS operations (ie failed), that is, the number of successful CAS operations is 4 times, and the number of failures is 6 times (including 3 times in the first round, 2 times in the second round, and 1 time in the third round). The overhead of each CAS operation is relatively large, and it also requires synchronous memory access between multiple cores and across chips, occupying memory bandwidth and computing resources.

[0077] Solution 2: Other functions that implement similar read and write functions (such as pinbuffer / unpinbuffer) control the sharing, exclusivity, and other status identification of data pages. Among them, sharing uses a sharing count, which is similar to adding a read lock and unreading a read lock. Pinbuffer can be simply understood as adding a read lock, and unpinbuffer can be simply understood as an unreading lock. Taking the Kunpeng 2P+openGauss (open source Gauss) scenario as an example, when multiple threads perform high-concurrency queries on the same table (data that can be shared), each query requires read-only access to the index root directory. Similar to the high concurrency of CAS operations with read locks, there are also problems like those in Solution 1. The failure rate of CAS operations is high, and the number of CAS operation failure retries is high. CAS instructions account for 51% of the entire server CPU overhead.

[0078] To this end, the present application proposes a multi-threaded concurrent management method and related devices, which are applied in the scenario of multi-threaded concurrent CAS operations, and can improve the success rate of CAS operations. Specifically, the global variables of shared data are divided into multiple areas, and the multiple threads that apply to read the shared data are divided into multiple thread groups, one thread group corresponds to one variable area, and different thread groups correspond to different variable areas, so that when threads in different thread groups apply to read shared data, they can obtain the permission to read the shared data by modifying the value of the corresponding variable area. Among them, when applying to read shared data, the modification of the values ​​of different variable areas between threads in different thread groups is independent, so that the value of each variable area can be modified successfully separately. Therefore, when multiple threads apply to read shared data, and concurrent CAS operations modify the values ​​of different variable areas, multiple CAS operations can be successful, which improves the success rate of CAS operations.

[0079] In order to better understand a multi-threaded concurrency management method provided in an embodiment of the present application, the system architecture and / or application scenario of the multi-threaded concurrency management method provided in an embodiment of the present application will be described below. It is understandable that the system architecture and application scenario described in the embodiment of the present application are to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided in the embodiment of the present application.

[0080] The system architecture to which the multi-threaded concurrent management method provided in the embodiment of the present application can be applied can be found in Figure 4 , Figure 4 1 is a schematic diagram of a system architecture for a multi-threaded concurrent management method provided in an embodiment of the present application. The system architecture may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), or one or more system-on-chips (SOCs), and a memory. The basic unit for independent operation and independent scheduling of the processor is a thread. For example, Figure 4The system architecture shown includes multiple CPUs (such as CPU1-CPU5), any one of which (such as CPU1) can be used to execute the multi-threaded concurrent management method provided in the embodiment of the present application. First, the global variable used to control multi-threaded access to shared data is divided into multiple sub-variable areas, and multiple threads requesting to read shared data in multiple CPUs are grouped. When multiple CPU concurrent threads read shared data in the memory, threads of different thread groups can be authorized to modify the mark bits in different sub-variable areas. If the thread modifies the mark bit successfully, CPU1 can allow it to read the shared data in the memory. Exemplarily, when CPU1 runs independently and schedules thread 1 to apply for reading shared data in the memory (taking application for read lock as an example), thread 1 can only modify the mark bit of the first partition of the global variable (such as the lock state variable), and after the modification is successful, thread 1 can read the shared data; when CPU2 runs independently and schedules thread 2 to apply for reading the shared data, thread 2 can only modify the mark bit of the second partition of the global variable, and after the modification is successful, thread 2 can read the shared data. Similarly, CPU3 runs or schedules thread 3 and CPU4 runs or schedules thread 4 to apply for reading the shared data. Thread 3 and thread 4 can modify the mark bits of the third partition and the fourth partition respectively. After the modification is successful, thread 3 and thread 4 can read the shared data. The length of the global variable can be 1 byte to 16 bytes, or even longer or shorter, and the range can be different in different architecture instruction sets. Figure 4 The example in the above example is that the length of a global variable is equal to the length of a cache line, which should not be construed as limiting the present application. It should be noted that each partition of a global variable may also include a control status bit (such as a write lock status bit). When a CPU runs or schedules a thread to apply for exclusive use of the shared data, the control status bit of each partition may be modified, such as Figure 4 When CPU5 runs or schedules thread 5 to exclusively occupy the shared data in the memory, the control status bit of each of the four partitions can be modified. After the modification is successful, thread 5 can perform operations such as reading and writing on the shared data.

[0081] It should be noted that the embodiments of the present application can be applied to various computer system architectures. Figure 4 The architecture in the embodiment of the present application is only an exemplary implementation, and the architecture applicable to the embodiment of the present application includes but is not limited to the above architecture. It should be understood that the architecture of the computer may have more or fewer units / modules than those shown in the figure, may combine two or more units / modules, or may have different unit / module configurations. Various units / modules may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application specific integrated circuits.

[0082] Understandably, the multi-threaded concurrent management method provided in the embodiment of the present application can be executed by an electronic device. An electronic device refers to a device that can be abstracted as a computer system, wherein an electronic device that supports the above-mentioned multi-threaded concurrent management function can also be referred to as a multi-threaded concurrent management device. The multi-threaded concurrent management device can be a complete machine of the electronic device, such as: a server, a vehicle-mounted computer or a terminal device, and the terminal device can be a smart wearable device, a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; it can also be a system / device composed of multiple complete machines; it can also be a part of the electronic device, such as: a chip related to the multi-threaded concurrent management function, such as a processor, a system chip (system on a chip, SoC), etc., which is not specifically limited in the embodiment of the present application. Among them, the system chip is also called a system on chip. It is understandable that the above-mentioned multi-threaded concurrent management method provided in the embodiment of the present application can also be applied to the operating system, database, application software, middleware or underlying software of the above-mentioned electronic device.

[0083] For ease of understanding, the technical solution provided by this application will be described below in conjunction with more drawings.

[0084] In this application, unless otherwise specified, the same or similar parts between various embodiments or implementations can refer to each other. In each embodiment of this application, and each implementation method / implementation method / implementation method in each embodiment, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments and each implementation method / implementation method / implementation method in each embodiment are consistent and can be referenced to each other. The technical features in different embodiments and each implementation method / implementation method / implementation method in each embodiment can be combined to form new embodiments, implementation methods, implementation methods, or implementation methods according to their inherent logical relationships. The implementation methods of this application described below do not constitute a limitation on the scope of protection of this application.

[0085] See also Figure 5 , Figure 5 : is a flowchart of a multi-threaded concurrent management method provided in an embodiment of the present application, the method includes but is not limited to the following steps:

[0086] S501: Divide the target global variable into multiple sub-variable areas.

[0087] Specifically, the target global variable is used to control multi-threaded access to target data. The target data is a resource that can be shared by multiple threads, and is generally referred to as shared data or shared resources. The target data can be specific data, such as a table that is shared and queried; the target data can also refer to a critical section, that is, a program fragment that accesses shared resources (such as shared devices, shared memory, etc.). In order to ensure the integrity of the target data, it is necessary to set a global variable (i.e., the target global variable) for controlling multi-threaded access to the target data. After the global variable is divided into regions, multiple sub-variable regions are obtained, each of which can include one or more mark bits. Subsequently, threads in different thread groups can modify the mark bits of different sub-variable regions. Taking the global variable as a lock state variable as an example, the mark bit can be called a read lock count bit. For example, see Figure 6 , Figure 6 The present application provides a structural diagram of a lock state variable partition, wherein the length of the lock state variable is 8 bytes as an example, and the lock state variable is divided into four 2-byte regions (including partition 1, partition 2, partition 3 and partition 4), and each partition may include one or more read lock count bits. Optionally, when dividing the regions for global variables, it can be divided equally (such as Figure 6 As shown), it can also be unequally divided, for example, it can be divided into four sub-variable areas with lengths of 1 byte, 1 byte, 2 bytes and 4 bytes respectively, which is not specifically limited here. Optionally, the length of the sub-variable area can be divided according to the number of threads in different thread groups. When the number of threads in a thread group is large, the length of the sub-variable area corresponding to the thread group can be longer; on the contrary, when the number of threads in a thread group is small, the length of the sub-variable area corresponding to the thread group can be shorter.

[0088] It should be noted that, in order to ensure the consistency of the modification of the sub-variable area mark bit, the thread generally modifies the mark bit through atomic operations (such as CAS operations). Because the minimum unit that can be operated by atomic operations is 1 byte at present, the minimum length of a single sub-variable area in the global variable should be 1 byte; the maximum length of the entire global variable supports the maximum number of bytes that the computer can perform atomic operations on (such as cache lines). Understandably, with the development of computer technology, if the minimum unit and maximum unit that can perform atomic operations change, in the embodiment of the present application, the global variable and the length range that the sub-variable area can support can also change accordingly, that is, the minimum length of the above-mentioned single sub-variable area is 1 byte, and the maximum length of the entire global variable is a cache line, which should not constitute a limitation on the embodiment of the present application.

[0089] S502: Divide the multiple threads into multiple thread groups.

[0090] S503: Authorize a target thread in the target thread group to modify a flag bit in the target subvariable area.

[0091] Specifically, multiple threads applying to read the target data can be grouped so that the threads in the multiple thread groups can modify the mark bits in the multiple sub-variable areas respectively, and the threads in the target thread group modify the mark bits of the target sub-variable area. Among them, one thread group corresponds to one sub-variable area, and different thread groups correspond to different sub-variable areas, that is to say, a thread group in the multiple thread groups corresponds to a sub-variable area in the multiple sub-variable areas one by one. Exemplarily, the multiple threads may need to read the target data in the process of executing a certain task, so they apply for permission to read the target data. In other words, the multiple threads can not only be used to apply for permission to read the target data, but also can be used to complete other tasks.

[0092] Optionally, when the target thread group among the multiple thread groups includes multiple threads, within one clock cycle, only one thread in the target thread group is allowed to successfully modify the mark bit in the sub-variable area (i.e., the target sub-variable area) corresponding to the target thread group. In other words, when multiple threads in the same thread group concurrently modify the mark bit of the sub-variable area corresponding to the thread group, only one thread can successfully modify the mark bit, thereby ensuring the consistency of the modification of the mark bit of the sub-variable area and avoiding confusion. Other threads in the same thread group that fail to modify the mark bit can try again to modify the mark bit of the sub-variable area corresponding to the thread group.

[0093] Optionally, the grouping of threads can be based on thread IDs, for example, threads 0 to 9 belong to group 1, threads 10 to 19 belong to group 2, threads 20 to 29 belong to group 3, etc.; the grouping of threads can also be based on identifying the group of the threads when they are created, for example, the threads created by CPU1 are identified as group 1, the threads created by CPU2 are identified as group 2, the threads created by CPU3 are identified as group 3, etc.

[0094] S504: If the target thread successfully modifies the mark bit, the target thread is allowed to read the target data.

[0095] Specifically, if a thread in the plurality of thread groups successfully modifies the mark bit when attempting to modify the mark bit, a request to read the target data may be applied for through the thread, that is, the thread is allowed to read the target data.

[0096] For ease of understanding, Figure 6In the example of dividing the global variable (lock state variable) into 4 sub-variable areas, when multiple threads are grouped, they can be divided into 4 groups (including Group 1, Group 2, Group 3 and Group 4). Exemplarily, the threads in Group 1 can modify the mark bit (read lock count bit) in Partition 1, the threads in Group 2 can modify the mark bit in Partition 2, and so on. In other words, when the threads in Group 1 apply to read the target data, it is equivalent to applying for a read lock. The thread can judge the lock state of the 2 bytes corresponding to the thread group (for example, Partition 1) according to the group of the thread group to which it belongs, determine whether no thread holds the write lock, and then modify the read lock count bit of the 2 bytes (such as an atomic plus 1 operation). If the modification is successful, the thread holds the read lock. Corresponding to the application for read is the release. When the thread in the first group wants to release the target data, it is equivalent to applying for a read lock. The thread modifies the read lock count bit of the 2 bytes (partition 1) corresponding to the thread group according to the group of its own thread group (atomic minus 1 operation). If the modification is successful, the thread releases the read lock.

[0097] In a possible implementation, each of the above sub-variable areas may also include a control status bit, and the control status bit is used to indicate whether the target data is exclusively owned. Still taking the global variable as a lock state variable as an example, the control status bit is a write lock status bit, which is used to indicate whether a thread holds a write lock. Figure 6 The structure of the lock state variable partition shown in the figure includes a write lock state bit in addition to the read lock count bit in each partition. In addition to steps S501-S504, the above method may also include steps S505 and S506, wherein:

[0098] S505: When a first thread of a target thread group among the multiple thread groups applies for exclusive use of the target data, the first thread is authorized to modify the control state bit of each sub-variable area respectively.

[0099] S506: If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively occupy the target data.

[0100] Specifically, if a thread in the above-mentioned multiple thread groups applies for exclusive use of the above-mentioned target data, the thread needs to modify the control status bit in each sub-variable area. If the thread successfully modifies the control status bit, the thread can apply for exclusive use of the above-mentioned target data, that is, the thread is allowed to exclusively use the above-mentioned target data. Figure 6The global variable shown in is a lock state variable, which is 8 bytes long. The four sub-variable areas are all 2 bytes. As an example, the control state bit is a write lock state bit. When a thread in the above-mentioned multiple thread groups applies for exclusive use of the target data, it is equivalent to applying for a write lock. The thread needs to perform a lock state judgment on the 8 bytes to determine whether no thread holds a write lock or a read lock, and then modify the write lock state bit in each 2-byte partition (such as an atomic plus 1 operation). If the modification is successful, the thread holds the write lock. Corresponding to the exclusive application is the exclusive release. When a thread wants to release the exclusive use of the target data, it is equivalent to applying for a write lock release. The thread modifies the write lock state bit in each 2-byte partition (such as an atomic minus 1 operation). If the modification is successful, the thread releases the write lock.

[0101] In a possible implementation, the above method may further include step S507 in addition to steps S501 to S506, wherein:

[0102] S507: Determine the total number of threads that can currently read the target data according to the status of the mark bit in each sub-variable area.

[0103] Specifically, when it is necessary to count the total number of threads currently allowed to read the target data, it can be determined according to the flag bit state of each sub-variable area. Figure 6 The global variable shown in is the lock state variable, which is 8 bytes long. The four sub-variable areas are all 2 bytes. As an example, when you need to determine the total number of threads currently holding a read lock, you can add the number of threads holding a read lock represented by the read lock count bit in each sub-variable area to get the total number of threads holding a read lock. For example, the read lock count bit of partition 1 indicates that 3 threads hold a read lock, partition 2 indicates that 5 threads hold a read lock, partition 3 indicates that 2 threads hold a read lock, and partition 4 indicates that 2 threads hold a read lock. The total number of threads holding a read lock is 12.

[0104] Optionally, in some scenarios, such as when the read-write lock is in the read lock state, and another thread attempts to apply for a write lock, the request to apply for a write lock will fail, and the thread may temporarily sleep. After the thread applies for a write lock, the read-write lock usually blocks subsequent read lock requests to avoid long-term occupation of the read lock state, which causes the thread requesting the write lock to wait for a long time. When the last thread holding the read lock releases the read lock, that is, when it is determined that the total number of threads that can currently read the above target data is 0, the thread that previously failed to apply for a write lock and temporarily sleeps can be awakened, and then through the write lock request of this thread, it is allowed to hold the write lock, allowing it to read, write, and other operations on the above target data.

[0105] It should be noted that in low-concurrency scenarios, that is, when the lock-reading conflicts are not obvious, the embodiments of the present application may not significantly change the performance of the computer system. However, in high-concurrency scenarios, that is, when the lock-reading conflicts between multiple threads are obvious, the more sub-variable areas that can be independently modified during the lock-reading operations, the more threads that can successfully complete the lock-reading operations, and the more obvious the performance benefits obtained by the computer system. See Figure 7 , Figure 7 4 threads are read at the same time, and the 4 threads are divided into 2 groups, each with 2 threads. The current value is read from the memory storing the lock state variable, and the old value and the new value are the input values ​​of the CAS operation. In the two rounds of concurrent CAS operations, there are 4 valid CAS operations and 2 invalid CAS operations. Figure 3 The 6 times in the example are reduced to 2 times, and the number of concurrent rounds is also reduced from 4 rounds to 2 rounds. Among them, when threads 1 and 2 in group 1 simultaneously add read locks (the first round of concurrency), only one thread (for example, thread 1) can successfully modify the mark bit of the sub-variable area corresponding to the thread group; then thread 2 can immediately retry the process of adding read locks (the second round) according to the latest value of the current sub-variable area, and successfully modify the mark bit of the sub-variable area and hold the read lock. Similarly, when threads 3 and 4 in group 2 are concurrent in the first round, one of the threads (for example, thread 3) successfully modifies the mark bit and holds the read lock; then the other thread can successfully modify it in the second round and also holds the read lock.

[0106] Furthermore, if the four threads are divided into four groups, with one thread in each group, that is, the four threads are in different thread groups, when these four threads apply for read locks concurrently, the mark bit of the sub-variable area corresponding to each thread group can be modified. At this time, from the perspective of the sub-variable area, only one thread applies to modify the mark bit. Therefore, these four threads can successfully modify the mark bit of the sub-variable area in one round of concurrency, that is, the number of modification operation failures is 0.

[0107] When the embodiments of the present application are applied to other scenarios that implement similar read and write functions (such as pinbuffer / unpinbuffer), the performance of the computer system can also be greatly improved. The pinbuffer / unpinbuffer function implements similar read and write functions, and can share, monopolize, and control other status identification of data pages. Among them, sharing uses a sharing count (similar to adding and reading locks), and each time a thread queries a data page, it needs to add a read lock to the index root directory page. In the Kunpeng 2P+openGauss (open source Gauss) scenario, the concurrent shared access to the same page is extremely large. If the multi-threaded concurrency management method of the embodiments of the present application is not adopted, the performance of the computer system can be seen. Figure 8 , Figure 8 This is a performance analysis perf flame graph provided by an embodiment of the present application, wherein when the query performance of openGauss reaches 1.1 million queries per second (QPS), the atomic operation instruction overhead of unlocking and decoding exceeds 50%, and the CPU is fully loaded.

[0108] When the multithreaded concurrent management method of the embodiment of the present application is adopted, two sub-variable areas are divided, two thread groups are divided, and the flag bits of the sub-variable areas are modified in two ways, the performance of the computer system can be seen in Fig. 9 , Fig. 9 This is another performance analysis perf flame graph provided by an embodiment of the present application, in which the query performance of openGauss is improved to 1.2 million QPS, and the atomic operation instruction overhead of unlocking and decoding has been reduced to 39.5%.

[0109] Furthermore, when the sub-variable areas are divided into 6 sub-variable areas, 6 thread groups are divided, and the flag bits of the sub-variable areas are modified in 6 ways, the performance of the computer system can be seen in Fig.10 , Fig.10 This is another performance analysis perf flame graph provided by the embodiment of the present application, in which the query performance of openGauss is improved to 1.56 million QPS, and the atomic operation instruction overhead of unlocking and decoding has been reduced to 14%. Figure 8 As shown in the figure, openGauss' query performance has increased by 41%, and its encryption and decoding performance has increased by 5 times.

[0110] In summary, the present application proposes a multi-threaded concurrent management method, which divides the global variable used to control multi-threaded access to shared data into multiple areas, divides the multiple threads applying to read the shared data into multiple thread groups, and makes one thread group correspond to one variable area, and different thread groups correspond to different variable areas, so that when threads in different thread groups apply to read shared data, they can obtain the permission to read the shared data by modifying the value of the corresponding variable area. Among them, when applying to read shared data, the modification of the values ​​of different variable areas between threads in different thread groups is independent, so that the value of each variable area can be modified successfully respectively, that is, in one round of concurrent modification, multiple threads can be modified successfully. Therefore, when the above method is applied to the scenario of multi-threaded concurrent CAS operation, if multiple threads apply to read shared data, and concurrent CAS operations modify the values ​​of different variable areas, multiple CAS operations can be successful, which improves the success rate of CAS operation.

[0111] The method of the embodiment of the present application is described in detail above. The following is a brief description of the related devices of the embodiment of the present application.

[0112] See also Fig.11, Fig.11 1 is a schematic diagram of the structure of a multi-threaded concurrent management device provided in an embodiment of the present application. The device 110 may include a first processing unit 1101, a second processing unit 1102, and a third processing unit 1103, and may also include a determination unit 1104. The detailed description of each unit is as follows:

[0113] The first processing unit 1101 is used to divide the target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each of the plurality of sub-variable areas includes one or more flag bits;

[0114] The second processing unit 1102 is used to divide the multiple threads into multiple thread groups; the multiple threads are used to apply for permission to read the target data;

[0115] Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one;

[0116] The third processing unit 1103 is configured to allow the target thread to read the target data if the target thread successfully modifies the mark bit.

[0117] In a possible implementation manner, the device further includes:

[0118] The determining unit 1104 is configured to determine the total number of threads that can currently read the target data according to the status of the flag bit in each sub-variable area.

[0119] In a possible implementation, when a target thread group among the multiple thread groups includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify a flag bit in a target sub-variable area corresponding to the target thread group.

[0120] In a possible implementation, the second processing unit 1102 is specifically configured to:

[0121] If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the mark bit in the target sub-variable area through a compare and exchange (CAS) operation.

[0122] In a possible implementation, each of the sub-variable regions further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the second processing unit 1102 is further used to authorize the first thread to modify the control status bit of each sub-variable region respectively when the first thread of the target thread group among the multiple thread groups applies for exclusive use of the target data;

[0123] The third processing unit 1103 is further configured to allow the first thread to exclusively occupy the target data if the first thread successfully modifies the control status bit.

[0124] In a possible implementation, the second processing unit 1102 is specifically configured to:

[0125] If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0126] In a possible implementation, the global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

[0127] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0128] It should be noted that the functions of each functional unit / module in the multi-threaded concurrency management device described in the embodiments of the present application can be found in the relevant description in the above method embodiments, and will not be repeated here.

[0129] like Fig.12 As shown, Fig.12 1 is a schematic diagram of the structure of another multi-threaded concurrent management device provided in an embodiment of the present application, wherein the device 120 includes at least one processor 1201, at least one memory 1202, and at least one communication interface 1203. In addition, the device may also include common components such as an antenna, which will not be described in detail here.

[0130] The processor 1201 may be a general purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above program.

[0131] The communication interface 1203 is used to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), core network, wireless local area networks (WLAN), etc.

[0132] The memory 1202 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0133] The memory 1202 is used to store application code for executing the multi-thread concurrent management method described above, and the execution is controlled by the processor 1201. The processor 1201 is used to execute the application code stored in the memory 1202.

[0134] The code stored in the memory 1202 can execute the above Figure 5 The provided multi-threaded concurrent management method includes, for example, dividing a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each of the plurality of sub-variable areas includes one or more flag bits; dividing a plurality of threads into a plurality of thread groups; the plurality of threads are used to apply for permission to read the target data; authorizing a target thread in a target thread group to modify the flag bit in a target sub-variable area; the target thread group is one of the plurality of thread groups, the target sub-variable area is one of the plurality of sub-variable areas, and a thread group in the plurality of thread groups corresponds to a sub-variable area in the plurality of sub-variable areas in one-to-one correspondence; if the target thread successfully modifies the flag bit, the target thread is allowed to read the target data.

[0135] It should be noted that the functions of the various functional units in the multi-threaded concurrent management device 120 described in the embodiment of the present application can be referred to in the above Figure 5 The descriptions of steps S501 to S504 in the method embodiment are not repeated here.

[0136] It should be noted that the multi-threaded concurrent management device described in this application is not limited to this. The multi-threaded concurrent management device can be located in any electronic device, such as a server, a computer, a mobile phone, a tablet, and other devices. The multi-threaded concurrent management device can specifically be a chip or a chipset or a circuit board equipped with a chip or a chipset. The chip or chipset or the circuit board equipped with a chip or a chipset can work under the necessary software drive. For example, the multi-threaded concurrent management device can be:

[0137] (1) Independent integrated circuit IC, chip, chip system or subsystem;

[0138] (2) having a set of one or more ICs, and optionally, the IC set may also include a storage component for storing data and computer programs;

[0139] (3) Modules that can be embedded in other devices;

[0140] (4)Others

[0141] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When the above-mentioned processor executes the computer program code, the computer executes the method in any of the above-mentioned embodiments.

[0142] The embodiment of the present application also provides an electronic device, which can exist in the form of a chip product, and the electronic device includes a processor, and the processor is configured to support the electronic device to implement the corresponding functions of the method in any of the above embodiments. The electronic device may also include a memory, which is coupled to the processor and stores the necessary program instructions and data of the electronic device. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

[0143] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the method in any of the aforementioned embodiments.

[0144] The embodiment of the present application provides a chip system, which includes a processor for supporting a device to implement the functions involved in the first aspect, for example, generating or processing the information involved in the multi-threaded concurrent management method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0145] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0147] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0148] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0149] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0150] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods in each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (read-only memory, abbreviated: ROM) or random access memory (random access memory, abbreviated: RAM) and other media that can store program codes.

[0151] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-threaded concurrent management method, characterized in that: The method comprises: Dividing a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, each of the plurality of sub-variable areas comprising one or more flag bits; Dividing a plurality of threads into a plurality of thread groups; the plurality of threads are used to apply for permission to read the target data; Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one; If the target thread successfully modifies the mark bit, the target thread is allowed to read the target data.

2. The method according to claim 1, characterized in that The method further comprises: The total number of threads that can currently read the target data is determined by the state of the mark bit in each sub-variable area.

3. The method according to any one of claims 1-2, wherein when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

4. The method according to any one of claims 1 to 3, characterized in that The target thread in the target thread group is authorized to modify the mark bit in the target sub-variable area, including: If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

5. The method according to any one of claims 1 to 4, characterized in that Each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the method further includes: When the first thread of the target thread group applies for exclusive use of the target data, authorizing the first thread to modify the control state bit of each sub-variable area respectively; If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively occupy the target data.

6. The method according to claim 5, characterized in that The authorizing the first thread to modify the control status bit of each sub-variable area respectively includes: If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

7. The method according to any one of claims 1 to 6, characterized in that The global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

8. The method according to any one of claims 5 to 6, characterized in that: The global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

9. A multi-thread concurrent management device, characterized in that: include: A first processing unit is used to divide a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each of the plurality of sub-variable areas includes one or more flag bits; A second processing unit, configured to divide the plurality of threads into a plurality of thread groups; The multiple threads are used to apply for permission to read the target data; Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one; The third processing unit is configured to allow the target thread to read the target data if the target thread successfully modifies the mark bit.

10. The device according to claim 9, characterized in that The device also includes: A determination unit is used to determine the total number of threads that can currently read the target data according to the state of the mark bit in each sub-variable area.

11. The device according to any one of claims 9 to 10, characterized in that When the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

12. The device according to any one of claims 9 to 11, characterized in that The second processing unit is specifically configured to: If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

13. The device according to any one of claims 9 to 12, characterized in that Each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the second processing unit is further used to authorize the first thread to modify the control status bit of each sub-variable area respectively when the first thread of the target thread group applies for exclusive use of the target data; The third processing unit is further configured to allow the first thread to exclusively occupy the target data if the first thread successfully modifies the control status bit.

14. The device according to claim 13, characterized in that The second processing unit is specifically configured to: If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

15. The device according to any one of claims 9 to 14, characterized in that The global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

16. The device according to any one of claims 13 to 14, characterized in that The global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

17. A multi-thread concurrent management device, characterized in that: The method comprises a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices and transmit them to the processor or send signals from the processor to other communication devices, and the processor is used to implement the method as described in any one of claims 1 to 8 through a logic circuit or executing code instructions.

18. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or instruction. When the computer program or instruction is executed by the communication device, the method according to any one of claims 1 to 8 is implemented.

19. A computer program, characterized in that The computer program comprises instructions, and when the computer program is executed by a communication device, the method according to any one of claims 1 to 8 is implemented.

20. A server, characterized in that: The server comprises a processor and a memory, wherein the memory is used to store program codes, and when the program codes are executed by the processor, the server implements the method according to any one of claims 1 to 8.

21. A chip system, characterized in that: The chip system includes a processor for supporting the device to implement the functions involved in the method as described in any one of claims 1-8.

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