Memory system and method of controlling memory device

Abstract

A memory system and a method of controlling a memory device are disclosed. The method includes: reading first read data from a memory device; correcting bits of a first memory region in which an error has occurred in the first read data, and inverting bits of a second memory region in which no error has occurred; identifying a first error type in the first memory region and a second error type in the second memory region, the second error type being different from the first error type; and writing the second write data having the smallest error to the memory device based on at least one of the first error type and the second error type.

Description

[0001] This application is a divisional application of the invention patent application with application number 202010326380.3 and invention name “Memory controller, memory system and method for operating a memory controller” submitted to the State Intellectual Property Office on April 23, 2020.

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0049828 filed on April 29, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a memory controller, and more particularly, to a memory controller for identifying errors in data written to a memory cell and avoiding the identified errors, a memory system including the memory controller, and a method of operating the memory controller. Background Art

[0004] As a non-volatile memory device, in addition to flash memory, resistive memory (such as phase change random access memory (PRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), etc.) is also well known in the art. Resistive memory has the non-volatile characteristics of flash memory and the high-speed characteristics of dynamic RAM (DRAM).

[0005] When a memory cell of a nonvolatile memory device wears out, a data bit may be stuck at 0 or 1. In this case, in response to a read request from a host, a data bit having a value different from the value of a data bit that has been previously written may be read out. For example, even if 0 is written to a memory cell in which a data bit is stuck at 1, 1 may be read out in response to a read request. Summary of the invention

[0006] The present disclosure provides a memory controller for determining a type of error in data written to a memory cell and avoiding a predetermined error, a memory system including the memory controller, and a method of operating the memory controller.

[0007] According to one aspect of the present disclosure, a memory controller for controlling memory operations of a memory device is provided, the memory controller comprising: an error correction code (ECC) circuit configured to: detect an error in first read data read from the memory device and correct the error; an error type detection logic configured to: write first write data into the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparison, and output information about an error type identified by the error bit; and a data patterning logic configured to: change a bit pattern of input data based on the information about the error type to reduce an error in the second read data, wherein the first write data is data in which the error of the first read data is corrected, and the second read data is data obtained by reading the first write data written into the memory device.

[0008] According to another aspect of the present disclosure, a method for operating a memory controller for controlling a memory device is provided, the method comprising: reading first read data from the memory device; correcting bits of a first memory region in which an error has occurred in the first read data, and inverting bits of a second memory region in which no error has occurred; identifying a first error type in the first memory region and a second error type in the second memory region, the second error type being different from the first error type; and writing second write data having a minimum error to the memory device based on at least one of the first error type and the second error type.

[0009] According to another aspect of the present disclosure, a memory system is provided, comprising: a memory device comprising a plurality of memory areas, each of the plurality of memory areas comprising at least one memory cell; and a memory controller configured to: control memory operations of the memory device, wherein the memory controller is configured to: read first read data stored in a first memory area and a second memory area from the memory device, perform a correction operation on data of the first memory area in which an error has occurred in the first read data, perform an inversion operation on data of the second memory area in which no error has occurred in the first read data, generate first write data based on the correction operation and the inversion operation, perform a comparison operation of comparing the first write data with second write data obtained by reading the first write data, and identify a plurality of error types based on the comparison operation.

[0010] According to another aspect of the present disclosure, a memory system having a memory device and a memory controller is provided. The memory controller: identifies a first memory component having a fault within the memory device, modifies write data received from a host device to generate modified data based on the first memory component and the fault, and stores the modified data in the memory device so that a first value within the modified data is stored in the first memory component. The memory controller modifies the write data to increase the likelihood that the first value matches a value generated by the fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram of a memory system according to an embodiment of the present disclosure.

[0013] Figure 2A and Figure 2B is a diagram for explaining a memory cell array according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram for explaining a process in which an error correction code (ECC) circuit and an error type detection logic cooperate with each other according to an embodiment of the present disclosure.

[0015] Figure 4 : is a diagram for explaining a process in which an error type detection logic and a data patterning logic cooperate with each other according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram for explaining data transferred in a memory system according to an embodiment of the present disclosure.

[0017] Figure 6 is a diagram for explaining an error type and a stagnation value, which are identified according to errors generated in first read data and second read data according to an embodiment of the present disclosure.

[0018] Figure 7 is a block diagram for illustrating data patterning logic according to an embodiment of the present disclosure.

[0019] Figure 8 is a diagram for explaining an operation of a memory system according to an embodiment of the present disclosure to randomize data received from a host and write the randomized data into a memory device.

[0020] Fig. 9 is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0021] Fig.10 and Fig.11 is a flowchart illustrating a method of operating a memory controller to determine an error type of data written to a memory cell according to an embodiment of the present disclosure.

[0022] Fig.12 is a flow chart illustrating a method of operating a memory controller to randomize data received from a host based on an error type according to an embodiment of the present disclosure.

[0023] Fig.13 is a block diagram of a memory controller according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram of a memory system 10 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a plurality of memory areas (e.g., a first memory area 210_1 to an Nth memory area 210_N). The memory controller 100 may control memory operations of the first memory area 210_1 to the Nth memory area 210_N. For example, a predetermined unit of data may be written to the first memory area 210_1 to the Nth memory area 210_N in a dispersed manner, or a predetermined unit of data may be read from the first memory area 210_1 to the Nth memory area 210_N. Each memory area may indicate one memory cell, or may indicate a plurality of memory cells. For example, a memory area may indicate a plurality of memory cells (such as a bank, a bay, a tile, a block, or a page).

[0027] According to an embodiment of the present disclosure, the memory device 200 may include a plurality of memory chips, and each of the first to N-th memory regions 210_1 to 210_N may correspond to a memory chip. Each memory chip may include a memory cell array for storing data and a peripheral circuit (e.g., a write / read circuit and control logic) for performing a memory operation.

[0028] Each of the first to N-th memory regions 210_1 to 210_N may include a plurality of memory cells respectively arranged in regions where the plurality of first signal lines and the plurality of second signal lines intersect. In one embodiment, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines. Each of the plurality of memory cells may be a single-level cell (SLC) storing one bit, or may be a multi-level cell (MLC) capable of storing two or more bits of data.

[0029] When one bit of data is written to one memory cell, the memory cell may have two resistance distributions according to the written data. Alternatively, when two bits of data are written to one memory cell, the memory cell may have four resistance distributions according to the written data. In another embodiment, in the case of a triple-layer cell (TLC) in which three bits of data are stored in one memory cell, the memory cell may have eight resistance distributions according to the written data. However, the present disclosure is not limited thereto, and in other embodiments, the memory cell may include a memory cell capable of storing four bits of data or more bits of data, respectively.

[0030] Each of the first memory region 210_1 to the Nth memory region 210_N may include a resistive memory cell, each of which includes a variable resistance element. For example, when the variable resistance element is a phase change material (e.g., Ge-Sb-Te (GST)) and the resistance of the variable resistance element changes with temperature, the resistive memory device may be a phase change random access memory (PRAM). As another example, when the variable resistance element includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the resistive memory device may be a resistive RAM (RRAM). As another example, when the variable resistance element includes an upper electrode of a magnetic body, a lower electrode of a magnetic body, and a dielectric therebetween, the resistive memory device may be a magnetic RAM (MRAM).

[0031] According to one embodiment of the present disclosure, when the memory device 200 includes a resistive memory cell, the memory device 200 may be referred to as a resistive memory device. Alternatively, in one embodiment of the present disclosure, the memory device 200 may include various types of memory cells, and when the memory cells are arranged in an area where a plurality of first signal lines intersect with a plurality of second signal lines, the memory device 200 may be referred to as a cross-point memory device. In the following embodiments, it is assumed that the memory device 200 is a resistive memory device, but the embodiments of the present disclosure may be applicable to various types of memory devices in which the data of the memory cell may be stagnant at a specific value. As an example, the embodiments of the present disclosure may be applied to various types of memory devices (such as volatile memory devices and flash memory devices).

[0032] In various implementations, the memory device 200 may be a memory module in which a plurality of memory chips are mounted on a module board. Alternatively, the memory device 200 may be a semiconductor package including a plurality of memory chips, the memory chips may be stacked in a bare die form in the semiconductor package, and each of the first to N-th memory regions 210_1 to 210_N may be a memory chip included in the semiconductor package.

[0033] Alternatively, the memory device 200 may be one semiconductor chip including a plurality of semiconductor layers. In this case, each of the first to N-th memory regions 210_1 to 210_N may be a semiconductor layer. Alternatively, when the memory device 200 includes one semiconductor layer and the semiconductor layer includes a memory cell array including a plurality of cell blocks, each of the first to N-th memory regions 210_1 to 210_N may correspond to a cell block.

[0034] The memory controller 100 may include a processor 110 , an error correction code (ECC) circuit 120 , an error type detection logic 130 , and a data patterning logic 140 , and the memory controller 100 may control memory operations in a hardware-, software-, or combination-based manner.

[0035] The memory controller 100 may control the memory device 200 to read data stored in the memory device 200 or write data to the memory device 200 in response to a write / read request from the host. Specifically, the memory controller 100 may control a program (or write) operation, a read operation, and an erase operation of the memory device 200 by providing an address ADD, a command CMD, and a control signal CTRL to the memory device 200. In addition, data DTA to be written to the memory device 200 and data DTA to be read from the memory device 200 may be transmitted and received between the memory controller 100 and the memory device 200.

[0036] According to various embodiments, the memory controller 100 may include a RAM, a host interface, and a memory interface. The RAM may be used as an operating memory of the processor 110. The processor 110 may control the overall operation of the memory controller 100. The host interface may include a protocol for performing data exchange between the host and the memory controller 100. For example, the memory controller 100 may be configured to communicate with the host via at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect-express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small device interface (ESDI), and an integrated drive electronics (IDE).

[0037] The memory controller 100 may read first read data from the memory device 200. The ECC circuit 120 may perform error detection and error correction on the first read data. In addition, the ECC circuit 120 may send information about error-corrected data and data bits having errors to the error type detection logic 130.

[0038] The error type detection logic 130 may output the first write data obtained by inverting some data bits included in the received data to the memory device 200 to write the first write data to the memory device 200. In addition, the error type detection logic 130 may read the written first write data to identify the error type. In this case, the read first write data is referred to as the second read data. The data bits of the first write data and the data bits of the second read data may be different from each other. For example, when some memory cells are worn and the data is in a stuck state, a stuck error may occur in some data bits of the first write data. That is, the stuck error may be an error that outputs the same value regardless of the value of the data written to the memory cell due to physical or structural changes in the memory cell. For example, data bit 1 is written, but data bit 0 may be read. Therefore, by comparing the first write data with the second read data, the data bit with an error and the memory cell causing the error may be identified. For example, the first write data may be stored in a memory inside the error type detection logic 130 or in an external memory, and the first write data may be read from the memory to be compared with the second read data. According to the embodiments described below, the memory controller 100 may identify the type of error and the stuck value.

[0039] A temporary error may be caused by a drift of the distribution according to the accumulation of memory operations, interference between a read operation and a write operation, etc. For example, when the memory controller 100 performs an operation (e.g., reclaim) of rewriting the same data to a memory cell included in the memory device 200, the temporary error may be resolved. As another example, the temporary error may indicate that a data bit having an error is output in a first read process, but a normal bit is output in a second read process performed after the first read process.

[0040] The memory controller 100 may pattern the data HDTA received from the host based on the information about the recognized error type and the information about the memory region where the error has occurred.

[0041] According to one embodiment, the data patterning logic 140 may randomize the received data HDTA based on a random seed. The randomized data may have data bits in each of a plurality of memory regions. In this case, some of the memory regions may be memory regions where a stagnation error has occurred. Each of the memory regions where a stagnation error has occurred may have a predetermined stagnation value. Therefore, when, among the data bits included in the data randomized by the data patterning logic 140, the data bits included in the memory region where a stagnation error has occurred have a high degree of consistency with the stagnation value, it can be seen that the error is reduced. That is, the data patterning logic 140 can reduce the error by selecting data having the highest degree of consistency with the stagnation value from the randomized data.

[0042] Then, the data patterning logic 140 may output the selected randomized data to the memory device 200. In this case, the data patterning logic 140 may add parity for decoding the randomized data to the randomized data.

[0043] Figure 2A and Figure 2B is a view for explaining a memory cell array according to an embodiment of the present disclosure. Figure 2A and Figure 2B An example where the resistive memory cell is a PRAM is shown.

[0044] Reference Figure 2A ,and Figure 1 The memory cell array of the first memory area 210_1 corresponding to the first memory area 210_1 in the memory cell array may be a two-dimensional memory cell array having a horizontal structure, and may include a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells MC. The memory cell array may include a plurality of memory blocks. Each memory block may have a structure in which a plurality of memory cells are arranged in rows and columns. The number of word lines WL, the number of bit lines BL, and the number of memory cells MC may vary according to the embodiment. However, the present disclosure is not limited thereto, and in another embodiment, the first memory area 210_1 may be a three-dimensional (3D) memory cell array having a vertical structure.

[0045] According to the present embodiment, each of the plurality of memory cells MC may include a variable resistance device R and a switch device SW. The variable resistance device R may be referred to as a variable resistance material, and the switch device SW may be referred to as a selection device.

[0046] In one embodiment, the variable resistance device R may be connected between one of the plurality of bit lines BL1 to BLm and the switching device SW, and the switching device SW may be connected between the variable resistance device R and one of the plurality of word lines WL1 to WLn. However, the present disclosure is not limited thereto, and the switching device SW may be connected between one of the plurality of bit lines BL1 to BLm and the variable resistance device R, and the variable resistance device R may be connected between the switching device SW and one of the plurality of word lines WL1 to WLn.

[0047] The switching device SW may be connected between one of the plurality of word lines WL1 to WLn and the variable resistance device R, and may control supply of current to the variable resistance device R according to voltages applied to the connected word line and bit line. Figure 2A , the switching device SW is illustrated as a diode, but the present disclosure is not limited thereto, and according to another embodiment, the switching device SW may include another switching device.

[0048] Reference Figure 2B , the memory cell MC may include a variable resistance device R and a switching device SW. The switching device SW may include various devices (such as a transistor, a diode, etc.). The variable resistance device R may include a phase change layer 11 including a mixture of germanium, antimony, and tellurium (Ge-Sb-Te (GST)), an upper electrode 12 on the phase change layer 11, and a lower electrode 13 below the phase change layer 11.

[0049] The upper electrode 12 and the lower electrode 13 may include various metals, metal oxides, or metal nitrides. The upper electrode 12 and the lower electrode 13 may include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAlyNz), iridium (Ir), platinum (Pt), silver (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO 2 ), strontium zirconate (SrZrO 3 )wait.

[0050] The phase change layer 11 may include a bipolar resistance memory material or a unipolar resistance memory material. The bipolar resistance memory material is programmed to a set state or a reset state according to the polarity of an applied current, and may include a perovskite-based material. The unipolar resistance memory material is programmed to a set state or a reset state by a current having the same polarity, and may include a transition metal oxide such as NiOx or TiOx.

[0051] The GST material can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. The GST material can be programmed by heating the GST material. The amplitude and time of heating can determine whether the GST material remains in the amorphous state or the crystalline state. High resistivity and low resistivity can be represented by programming values ​​(i.e., logic 0 and logic 1), respectively, and can be detected by measuring the resistivity of the GST material. Conversely, high resistivity and low resistivity can be represented by programming values ​​(i.e., logic 1 and logic 0), respectively.

[0052] exist Figure 2B In the embodiment, when the write current I is applied to the memory cell MC, the write current I flows through the lower electrode 13. When the write current I is applied to the memory cell MC for a very short period of time, the phase change layer 11 adjacent to the lower electrode 13 is heated only by Joule heat. Here, due to the change in the heating curve, the phase change layer 11 may be partially in a crystalline state (or set state) or an amorphous state (or reset state).

[0053] Figure 3 1 is a diagram for explaining a process in which an ECC circuit and an error type detection logic cooperate with each other according to an embodiment of the present disclosure. Figure 1 and Figure 3 The following description is given.

[0054] The memory controller 100 may read the first read data RD1 from the memory device 200. For example, the first read data RD1 may be data written to at least one of the first memory area 210_1 to the Nth memory area 210_N. The ECC circuit 120 may perform an error detection operation and an error correction operation on the first read data RD1. For example, the first read data RD1 may be a codeword combining a data bit and a parity bit, and as another example, the first read data RD1 may include a data bit.

[0055] According to one embodiment of the present disclosure, when error correction fails, the ECC circuit 120 may perform a read retry operation by inputting a defensive code. In addition, when error correction is successful, the ECC circuit 120 may write the first write data WD1 to the memory device 200 when the number of error bits exceeds a threshold value. When error correction is successful, the ECC circuit 120 may not write the first write data WD1 to the memory device 200 when the number of error bits is less than or equal to the threshold value. In this case, the ECC circuit 120 may determine that the data is normally written to the memory device 200, thereby keeping the first read data RD1 in the memory device 200.

[0056] The ECC circuit 120 may perform an error detection operation and an error correction operation on the first read data RD1, and output the corrected data CD after the error correction. In addition, the ECC circuit 120 may identify a memory area (or a location of a memory area) where an error has occurred in the memory operation of the memory device 200, and output error bit information EBI. That is, the error bit information EBI may include various types of information that the ECC circuit 120 may derive as a result of performing error detection and error correction. For example, the error bit information EBI may include information about a memory area (or a location of a memory area) where an error has occurred in the first read data RD1, information about an error value, and the like.

[0057] The error type detection logic 130 may output the first write data WD1 in response to receiving the correction data CD and the error bit information EBI. Specifically, the error type detection logic 130 may generate the first write data WD1, which is the inverted data of the data (including the data in the correction data CD) of another memory area other than the error-corrected memory area among the plurality of memory areas. For example, the first read data RD1 may be [0, 1, 1, 0, 1] consisting of 5 bits, and the correction data CD may be [1, 0, 1, 0, 1] in which two error bits are corrected. The first write data WD1 may be [1, 0, 0, 1, 0] in which the last three bits on which the error correction operation is not performed are inverted. The above bits and the number of bits are for convenience of explanation, and the present disclosure is not limited thereto.

[0058] The memory controller 100 may write the first write data WD1 into the memory device 200. Then, the memory controller 100 may write the second read data RD2 (see Figure 4 ) is compared with the first write data WD1 to detect the error type, wherein the second read data RD2 is obtained by reading the first write data WD1 written into the memory device 200. Figure 4 Describe this.

[0059] Figure 4 is a diagram for explaining a process in which an error type detection logic and a data patterning logic cooperate with each other according to an embodiment of the present disclosure.

[0060] Reference Figure 4, the memory controller 100 may read the second read data RD2 by sending a read command to the memory device 200 to read the data in the memory area storing the first write data WD1. In this case, although the second read data RD2 is data obtained by reading the data in the memory area storing the first write data WD1, the second read data RD2 and the first write data WD1 may be different from each other due to various errors. For example, an error may occur in at least one of the data bits of the second read data RD2, and therefore, the second read data RD2 and the first write data WD1 may be different from each other.

[0061] The error type detection logic 130 may perform an operation of comparing the second read data RD2 with the first write data WD1, and identify the error type of the second read data RD2 based on the error bit information EBI. For example, the error type detection logic 130 may identify the error type of each data bit included in the second read data RD2. As another example, by identifying the error type of each data bit included in the second read data RD2, the error type of the memory area corresponding to the data bit where an error has occurred may be identified.

[0062] The error type detection logic 130 may output error type information ETI as information about the identified error type. The error type information ETI may include information about the second read data RD2 and an error type associated with at least one memory region included in the memory device 200. For example, the error type information ETI may include information about the type of error occurring in each memory cell storing a data bit. The error type may include a stall error, a temporary error, and a hidden stall error, and each memory cell may be a normal cell or may have one of the error types. This will be referred to later. Figure 5 and Figure 6 etc. to describe methods for identifying error types.

[0063] The data patterning logic 140 may randomize the data HDTA received from the host based on the error type information ETI. For example, the data HDTA may be new data to be written to the memory device 200. The data patterning logic 140 may select the second write data WD2 containing the least error in the randomized data, and write the second write data WD2 to the memory device 200. According to one embodiment, a parity PA for decoding the randomized data may be generated. For example, the data patterning logic 140 may add the parity PA to the second write data WD2, and send the second write data WD2 with the parity PA to the memory device 200. This will be referred to later. Figure 7 and Figure 8 etc. to describe the details.

[0064] Figure 5 1 is a diagram for explaining data transmitted in a memory system according to an embodiment of the present disclosure. Figure 5 The following description is given. Figure 5 An example is shown in which each data includes five bits and each data bit is 0 or 1, but the present disclosure is not limited thereto. Figure 1 and Figure 5 The following description is given.

[0065] According to an embodiment of the present disclosure, the original data OD written to the memory device 200 may be [1, 0, 1, 0, 1]. The memory controller 100 may read the first read data RD1 based on a read request or an error detection request from the host. For example, the first read data RD1 may be [0, 1, 1, 0, 1].

[0066] An error may occur in the data included in the first memory area 31 of the first read data RD1, while an error may not occur in the data included in the second memory area 32 of the first read data RD1. For example, the first memory area 31 may be an area including the first data bit and the second data bit, and the second memory area 32 may be an area including the remaining data bits. In this case, the ECC circuit 120 may detect that an error has occurred in the data included in the first memory area 31, and perform error correction by using a parity bit included in the first read data RD1 or outside the first read data RD1.

[0067] The ECC circuit 120 may perform error detection and error correction on the first read data RD1 and output correction data CD. Specifically, the ECC circuit 120 may correct errors included in the first memory area 31 and maintain data included in the second memory area 32. For example, the correction data CD may be [1, 0, 1, 0, 1] and may be the same as the original data OD.

[0068] The error type detection logic 130 may generate the first write data WD1. Specifically, the error type detection logic 130 may maintain the data of the first memory area 31 that is corrected in the correction data CD. In addition, the error type detection logic 130 may invert the data of the second memory area 32 that is not corrected in the correction data CD. For example, the data bits [1, 0, 1] that are not corrected in the correction data CD may be inverted to [0, 1, 0], and the inverted data bits may be included as part of the first write data WD1. The error type detection logic 130 may generate the first write data WD1 to perform an operation of comparing the first write data WD1 with the second read data RD2.

[0069] The error type detection logic 130 may output the first write data WD1 to be written to the memory device 200. Then, the memory controller 100 may read the second read data RD2 based on a request received from the host or a signal generated in the memory controller 100. The memory controller 100 may identify the location where the first write data WD1 is written to the memory device 200, and read the second read data RD2 as data included in the location. For example, the memory controller 100 may read the second read data RD2 based on the address ADD of the memory device 200 where the first write data WD1 is written. Specifically, the error type detection logic 130 may compare data bits located at the same address ADD with each other.

[0070] The error type detection logic 130 may perform a comparison operation of comparing the first write data WD1 with the second read data RD2. According to one embodiment, the comparison operation may include a first partial comparison operation and a second partial comparison operation. The first partial comparison operation may be an operation of comparing data of the first memory region 31 of the first write data WD1 with data of the first memory region 31 of the second read data RD2. The second partial comparison operation may be an operation of comparing data of the second memory region 32 of the first write data WD1 with data of the second memory region 32 of the second read data RD2.

[0071] According to one embodiment of the present disclosure, the error type detection logic 130 may compare the data bits of the first write data WD1 included in the first memory region 31 with the data bits of the second read data RD2 included in the first memory region 31. Figure 5 , the data bits of the first memory area 31 of the first write data WD1 may be [1, 0], and the data bits of the first memory area 31 of the second read data RD2 may be [0, 0].

[0072] The error type detection logic 130 may recognize that a stall error has occurred in the memory cell corresponding to the first partial region 41. Specifically, this is because, in the first partial region 41, the data bit [0] of the first read data RD1 and the data bit [1] of the original data OD are different from each other, and the data bit [0] of the second read data RD2 read again after the first read data RD1 is read is also different from the data bit [1] of the first write data WD1. Each of the plurality of partial regions (i.e., the first partial region 41 to the fifth partial region 45) may correspond to one memory cell, or may correspond to a plurality of memory cells. The operation of comparing the first write data WD1 with the second read data RD2 may be referred to as a comparison operation, and the operation of comparing a partial region of the first write data WD1 (e.g., the first partial region 41) with a partial region of the second read data RD2 that is the same as the partial region of the first write data WD1 may be referred to as a partial comparison operation.

[0073] The error type detection logic 130 may recognize that a temporary error has occurred in the memory cell corresponding to the second partial area 42. Specifically, this is because, in the second partial area 42, the data bit [1] of the first read data RD1 and the data bit [0] of the original data OD are different from each other, but the data bit [0] of the second read data RD2 read again after the first read data RD1 is read is the same as the data bit [0] of the first write data WD1. That is, the temporary error may be an error that occurs temporarily only in the process of reading the first read data RD1.

[0074] The error type detection logic 130 may recognize that the memory cells corresponding to the third partial area 43 and the fourth partial area 44 are normal because no error occurs in any of the first read data RD1 and the second read data RD2.

[0075] The error type detection logic 130 may identify that a stall error has occurred in the memory cell corresponding to the fifth partial area 45. For example, the memory cell of the fifth partial area 45 may be identified as a memory cell in which a hidden stall error in which a data bit is stalled at 1 has occurred. A hidden stall error may be a type of stall error. In the fifth partial area 45, a data bit of the original data OD may be [1], and a data bit of the first read data RD1 obtained by reading the original data OD written in the memory device 200 may also be [1]. However, in the fifth partial area 45, even if a data bit of the first write data WD1 is [0], a data bit of the second read data RD2 obtained by reading the first write data WD1 written in the memory device 200 may also be [1]. That is, the error type detection logic 130 generates the first write data WD1 by inverting some data of the correction data CD to identify a hidden stall error.

[0076] According to an embodiment of the present disclosure, the memory controller 100 can identify whether the memory device 200 has an error, can identify a plurality of error types including a stagnation error and a temporary error, and can also identify a hidden stagnation error that is difficult to detect in a first reading process. When the memory controller 100 identifies various error types, the memory controller 100 can perform an operation to reduce errors occurring in the memory device 200 based on the identified error type. Therefore, data reliability can be improved in a short time using only a single additional read operation and a simple comparison operation.

[0077] The memory controller 100 may: (1) write the second write data WD2 to the same memory cell of the memory device 200 from which the memory controller 100 reads the second read data RD2; (2) read the second read data RD2 from the same memory cell in which the memory controller 100 of the memory device 200 writes the first write data WD1; (3) write the first write data WD1 to the same memory cell in which the memory controller 100 of the memory device 200 reads the first read data RD1; and (4) read the first read data RD1 from the same memory cell in which the memory controller 100 of the memory device 200 writes the original data OD.

[0078] Figure 6 is a diagram for explaining an error type and a stagnation value, which are identified according to errors generated in first read data RD1 and second read data RD2 , according to an embodiment of the present disclosure.

[0079] According to one embodiment of the present disclosure, the error type detection logic 130 may identify the memory cell corresponding to the error data bit in the first read operation and the second read operation as a cell having a stall error. The error type detection logic 130 may determine a stall value of at least one memory cell storing data identified as a stall error. For example, the stall value may be the value of the data bit in the second read data RD2 where a stall error has occurred.

[0080] According to one embodiment of the present disclosure, when a data bit that has an error in the first read operation does not have an error in the second read operation, the error type detection logic 130 may identify the memory cell including the data bit as a cell having a temporary error. In addition, the error type detection logic 130 may identify the memory cell corresponding to the data bit that has not an error in the first read operation and the second read operation as a normal cell.

[0081] According to one embodiment of the present disclosure, when a data bit that has no error in the first read operation has an error in the second read operation, the error type detection logic 130 may identify the memory cell including the data bit as a cell having a hidden stall error. For example, the stall value may be the value of the data bit in the second read data RD2 where the hidden stall error has occurred.

[0082] In one example, the error type detection logic 130 may store a code for performing a series of operations to identify the error type and the stagnation value. According to one embodiment, a memory (e.g., SRAM) may be included in the error type detection logic 130 or outside the error type detection logic 130, and the code stored in the memory may be read to perform the series of operations. As another example, the error type detection logic 130 itself may be software implemented with at least one piece of code. As another example, the error type detection logic 130 may perform a series of operations in the form of hardware and software combined with each other (e.g., firmware). As another example, the error type detection logic 130 may be based on the error type detection logic 130. Figure 6 The same or similar lookup table shown in FIG. 1 can be used to identify the error type and the stuck value.

[0083] Figure 7 is a block diagram for illustrating the data patterning logic 140 according to an embodiment of the present disclosure, Figure 8 is a diagram for explaining an operation of a memory system according to an embodiment of the present disclosure to randomize data received from a host and write the randomized data into a memory device.

[0084] Reference Figure 7 and Figure 8 , the data patterning logic 140 may include a random seed generator 141 , a randomizer 142 , and a minimum error selector 143 .

[0085] The random seed generator 141 may generate a plurality of random seeds for randomizing the data HDTA received from the host. For example, the random seed may be a fixed value or a value that changes with time, and may be a value generated by random number generation. In addition, each of the plurality of random seeds may be applied to the received data HDTA, and a plurality of random data RD as many as the number of random seeds may be generated. For example, Figure 8 As shown in , eight random seeds may be generated by the random seed generator 141, and eight pieces of random data RD may be generated by the randomizer 142. The random seed generator 141 may store the generated random seeds. For example, information about the stored random seeds may be used to generate parity PA, and the parity PA may be used for de-randomization (or decoding).

[0086] The randomizer 142 may randomize the received data HDTA based on a random seed. The randomizer 142 may output the random data RD to the minimum error selector 143. For example, the randomizer 142 may randomize the received data HDTA [1, 1, 0, 0, 1, 0, 1, 0] based on different random seeds, and output different random data RD. A plurality of data bits corresponding to the first to eighth partial areas 51 to 58 may be different between the random data RD of different strips. For example, the randomizer 142 may generate first random data having data [1, 0, 0, 1, 1, 0, 1, 0] based on a first random seed, and may generate second random data having data [1, 1, 0, 1, 0, 1,0, 1] different from the first random data based on a second random seed. Each of the first to eighth partial areas 51 to 58 may correspond to one memory cell, or may correspond to a plurality of memory cells.

[0087] The minimum error selector 143 may generate the second write data WD2 based on the error type information ETI and the random data RD. According to one embodiment, the minimum error selector 143 may generate the parity PA for de-randomizing (or decoding) the second write data WD2.

[0088] The minimum error selector 143 may select random data with the minimum error from a plurality of random data RD. For example, the minimum error selector 143 may select random data with the minimum stagnation error, or may select random data without stagnation error. For example, the minimum error selector 143 may select the sixth random data generated based on the sixth random seed from a plurality of random data RD. In the sixth random data, the first partial region 51, the third partial region 53, the fourth partial region 54, and the seventh partial region 57 have values ​​0, 1, 1, and 0, respectively. This is because the memory cells corresponding to the first partial region 51, the third partial region 53, the fourth partial region 54, and the seventh partial region 57 are stagnant at stagnation values ​​of 0, 1, 1, and 0, and therefore, the sixth random data may be data without errors. Therefore, the minimum error selector 143 may select the sixth random data.

[0089] For understanding, in the opposite case, when the memory controller 100 writes the third random data generated based on the third random seed to the memory device 200, the data to be written to the memory device 200 may be [0, 0, 1, 0, 1, 0, 1, 0]. However, the data to be read from the memory device 200 may be [0, 0, 1, 1, 1, 0, 1, 0]. That is, due to the set stalled memory cells corresponding to the fourth partial area 54, a stalled error may occur in the data to be read. Therefore, the minimum error selector 143 may select the sixth random data instead of the third random data.

[0090] According to one embodiment of the present disclosure, the minimum error selector 143 may identify the address of the memory cell to which the data of the first partial area 51 to the eighth partial area 58 included in each of the plurality of random data RD is to be written. Alternatively, the minimum error selector 143 may identify the address of the memory cell to which the data HDTA received from the host is to be written. The minimum error selector 143 may determine whether the memory cell corresponding to the identified address is in an error state. In this case, the minimum error selector 143 may determine whether the memory cell is in an error state based on the error type information ETI received from the error type detection logic 130. For example, the error type information ETI may include the error type of the memory cell, the location of the memory cell where an error has occurred, the error value, the stagnation value, etc. The minimum error selector 143 may refer to the stagnation value of the memory cell corresponding to each of the first partial area 51 to the eighth partial area 58 in the plurality of random data RD, and select the random data in which the partial area corresponding to the memory cell having the stagnation error has a data bit matching the stagnation value.

[0091] According to one embodiment of the present disclosure, the minimum error selector 143 may output random data selected as the second write data WD2. The memory controller 100 may write the second write data WD2 to the memory device 200. For example, when the sixth random data is selected as the second write data WD2, the parity PA may be generated based on the sixth random seed. When the host wants to read the second write data WD2, the generated parity PA may be used to derandomize (or decode) the second write data WD2.

[0092] Fig. 9 1 is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure. Fig. 9 The following description is given.

[0093] According to one embodiment of the present disclosure, the memory controller 100 may read data from the memory device 200 (S610). In this case, the memory controller 100 may read first read data RD1, and at least some of the first read data RD1 may be different from the original data OD written in the memory device 200 due to various types of errors.

[0094] The memory controller 100 may perform an ECC operation on the read data (S620). For example, the ECC circuit 120 may perform an error detection operation and an error correction operation on the first read data RD1. As another example, an error of the first read data RD1 may be detected and corrected by an ECC engine included outside the memory controller 100.

[0095] When the number of error bits included in the data read from the memory device 200 exceeds a threshold, the memory controller 100 may invert the data bits of the remaining area except the error occurrence area and write the inverted data bits into the memory device 200 (S630). Figure 5 , the memory controller 100 may invert the data included in the second memory area 32 of the correction data CD on which error detection and correction have been performed, and write the inverted data into the memory device 200. The inversion operation is performed to identify hidden stall errors in subsequent operations.

[0096] Return to reference Fig. 9 , the memory controller 100 may read the write data from the memory device 200 and identify an error (S640). For example, information about the first write data WD1 written by the memory controller 100 may be stored in the internal memory, and the second read data RD2 read from the memory device 200 may be compared with the first write data WD1 to identify an error. Fig.11 Embodiments for identifying errors are described.

[0097] The memory controller 100 may perform a randomization operation (S650). For example, the memory controller 100 may randomize input data received from the host, and may select random data, among which data to be written to the memory device 200 has the smallest error, based on the identified errors. Then, the memory controller 100 may write the selected random data to the memory device 200 (S660). This will be referred to later. Fig.10 and Fig.11 Operations S610 to S640 are described and will be referred to later. Fig.12 Operations S650 and S660 are described.

[0098] Fig.10 and Fig.11 1 is a flowchart illustrating a method of operating a memory controller to determine an error type of data written to a memory cell according to an embodiment of the present disclosure. Fig.10 and Fig.11 The following description is given.

[0099] Reference Fig.10 , the memory controller 100 may read data from the memory device 200 ( S610 ), and may perform an error detection operation and an error correction operation on the read data ( S620 ).

[0100] According to an embodiment of the present disclosure, the memory controller 100 may output error bit information EBI about an error included in the first read data RD1 by performing an error detection operation and an error correction operation. For example, the error bit information EBI may include the location of a memory cell where an error has occurred, the location of a data bit where an error has occurred in a data string, an error value, and a corrected value after error correction.

[0101] According to one embodiment of the present disclosure, the memory controller 100 may invert the remaining data bits except the corrected data bits (S631). For example, based on the error bit information EBI, the first write data WD1 may be generated by inverting the remaining data bits except some corrected data bits in the corrected data CD.

[0102] According to one embodiment of the present disclosure, the memory controller 100 may write data including inverted data bits to the memory device 200 (S632). For example, the memory controller 100 may output first write data WD1 to be written to the memory device 200. Some of the data bits of the first write data WD1 may include inverted data bits in the correction data CD, and the remaining data bits of the first write data WD1 may be the same as the bits of the correction data CD.

[0103] According to one embodiment of the present disclosure, the memory controller 100 may read the written data (S641). For example, the memory controller 100 may store information (e.g., address) about the location of the memory device 200 where the first write data WD1 is written, and may send a read command for reading data at the location where the first write data WD1 is written to the memory device 200.

[0104] According to one embodiment of the present disclosure, the memory controller 100 may perform a comparison operation comparing data written to the memory device 200 with data read from the memory device 200. For example, the memory controller 100 may compare the first write data WD1 with the second read data RD2 to identify an error type.

[0105] According to one embodiment of the present disclosure, the memory controller 100 may identify whether the target for identifying the error type is a memory region of corrected data in the first write data WD1 and the second read data RD2 (S642). For example, the memory controller 100 may identify a memory region (e.g., Figure 5 The first memory area 31 in FIG.

[0106] When an error occurs again in the data of the error-corrected memory area (S643), the memory controller 100 may identify the bit of the area where the error has occurred as a stuck error (S645a). When an error does not occur in the data of the error-corrected memory area, the memory controller 100 may identify the bit of the area where the error does not occur as a temporary error (S645b). This is because the error is an error that occurs only in the first reading process.

[0107] When an error occurs again in the data of the memory area where the error has not been corrected (S644), the memory controller 100 may identify the bit of the area where the error has occurred as a hidden stall error (S645c). This is because the error is an error that occurs only during the second read process. When no error occurs in the data of the memory area where the error has not been corrected, the memory controller 100 may identify the bit of the area where the error has not occurred as a normal bit (S645d).

[0108] The memory controller 100 may output information obtained through a series of operations regarding errors associated with the memory device 200 and data read from the memory device 200. That is, the memory controller 100 may output error type information (ETI) (S646).

[0109] Fig.121 is a flowchart illustrating a method of operating a memory controller to randomize data received from a host based on an error type according to an embodiment of the present disclosure. Fig.12 The following description is given.

[0110] Reference Fig.12 , the memory controller 100 may receive a random seed and receive data HDTA from a host (S651). The memory controller 100 may perform a randomization operation to randomize the data HDTA received from the host based on the random seed (S652). As a result of performing the randomization operation, a plurality of random data RD may be output.

[0111] According to one embodiment of the present disclosure, the memory controller 100 may select data having the smallest error from the randomized data based on the error type information (ETI) (S653). For example, when at least some data bits included in the plurality of random data RD are written to a memory cell in which a stall error has occurred, the memory controller 100 may select random data in which at least some data bits match the stall value of the memory cell.

[0112] According to one embodiment of the present disclosure, the memory controller 100 may write the selected data and the parity corresponding to the selected data into the memory device 200 (S661). For example, the memory controller 100 may write the second write data WD2 into the memory device 200, and the parity PA may be a data bit for derandomizing (or decoding) the second write data WD2.

[0113] Fig.13 is a block diagram of a memory controller 700 according to an embodiment of the present disclosure.

[0114] Reference Fig.13 , the memory controller 700 may include a processor 710, a RAM 720, a host interface 730, a memory interface 740, an ECC circuit 750, an error type detection logic 760, and a data patterning logic 770. As an embodiment, the memory controller 700 may be a device included in an application processor (AP, not shown) that may be implemented as a system on a chip. In addition, the error type detection logic 760 and the data patterning logic 770 may also include the configuration described above with reference to the accompanying drawings.

[0115] The processor 710 may include a central processing unit or a microprocessor, and may control the overall operation of the memory controller 700. For example, the processor 710 may be configured to drive software or firmware for controlling the memory controller 700, and the software or firmware may be loaded onto the RAM 720 to be operated. The RAM 720 may be used as an operating memory, a cache memory, or a buffer memory of the processor 710. The RAM 720 may temporarily store data to be written into or read from a memory device.

[0116] The host interface 730 interfaces with the host to receive requests for memory operations from the host. For example, the host interface 730 receives various requests (such as data read requests, data write requests, etc.) from the host, and may generate various internal signals for performing memory operations on the memory device in response to the requests.

[0117] The memory interface 740 may provide an interface between the memory controller 700 and the memory device, for example, write data may be sent to the memory device via the memory interface 740, and read data may be received from the memory device via the memory interface 740. In addition, the memory interface 740 may provide commands and addresses to the memory device, and may receive various information from the memory device to provide the information to the inside of the memory controller 700.

[0118] The ECC circuit 750 may detect an error of the read data through an ECC decoding process, and the result of detecting the error may be used in an operation of determining an error type in the error type detection logic 760. The data patterning logic 770 may generate a plurality of pieces of random data by randomizing data received via the host interface 730. Based on information about the error type determined in the error type detection logic 760, the data patterning logic 770 may select random data having a minimum error from the plurality of pieces of random data. The selected random data may be output to the memory device 200 via the memory interface 740.

[0119] Various functions that can be performed by the error type detection logic 760 and the data patterning logic 770 may be implemented via hardware or software or a combination of hardware and software. As an example, when a function is implemented via hardware, the function may be performed by a hardware circuit arranged in the interior of each of the error type detection logic 760 and the data patterning logic 770. Alternatively, when a function is implemented via software, a program provided in the interior or exterior of each of the error type detection logic 760 and the data patterning logic 770 may be loaded onto the RAM 720, and the processor 710 may execute the program to perform the function.

[0120] As is conventional in the art, embodiments may be described and illustrated in accordance with blocks that perform one or more functions described. These blocks, which may be referred to herein as units or modules, are physically implemented by analog circuits and / or digital circuits (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and may optionally be driven by firmware and / or software. The circuit may be implemented, for example, in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuits constituting the blocks may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware that performs some functions of the blocks and a processor that performs other functions of the blocks. Without departing from the scope of the present disclosure, each block of the embodiment may be physically separated into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present disclosure, the blocks of the embodiment may be physically combined into more complex blocks. Aspects of the embodiments may be implemented by instructions stored in a non-temporary storage medium and executed by a processor.

[0121] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for controlling a memory device, the method include: reading first read data from the memory device; Correcting bits of the first memory region in which an error has occurred in the first read data, and inverting bits of the second memory region in which no error has occurred; identifying a first error type in the first memory region and a second error type in the second memory region, the second error type being different from the first error type; and Based on at least one of the first error type and the second error type, second write data having a minimum error is written to the memory device.

2. The method according to claim 1, in, The first error type includes stuck errors and temporary errors, and the second error type includes hidden stuck errors.

3. The method according to claim 2, in, The second write data is configured such that a bit value matching a first stall value caused by a stall error is written to a memory cell where a stall error has occurred, and a bit value matching a second stall value caused by a hidden stall error is written to a memory cell where a hidden stall error has occurred.

4. The method according to claim 1, further comprising: include: Read the second read data, wherein, The step of identifying includes comparing the correction and inversion result with the second read data, and identifying at least one of the first error type and the second error type according to the comparison result.

5. A memory system, include: A memory device comprising a plurality of memory regions, each memory region comprising at least one memory cell; as well as A memory controller is configured to: control memory operations of the memory device, wherein The memory controller is also configured to: reading first read data stored in the first memory area and the second memory area from the memory device, performing a correction operation on data in the first memory region in which an error has occurred in the first read data, performing an inversion operation on the data in the second memory area in which no error occurs in the first read data, generating first write data based on the correction operation and the inversion operation, performing a comparison operation of comparing the first write data with second read data obtained by reading the first write data, and Identify multiple error types based on comparison operations.

6. The memory system according to claim 5, in, Comparison operations include: A first partial comparison operation compares data of the first write data stored in the first memory area with data of the second read data stored in the first memory area, and The second partial comparison operation compares the data of the first write data stored in the second memory area with the data of the second read data stored in the second memory area.

7. The memory system according to claim 6, in, The memory controller is further configured to identify at least one of a stuck error and a transient error based on the first partial comparison operation, and to identify a hidden stuck error or a normal state based on the second partial comparison operation.

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