Built-in self-test method and system on chip

Abstract

The invention provides a built-in self-test method and a system on chip. The built-in self-inspection test method is applied to the SOC of an automatic driving system on a vehicle, and the SOC comprises an SOC built-in self-inspection scheduler, an SOC built-in self-inspection actuator and an SOC built-in self-inspection result collector. The method comprises the following steps: when the SOC is in a first process, an SOC built-in self-test scheduler sends a first self-test starting command; the SOC built-in self-test actuator receives the first self-test starting command and obtains a first test sequence according to the first self-test starting command; a built-in self-test actuator of the SOC runs BIST to execute the first test sequence and one or more test sequences arranged behind the first test sequence in the first test sequence set until an end condition in the first self-test starting command is met; and the SOC built-in self-test result collector obtains a test result according to the condition that the SOC built-in self-test actuator operates the BIST. According to the method, the self-checking efficiency can be improved, the starting time can be reduced, and the influence time on the running state business and the starting time can be reduced.

Description

Technical Field

[0001] The present application relates to autonomous driving technology, and more particularly to a built-in self-test method and a system on chip. Background Art

[0002] In order to achieve the diagnostic coverage of the latent fault metric (LFM) of autonomous driving technology, the autonomous driving system (ADS) needs to have a corresponding built-in self-test (BIST) architecture within a vehicle driving cycle to cover and test the functional safety performance of the ADS internally and meet the requirements of the LFM within the system.

[0003] Related technologies mainly adopt the strategy of BIST detection and execution logic hardening and software assistance. The BIST architecture of the object under test includes vector loading, execution, result acquisition and other logic based on chip hardening, so as to achieve the purpose of rapid self-test. Usually, the software only needs to configure the relevant self-test functions and parameters during the power-on startup phase. The execution is mainly completed automatically by the hardware, and the software obtains the final results.

[0004] However, as the autonomous driving functions become increasingly complex, the above-mentioned BIST fully hardened implementation technology will require higher computing power, thereby doubling the system scale, which will not only increase the design complexity of the chip, but also increase the manufacturing cost of the chip. Summary of the invention

[0005] The present application provides a built-in self-test test method and a system on chip to improve self-test efficiency and reduce startup time, and can also reduce the impact on running services and startup time.

[0006] In a first aspect, the present application provides a built-in self-test test method, which is applied to a system-on-chip (SOC) of an autonomous driving system on a vehicle, wherein the SOC includes a SOC built-in self-test scheduler, a SOC built-in self-test executor, and a SOC built-in self-test result collector; the method includes: when the SOC is in a first process, the SOC built-in self-test scheduler sends a first self-test start command; the SOC built-in self-test executor receives the first self-test start command, and obtains a first test sequence according to the first self-test start command, wherein the first test sequence is a test sequence that has not been executed and is at the front in a first test sequence set, wherein the first test sequence set includes multiple test sequences, and the first test sequence set is any one of at least one test sequence set obtained based on the division of the SOC self-test object; the SOC built-in self-test executor runs a built-in self-test test BIST to execute the first test sequence and one or more test sequences in the first test sequence set that are arranged after the first test sequence until the end condition in the first self-test start command is met; the SOC built-in self-test result collector obtains the test result according to the situation of the SOC built-in self-test executor running the BIST.

[0007] In the embodiment of the present application, by differentiating the test sequence into logical areas (test sequence sets), on the one hand, BIST can be run in more SOC processes to improve the self-test efficiency; on the other hand, the test sequence in the power-on phase can be reduced through logical partitioning, thereby reducing the startup time; and for the test sequence of the minimum execution unit BF, a segmented and time-sharing execution method can be adopted to reduce the impact on the running business and the startup time.

[0008] SOC can include 4 states: Working, Idle, Suspend and Shutdown, where SOC Shutdown means that all SOC self-test objects have entered the idle and power-off state; SOC Suspend means that at least one SOC self-test object has entered the idle and power-off state, and at least one SOC self-test object has not entered the idle and power-off state; SOC Idle means that at least one SOC self-test object has entered the business idle state and the clock is turned off and reset in a low-power state; SOC Working means that at least one SOC self-test object has entered the business operation state. The aforementioned SOC self-test objects may include but are not limited to SOC processors, SOC memories, buses, etc.

[0009] SOC can switch between the above four states, so there may be the following six switching processes (referred to as processes):

[0010] 1. The switching process from SOC Shutdown to SOC Working;

[0011] 2. The switching process from SOC Working to SOC Shutdown;

[0012] 3. The switching process from SOC Working to SOC Suspend;

[0013] 4. The switching process from SOC Suspend to SOC Working;

[0014] 5. The switching process from SOC Working to SOC Idle;

[0015] 6. The switching process from SOC Idle to SOC Working.

[0016] When only one test sequence set is obtained, the first process mentioned above may include the process of switching the SOC from the working state to the shutdown state (i.e. the above process 2), the process of switching the SOC from the working state to the sleep state (i.e. the above process 3), or the process of switching the SOC from the working state to the idle state (i.e. the above process 5).

[0017] When it is detected that the SOC is in the first process, the SOC built-in self-test scheduler may send a first self-test start command to trigger the BIST operation.

[0018] In the embodiment of the present application, the SOC built-in self-test scheduler (i.e., the above-mentioned ADS System Manager Scheduler B) can count and calculate the coverage of the test sequence execution in the entire driving cycle, and use the sequence number of the test sequence at the end of the last execution (also called the vector number) as the initial sequence number, set the system vector executable time, and pass the above two to the SOC BIST Manager through the self-test start command.

[0019] The first self-test start command may include a first serial number, which may be the serial number of a second test sequence, and the second test sequence is a test sequence that has been executed in the currently executed test sequence set (corresponding to the first test sequence set below) and has a serial number before the first test sequence. The first test sequence is a test sequence that has not been executed in the currently executed test sequence set and has the earliest serial number. As described above, the test sequence set includes multiple test sequences, and each test sequence may correspond to a serial number to distinguish the test sequence.

[0020] That is, the last test sequence executed before the first test sequence to be executed is the second test sequence.

[0021] In addition, the first self-test start command also includes the runnable time of the BIST (ie, the time during which the vector provided by the system can be executed). Alternatively, the self-test start command also includes the number of test sequences N, where N is a positive integer.

[0022] The above two situations can be used in the first self-test start command to notify the SOC built-in self-test executor (i.e., the above-mentioned SOC BIST Executor) of the end conditions of this BIST. In the former, the runnable time of the BIST is the time when the SOC built-in self-test scheduler counts the executable time of the system supply vector, and notifies the SOC built-in self-test executor how long the BIST can be run. Once the time is up, the SOC built-in self-test executor needs to stop the BIST immediately; in the latter, the number of test sequences N is the number of test sequences that can be executed in one BIST run obtained by the SOC built-in self-test scheduler according to the pre-set or executable time of the system supply vector, and then notifies the SOC built-in self-test executor of the number. Once the SOC built-in self-test executor executes N test sequences, the SOC built-in self-test executor needs to stop the BIST immediately.

[0023] The first test sequence is a test sequence that has not been executed and is ranked first in the first test sequence set. The first test sequence set includes multiple test sequences. The first test sequence set is any one of at least one test sequence set obtained based on the SOC self-test object.

[0024] The SOC built-in self-test executor can determine the test sequence set (i.e., the first test sequence set) to be processed by the current SOC process according to the preset setting. Then, the first test sequence is determined according to the processing progress of the first test sequence set, that is, according to the self-test start command, the sequence number (also called vector number) of the test sequence at the end of the last execution is used as the initial sequence number, and the test sequence identified by the initial sequence number (i.e., the first test sequence) is obtained.

[0025] The SOC built-in self-test executor starts from the first test sequence and executes the test sequences one by one backwards according to the serial number order of the test sequence (it can be in order from large to small, or in order from small to large, or in other order of serial numbers, without specific limitation) until the end condition is met and the BIST ends.

[0026] In the case where the first self-test start command includes the runnable time of the BIST, the end condition includes the end of the runnable time of the BIST. That is, if the SOC built-in self-test scheduler carries the runnable time of the BIST in the self-test start command, then the moment when the SOC built-in self-test executor stops the BIST may be the moment when the runnable time of the BIST ends.

[0027] In the case where the first self-test start command includes the number of test sequences N, the end condition includes running the BIST to execute the N test sequences. That is, if the SOC built-in self-test scheduler carries the number of test sequences N in the self-test start command, the moment when the SOC built-in self-test executor stops the BIST may be the moment when the N test sequences are executed.

[0028] It should be noted that the end condition may also include other situations, and may also be set according to the information contained in the self-test start command, and the embodiment of the present application does not specifically limit this.

[0029] After the SOC built-in self-test executor runs a BIST, the SOC built-in self-test result collector (i.e., the above-mentioned SOCBIST Result Collector) can collect test results according to the running status of the BIST. If the test result shows an error, the error can be distinguished between a software error and a hardware error, wherein a hardware error corresponds to a hardware failure, and a software error corresponds to a software failure.

[0030] In one possible implementation, when the SOC is in the second process, the SOC built-in self-test scheduler sends a second self-test start command; the SOC built-in self-test executor receives the second self-test start command, and obtains a second test sequence according to the second self-test start command, the second test sequence is a test sequence that has not been executed and is at the front in the second test sequence set, the second test sequence set includes multiple test sequences, and the second test sequence set is any one of at least one test sequence set except the first test sequence set; the SOC built-in self-test executor runs BIST to execute the second test sequence and one or more test sequences in the second test sequence set that are arranged after the second test sequence until the end condition in the second self-test start command is met; the SOC built-in self-test result collector obtains the test result according to the situation of the SOC built-in self-test executor running BIST.

[0031] As described above, when two test sequence sets are obtained by division, the first process may also include a process of switching the SOC from a shutdown state to a working state (i.e., the process 1 above), a process of switching the SOC from a sleep state to a working state (i.e., the process 4 above), or a process of switching the SOC from an idle state to a working state (i.e., the process 6 above). That is, the SOC built-in self-test scheduler may trigger the SOC built-in self-test executor to run the BIST to execute the test sequence in the first test sequence set in process 1, 4, or 6.

[0032] Meanwhile, another test sequence set (ie, the second test sequence set) can be triggered by the SOC built-in self-test scheduler to run the SOC built-in self-test executor to execute the test sequences in the second test sequence set in the second process.

[0033] The second process includes the switching process of the SOC from the working state to the shutdown state (i.e. the above-mentioned process 2), the switching process of the SOC from the working state to the sleep state (i.e. the above-mentioned process 3), the switching process of the SOC from the working state to the idle state (i.e. the above-mentioned process 5), the switching process of the SOC from the shutdown state to the working state (i.e. the above-mentioned process 1), the switching process of the SOC from the sleep state to the working state (i.e. the above-mentioned process 4) or the switching process of the SOC from the idle state to the working state (i.e. the above-mentioned process 6); and the second process is different from the first process.

[0034] In one possible implementation, when the SOC is in the third process, the SOC built-in self-test scheduler sends a third self-test start command; the SOC built-in self-test executor receives the third self-test start command, and obtains a third test sequence according to the third self-test start command, the third test sequence is a test sequence that has not been executed and is at the front in the third test sequence set, the third test sequence set includes multiple test sequences, and the third test sequence set is any one of at least one test sequence set except the first test sequence set and the second test sequence set; the SOC built-in self-test executor runs BIST to execute the third test sequence and one or more test sequences in the third test sequence set that are arranged after the third test sequence until the end condition in the third self-test start command is met; the SOC built-in self-test result collector obtains the test result according to the situation of the SOC built-in self-test executor running BIST.

[0035] As described above, when three test sequence sets are obtained, in addition to the first and second processes, the SOC built-in self-test scheduler can also trigger the SOC built-in self-test executor to run BIST in the third process to execute the test sequences in the third test sequence set.

[0036] The third process includes the switching process of the SOC from the working state to the shutdown state (i.e. the above-mentioned process 2), the switching process of the SOC from the working state to the sleep state (i.e. the above-mentioned process 3), the switching process of the SOC from the working state to the idle state (i.e. the above-mentioned process 5), the switching process of the SOC from the shutdown state to the working state (i.e. the above-mentioned process 1), the switching process of the SOC from the sleep state to the working state (i.e. the above-mentioned process 4) or the switching process of the SOC from the idle state to the working state (i.e. the above-mentioned process 6); and the third process is different from the first process and the second process respectively.

[0037] In a possible implementation, when it is detected that the vehicle is in the fourth process, the SOC built-in self-test scheduler sends a self-test stop command; the SOC built-in self-test executor receives the self-test stop command and stops running the BIST according to the self-test stop command.

[0038] The fourth process may include starting the vehicle, starting the autonomous driving service on the vehicle, or an application APP on the vehicle issuing an activation operation command.

[0039] In one possible implementation, if the test sequence fails to execute and the SOC needs to restore to a normal state, the SOC built-in self-test executor can confirm the failed test sequence and then record it in the shared memory; if the BIST fails to run, causing the SOC to be unable to restore to a normal state, then ADS System Manager Scheduler A can assist the SOC built-in self-test result collector from the software to determine whether a hardware failure has occurred.

[0040] In a second aspect, the present application provides a system on chip (SOC), comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement a method as described in any one of the above-mentioned first aspects.

[0041] In a third aspect, the present application provides a computer-readable storage medium, comprising a computer program, wherein when the computer program is executed on a computer, the computer executes any one of the methods described in the first aspect.

[0042] In a fourth aspect, the present application provides a computer program product, wherein the computer program product comprises a computer program code, and when the computer program code is executed on a computer, the computer executes any one of the methods in the first aspect.

[0043] In a fifth aspect, the present application provides a chip comprising a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute a method as described in any one of the above-mentioned first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of the ADS architecture for this application;

[0045] Figure 2 A schematic diagram of the status of the SOC for this application;

[0046] Figure 3 The process 300 of the built-in self-test method of the embodiment of the present application is as follows;

[0047] Figure 4 A flow chart of the built-in self-test method for this application;

[0048] Figure 5 Flowchart of the vector execution of this application.

[0049] Specific implementation method

[0050] In order to make the purpose, technical solution and advantages of this application clearer, the technical solution in this application will be described clearly and completely in conjunction with the drawings in this application. Obviously, the implementation examples described are part of the implementation examples of this application, not all of the implementation examples. Based on the implementation examples in this application, all other implementation examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] The terms "first", "second", etc. in the specification examples, claims and drawings of this application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0053] Figure 1 The schematic diagram of the ADS architecture for this application is as follows: Figure 1As shown, the autonomous driving system (ADS) includes an ADS system manager scheduler A (ADS System Manager Scheduler A) and an ADS system manager scheduler B (ADS System Manager Scheduler B), wherein the ADS system manager scheduler B is set in the ADS system on chip (System on Chip, SOC). The ADS system manager scheduler A is set in other chips outside the ADS SOC, and also includes a memory display program (MEM) outside the ADS SOC. The ADS system manager scheduler A and the memory can interact with the aforementioned ADS SOC respectively.

[0054] In the ADS SOC, in addition to the above-mentioned ADS system management scheduling B, it also includes SOC built-in self-test (Build InSelf Test, BIST) management (SOC BIST Manager), SOC power consumption mode management (SOC PowerMode Manager), SOC BIST executor (SOC BIST Executor), SOC BIST result collector (SOC BIST Result Collector), shared memory (Share MEM) and multiple logic areas, such as Always On (AO) area and non-AO area. The aforementioned logic area includes multiple components, such as non-AO area component A (Non AO Component A), non-AO area component B (Non AO C omponent B), non-AO area component C (Non AO Component C), non-AO area component D (Non AOComponent D), ...).

[0055] In the present application, in order to reduce the impact of BIST on the system startup time, based on the above-mentioned ADS architecture, the BIST test sequence (also referred to as test vector, vector, etc., without specific limitation) is divided into at least one test sequence set (test sequence set can also be referred to as logic area, without specific limitation) according to at least one factor in the power domain, reset domain, clock domain and functional domain to which the SOC self-test object belongs. Each test sequence set can include multiple test sequences, and different test sequence sets can be executed by BIST and obtain corresponding test results when the SOC is in different processes. It should be noted that in addition to the above-mentioned factors, the test sequence set can also be divided based on other factors, and the embodiments of the present application do not specifically limit this.

[0056] In a possible implementation, the divided logical area may include an AO area and a non-AO area, wherein:

[0057] The AO area test sequence set includes the SOC BIST and the necessary AO area self-detection circuit. The BIST in the AO area is hardened logic in chip implementation and can run automatically when powered on, so it will inevitably affect the startup time. Based on this, when designing the AO area test sequence set, the test sequences included in the AO area can be kept as few and simple as possible, so that when the BIST executes this part of the test sequence, the running time is guaranteed to be as short as possible to reduce the impact on the startup time.

[0058] The non-AO area test sequence set contains most of the chip function implementation logic circuits. Therefore, when executing the non-AO area test sequence set, BIST operation takes a long time and has the greatest impact on the business. Based on this, a segmented and time-sharing execution method can be adopted to reduce the impact on the running business and startup time.

[0059] In the embodiment of the present application, one test sequence corresponds to one BIST function unit (BIST function, BF). BF may be the smallest unit of a single vector execution. BF may be composed of a series of binary sub-test sequences, which may be converted into executable vectors by tools for software scheduling and execution.

[0060] When dividing the BF, the factors to be considered include: at least one of execution time, space occupancy, voltage specification, current specification, ripple, noise, heat, and power consumption. It should be noted that in addition to the aforementioned factors, the test sequence can also be divided based on other factors, which are not specifically limited in the embodiments of the present application.

[0061] BF is the smallest unit that cannot be split during BIST execution. If an event to exit BIST is triggered externally during BIST execution (for example, vehicle startup triggers an ADS BIST interrupt), the SOC BIST Executor needs to complete the processing of the vector being executed before responding to the interrupt event. Therefore, during the generation of a single vector, the impact of the longest execution time of a single vector on the system must be considered to meet the time requirements for the system to quickly resume work.

[0062] Single BF execution takes up both storage space and running space. Therefore, within the limited running space of the SOC BIST Executor (large space occupation means large chip area cost), single vector segmentation is expected to occupy as little space as possible to ensure that it can be executed in time-sharing within the limited space. In addition, in terms of overall space occupation, the vector image is compressed through a compression algorithm to save storage space.

[0063] During the execution of a single BF vector, the impact on the power supply needs to be considered. The vector splitting needs to meet the system power supply requirements. High parallelism means high peak current. As a single BF vector is executed, heat accumulation will occur, which may cause local overheating of the chip. Therefore, vector splitting cannot blindly pursue high parallelism and low latency, but must meet the system heat dissipation requirements.

[0064] Figure 2 A schematic diagram of the state of the SOC for this application is shown as follows: Figure 2 As shown, SOC can include 4 states: Working, Idle, Suspend and Shutdown, where SOC Shutdown means that all SOC self-test objects have entered the idle and power-off state; SOC Suspend means that at least one SOC self-test object has entered the idle and power-off state, and at least one SOC self-test object has not entered the idle and power-off state; SOC Idle means that at least one SOC self-test object has entered the business idle state and the clock is turned off and reset in a low-power state; SOC Working means that at least one SOC self-test object has entered the business operation state. The aforementioned SOC self-test objects may include but are not limited to SOC processors, SOC memories, buses, etc.

[0065] SOC can switch between the above four states, so there may be the following six switching processes (referred to as processes):

[0066] 1. The switching process from SOC Shutdown to SOC Working;

[0067] 2. The switching process from SOC Working to SOC Shutdown;

[0068] 3. The switching process from SOC Working to SOC Suspend;

[0069] 4. The switching process from SOC Suspend to SOC Working;

[0070] 5. The switching process from SOC Working to SOC Idle;

[0071] 6. The switching process from SOC Idle to SOC Working.

[0072] In the embodiment of the present application, when only one test sequence set is obtained by division, the SOC may run BIST in any one of the above processes 2, 3, and 5 to execute the test sequences in the test sequence set. When two test sequence sets are obtained by division, the SOC may run BIST in one of the above processes 1-6 to execute the test sequences in one test sequence set, and run BIST in another process to execute the test sequences in another test sequence set, for example, respectively running a test sequence in process 1 and process 3; respectively running a test sequence in process 2 and process 5. When three test sequence sets are obtained by division, the SOC may run BIST in one of the above processes 1-6 to execute the test sequences in one test sequence set, run BIST in another process to execute the test sequences in another test sequence set, and run BIST in the third process to execute the test sequences in another test sequence set, for example, respectively running a test sequence in process 1, process 3, and process 5; respectively running a test sequence in process 2, process 3, and process 6. By analogy, more test sequence sets can be divided, and the aforementioned multiple test sequence sets can be respectively run in different processes of the above processes 1-6, that is, one process corresponds to one test sequence set. It should be noted that the embodiment of the present application does not specifically limit the number of divisions of the test sequence set and the process corresponding to the execution of the test sequence.

[0073] In the ADS of the implementation example of this application, taking the division of AO area and non-AO area as an example, the functions of each component are as follows:

[0074] ADS System Manager Scheduler A is a system management scheduler outside the SOC that is mainly responsible for autonomous driving business.

[0075] ADS System Manager Scheduler B is the system management scheduler in the SOC that is mainly responsible for autonomous driving business.

[0076] SOC BIST Manager is responsible for managing the BIST of the AO area and the BIST of the non-AO area in the SOC. The BIST of the AO area (AO BIST) is automatically completed by the hardware logic during the power-on startup phase, and the software is responsible for checking the execution results, and then passing the results to the upper-level software or host computer through the SOC BIST Result Collector.

[0077] SOC PowerMode Manager is mainly responsible for switching the internal power consumption mode of the SOC, involving component shutdown, enabling, power on and off, and SOC backup and recovery.

[0078] SOC BIST Executor, the BIST in the AO area is an interface for entering and exiting the BIST that is open to the upper-layer software. It is mainly responsible for entering / exiting the BIST mode, BIST mode setting, running the BIST to execute the non-AO area test sequence set (non-AO area test sequence A, non-AO area test sequence B, non-AO area test sequence C, non-AO area test sequence D, ...), and sending the execution results to the SOC BIST Result Collector through the Share MEM, and sending the instructions to the underlying software module for execution.

[0079] In the implementation example of this application, the BIST mode includes: interruptible mode, non-interruptible mode, timing mode, etc. Among them,

[0080] The interruptible mode means that by setting the time when the system supply vector can be executed, the SOC BIST Executor runs the BIST to execute one or more test sequences. If an event to exit the BIST occurs at any time during the operation (for example, the vehicle is started, the autonomous driving service on the vehicle is started, the application (APP) on the vehicle issues an activation operation instruction, etc.), the SOC BIST Executor will interrupt after executing the current test sequence and execute the exit BIST process.

[0081] The timing mode means that the execution time of the SOC BIST Executor (that is, the time when the above-mentioned system supply vector can be executed) can be set. When the timing time is reached, the SOC BIST Executor will interrupt after executing the current test sequence and exit the BIST process. In the timing mode, the ADS System Manager Scheduler B can use the sequence number of the test sequence at the end of the last execution (also known as the vector number) as the initial sequence number, and set the time when the system supply vector can be executed, and pass the above two to the SOC BIST Manager through the self-test start command.

[0082] The non-interruptible mode means that the execution process of the test sequence will not be interrupted until the final results are obtained after all test sequences are executed.

[0083] SOC BIST Result Collector is responsible for collecting the execution results of BIST through Share MEM. This application implementation example provides two storage methods. The execution results can distinguish between software errors and hardware errors, where hardware errors correspond to hardware failures.

[0084] Share MEM is used to store the execution results of BIST. Its storage medium may include the running double data rate synchronous dynamic random access memory (DDR) space and the solidified serial peripheral interface (SPI) flash memory space. On the other hand, it is used to store the test sequence set executed during BIST operation. The test sequence is loaded and executed by SOC BIST Executor.

[0085] It should be noted that Figure 1 The ADS architecture shown is merely an example of an application scenario of the embodiment of the present application. It does not limit the architecture of the ADS, and the embodiment of the present application does not make any specific limitation on this.

[0086] Based on this, an embodiment of the present application provides a built-in self-test method and device, and the technical solution of the present application will be described below.

[0087] Figure 3 Flow chart of process 300 of the built-in self-test method of the present application embodiment. Process 300 may be performed by the ADS in the above embodiment. Process 300 is described as a series of steps or operations. It should be understood that process 300 may be performed in various orders and / or occur simultaneously, not limited to Figure 3 The execution order shown. Process 300 includes the following steps:

[0088] Step 301: When the SOC is in a first process, the SOC built-in self-test scheduler sends a first self-test start command.

[0089] As described above, when only one test sequence set is obtained, the first process mentioned above may include the process of switching the SOC from the working state to the shutdown state (i.e., the above process 2), the process of switching the SOC from the working state to the sleep state (i.e., the above process 3), or the process of switching the SOC from the working state to the idle state (i.e., the above process 5).

[0090] When it is detected that the SOC is in the first process, the SOC built-in self-test scheduler may send a first self-test start command to trigger the BIST operation.

[0091] In the embodiment of the present application, the SOC built-in self-test scheduler (i.e., the above-mentioned ADS System Manager Scheduler B) can count and calculate the coverage of the test sequence execution in the entire driving cycle, and use the sequence number of the test sequence at the end of the last execution (also called the vector number) as the initial sequence number, set the system vector executable time, and pass the above two to the SOC BIST Manager through the self-test start command.

[0092] The first self-test start command may include a first serial number, which may be the serial number of a second test sequence, and the second test sequence is a test sequence that has been executed in the currently executed test sequence set (corresponding to the first test sequence set below) and has a serial number before the first test sequence. The first test sequence is a test sequence that has not been executed in the currently executed test sequence set and has the earliest serial number. As described above, the test sequence set includes multiple test sequences, and each test sequence may correspond to a serial number to distinguish the test sequence.

[0093] That is, the last test sequence executed before the first test sequence to be executed is the second test sequence.

[0094] In addition, the first self-test start command also includes the runnable time of the BIST (ie, the time during which the vector provided by the system can be executed). Alternatively, the self-test start command also includes the number of test sequences N, where N is a positive integer.

[0095] The above two situations can be used in the first self-test start command to notify the SOC built-in self-test executor (i.e., the above-mentioned SOC BIST Executor) of the end conditions of this BIST. In the former, the runnable time of the BIST is the time when the SOC built-in self-test scheduler counts the executable time of the system supply vector, and notifies the SOC built-in self-test executor how long the BIST can be run. Once the time is up, the SOC built-in self-test executor needs to stop the BIST immediately; in the latter, the number of test sequences N is the number of test sequences that can be executed in one BIST run obtained by the SOC built-in self-test scheduler according to the pre-set or executable time of the system supply vector, and then notifies the SOC built-in self-test executor of the number. Once the SOC built-in self-test executor executes N test sequences, the SOC built-in self-test executor needs to stop the BIST immediately.

[0096] Step 302: The SOC built-in self-test executor receives a first self-test start command, and acquires a first test sequence according to the first self-test start command.

[0097] The first test sequence is a test sequence that has not been executed and is ranked first in the first test sequence set. The first test sequence set includes multiple test sequences. The first test sequence set is any one of at least one test sequence set obtained based on the SOC self-test object.

[0098] The SOC built-in self-test actuator can determine the process that the SOC is currently in according to the preset settings (for example Figure 2The first test sequence is then determined according to the processing progress of the first test sequence set, that is, according to the self-test start command, the sequence number (also called vector number) of the test sequence at the end of the last execution is used as the initial sequence number, and the test sequence identified by the initial sequence number (that is, the first test sequence) is obtained.

[0099] Step 303: The SOC built-in self-test executor runs the built-in self-test test BIST to execute the first test sequence and one or more test sequences in the first test sequence set that are arranged after the first test sequence until an end condition in the first self-test start command is met.

[0100] The SOC built-in self-test executor starts from the first test sequence and executes the test sequences one by one backwards according to the serial number order of the test sequence (it can be in order from large to small, or in order from small to large, or in other order of serial numbers, without specific limitation) until the end condition is met and the BIST ends.

[0101] For the case where the first self-test start command includes the runnable time of the BIST in step 301, the end condition includes the end of the runnable time of the BIST. That is, if the SOC built-in self-test scheduler carries the runnable time of the BIST in the self-test start command, the moment when the SOC built-in self-test executor stops the BIST may be the moment when the runnable time of the BIST ends.

[0102] For the case in step 301 where the first self-test start command includes the number of test sequences N, the end condition includes running the BIST to execute the N test sequences. That is, if the SOC built-in self-test scheduler carries the number of test sequences N in the self-test start command, the moment when the SOC built-in self-test executor stops the BIST may be the moment when the N test sequences are executed.

[0103] It should be noted that the end condition may also include other situations, and may also be set according to the information contained in the self-test start command, and the embodiment of the present application does not specifically limit this.

[0104] Step 304: The SOC built-in self-test result collector obtains a test result according to the condition of the SOC built-in self-test executor running the BIST.

[0105] After the SOC built-in self-test executor runs a BIST, the SOC built-in self-test result collector (i.e., the above-mentioned SOCBIST Result Collector) can collect test results according to the running status of the BIST. If the test result shows an error, the error can be distinguished between a software error and a hardware error, wherein a hardware error corresponds to a hardware failure, and a software error corresponds to a software failure.

[0106] In one possible implementation, when the SOC is in the second process, the SOC built-in self-test scheduler sends a second self-test start command; the SOC built-in self-test executor receives the second self-test start command, and obtains a second test sequence according to the second self-test start command, the second test sequence is a test sequence that has not been executed and is at the front in the second test sequence set, the second test sequence set includes multiple test sequences, and the second test sequence set is any one of at least one test sequence set except the first test sequence set; the SOC built-in self-test executor runs BIST to execute the second test sequence and one or more test sequences in the second test sequence set that are arranged after the second test sequence until the end condition in the second self-test start command is met; the SOC built-in self-test result collector obtains the test result according to the situation of the SOC built-in self-test executor running BIST.

[0107] As described above, when two test sequence sets are obtained by division, the first process may also include a process of switching the SOC from a shutdown state to a working state (i.e., the process 1 above), a process of switching the SOC from a sleep state to a working state (i.e., the process 4 above), or a process of switching the SOC from an idle state to a working state (i.e., the process 6 above). That is, the SOC built-in self-test scheduler may trigger the SOC built-in self-test executor to run the BIST to execute the test sequence in the first test sequence set in process 1, 4, or 6.

[0108] Meanwhile, another test sequence set (ie, the second test sequence set) can be triggered by the SOC built-in self-test scheduler to run the SOC built-in self-test executor to execute the test sequences in the second test sequence set in the second process.

[0109] The second process includes the switching process of the SOC from the working state to the shutdown state (i.e. the above-mentioned process 2), the switching process of the SOC from the working state to the sleep state (i.e. the above-mentioned process 3), the switching process of the SOC from the working state to the idle state (i.e. the above-mentioned process 5), the switching process of the SOC from the shutdown state to the working state (i.e. the above-mentioned process 1), the switching process of the SOC from the sleep state to the working state (i.e. the above-mentioned process 4) or the switching process of the SOC from the idle state to the working state (i.e. the above-mentioned process 6); and the second process is different from the first process.

[0110] In one possible implementation, when the SOC is in the third process, the SOC built-in self-test scheduler sends a third self-test start command; the SOC built-in self-test executor receives the third self-test start command, and obtains a third test sequence according to the third self-test start command, the third test sequence is a test sequence that has not been executed and is at the front in the third test sequence set, the third test sequence set includes multiple test sequences, and the third test sequence set is any one of at least one test sequence set except the first test sequence set and the second test sequence set; the SOC built-in self-test executor runs BIST to execute the third test sequence and one or more test sequences in the third test sequence set that are arranged after the third test sequence until the end condition in the third self-test start command is met; the SOC built-in self-test result collector obtains the test result according to the situation of the SOC built-in self-test executor running BIST.

[0111] As described above, when three test sequence sets are obtained, in addition to the first and second processes, the SOC built-in self-test scheduler can also trigger the SOC built-in self-test executor to run BIST in the third process to execute the test sequences in the third test sequence set.

[0112] The third process includes the switching process of the SOC from the working state to the shutdown state (i.e. the above-mentioned process 2), the switching process of the SOC from the working state to the sleep state (i.e. the above-mentioned process 3), the switching process of the SOC from the working state to the idle state (i.e. the above-mentioned process 5), the switching process of the SOC from the shutdown state to the working state (i.e. the above-mentioned process 1), the switching process of the SOC from the sleep state to the working state (i.e. the above-mentioned process 4) or the switching process of the SOC from the idle state to the working state (i.e. the above-mentioned process 6); and the third process is different from the first process and the second process respectively.

[0113] In a possible implementation, when it is detected that the vehicle is in the fourth process, the SOC built-in self-test scheduler sends a self-test stop command; the SOC built-in self-test executor receives the self-test stop command and stops running the BIST according to the self-test stop command.

[0114] The fourth process may include starting the vehicle, starting the autonomous driving service on the vehicle, or an application APP on the vehicle issuing an activation operation command.

[0115] In one possible implementation, if the test sequence fails to execute and the SOC needs to restore to a normal state, the SOC built-in self-test executor can confirm the failed test sequence and then record it in the shared memory; if the BIST fails to run, causing the SOC to be unable to restore to a normal state, then ADS System Manager Scheduler A can assist the SOC built-in self-test result collector from the software to determine whether a hardware failure has occurred.

[0116] In the embodiment of the present application, by differentiating the test sequence into logical areas (test sequence sets), on the one hand, BIST can be run in more SOC processes to improve the self-test efficiency; on the other hand, the test sequence in the power-on phase can be reduced through logical partitioning, thereby reducing the startup time; and for the test sequence of the minimum execution unit BF, a segmented and time-sharing execution method can be adopted to reduce the impact on the running business and the startup time.

[0117] The technical solution of the present application is described below through specific embodiments.

[0118] Figure 4 A flow chart of the built-in self-test method for this application is shown in FIG. Figure 4 As shown, the process of this embodiment includes:

[0119] The overall core process is shown in the figure below:

[0120] (1) ADS System Manager Scheduler A and ADS System Manager Scheduler B decide whether to run BIST. They monitor the operating status of the vehicle computer and autonomous driving, identify the vehicle stop status and scenarios (charging, long-term parking, etc.) when running BIST, set the BIST mode, and send a self-test start command to the SOC BIST Manager.

[0121] During the BIST operation, if a signal requiring exit is detected, such as a person approaching or a vehicle igniting, ADS System Manager Scheduler B notifies the SOC BIST Executor to stop the BIST and enter the normal state.

[0122] (2) After receiving the self-test start command, the SOC BIST Manager identifies the BIST mode and runs the BIST. If there is a breakpoint scenario, it supports breakpoint continuation and notifies the SOC PowerMode Manager to prepare for the SOC sleep (Suspend) process. At the same time, it sets the BIST switch and mode.

[0123] (3) In the Suspend process, when the SOC BIST Executor detects that the BIST needs to be run, it loads, executes, and records the results of the BIST vector (Non-AO BIST) in the non-AO area.

[0124] During the BIST operation, if an exit signal is detected, such as a person approaching or the vehicle igniting, ADSSystem Manager Scheduler B notifies the SOC BIST Executor to exit the BIST state and enter the normal state. The SOC BIST Result Collector records the sequence number of the current execution vector in the flash (to ensure that it is not lost when the power is off). The next time the BIST is run, the SOC BIST Executor can continue to execute from the interrupted vector. If no exit signal is detected, the SOC BIST Executor executes the corresponding test vector according to the established execution time or vector execution quantity.

[0125] After the execution vector is completed, it enters the Suspend state or exits to the Runtime state. This process can be determined by ADS System Manager Scheduler A according to the business needs of the self-driving scenario.

[0126] (4) If the vector execution fails, the SOC needs to be restored to normal, and the SOC BIST Manager and SOC BISTResult Collector need to confirm the failed vector and then record the result into the flash.

[0127] (5) If the BIST fails and the SOC cannot be restored to normal status, ADS SystemManager Scheduler A is required to assist the SOC BIST Result Collector in determining whether a hardware failure has occurred through software.

[0128] Figure 5 The flowchart of the vector execution of this application is as follows: Figure 5 As shown, the process of this embodiment includes:

[0129] (1) Divide the functions to be tested to obtain a non-AO area test sequence set containing multiple BFs. The aforementioned BFs are the smallest units that are executed independently and do not depend on each other, for example, BF1, BF2, ..., BFN.

[0130] (2) In the Runtime OF ADS SOC state, run normal business with the BF Test MinExecute Time, for example, R1.

[0131] (3) ADS System Manager Scheduler B identifies the vehicle stop status and scenario, sets the BIST mode, and sends a self-test start command to the SOC BIST Manager.

[0132] (4) BIST operation supports execution or interrupt execution at BF granularity, and enters Suspend after execution. The execution time of BF is optimized to the smallest unit according to the user experience of ADS chip. For example, execution starts from BF1.

[0133] (5) During the BIST operation, if ADS System Manager Scheduler B recognizes or the execution time has expired, BF is interrupted and enters the Suspend state. For example, after executing BF4, it enters the Suspend state.

[0134] (6) BF Interrupted and Resume to Runtime, that is, RuntimeOF ADS SOC state, running normal business R2.

[0135] (7) During the BIST operation, if ADS System Manager Scheduler B recognizes or the execution time has expired, BF is interrupted and enters the Suspend state. For example, if BF6 fails to execute, it will continue to execute in the next cycle.

[0136] (8) BF can be executed in each cycle, or the vector can be executed in full.

[0137] (9) After the execution fails, the corresponding failure vector can be rescheduled and confirmed through ADS System Manager Scheduler B (BIST Fail for result confirm).

[0138] In the embodiment of the present application, the division and execution process of BF may include:

[0139] (1) The SOC BIST Executor in the AO area is a hardened state machine connected to each test component. Its BIST is completed by hardware power-on. The test vectors are stored in the read-only memory (ROM). The test results are determined by hardened logic. External input and output (IO) can bypass the self-test function of the AO area.

[0140] (2) The test of the SOC BIST Executor in the AO area to detect the components in the non-AO area is a series of test sequences, which can be one BIT or multiple BITs;

[0141] (3) The test sequence combines the clock, power, reset domain information, the setting value of the execution time of a single BF, and the setting value of the memory space occupied by a single BF through the tool to generate the BF that the component needs to execute;

[0142] (4) A BF can correspond to one input test serial or multiple test serials.

[0143] (5) The multiple BFs output by the tool are compressed and compiled to generate the original BF img, which can save the memory space occupied by the BF Img;

[0144] (6) Encrypt the BF img with data signature to ensure security. It should be noted that the BIST data zone composed of BF can be encrypted here. The BIST Data Zone can be used as the smallest execution unit in the BIST execution process. At the same time, the BIST img composed of the BIST Data Zone also needs to be encrypted with data signature. There may be multiple BIST Imgs.

[0145] (7) Decrypt and verify the BIST img signature during the data execution phase. After the BIST img decryption and signature verification is executed, the image can be moved to the running space for test execution. If there is a BIST Data Zone, it can support the BIST img decryption and signature verification, and then decrypt and verify the BIST Data Zone. After the completion, the image is moved to the running space for test execution, and then the BIST Data Zone is moved again after the execution is completed. Repeat the execution to achieve the purpose of saving running space;

[0146] (8) If there is an external interrupt request during the execution, the SOC BIST Result Collector executes based on the BF granularity interrupt vector and records the result and sequence number N-1. The next time the BIST is run, BFN, BFN+1, BFN+2, ... are executed. It can also continue from sequence number N-1, N-2, ... or 1.

[0147] In the implementation process, each step of the above method execution example can be completed by the hardware integrated logic circuit or software instructions in the processor. The processor can be a general-purpose processor, a digital signal processor (digital signal processor, DSP), an application-specific integrated circuit (application-specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the execution example of this application can be directly embodied as a hardware coding processor to be executed, or the hardware and software modules in the coding processor are combined to be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0148] The memory mentioned in each of the above execution examples may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0149] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the execution examples disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0150] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method execution examples and will not be repeated here.

[0151] In the several implementation examples provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation examples described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0152] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this implementation example.

[0153] In addition, each functional unit in each execution example of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0154] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or in other words, the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including several instructions for a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in each execution example of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0155] The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A built-in self-test method, characterized in that: The method is applied to a system on chip (SOC) of an autonomous driving system on a vehicle, wherein the SOC includes a SOC built-in self-test scheduler, a SOC built-in self-test executor, and a SOC built-in self-test result collector; the method includes: When the SOC is in a first process, the SOC built-in self-test scheduler sends a first self-test start command; The SOC built-in self-test executor receives the first self-test start command, and acquires a first test sequence according to the first self-test start command, wherein the first test sequence is a test sequence that has not been executed and is ranked first in a first test sequence set, wherein the first test sequence set includes a plurality of test sequences, and the first test sequence set is any one of at least one test sequence set obtained based on the division of the SOC self-test object; The SOC built-in self-test executor runs a built-in self-test test BIST to execute the first test sequence and one or more test sequences in the first test sequence set that are arranged after the first test sequence until an end condition in the first self-test start command is met; The SOC built-in self-test result collector obtains a test result according to a condition in which the SOC built-in self-test executor runs the BIST.

2. The method according to claim 1, characterized in that The first process includes a process of switching the SOC from a working state to a shutdown state, a process of switching the SOC from the working state to a sleep state, or a process of switching the SOC from the working state to an idle state.

3. The method according to claim 1 or 2, characterized in that: Also includes: When the SOC is in the second process, the SOC built-in self-test scheduler sends a second self-test start command; The SOC built-in self-test executor receives the second self-test start command, and acquires a second test sequence according to the second self-test start command, wherein the second test sequence is a test sequence that has not been executed and is ranked first in a second test sequence set, the second test sequence set includes a plurality of test sequences, and the second test sequence set is any one of the at least one test sequence set except the first test sequence set; The SOC built-in self-test executor runs the BIST to execute the second test sequence and one or more test sequences in the second test sequence set that are arranged after the second test sequence until an end condition in the second self-test start command is met; The SOC built-in self-test result collector obtains a test result according to a condition in which the SOC built-in self-test executor runs the BIST.

4. The method according to claim 3, characterized in that The first process also includes a process of switching the SOC from a shutdown state to a working state, a process of switching the SOC from a sleep state to the working state, or a process of switching the SOC from an idle state to the working state; The second process includes a switching process of the SOC from the working state to the shutdown state, a switching process of the SOC from the working state to the sleep state, a switching process of the SOC from the working state to the idle state, a switching process of the SOC from the shutdown state to the working state, a switching process of the SOC from the sleep state to the working state, or a switching process of the SOC from the idle state to the working state; And the second process is different from the first process.

5. The method according to claim 3 or 4, characterized in that: Also includes: When the SOC is in the third process, the SOC built-in self-test scheduler sends a third self-test start command; The SOC built-in self-test executor receives the third self-test start command, and acquires a third test sequence according to the third self-test start command, wherein the third test sequence is a test sequence that has not been executed and is ranked first in a third test sequence set, wherein the third test sequence set includes a plurality of test sequences, and the third test sequence set is any one of the at least one test sequence set except the first test sequence set and the second test sequence set; The SOC built-in self-test executor runs the BIST to execute the third test sequence and one or more test sequences in the third test sequence set that are arranged after the third test sequence until an end condition in the third self-test start command is met; The SOC built-in self-test result collector obtains a test result according to a condition in which the SOC built-in self-test executor runs the BIST.

6. The method according to claim 5, characterized in that The third process includes a process of switching the SOC from the working state to the shutdown state, a process of switching the SOC from the working state to the sleep state, a process of switching the SOC from the working state to the idle state, a process of switching the SOC from the shutdown state to the working state, a process of switching the SOC from the sleep state to the working state, or a process of switching the SOC from the idle state to the working state; and the third process is different from the first process and the second process respectively.

7. The method according to any one of claims 1 to 6, characterized in that The at least one test sequence set is obtained by dividing according to at least one factor among a power domain, a reset domain, a clock domain and a functional domain to which the SOC self-test object belongs.

8. The method according to claim 1, characterized in that: The first self-test start command includes the runnable time of the BIST; correspondingly, the end condition in the first self-test start command includes the end of the runnable time of the BIST; or, The first self-test start command includes the number N of test sequences, where N is a positive integer; correspondingly, the end condition in the first self-test start command includes running the BIST to execute N test sequences.

9. The method according to claim 3, characterized in that: The second self-test start command includes the runnable time of the BIST; correspondingly, the end condition in the second self-test start command includes the end of the runnable time of the BIST; or, The second self-test start command includes the number of test sequences N, where N is a positive integer; correspondingly, the end condition in the second self-test start command includes running the BIST to execute N test sequences.

10. The method according to claim 5, characterized in that The third self-test start command includes the runnable time of the BIST; accordingly, the end condition in the third self-test start command includes the end of the runnable time of the BIST; or, The third self-test start command includes the number of test sequences N, where N is a positive integer; accordingly, the end condition in the third self-test start command includes running the BIST to execute N test sequences.

11. The method according to any one of claims 1 to 10, characterized in that Any one of the at least one test sequence set is obtained by dividing according to at least one factor of execution time, space occupancy, voltage specification, current specification, ripple, noise, heat and power consumption, and is the minimum data unit of the BIST execution.

12. A system on chip (SOC), characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that: The invention comprises a computer program, which, when executed on a computer, causes the computer to execute the method according to any one of claims 1 to 11.

14. A computer program product, characterized in that The computer program product comprises a computer program code, and when the computer program code is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 11.

15. A chip, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the method according to any one of claims 1 to 11.

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