Test case online updating method and device, equipment and storage medium

Abstract

The invention provides a test case online updating method and device, equipment and a storage medium, and the method comprises the steps: receiving a script file corresponding to a test case, and analyzing the script file to obtain a plurality of operation instructions and an instruction sequence, the operation instructions comprising instruction objects; sequentially converting the plurality of operation instructions into a plurality of bus protocol operation instructions through a bus interface debugging module; according to the instruction object and the instruction sequence of each bus protocol operation instruction, sequentially sending the plurality of bus protocol operation instructions to corresponding controllers through a bus; and the controller writes the test cases into corresponding storage chips according to the plurality of bus protocol operation instructions.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a test case online updating method, device, equipment and storage medium. Background Art

[0002] At present, FPGA (Field Programmable Gate Array) prototype verification has become the mainstream and mature verification method in the current SoC (System on Chip) chip design. Using the FPGA prototype verification platform, the RTL (register transfer level) code is transplanted to the FPGA for functional verification. In order to fully and completely perform prototype verification on the BMC (Baseboard Management Controller) chip, each module needs to be tested through multiple test cases. The test case program is burned into the flash memory chip for testing, which is generally achieved by burning the flash memory with an external burner. Each time the burning needs to be done, the system needs to be powered off and the flash memory chip is taken out. Repeated powering on and powering off the verification platform will damage the service life of the prototype verification hardware platform; at the same time, the burner takes a long time to burn the flash memory chip, which increases the test time; and repeatedly taking out and placing the flash memory chip from the flash memory base and the burner is easy to cause physical damage to the flash memory chip. In addition, repeated operations may cause the power and ground pins of the flash memory chip to be placed in reverse, thereby affecting the service life of the flash memory chip.

[0003] Therefore, in view of the shortcomings of the prior art solutions, the present invention provides a test case online update method. Summary of the invention

[0004] Based on this, it is necessary to provide a test case online update method, device, equipment and storage medium to address the above technical problems.

[0005] On the one hand, a method for online updating of test cases is provided, the method comprising: receiving a script file corresponding to the test case and parsing the script file to obtain a plurality of operation instructions and an instruction sequence, wherein the operation instruction comprises an instruction object; converting the plurality of operation instructions into a plurality of bus protocol operation instructions in sequence through a bus interface debugging module; sending the plurality of bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; and the controller writing the test case into a corresponding storage chip according to the plurality of bus protocol operation instructions.

[0006] Optionally, before receiving the script file corresponding to the test case, the method includes: determining whether the test case is a bare metal program or a driver program according to user requirements; when the test case is a bare metal program, determining that the instruction object in the script file is a first type of program; when the test case is a driver program, determining that the instruction object in the script file is a first type of program and a second type of program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type of programs, and the driver file is a second type of program.

[0007] Optionally, before receiving the script file corresponding to the test case, it includes: when the instruction object is the first type of program, configuring register parameters, first write parameters, erase parameters and read parameters according to user requirements and the size of the first type of program; determining the configuration instruction according to the register parameters; determining the erase instruction according to the erase parameters, wherein the erase parameters include the number of erase times and the size of the erase unit; determining the first write instruction according to the first write parameters, wherein the first write parameters include the first number of write times and the first write unit size; determining the read instruction according to the read parameters; determining the operation instruction corresponding to the first type of program according to the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; when the instruction object is the second type of program, configuring the second write parameter according to the user requirements and the size of the second type of program; determining the second write instruction according to the second write parameter, wherein the second write parameter includes the second number of write times and the second write unit size; determining the operation instruction corresponding to the second type of program according to the second write instruction.

[0008] Optionally, according to the instruction object of each bus protocol operation instruction and the instruction sequence, the multiple bus protocol operation instructions are sent to the corresponding controller in sequence via the bus, including: when the instruction object in the bus protocol operation instruction is a first type of program, the bus protocol operation instruction is sent to the flash memory controller via the bus; when the instruction object in the bus protocol operation instruction is a second type of program, the bus protocol operation instruction is sent to the double data rate controller via the bus.

[0009] Optionally, according to the instruction object and the instruction sequence of each bus protocol operation instruction, the multiple bus protocol operation instructions are sent to the corresponding controller in sequence through the bus, including: when the instruction object of the bus protocol operation instruction is a first type of program, parsing the multiple bus protocol operation instructions corresponding to the first type of program, and obtaining the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; sending the configuration instruction to the flash memory controller; sending the erase instruction to the flash memory controller, monitoring whether the number of times the erase instruction is sent meets the erase number, and if so, sending the first write instruction to the flash memory controller in sequence; monitoring whether the number of times the first write instruction is sent meets the first write number, and if so, sending the read instruction to the flash memory controller to receive read data; comparing the read data with the first type of program, if the read data is different from the first type of program, returning to send the erase instruction; if the read data is the same as the first type of program, performing a reset operation; when the instruction object of the bus protocol operation instruction is a second type of program, parsing the multiple bus protocol operation instructions corresponding to the second type of program to obtain the second write instruction; sending the second write instruction to the double data transfer rate controller.

[0010] Optionally, the controller writes the test case into a corresponding storage chip according to the multiple bus protocol operation instructions, including: when the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions; when the test case is a driver program, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data transfer rate controller writes the driver file into the double data transfer rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

[0011] Optionally, the method also includes: parsing the driver file to obtain an image file, a system file and a device tree file; according to the starting address of the image file, the starting address of the system file and the starting address of the device tree file in the boot program, the double data transfer rate controller writes the image file, the system file and the device tree file into the double data transfer rate storage chip in sequence.

[0012] On the other hand, a test case online update device is provided, the device comprising: a processing module, used to receive a script file corresponding to the test case and parse the script file to obtain multiple operation instructions and instruction sequences, wherein the operation instruction comprises an instruction object; a conversion module, used to convert the multiple operation instructions into multiple bus protocol operation instructions in sequence through a bus interface debugging module; a sending module, used to send the multiple bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; an updating module, used for the controller to write the test case into a corresponding storage chip according to the multiple bus protocol operation instructions.

[0013] On the other hand, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: receiving a script file corresponding to a test case and parsing the script file to obtain a plurality of operation instructions and instruction sequences, wherein the operation instructions include instruction objects; converting the plurality of operation instructions into a plurality of bus protocol operation instructions in sequence through a bus interface debugging module; sending the plurality of bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; and the controller writing the test case into a corresponding storage chip according to the plurality of bus protocol operation instructions.

[0014] On the other hand, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: receiving a script file corresponding to a test case and parsing the script file to obtain multiple operation instructions and instruction sequences, wherein the operation instructions include instruction objects; converting the multiple operation instructions into multiple bus protocol operation instructions in sequence through a bus interface debugging module; sending the multiple bus protocol operation instructions in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; and the controller writing the test case to a corresponding storage chip according to the multiple bus protocol operation instructions.

[0015] The above-mentioned test case online update method, device, equipment and storage medium, the method includes: receiving a script file corresponding to the test case and parsing the script file to obtain multiple operation instructions and instruction sequences, wherein the operation instruction includes an instruction object; converting the multiple operation instructions into multiple bus protocol operation instructions in sequence through a bus interface debugging module; according to the instruction object and the instruction sequence of each bus protocol operation instruction, sending the multiple bus protocol operation instructions to a corresponding controller in sequence through a bus; the controller writes the test case into a corresponding storage chip according to the multiple bus protocol operation instructions; in this way, the verification time of the prototype verification test case is shortened, the chip burning steps are simplified, the power-on and power-off times of the prototype verification platform are reduced, and the service life of the hardware platform is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a flow chart of a method for online updating of test cases in an embodiment;

[0017] Figure 2 A schematic diagram of an update process of a test case online update method in an embodiment;

[0018] Figure 3 A schematic diagram of the system architecture of a method for online updating of test cases in an embodiment;

[0019] Figure 4 A schematic diagram of a script file flow of a test case online update method in an embodiment;

[0020] Figure 5 It is a structural block diagram of a test case online updating device in an embodiment;

[0021] Figure 6 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] It should be understood that in the description of the present invention, unless the context clearly requires otherwise, words such as “include”, “including” and the like throughout the specification should be interpreted as including rather than being exclusive or exhaustive; that is, as including but not limited to “including”.

[0024] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0025] It should be noted that the terms "S1", "S2", etc. are only used for the purpose of describing the steps, and do not specifically refer to the order or sequence, nor are they used to limit the present invention. They are only for the convenience of describing the method of the present invention, and cannot be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0026] In one embodiment, Figure 1 As shown, a test case online update method is provided, comprising the following steps:

[0027] S101: receiving a script file corresponding to a test case and parsing the script file to obtain a plurality of operation instructions and instruction sequences, wherein the operation instructions include instruction objects.

[0028] Here, the test case is used to verify the function of the chip. For example, the test case can be used to test whether a certain function in the watchdog module is normal. The operation instructions can include read instructions, erase instructions, and write instructions.

[0029] Specifically, a script file configured by a user according to a test case is received, and the script file is parsed to obtain operation instructions for writing the test case into a corresponding chip and the order of the operation instructions.

[0030] S102: Convert the multiple operation instructions into multiple bus protocol operation instructions in sequence through the bus interface debugging module.

[0031] Here, the bus interface debugging module, namely, the IP (Intellectual Property) core, is used to convert the operation instructions of the script file into bus protocol operation instructions that comply with the AXI (Advanced eXtensible Interface) bus operation.

[0032] Specifically, the operation instructions in the script file are formatted and converted into bus protocol operation instructions that meet the bus conditions.

[0033] S103: sending the plurality of bus protocol operation instructions to corresponding controllers in sequence via the bus according to the instruction object and the instruction sequence of each bus protocol operation instruction.

[0034] Here, the instruction object of the bus protocol operation instruction is the instruction object of the operation instruction; the bus is an information transmission line connecting various components, allowing various components to share the transmission medium.

[0035] Furthermore, after the bus protocol operation instruction is sent, the bus protocol operation instruction on the bus needs to be deleted to prevent the bus from being occupied and the next transmission from being unable to be performed.

[0036] Specifically, multiple bus protocol operation instructions are sent to corresponding controllers in sequence through the bus according to the instruction sequence.

[0037] S104: The controller writes the test case into a corresponding storage chip according to the multiple bus protocol operation instructions.

[0038] Specifically, the controller writes the content of the test case into the corresponding storage chip according to the bus protocol operation instruction, thereby realizing online updating of the test case.

[0039] It should be noted that the present invention writes test cases into the chip through script files to realize online update of test cases, which can shorten the verification time of prototype verification test cases, simplify the chip burning steps, reduce the power-on and power-off times of the prototype verification platform, and increase the service life of the hardware platform.

[0040] In some specific implementations, before receiving the script file corresponding to the test case, the process includes:

[0041] According to user requirements, determining that the test case is a bare metal program or a driver;

[0042] When the test case is a bare metal program, determining that the instruction object in the script file is a first type of program;

[0043] When the test case is a driver program, it is determined that the instruction object in the script file is a first type program and a second type program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type programs, and the driver file is a second type program.

[0044] Here, the bare metal module is used to verify the function of the module in the chip, and the driver is used to verify the function of the driver in the chip system.

[0045] The driver includes a boot program and a driver file. Exemplarily, the boot program may be a uboot boot program, and the corresponding driver may be a uImage image file, a uInitrd system file, and a .dtb device tree file.

[0046] In some specific implementations, before receiving the script file corresponding to the test case, the process includes:

[0047] When the instruction object is the first type of program, configuring register parameters, first write parameters, erase parameters and read parameters according to user requirements and the size of the first type of program;

[0048] Determining a configuration instruction according to the register parameter;

[0049] Determining an erase instruction according to the erase parameters, wherein the erase parameters include the number of erase times and the erase unit size;

[0050] Determine a first write instruction according to the first write parameter, wherein the first write parameter includes a first write count and a first write unit size;

[0051] Determining a read instruction according to the read parameter;

[0052] Determining an operation instruction corresponding to the first type of program according to the configuration instruction, the erase instruction, the first write instruction, and the read instruction in sequence;

[0053] When the instruction object is the second type of program, configuring the second writing parameter according to the user requirements and the size of the second type of program;

[0054] Determining a second write instruction according to the second write parameter, wherein the second write parameter includes a second write count and a second write unit size;

[0055] An operation instruction corresponding to the second type program is determined according to the second write instruction.

[0056] Here, the erase instruction is used to instruct to erase a storage space in the chip that is greater than or equal to the size of the first type of program; the first write instruction is used to instruct to write the first type of program into the erased storage space in the chip; the second write instruction is used to instruct to write the second type of program into the chip, which can overwrite the historical second type of program in the chip without performing a chip erase operation.

[0057] The configuration instructions can be used to configure the address mode, line width, etc. For example, you can select a 3-byte address mode or a 4-byte address mode, or you can select a single-line, double-line, or quad-line line width. The configuration instructions can be directly selected according to user needs, or you can combine user needs and test case size to determine the configuration parameters. For example, if the user needs to complete the update within a specified time, combined with the test case size, a line width that meets the requirements can be obtained.

[0058] The number of erase times can be set directly by the user, or the erase unit size can be selected by the user, and the number of erase times can be automatically calculated in combination with the test case size. Correspondingly, the first number of write times and the second number of write times can also be set directly by the user or calculated. Assuming that the erase unit size is 32K bytes and the test case program size is 30K bytes, the number of erase times can be one erase set by the user.

[0059] The read instruction is used to read data of the first type of program written in the chip.

[0060] Furthermore, when the size of the first type of program is larger than the size of the first write unit, the address to which the first first type of program slice is written is a preset starting address, which defaults to 0 and may also be a starting address set by the user. The starting address of the second first type of program slice is the address one digit after the end address of the first first type of program slice, and the starting address of the third first type of program slice is the address one digit after the end address of the second first type of program slice, and so on. The above address determination method is also applicable to erase instructions.

[0061] Furthermore, the second type of program may include multiple subroutines, and the starting address of each subroutine may be a fixed address set by the user. Exemplarily, assuming that the second type of program includes an image file, a system file, and a device tree file, the starting address of the image file may be fixed to 0x100000000, the starting address of the system file may be fixed to 0x103000000, and the device tree address may be fixed to 0x105000000.

[0062] In one embodiment, assuming that two consecutive test cases are both drivers, it is detected whether the boot program and the historical boot program in the chip are the same. If they are the same, the boot program does not need to be updated, and the historical boot program is used as the boot program of the current driver.

[0063] In this way, by setting the number of erasures and the erase unit size, it is not necessary to erase the entire chip each time, and only the chip space required can be erased, thus saving erasure time and improving update efficiency.

[0064] In some specific implementations, the instruction object according to each bus protocol operation instruction sequentially sends the plurality of bus protocol operation instructions to the corresponding controller through the bus, including:

[0065] When the instruction object in the bus protocol operation instruction is a first type of program, sending the bus protocol operation instruction to the flash memory controller via the bus;

[0066] When the instruction object in the bus protocol operation instruction is a second type program, the bus protocol operation instruction is sent to the double data rate controller via the bus.

[0067] Here, the bus protocol operation instruction may also include a controller identification, such as an address or an ID, for identifying a target controller.

[0068] In some specific implementations, the instruction object according to each bus protocol operation instruction sequentially sends the plurality of bus protocol operation instructions to the corresponding controller through the bus, including:

[0069] When the instruction object of the bus protocol operation instruction is a first type of program, parsing multiple bus protocol operation instructions corresponding to the first type of program to sequentially obtain the configuration instruction, the erase instruction, the first write instruction and the read instruction;

[0070] Sending the configuration instruction to a flash memory controller;

[0071] Sending the erase instruction to the flash memory controller, monitoring whether the number of times the erase instruction is sent meets the erase number, and if so, sending the first write instruction to the flash memory controller in sequence;

[0072] monitoring whether the number of times the first write instruction is sent meets the first write number, and if so, sending the read instruction to the flash memory controller to receive read data;

[0073] Compare the read data with the first type of program, and if the read data and the first type of program are not the same, return and send the erase instruction; if the read data and the first type of program are the same, perform a reset operation;

[0074] When the instruction object of the bus protocol operation instruction is a second type of program, parsing a plurality of bus protocol operation instructions corresponding to the second type of program to obtain the second write instruction;

[0075] The second write instruction is sent to the double data rate controller.

[0076] Here, the command sequence corresponding to the first type of program is to first send the configuration command, then send the erase command, then send the write command, and finally send the read command. The command sequence corresponding to the second type of program is to send the write command.

[0077] Furthermore, when the test case is a driver program, the instructions corresponding to the first type of program are sent first, and then the instructions corresponding to the second type of program are sent.

[0078] Exemplarily, the read instruction is specifically to read back the test case program (i.e., the first type of program written into the chip) from the flash chip (i.e., the flash memory chip) for verification, and set the read-back data (i.e., the first type of program written into the chip) to be stored in the file b.txt. In the Linux system of the personal computer, the a.bin (i.e., the test case) is converted into a hexadecimal format file a.txt through the xxd command. By comparing the a.txt and b.txt files, it is confirmed that the first type of program is burned correctly.

[0079] For example, Figure 2 FIG. 1 is a schematic diagram of an update process in an embodiment of the present invention, such as Figure 2 As shown, the update process includes: S201 determines whether the test case is a bare metal program or a uboot program (boot program) or a driver; when the test case is a bare metal program or a uboot program, S202: configure the register of the flash controller; S203: starting from address 0, set the size of the erased space according to the size of the file (i.e., the bare metal program or the uboot program); S204: whether it is completed, if not completed, return to S203, if completed, execute S205; S205: according to the file size, write multiple times in a loop, and accumulate addresses; S206: whether it is completed, if not completed, return to S205, if completed, execute S207; S207: read the data burned into the flash into the file, and compare it with the original file; S208: whether it is consistent, if not consistent, return to S203, if consistent, execute S212; S212: press the system reset button. When the test case is a driver, S209: write uImage file to DDR, with the starting address of 0x100000000, write 4KB each time, and write multiple times in a loop according to the file size, and the address is accumulated; S210: write uInitrd file to DDR, with the starting address of 0x103000000, write 4KB each time, and write multiple times in a loop according to the file size, and the address is accumulated; S211: write .dtb file to DDR, with the starting address of 0x105000000, write 4KB each time, and write multiple times in a loop according to the file size, and the address is accumulated; S212: press the system reset button.

[0080] In one embodiment, after the second type program write instruction is sent, a read instruction may also be sent to read the second type program to detect whether the second type program is burned correctly.

[0081] In this way, the program written into the chip is read back by reading the instruction, and the written data is compared with the test case to see if they are the same, so as to confirm whether the burning is correct.

[0082] In some specific implementations, the controller writes the test case into the corresponding storage chip according to the multiple bus protocol operation instructions, including:

[0083] When the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions;

[0084] When the test case is a driver program, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data rate controller writes the driver file into the double data rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

[0085] Here, the flash memory chip is the flash chip, the double data rate chip is the DDR (Double Data Rate) chip, and the DDR memory speed is greater than the flash programming speed.

[0086] Among them, when the test case is a driver, the boot program is first written into the flash chip, and then the driver file is written into the DDR chip. Exemplarily, when the test case is a driver, uImage, uInitrd and .dtb files can be written into the DDR in sequence according to the address set in the boot program, the number of bytes for each write operation is set to 4KB, the size of each file is read, and the cycle is repeated multiple times until all data is written into the DDR chip.

[0087] Specifically, the flash controller performs operations of erasing, burning, and reading the flash chip according to the received instructions, and the DDR controller writes the program into the external DDR chip.

[0088] In this way, by writing the second type of program into the DDR chip, the update rate is increased.

[0089] In some embodiments, the method further comprises:

[0090] Parsing the driver file to obtain an image file, a system file and a device tree file;

[0091] According to the starting addresses of the image file, the system file and the device tree file in the boot program, the double data rate controller writes the image file, the system file and the device tree file into the double data rate storage chip in sequence.

[0092] Here, the driver file includes an image file, a system file, and a device tree file. The starting address of each sub-file may be fixed. The starting address of the image file may be fixed to 0x100000000, the starting address of the system file may be fixed to 0x103000000, and the starting address of the device tree file may be fixed to 0x105000000.

[0093] Among them, the starting addresses of the image file, system file and device tree file are stored in the boot program, that is, in the flash memory chip. Therefore, it is necessary to write the boot file to the flash memory chip first, read the corresponding address from the boot program of the flash memory chip, and write the image file, system file and device tree file to the corresponding position in the DDR chip according to the address.

[0094] Specifically, uImage, uInitrd and .dtb files are written into DDR in sequence according to the address set by the boot program in the flash chip. The number of bytes for each write operation can be set to 4KB, and the size of each file is read, and the cycle is repeated multiple times until all data is written into DDR.

[0095] In some embodiments, the method further comprises:

[0096] Generate slice check instructions;

[0097] Sending a write instruction and the slice check instruction to a corresponding controller; wherein the write instruction includes a first write instruction or a second write instruction;

[0098] Receive a slice verification result, and determine whether the slice verification is successful according to the slice verification result. If not, retransmit the current program slice until the slice verification is successful.

[0099] Here, the write instruction is used to instruct the controller to write a program slice. The program slice can be a first type program slice or a second type program slice. The corresponding controller can also be a flash memory controller or a double data transfer rate controller. The slice check instruction is used to check whether the splicing between the written program slice and the previous program slice is correct.

[0100] Specifically, according to the write unit size, the test case is divided into multiple program slices, and write instructions and slice verification instructions are sent to the controller, where the write instruction is used to indicate the writing of a program slice. The controller writes the program slice into the corresponding chip according to the write instruction, performs slice verification, and returns the slice verification result.

[0101] In this way, slice verification is performed after each program slice is written, which can improve the correctness of transmission and the stability of data transmission.

[0102] In one embodiment, Figure 3 Schematic diagram of the architecture in the embodiment of the present invention, Figure 3As shown, the architecture of the present invention includes: a PC (Personal Computer) module, a downloader module, a bus interface debugging IP module, a bus arbitration module, a CPU (Central Processing Unit) module, a JTAG (Joint Test Action Group) module, a WDT (Watch Dog Timer) module, a DDR controller module, a flash controller module, a reset button module, a flash chip module and a DDR chip module.

[0103] Specifically, the CPU module is used to run test case programs, such as configuration of test modules, data read and write operations, etc. The flash controller module is a module in the BMC chip, used to perform erase, read and write operations on the flash chip. The bus arbitration module is responsible for arbitration of different types of buses, such as CPU, DDR, flash controller, bus interface debugging IP, WDT module and other modules. The DDR controller module is a DDR controller in the BMC chip, used to perform cache operations on the DDR chip. The WDT module is a watchdog module in the BMC chip to prevent the system from locking. The bus interface debugging IP module is an IP inside the FPGA, which can be instantiated and used to support the axi bus interface.

[0104] Exemplarily, the execution process can be: run the script file on the PC software, the bus interface debugging IP module converts the operation instructions in the script program into axi bus operations, connects to the bus arbitration module, and the bus is sent to the flash controller module or DDR controller module according to the address, ID and other information. The flash controller receives the instructions to erase, burn and read the flash chip, and the DDR controller writes the data to the external DDR chip.

[0105] In one embodiment, Figure 4 Schematic diagram of the script file flow in the embodiment of the present invention, such as Figure 4As shown, the flow of each operation instruction in the script file includes: the write_reg{addr data} subprocess and the read_reg{addr} subprocess both create a write or read operation through create_hw_axi_txn, specify whether it is a write operation or a read operation through the -type parameter, specify the write or read address through the -address parameter, specify the data to be written through -Data during a write operation, and return the read value through return during a read operation. Secondly, run_hw_axi runs the created write or read operation, which is converted into an axi bus write or read operation of the bus debug interface IP. Finally, delete_hw_axi_txn is used to delete this operation, otherwise the bus will be occupied all the time and the next operation cannot be performed. The file is opened through open, and the file is closed through close.

[0106] When the operation instructions are used to operate the bare metal program or boot program, they include proc flash_config, procflash_erase, proc flash_prog, and proc flash_read.

[0107] Specifically, when the proc process is proc flash_config, the proc process calls the write_reg{addrdata} subprocess to configure the register by passing the register address and value. The register value of the read address is returned by calling the read_reg{addr} subprocess and printed out. Configure / read different registers as required.

[0108] Specifically, when the proc process is proc flash_erase, the proc process calls the write_reg{addrdata} subprocess to configure the erase register by passing the register address and value. Check whether the erase is completed by calling the read_reg{addr} subprocess. Configure different erase addresses and sizes multiple times according to requirements.

[0109] Specifically, when the proc process is proc flash_prog, the proc process embeds the flash_write subprocess and is called in a loop, with the number of loops = a.bin size / 256 bytes. The flash controller supports the fifo write mode, and the fifo operation depth is 256 bytes. First, open the a.bin file and convert the binary file into hexadecimal format data, and then read 256 bytes of data in a loop and store them in the array array. Secondly, call the write_reg{addr data} subprocess to configure the write register by passing the register address and value. Check whether the write operation is completed by calling the read_reg{addr} subprocess. After the loop operation is completed, close the open file.

[0110] Specifically, when the proc process is proc flash_read, the proc process sets len to loop through reading, creates b.txt, stores the read data in b.txt, calls the write_reg{addr data} subprocess, and configures the fifo read operation by passing the register address and value. It checks whether the read operation is completed by calling the read_reg{addr} subprocess. After the operation is completed, the open file is closed.

[0111] When the operation instruction is used to operate the driver file, it includes proc wr_4KB, Proc wr_uImage, proc wr_uInitrd and proc wr_dtb. Specifically, Proc wr_uImage, proc wr_uInitrd and proc wr_dtb are all implemented by calling the proc wr_4KB process.

[0112] It should be understood that although Figure 1-4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0113] In one embodiment, Figure 5As shown, a test case online update device is provided, and the device includes: a processing module 501, which is used to receive a script file corresponding to the test case and parse the script file to obtain multiple operation instructions and instruction sequences, wherein the operation instruction includes an instruction object; a conversion module 502, which is used to convert the multiple operation instructions into multiple bus protocol operation instructions in sequence through a bus interface debugging module; a sending module 503, which is used to send the multiple bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; an updating module 504, which is used for the controller to write the test case into a corresponding storage chip according to the multiple bus protocol operation instructions.

[0114] As a preferred implementation manner, in an embodiment of the present invention, the device also includes: a first processing module, the first processing module is specifically used to: determine whether the test case is a bare metal program or a driver program according to user needs; when the test case is a bare metal program, determine that the instruction object in the script file is a first type of program; when the test case is a driver program, determine that the instruction object in the script file is a first type of program and a second type of program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type of programs, and the driver file is a second type of program.

[0115] As a preferred implementation mode, in an embodiment of the present invention, the device further includes: a second processing module, wherein the second processing module is specifically used for: when the instruction object is the first type of program, configuring register parameters, first write parameters, erase parameters and read parameters according to user requirements and the size of the first type of program; determining the configuration instruction according to the register parameters; determining the erase instruction according to the erase parameters, wherein the erase parameters include the number of erase times and the size of the erase unit; determining the first write instruction according to the first write parameters, wherein the first write parameters include the first number of write times and the first write unit size; determining the read instruction according to the read parameters; determining the operation instruction corresponding to the first type of program according to the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; when the instruction object is the second type of program, configuring the second write parameter according to the user requirements and the size of the second type of program; determining the second write instruction according to the second write parameters, wherein the second write parameters include the second number of write times and the second write unit size; determining the operation instruction corresponding to the second type of program according to the second write instruction.

[0116] As a preferred implementation manner, in an embodiment of the present invention, the sending module 503 is specifically used for: when the instruction object in the bus protocol operation instruction is a first type of program, sending the bus protocol operation instruction to the flash memory controller via the bus; when the instruction object in the bus protocol operation instruction is a second type of program, sending the bus protocol operation instruction to the double data transfer rate controller via the bus.

[0117] As a preferred implementation mode, in an embodiment of the present invention, the sending module 503 is specifically used for: when the instruction object of the bus protocol operation instruction is a first type of program, parsing multiple bus protocol operation instructions corresponding to the first type of program, and obtaining the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; sending the configuration instruction to the flash memory controller; sending the erase instruction to the flash memory controller, monitoring whether the number of times the erase instruction is sent meets the erase number, and if so, sending the first write instruction to the flash memory controller in sequence; monitoring whether the number of times the first write instruction is sent meets the first write number, and if so, sending the read instruction to the flash memory controller to receive read data; comparing the read data with the first type of program, if the read data is different from the first type of program, returning to send the erase instruction; if the read data is the same as the first type of program, performing a reset operation; when the instruction object of the bus protocol operation instruction is a second type of program, parsing multiple bus protocol operation instructions corresponding to the second type of program, and obtaining the second write instruction; sending the second write instruction to the double data transfer rate controller.

[0118] As a preferred implementation manner, in an embodiment of the present invention, the update module 504 is specifically used for: when the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions; when the test case is a driver, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data rate controller writes the driver file into the double data rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

[0119] As a preferred implementation manner, in an embodiment of the present invention, the update module 5504 is specifically further used to: parse the driver file to obtain a mirror file, a system file and a device tree file; according to the starting address of the mirror file, the starting address of the system file and the starting address of the device tree file in the boot program, the double data transfer rate controller writes the mirror file, the system file and the device tree file into the double data transfer rate storage chip in sequence.

[0120] The specific definition of the test case online update device can be found in the definition of the test case online update method above, which will not be repeated here. Each module in the above-mentioned test case online update device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0121] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a test case online update method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0122] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0123] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: S1: receiving a script file corresponding to a test case and parsing the script file to obtain a plurality of operation instructions and instruction sequences, wherein the operation instructions include instruction objects; S2: converting the plurality of operation instructions into a plurality of bus protocol operation instructions in sequence through a bus interface debugging module; S3: sending the plurality of bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; S4: the controller writes the test case into a corresponding storage chip according to the plurality of bus protocol operation instructions.

[0124] In one embodiment, when the processor executes the computer program, the following steps are also implemented: according to user requirements, determining that the test case is a bare metal program or a driver program; when the test case is a bare metal program, determining that the instruction object in the script file is a first type of program; when the test case is a driver program, determining that the instruction object in the script file is a first type of program and a second type of program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type of programs, and the driver file is a second type of program.

[0125] In one embodiment, when the processor executes the computer program, the following steps are also implemented: when the instruction object is the first type of program, the register parameters, the first write parameters, the erase parameters and the read parameters are configured according to user requirements and the size of the first type of program; the configuration instruction is determined according to the register parameters; the erase instruction is determined according to the erase parameters, wherein the erase parameters include the number of erase times and the erase unit size; the first write instruction is determined according to the first write parameters, wherein the first write parameters include the first number of write times and the first write unit size; the read instruction is determined according to the read parameters; the operation instruction corresponding to the first type of program is determined according to the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; when the instruction object is the second type of program, the second write parameter is configured according to the user requirements and the size of the second type of program; the second write instruction is determined according to the second write parameters, wherein the second write parameter includes the second number of writes and the second write unit size; the operation instruction corresponding to the second type of program is determined according to the second write instruction.

[0126] In one embodiment, when the processor executes a computer program, the following steps are also implemented: when the instruction object in the bus protocol operation instruction is a first type of program, the bus protocol operation instruction is sent to a flash memory controller via a bus; when the instruction object in the bus protocol operation instruction is a second type of program, the bus protocol operation instruction is sent to a double data rate controller via a bus.

[0127] In one embodiment, when the processor executes the computer program, the following steps are also implemented: when the instruction object of the bus protocol operation instruction is a first type of program, multiple bus protocol operation instructions corresponding to the first type of program are parsed to obtain the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; the configuration instruction is sent to the flash memory controller; the erase instruction is sent to the flash memory controller to monitor whether the number of times the erase instruction is sent meets the erase number, and if so, the first write instruction is sent to the flash memory controller in sequence; the number of times the first write instruction is sent meets the first write number, and if so, the read instruction is sent to the flash memory controller to receive read data; the read data is compared with the first type of program, and if the read data is different from the first type of program, the erase instruction is returned to send; if the read data is the same as the first type of program, a reset operation is performed; when the instruction object of the bus protocol operation instruction is a second type of program, multiple bus protocol operation instructions corresponding to the second type of program are parsed to obtain the second write instruction; and the second write instruction is sent to the double data rate controller.

[0128] In one embodiment, the processor further implements the following steps when executing a computer program: when the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions; when the test case is a driver program, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data rate controller writes the driver file into the double data rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

[0129] In one embodiment, when the processor executes the computer program, the following steps are also implemented: parsing the driver file to obtain an image file, a system file and a device tree file; according to the starting address of the image file, the starting address of the system file and the starting address of the device tree file in the boot program, the double data rate controller writes the image file, the system file and the device tree file into the double data rate storage chip in sequence.

[0130] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: S1: receiving a script file corresponding to a test case and parsing the script file to obtain multiple operation instructions and instruction sequences, wherein the operation instructions include instruction objects; S2: converting the multiple operation instructions into multiple bus protocol operation instructions in sequence through a bus interface debugging module; S3: sending the multiple bus protocol operation instructions to a corresponding controller in sequence through a bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; S4: the controller writes the test case into a corresponding storage chip according to the multiple bus protocol operation instructions.

[0131] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to user requirements, determining that the test case is a bare metal program or a driver program; when the test case is a bare metal program, determining that the instruction object in the script file is a first type of program; when the test case is a driver program, determining that the instruction object in the script file is a first type of program and a second type of program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type of programs, and the driver file is a second type of program.

[0132] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the instruction object is the first type of program, the register parameters, the first write parameters, the erase parameters and the read parameters are configured according to user requirements and the size of the first type of program; the configuration instruction is determined according to the register parameters; the erase instruction is determined according to the erase parameters, wherein the erase parameters include the number of erase times and the erase unit size; the first write instruction is determined according to the first write parameters, wherein the first write parameters include the first number of write times and the first write unit size; the read instruction is determined according to the read parameters; the operation instruction corresponding to the first type of program is determined according to the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; when the instruction object is the second type of program, the second write parameter is configured according to the user requirements and the size of the second type of program; the second write instruction is determined according to the second write parameters, wherein the second write parameter includes the second number of write times and the second write unit size; the operation instruction corresponding to the second type of program is determined according to the second write instruction.

[0133] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the instruction object in the bus protocol operation instruction is a first type of program, the bus protocol operation instruction is sent to the flash memory controller via the bus; when the instruction object in the bus protocol operation instruction is a second type of program, the bus protocol operation instruction is sent to the double data rate controller via the bus.

[0134] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the instruction object of the bus protocol operation instruction is a first type program, a plurality of bus protocol operation instructions corresponding to the first type program are parsed to obtain the configuration instruction, the erase instruction, the first write instruction and the read instruction in sequence; the configuration instruction is sent to the flash memory controller; the erase instruction is sent to the flash memory controller to monitor whether the number of times the erase instruction is sent meets the erase number, and if so, the first write instruction is sent to the flash memory controller in sequence; the number of times the first write instruction is sent meets the first write number, and if so, the read instruction is sent to the flash memory controller to receive read data; the read data is compared with the first type program, and if the read data is different from the first type program, the erase instruction is sent back; if the read data is the same as the first type program, a reset operation is performed; when the instruction object of the bus protocol operation instruction is a second type program, a plurality of bus protocol operation instructions corresponding to the second type program are parsed to obtain the second write instruction; and the second write instruction is sent to the double data rate controller.

[0135] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions; when the test case is a driver program, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data rate controller writes the driver file into the double data rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

[0136] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: parsing the driver file to obtain an image file, a system file and a device tree file; according to the starting address of the image file, the starting address of the system file and the starting address of the device tree file in the boot program, the double data rate controller writes the image file, the system file and the device tree file into the double data rate storage chip in sequence.

[0137] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0138] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A test case online update method, It is characterized in that The method comprises: Receiving a script file corresponding to the test case and parsing the script file to obtain a plurality of operation instructions and instruction sequences, wherein the operation instructions include instruction objects; Converting the plurality of operation instructions into a plurality of bus protocol operation instructions in sequence through a bus interface debugging module; According to the instruction object and the instruction sequence of each bus protocol operation instruction, the plurality of bus protocol operation instructions are sequentially sent to the corresponding controller via the bus; The controller writes the test case into a corresponding storage chip according to the multiple bus protocol operation instructions.

2. The test case online updating method according to claim 1, It is characterized in that Before receiving the script file corresponding to the test case, the following steps are included: According to user requirements, determining that the test case is a bare metal program or a driver; When the test case is a bare metal program, determining that the instruction object in the script file is a first type of program; When the test case is a driver program, it is determined that the instruction object in the script file is a first type program and a second type program, wherein the driver program includes a boot program and a driver file, the boot program and the bare metal program are first type programs, and the driver file is a second type program.

3. The test case online updating method according to claim 2, It is characterized in that Before receiving the script file corresponding to the test case, the following steps are included: When the instruction object is the first type of program, configuring register parameters, first write parameters, erase parameters and read parameters according to user requirements and the size of the first type of program; Determining a configuration instruction according to the register parameter; Determining an erase instruction according to the erase parameters, wherein the erase parameters include the number of erase times and the erase unit size; Determine a first write instruction according to the first write parameter, wherein the first write parameter includes a first write count and a first write unit size; Determining a read instruction according to the read parameter; Determining an operation instruction corresponding to the first type of program according to the configuration instruction, the erase instruction, the first write instruction, and the read instruction in sequence; When the instruction object is the second type of program, configuring the second writing parameter according to the user requirements and the size of the second type of program; Determining a second write instruction according to the second write parameter, wherein the second write parameter includes a second write count and a second write unit size; An operation instruction corresponding to the second type program is determined according to the second write instruction.

4. The test case online updating method according to claim 2, It is characterized in that The method of sending the plurality of bus protocol operation instructions to the corresponding controller in sequence through the bus according to the instruction object and the instruction sequence of each bus protocol operation instruction comprises: When the instruction object in the bus protocol operation instruction is a first type of program, sending the bus protocol operation instruction to the flash memory controller via the bus; When the instruction object in the bus protocol operation instruction is a second type program, the bus protocol operation instruction is sent to the double data rate controller via the bus.

5. The test case online updating method according to claim 3, It is characterized in that The method of sending the plurality of bus protocol operation instructions to the corresponding controller in sequence through the bus according to the instruction object and the instruction sequence of each bus protocol operation instruction comprises: When the instruction object of the bus protocol operation instruction is a first type of program, parsing multiple bus protocol operation instructions corresponding to the first type of program to sequentially obtain the configuration instruction, the erase instruction, the first write instruction and the read instruction; Sending the configuration instruction to a flash memory controller; Sending the erase instruction to the flash memory controller, monitoring whether the number of times the erase instruction is sent meets the erase number, and if so, sending the first write instruction to the flash memory controller in sequence; monitoring whether the number of times the first write instruction is sent meets the first write number, and if so, sending the read instruction to the flash memory controller to receive read data; Compare the read data with the first type of program, and if the read data and the first type of program are not the same, return and send the erase instruction; if the read data and the first type of program are the same, perform a reset operation; When the instruction object of the bus protocol operation instruction is a second type of program, parsing a plurality of bus protocol operation instructions corresponding to the second type of program to obtain the second write instruction; The second write instruction is sent to the double data rate controller.

6. The test case online updating method according to claim 2, It is characterized in that The controller writes the test case into the corresponding storage chip according to the multiple bus protocol operation instructions, including: When the test case is a bare metal program, the flash memory controller writes the bare metal program into the flash memory chip according to the multiple bus protocol operation instructions; When the test case is a driver program, the flash memory controller writes the boot program into the flash memory chip according to the bus protocol operation instructions corresponding to the boot program, and the double data rate controller writes the driver file into the double data rate storage chip according to the bus protocol operation instructions corresponding to the driver file.

7. The test case online updating method according to claim 6, It is characterized in that The method further comprises: Parsing the driver file to obtain an image file, a system file and a device tree file; According to the starting addresses of the image file, the system file and the device tree file in the boot program, the double data rate controller writes the image file, the system file and the device tree file into the double data rate storage chip in sequence.

8. A test case online updating device, It is characterized in that The device comprises: A processing module, configured to receive a script file corresponding to a test case and parse the script file to obtain a plurality of operation instructions and instruction sequences, wherein the operation instructions include instruction objects; A conversion module, used for converting the plurality of operation instructions into a plurality of bus protocol operation instructions in sequence through a bus interface debugging module; A sending module, used for sending the plurality of bus protocol operation instructions to the corresponding controller in sequence through the bus according to the instruction object and the instruction sequence of each bus protocol operation instruction; An update module is used for the controller to write the test case into the corresponding storage chip according to the multiple bus protocol operation instructions.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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