Highly programmable processor array network

Abstract

The invention belongs to the technical field of computers, and particularly relates to a highly programmable processor array network which comprises a processor array, the processor array is provided with a plurality of processor units distributed in an array, each processor unit is provided with a processor node and a register group, and adjacent processor nodes perform data interaction through the register group; and the dynamic random access memory layer is provided with one or more layers of dynamic random access memories, the dynamic random access memory layer is stacked on the upper layer of the processor array, and each dynamic random access memory is connected with each processor node. The chip is designed into a processor array form, the size of the processor array can be customized at will during packaging, cutting is carried out according to requirements, and the purpose of a single-wafer large chip can be achieved.

Description

Technical Field

[0001] The invention belongs to the field of computer technology, and in particular relates to a highly programmable processor array network. Background Art

[0002] Traditional field programmable gate arrays (FPGAs) provide extremely high design flexibility through programmable logic blocks and interconnect resources, and are widely used in customized computing and acceleration fields. However, when implementing highly complex computing tasks, FPGAs have high programming complexity and relatively low energy efficiency because their basic building blocks are logic gates and lookup tables. Summary of the invention

[0003] The present invention aims to provide a highly programmable processor array network in order to solve the technical problems that traditional FPGAs have high programming complexity and relatively low energy efficiency when implementing highly complex computing tasks.

[0004] In order to solve the above technical problems, the present invention provides a highly programmable processor array network, the highly programmable processor array network comprising:

[0005] A processor array, wherein the processor array has a plurality of processor units distributed in an array, the processor units have processor nodes and register groups, and adjacent processor nodes exchange data through the register groups;

[0006] A dynamic random access memory layer, wherein the dynamic random access memory layer has one or more layers of dynamic random access memory, the dynamic random access memory layer is stacked on the upper layer of the processor array, and each dynamic random access memory is connected to each processor node respectively.

[0007] Optionally, in the highly programmable processor array network as described above, the processor array has 2 n The processor units are distributed in an array, wherein n is a natural number;

[0008] When n is an even number, the processor array has 2 n / 2 Row and 2 n / 2 List;

[0009] When n is an odd number, the processor array has 2 (n-1) / 2 Row and 2 (n+1) / 2 List.

[0010] Optionally, in the highly programmable processor array network as described above, in a single processor unit, the register group is located around the processor node, and the register group exchanges data with other adjacent processor units in four directions respectively.

[0011] Optionally, in the highly programmable processor array network as described above, in a single processor unit, the processor node and the register group are connected via a metal layer copper interconnection;

[0012] In adjacent processor units, two adjacent register groups are connected via metal layer copper interconnection.

[0013] Optionally, in the highly programmable processor array network as described above, in a single processor unit, storage controller nodes are arranged around the processor node, and the processor node interacts with the register groups in four directions through the storage controller nodes in four directions respectively.

[0014] Optionally, in the highly programmable processor array network as described above, in a single processor unit, the processor node is connected to the storage controller node via a metal layer copper interconnect, and the storage controller node is connected to the register group via a metal layer copper interconnect;

[0015] In adjacent processor units, two adjacent register groups are connected via metal layer copper interconnection.

[0016] Optionally, in the highly programmable processor array network as described above, the processor node includes a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a data processing unit (DPU), an intelligent processor (IPU) or a neural-network processing unit (NPU).

[0017] Optionally, in the highly programmable processor array network as described above, the processor array projection completely overlaps with the dynamic random access memory layer area.

[0018] Optionally, in the highly programmable processor array network as described above, the processor node is connected to the dynamic random access memory layer through the register group.

[0019] Optionally, in the highly programmable processor array network as described above, the register group and the dynamic random access memory layer are connected via metal layer copper interconnection.

[0020] Optionally, in the highly programmable processor array network as described above, the dynamic random access memory layer has independent storage space belonging to each of the processor nodes.

[0021] Optionally, in the highly programmable processor array network as described above, each of the processor nodes shares all address spaces within the dynamic random access memory layer.

[0022] The positive and progressive effects of the present invention are:

[0023] 1. The present invention is designed in the form of a processor array. The size of the processor array can be customized at will during packaging, and it can be cut according to demand, and the purpose of a single wafer large chip can also be achieved.

[0024] 2. The equality and decentralization among all processor nodes of the present invention enable each processor node in the network to have the function of a host, without the distinction between master and slave. Each processor node has its own memory management, control logic and external communication capabilities. Any node can initiate computing tasks, manage data transmission and control the collaboration of other nodes without relying on a single central controller.

[0025] 3. The present invention provides a higher level of abstraction by using processor nodes as basic units, reduces programming complexity, and facilitates the development of complex algorithms and applications. The fine control and dynamic resource management of processor nodes can effectively reduce idle power consumption and improve the energy efficiency ratio when processing specific tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The disclosure of the present invention will become more apparent with reference to the accompanying drawings. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings:

[0027] Figure 1 A local connection diagram of a processor array of the present invention;

[0028] Figure 2 Another partial connection diagram of the processor array of the present invention;

[0029] Figure 3 It is a partial connection schematic diagram of the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be noted that the following embodiments and features therein may be combined with each other if there is no conflict.

[0032] In the description of the present invention, it should be noted that directional words such as the terms "outside", "middle", "inside", "outside", etc., which indicate directions and positional relationships, are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific protection scope of the present invention.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the definition of "first" and "second" features can explicitly or implicitly include one or more of the features. In the description of the present invention, "several" and "a number" mean two or more, unless otherwise clearly and specifically defined.

[0034] Reference Figures 1 to 3 An embodiment of the present invention provides a highly programmable processor array network (CPPA: Configurable Processor Array Network), which replaces the basic unit of FPGA from logic gate array to small processor nodes (such as CPU core or GPU core, etc.), forming a highly programmable processor array network to achieve a higher level of computing abstraction and energy efficiency improvement.

[0035] The highly programmable processor array network of the present invention comprises a processor array 1 and a dynamic random access memory layer 2 .

[0036] The processor array 1 has a plurality of processor units 11 distributed in an array. The processor unit 11 has a processor node 111 and a register group 112 (also called a register group). Adjacent processor nodes 111 exchange data via the register group 112 .

[0037] The DRAM layer 2 has one or more layers of DRAM 21 . The DRAM layer 2 is stacked on the upper layer of the processor array 1 . Each DRAM 21 is connected to each processor node 111 .

[0038] The present invention is designed in the form of a processor array. The size of the processor array can be customized at will during packaging, and it can be cut according to demand, and the purpose of a single wafer large chip can also be achieved.

[0039] The present invention uses three-dimensional stacking technology to construct a CPPA consisting of a multi-core processor node core layer and multiple DRAM layers. All processor nodes share the DRAM space of the upper stack to achieve efficient data exchange and computing resource optimization, which is particularly suitable for data-intensive tasks such as AI and big data processing.

[0040] Each processor node of the present invention is designed as an autonomous unit with its own memory management, control logic and external communication capabilities. Each processor node is equipped with complete computing resources and control logic, and can independently execute program code, manage local memory and interact with peripherals. This means that any processor node can initiate computing tasks, manage data transmission and control the collaboration of other nodes without relying on a single central controller.

[0041] The task scheduling and allocation of the present invention is no longer controlled by a single host, but can be achieved through a distributed task scheduling algorithm on the network, which balances task allocation based on the current load, resource availability and task characteristics of the processor node. Each processor node communicates directly through a standardized protocol without the need for a central controller. Each processor node can dynamically decide to accept new tasks, delegate tasks to other nodes or request resources based on the current load, resource status and task queue, thus realizing a true peer-to-peer computing environment.

[0042] Specifically, a resource scheduling system with a distributed task scheduling algorithm can be used to dynamically allocate memory resources, optimize data distribution according to task requirements and runtime conditions, reduce data replication and migration, and improve data access efficiency.

[0043] In some embodiments, the processor array 1 has 2 n processor units 11 are arranged in an array, where n is a natural number. When n is an even number, the processor array 1 has 2 n / 2 Row and 2 n / 2 When n is an odd number, processor array 1 has 2 (n -1) / 2 Row and 2 (n+1) / 2 List.

[0044] Through the above reasonable design, it is convenient to cut the processor array 1 into the required network size according to the demand.

[0045] In some embodiments, reference Figure 1 In a single processor unit 11, the register group 112 is located around the processor node 111, and the register group 112 exchanges data with other adjacent processor units 11 in four directions respectively.

[0046] In some embodiments, in a single processor unit 11, the processor node 111 and the register group 112 are connected via metal layer copper interconnects.

[0047] In adjacent processor units 11, two adjacent register groups 112 are connected via metal layer copper interconnection.

[0048] Metal layer copper interconnects ensure low latency for data transmission.

[0049] In some embodiments, reference Figure 2 In a single processor unit 11 , memory controller nodes 113 (Memory control, MC) are arranged around the processor node 111 , and the processor node 111 exchanges data with register groups 112 in four directions through the memory controller nodes 113 in four directions.

[0050] In some embodiments, reference Figure 3 In a single processor unit 11, the processor node 111 is connected to the storage controller node 113 via a metal layer copper interconnection, and the storage controller node 113 is connected to the register group 112 via a metal layer copper interconnection.

[0051] In adjacent processor units 11, two adjacent register groups 112 are connected via metal layer copper interconnection.

[0052] In some embodiments, the processor node 111 includes a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a data processing unit (DPU), an intelligent processor (IPU), or a neural-network processing unit (NPU).

[0053] Therefore, the present invention adopts three-dimensional stacking technology to construct a CPPA mainly consisting of a multi-core CPU / GPU / TPU / DPU / IPU / NPU core layer and multiple DRAM layers.

[0054] In some embodiments, the projection of the processor array 1 completely overlaps with the area of ​​the upper DRAM layer 2 .

[0055] In some embodiments, reference Figure 3 The processor node 111 is connected to the dynamic random access memory layer 2 through the register group 112.

[0056] In some embodiments, the register group 112 is connected to the dynamic random access memory layer 2 via a metal layer copper interconnect.

[0057] Specifically, when the dynamic random access memory layer 2 is composed of several layers of dynamic random access memories 21 , the register group 112 is distributed and connected to each layer of the dynamic random access memories 21 through metal layer copper interconnections.

[0058] In some embodiments, in order to achieve decentralization between processor nodes, in the storage space of the upper DRAM, the dynamic random access memory layer 2 has an independent storage space belonging to each processor node 111. The independent storage space is controlled and allocated by the local memory management circuit of the processor node.

[0059] In some embodiments, in order to achieve high-speed data communication and strong data correlation between processor nodes, each processor node 111 shares all address spaces in the dynamic random access memory layer 2. That is, all processor nodes 111 can access all addresses in the dynamic random access memory layer 2.

[0060] In some embodiments, in the CPPA of the present invention, an efficient NoC (network on chip) can be integrated to optimize the transmission of data between processor nodes and DRAM, and support high-bandwidth, low-latency communication. NoC uses a dynamic routing algorithm to intelligently adjust the data flow according to network conditions and task priorities to improve the parallelism of data processing. The NoC architecture adopts a multi-dimensional ring or two-dimensional grid topology to ensure that data can be transmitted in multiple directions and reduce transmission bottlenecks. The dynamic routing algorithm is based on a distributed adaptive mechanism, collects network traffic information and task priority indicators, and uses a first-in-first-out (FIFO) queue combined with a priority queue management strategy to dynamically plan the best path for data transmission. In addition, the flow control mechanism embedded in the NoC can prevent data packet conflicts and congestion, further improving the smoothness and efficiency of data transmission.

[0061] In some embodiments, in the CPPA of the present invention, the micro-architecture of the processor node can be fine-grained customized using the hardware description language (HDL) level, such as instruction set, cache size, and interconnect topology.

[0062] The present invention is described in detail above in conjunction with the embodiments of the drawings, and those skilled in the art can make various variations of the present invention according to the above description. Therefore, certain details in the embodiments should not constitute limitations on the present invention, and the present invention shall be protected by the scope defined by the attached claims.

Claims

1. A highly programmable processor array network, characterized in that: The highly programmable processor array network comprises: A processor array, wherein the processor array has a plurality of processor units distributed in an array, the processor units have processor nodes and register groups, and adjacent processor nodes exchange data through the register groups; A dynamic random access memory layer, wherein the dynamic random access memory layer has one or more layers of dynamic random access memory, the dynamic random access memory layer is stacked on the upper layer of the processor array, and each dynamic random access memory is connected to each processor node respectively.

2. The highly programmable processor array network of claim 1, wherein: The processor array has 2 n The processor units are distributed in an array, wherein n is a natural number; When n is an even number, the processor array has 2 n / 2 Row and 2 n / 2 List; When n is an odd number, the processor array has 2 (n-1) / 2 Row and 2 (n+1) / 2 List.

3. The highly programmable processor array network of claim 1, wherein: In a single processor unit, the register group is located around the processor node, and the register group exchanges data with other adjacent processor units in four directions respectively.

4. The highly programmable processor array network of claim 3, wherein: In a single processor unit, the processor node and the register group are connected via a metal layer copper interconnection; In adjacent processor units, two adjacent register groups are connected via metal layer copper interconnection.

5. The highly programmable processor array network of claim 1, wherein: In a single processor unit, storage controller nodes are arranged around the processor node, and the processor node exchanges data with the register groups in four directions respectively through the storage controller nodes in four directions.

6. The highly programmable processor array network of claim 5, wherein: In a single processor unit, the processor node is connected to the storage controller node via a metal layer copper interconnect, and the storage controller node is connected to the register group via a metal layer copper interconnect; In adjacent processor units, two adjacent register groups are connected via metal layer copper interconnection.

7. The highly programmable processor array network of claim 1, wherein: The processor node includes a central processing unit, a graphics processing unit, a tensor processor, a processor distribution processor, an intelligent processor or a neural network processor.

8. A highly programmable processor array network as claimed in any one of claims 1 to 7, characterized in that: The processor array projection completely overlaps with the dynamic random access memory layer area.

9. The highly programmable processor array network of claim 8, wherein: The processor node is connected to the dynamic random access memory layer through the register group.

10. The highly programmable processor array network of claim 9, wherein: The register group is connected to the dynamic random access memory layer through a metal layer copper interconnection.

11. The highly programmable processor array network of claim 8, wherein: The dynamic random access memory layer has independent storage space belonging to each processor node.

12. The highly programmable processor array network of claim 8, wherein: Each of the processor nodes shares all address spaces in the dynamic random access memory layer.

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