Chip, data processing method and electronic equipment
By using the random number latch module, operation module and clock scrambling module in the chip to XOR processing and random clock signal scrambling the initial key and data to be encrypted, the data security problem caused by key leakage is solved, and the data is realized. Higher data security and attack resistance.
Patent Information
- Application Number
- CN202411218125.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-17
AI Technical Summary
During the encryption algorithm operation of existing chips, key leakage is easily cracked, resulting in data security being unable to be guaranteed.
Design a chip, including a random number latch module, a computing module, an encryption module and a clock scrambling module, generate target key and initial encrypted data by XOR processing of the initial key and data to be encrypted, and use target encryption The key is encrypted and the clock signal is randomly scrambled, and a random clock signal is generated and inputted to the encryption module to enhance data security.
Through XOR processing and random clock signal scrambling, the security of the key and data resistance to attacks are improved, the risk of cracking is reduced, and the data security of the chip is enhanced.
Smart Images
Figure CN119150373A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and more specifically to a chip, a data processing method and an electronic device. Background Art
[0002] In order to ensure the security of chip data, the key corresponding to the encryption algorithm is usually used to encrypt the data to be encrypted. However, if the key is leaked, it is easy to be used by data theft methods combined with the corresponding encryption algorithm to crack the encrypted data, and the security of chip data cannot be guaranteed. Summary of the invention
[0003] In view of this, this application provides the following technical solutions:
[0004] A chip, comprising:
[0005] Random number latch module, operation module, encryption module and clock scrambling module;
[0006] The random number latch module is used to latch the generated random number to obtain a first random number and a second random number;
[0007] The operation module is used to perform XOR processing on the initial key based on the first random number to obtain the target key; and perform XOR processing on the data to be encrypted based on the second random number to obtain the initial encrypted data;
[0008] The encryption module is used to encrypt the initial encrypted data using the target key to obtain target encrypted data;
[0009] The clock scrambling module is used to perform random scrambling processing on the clock signal based on a random number to obtain a target clock signal, and input the target clock signal into the encryption module.
[0010] Optionally, the chip further includes: a decryption module;
[0011] The decryption module is used to decrypt the target encrypted data based on the key to obtain initial encrypted data;
[0012] The operation module is further used to perform XOR initialization on the initial encrypted data based on the second random number to obtain plaintext data.
[0013] Optionally, the chip further includes a control module and a random number generator;
[0014] The random number generator is used to output a random number;
[0015] The control module is used to generate a target control signal according to a time interval for latching a random number, and input the target control signal into the random number latch module;
[0016] The random number latch module is used to latch the random number output by the random number generator according to the target signal to obtain a first random number or a second random number.
[0017] Optionally, the control module is further used to: generate a first random number control signal in the target control signal based on the length of the initial key, wherein the first random number control signal includes a first number of first control sub-signals;
[0018] The random number latch module is used to latch the random number output by the random number generator based on each of the first control sub-signals to obtain a first random number set, wherein the number of first random numbers in the first random number set matches the first number, and the first number is related to the length of the initial key;
[0019] The operation module is further used to perform XOR processing on each first random number in the first random number set and the initial key to obtain a target key.
[0020] The control module is also used for:
[0021] Based on the length of the data to be encrypted, generating a second random number control signal in the target control signal, wherein the second random number control signal includes a second number of second control sub-signals;
[0022] The random number latch module is further used to latch the random number output by the random number generator based on each of the second control sub-signals to obtain a second random number set, the number of second random numbers in the second random number set matches the second number, and the second number is related to the length of the data to be encrypted;
[0023] The operation module is further used to perform XOR processing on each second random number in the second random number set and the data to be encrypted to obtain initial encrypted data.
[0024] Optionally, the clock scrambling module is further used to input the target clock signal into the decryption module.
[0025] Optionally, the clock scrambling module is further used to input the target clock signal into the random number latch module.
[0026] A data processing method, applied to the above-mentioned chip, comprising:
[0027] The generated random number is latched to obtain a first random number and a second random number;
[0028] The generated random number is latched to obtain a first random number and a second random number;
[0029] Performing XOR processing on the initial key based on the first random number to obtain a target key;
[0030] Performing XOR processing on the data to be encrypted based on the second random number to obtain initial encrypted data;
[0031] Using the target key to encrypt the initial encrypted data to obtain target encrypted data;
[0032] The clock signal is randomly scrambled based on a random number to obtain a target clock signal, and the target clock signal is input into the encryption module.
[0033] Optionally, the method further comprises:
[0034] Decrypting the target encrypted data based on the target key to obtain initial encrypted data;
[0035] The initial encrypted data is XOR-ed based on the second random number to obtain plaintext data.
[0036] An electronic device comprises a chip as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0038] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of the present application;
[0039] Figure 2 A module composition diagram of a chip capable of encryption and decryption provided in an embodiment of the present application;
[0040] Figure 3 A data flow diagram of each module in a chip provided in an embodiment of the present application;
[0041] Figure 4 A power consumption waveform diagram provided in an embodiment of the present application;
[0042] Figure 5 A flowchart of a data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0044] The terms "first" and "second" in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.
[0045] The present application provides another chip, which can be used in different scenarios, such as in financial bank cards, computer equipment, vehicle processors or cloud computing equipment. In order to ensure the security of chip data, a corresponding encryption algorithm will be used to encrypt the data. However, when the chip is performing cryptographic algorithm calculations, the current curve consumed by the chip will contain certain key information. Some attack techniques can analyze the key through multiple current curves and then crack the chip data. To solve this type of problem, the present application provides a chip, see Figure 1 , the chip includes:
[0046] A random number latch module 101 , a calculation module 102 , an encryption module 103 and a clock scrambling module 104 .
[0047] The random number latch module 101 is used to latch the generated random number to obtain the first random number and the second random number. The operation module 102 is used to perform XOR processing on the initial key based on the first random number to obtain the target key; and perform XOR processing on the encrypted data based on the second random number to obtain the initial encrypted data. The encryption module 103 is used to encrypt the initial encrypted data using the target key to obtain the target key data. The clock scrambling module 104 is used to perform random scrambling processing on the clock signal based on the random number to obtain the target clock information, and input the target clock signal into the encryption module 103.
[0048] The random number latch module 101 can latch the generated random number according to the enable signal, even when the random number latch module is enabled, the current random number will be latched, and the latched random number will be applied to the subsequent processing. Specifically, the random number can be generated by a random number generator, and the random number generator can continuously generate random numbers. The random number latch module can also randomly latch the random number it generates, or latch it at an irregular time interval, so its latching process does not have a certain rule, and the random number applied to the subsequent processing is more uncertain, which can ensure that when the random number is applied to the subsequent data encryption process, it is not easy to be cracked to obtain the corresponding random number. Further, the chip can include at least one random number latch module, and the random number obtained by its latching can encrypt the initial key, and can also encrypt the encrypted data, that is, the random number can be latched by the random number latch module to obtain the first random number and the second random number, and the two random numbers are used in different encryption processing steps respectively. Correspondingly, the chip may also include multiple random number latch modules, each random number latch module corresponds to a processing flow, that is, when there is a process that needs to be processed by random numbers, a random number latch module is configured, so that the random number latching process is more uncertain and difficult to crack to obtain the corresponding random number.
[0049] The operation module 102 is used to perform data operations in the chip, including XOR processing of the initial key based on the first random number to obtain the target key. In the embodiment of the present application, the initial key is not directly used to encrypt the encrypted data, so that the risk of cracking the encrypted data can be avoided when the initial key is intercepted. Therefore, the first encrypted data and the initial encrypted data are XORed to obtain the target key, which can make the target key less likely to be cracked. When the operation module adopts XOR processing, due to the relatively simple calculation method, it is easy to implement in software and hardware, reducing the occupation of chip processing resources and reducing the cost of chip design; at the same time, the XOR operation is reversible, and it is also convenient to be applied in the subsequent data decryption process. Similarly, the operation module performs XOR processing on the encrypted data based on the second random number to obtain the initial encryption key. In the embodiment of the present application, random numbers are also used to encrypt the encrypted data, so that even if the target key is intercepted, the current target encrypted data cannot be directly decrypted based on the target key, thereby improving the security of the data in the chip.
[0050] After obtaining the target key and the initial encrypted data after random number XOR processing, the initial encrypted data can be encrypted using the target key through a pre-set target encryption algorithm. The type of the pre-set target encryption algorithm in the embodiment of the present application is not restricted. For example, a symmetric encryption algorithm AES or an asymmetric encryption algorithm RSA can be used.
[0051] In order to further avoid obtaining the corresponding key information by means of energy attack, in the embodiment of the present application, the clock scrambling module 104 is also included in the random scrambling process of the clock signal based on the random number to obtain the target clock signal. The target clock signal is randomly changed, so that the current curve inside the security chip is no longer a regular change, but a random change, which increases the difficulty of attack and improves the anti-attack performance of the chip. Among them, in the process of random scrambling process of the clock signal by the clock scrambling module, it can be directly based on the random number generated by the random number generator for random scrambling, or it can be based on the random number randomly latched by the random number latch module for random scrambling. As long as the true randomness of the random number is guaranteed, the present application does not limit this. In the embodiment of the present application, the target number generated in the clock scrambling module can be input into the encryption module, so that the predictability of the electromagnetic radiation pattern caused by the clock signal can be reduced in the process of encryption by the encryption module, and the execution time of the encryption operation is also made more random, which increases the difficulty of attacker prediction and analysis. The target clock signal of the scrambling process can make the power consumption mode of the encryption module more complicated, and reduce the possibility of cracking the encryption algorithm through power consumption analysis. Specifically, the process of randomly scrambling the clock signal using random numbers may be to adjust the clock frequency by using random numbers so that the clock frequency varies within a certain range, increasing the difficulty of prediction; or to add a random offset to the phase of the clock signal; or to use random numbers to control the clock gate to determine whether to allow the clock signal to pass; or to randomly disable or enable the clock signal, making it difficult for an attacker to predict the relevant period of the clock signal. The embodiments of the present application do not limit the specific process of randomly scrambling the clock signal based on random numbers.
[0052] In a chip provided in an embodiment of the present application, not only different random numbers are used to preliminarily encrypt the initial key and the data to be encrypted, but even if the initial key or the target key encrypted by the random number is obtained, the corresponding original data to be encrypted cannot be accurately decrypted. In addition, a clock scrambling module is applied in the chip, and the scrambled target clock signal is input into the encryption module to ensure that the key information cannot be obtained by means of side channel attacks.
[0053] Furthermore, the clock scrambling module is also used to input the target clock signal into the random number latch module, so that the scrambled clock signal can significantly improve the unpredictability of the random number, thereby enhancing the data security of the entire chip. Specifically, the scrambled target clock signal can be used as a trigger signal for the random number latch module, which can lock the random number at an unpredictable time, further increasing the unpredictability of the random number, and preventing related types of side channel attacks on the random number latch module to avoid the risk of obtaining random numbers through power consumption analysis.
[0054] In order to facilitate the application of the encrypted data in the chip, in one implementation of the embodiment of the present application, see Figure 2 The chip includes: a random number latch module 101, a calculation module 102, an encryption module 103, a clock scrambling module 104 and a decryption module 105.
[0055] At different security levels, the decryption module can obtain the corresponding key information, such as the initial key that has not been encrypted by a random number or the target key that has been encrypted by a random number; if the current chip application environment is relatively safe, the computing module can transmit the target key to the decryption module, so that the decryption module decrypts the target encrypted data by the target key to obtain the initial encrypted data; wherein, the decryption algorithm applied by the decryption module corresponds to the encryption algorithm applied by the encryption module. Then, the computing module is used to perform XOR processing on the initial encrypted data based on the second random number recorded by the random number latch module to obtain the plaintext data, which is the data before encryption described above, i.e., the data to be encrypted. Correspondingly, if the initial key is obtained, it is necessary to use the computing module to perform XOR processing with the first random number and the initial key to obtain the target key, and apply the target key to the decryption process of the target encrypted data.
[0056] Furthermore, in order to improve the security of data decryption, in the embodiment of the present application, the clock scrambling module is also used to input the target clock signal into the decryption module. The scrambled target clock signal is used in the decryption module to control the power consumption of the module, making the power consumption mode more random and difficult to be exploited by power consumption analysis attacks, and also making the timing mode of the decryption operation unpredictable, thereby increasing the difficulty of timing attacks.
[0057] In order to facilitate the acquisition of random numbers, in another chip structure of an embodiment of the present application, the chip also includes a control module and a random number generator. Among them, the random number generator is used to output random numbers. The control module is used to generate a target control signal according to the time interval for latching the random number, and input the target control signal to the random number latch module, that is, the target control signal is an enable signal of the random number latch module, so that the random number latch module can latch the random number output by the random number generator according to the target control signal to obtain a first random number or a second random number. Among them, the time interval for latching the random number is also not fixed, that is, the random number is latched once every period of time, such as currently latching a random number once every 0.1 seconds, and then it can be latched again every 0.3 seconds to obtain the next random number. The encrypted power consumption waveform brought about by this is also uncertain.
[0058] In order to ensure the security of chip data, multiple encryptions can be performed, which will increase the difficulty of cracking. In one implementation of the present application, the control module in the chip is also used to generate a first random number control signal in the target control signal based on the length of the initial key, and the first random number control signal includes a first number of first control sub-signals. The random number latch module is used to latch the random number output by the random number generator based on each first control sub-signal to obtain a first random number set. Among them, the number of first random numbers in the first random number set matches the first number, and the first number is related to the length of the initial key. At this time, the operation module in the chip can perform XOR processing based on each first random number in the first random number set and the initial key to obtain the target key.
[0059] The first control sub-signal is an enable signal of the random number latch module. For example, the length of the initial key is 8KB. If the unit length of the encrypted data is preset to 2KB, the random number latch module is controlled to latch 4 times to obtain 4 (i.e., the first number described above) first random numbers, that is, the initial key is encrypted four times by the first random number, and the first random number used for each encryption is different. In this way, as the number of encryption times increases, the cracking analysis becomes more difficult, and the security of the obtained target key becomes higher.
[0060] Correspondingly, multiple encryptions can also be used in the process of encrypting the data to be encrypted using random numbers. That is, the control module is also used to generate a second random number control signal in the target control signal based on the length of the data to be encrypted, and the second random number control signal includes a second number of second control sub-signals. The random number latch module is also used to latch the random number generated by the random number based on each second control sub-signal to obtain a second random number set. The number of second random numbers in the second random number set matches the second number, and the second number is related to the length of the data to be encrypted. At this time, the operation module is used to perform XOR processing based on each second random number in the second random number set and the data to be encrypted to obtain initial encrypted data.
[0061] In this embodiment, the number of times the encrypted data is encrypted using a random number (i.e., the number of times the XOR process is performed) is determined according to the length of the data to be encrypted, thereby increasing the difficulty of cracking the encrypted data. The second number is determined according to the length of the data to be encrypted and the preset condition of encrypting the data of a unit length once. If the length of the data to be encrypted is 15KB and the length of the unit data is 3KB, the second number is 5, i.e., 5 second random numbers need to be obtained based on the random number latch module, and the number of second control sub-signals generated by the control module is 5, i.e., the random number latch module needs to be controlled to be enabled 5 times. Correspondingly, when the data encryption process adopts a multiple encryption processing mode, multiple decryption processes also need to be performed in the data decryption process to obtain plaintext data.
[0062] See also Figure 3 , is a data flow diagram of each module in a chip provided in an embodiment of the present application. Figure 3 The chip shown includes a random number generator, a control module, a random number latch module, a first operation module, a second operation module, a third operation module, an encryption module, a decryption module, and a clock gate in a clock scrambling module. Figure 3 The various modules in the chip shown are only examples, and the modules in the chip can also be adjusted based on actual application scenarios, which is not limited in the embodiments of the present application.
[0063] First, the clock gate in the clock scrambling module used in the relevant modules is explained. The random number directly output by the random number generator or the random number latched by the random number latch module is used in Figure 3 It mainly shows that the opening of the clock gate is controlled by the random number output by the random number generator, that is, the clock signal and the random number are input to the clock gate, and the random number is used to control the clock gate to decide when to allow the clock signal to be passed to the corresponding module, so that the clock signal input to the corresponding module (such as encryption module, various operation modules, decryption module, etc.) is the target clock signal after random scrambling, which increases the difficulty of cracking each module.
[0064] Then, the random latch module can randomly latch the random number output by the random number generator, or latch the random number according to the control instruction (i.e., enable signal) transmitted by the control module. For example, the latch module 1 inputs the latched first random number into the first operation module, and the initial key is also input into the first operation module, so that the first operation module performs XOR processing on the initial key based on the first random number to obtain the target key. Specifically, multiple random numbers can also be determined according to the key length of the initial key, and the initial key is XORed multiple times using these random numbers to obtain the target key, so that the encrypted data security is higher through multiple XOR encryption processing. Similarly, the second operation module performs XOR processing on the encrypted data based on the second random number output by the latch module 2 to obtain the initial encrypted data. In this process, multiple random numbers can also be determined according to the length of the data to be encrypted, and the initial encrypted data is XORed multiple times to improve the security of the data. Then the target key output by the first operation module and the initial encrypted data output by the second operation module are transmitted to the encryption module, and the encryption module uses the target key to encrypt the initial encrypted data through the corresponding encryption algorithm to obtain the target encrypted data. If decryption is required, the target encrypted data can be input into the decryption module, and then the decryption module uses the target key to decrypt the target encrypted data to obtain the initial encrypted data. The third operation module then performs XOR calculation on the initial encrypted data through the second random number to obtain the plaintext data.
[0065] It can be seen that in this application scenario, the clock signal outputted to the corresponding module can be a randomly scrambled clock signal, and the encryption process adopts multiple encryptions, that is, the initial key is first encrypted to obtain the target key, and then the encrypted data is encrypted to obtain the initial encrypted data, and finally the initial encrypted data is encrypted with the target key to obtain the target encrypted data, thereby preventing the encrypted information from being obtained through side-channel attacks, ensuring the security of chip data, and also using relatively simple XOR processing to occupy less computing resources, thereby achieving the purpose of low power consumption and low cost.
[0066] Correspondingly, see Figure 4 , is a power consumption waveform comparison diagram provided by an embodiment of the present application. In the power consumption waveform diagram, the horizontal axis represents time t, the vertical axis represents power P, and the vertical axis is represented by 1 and 0, 1 represents a high level, in this state, a part of the circuit in the chip is consuming power; 0 represents a low level, in this state, a part of the circuit in the chip may not consume or consume very little power. Figure 4 In the figure, the first power consumption waveform is the power consumption waveform of the unencrypted key, that is, Figure 4The power consumption waveform in (1) is the state where the clock is always on. It can be seen that its power consumption is always in a high state, and the form of the power consumption waveform is relatively fixed, so it is easy to infer the corresponding encrypted information based on its power consumption. The second power consumption waveform is an effective power consumption waveform that only randomly scrambles the clock of the encryption and decryption process, that is, Figure 4 (2) The clock signal in the power consumption waveform is generated based on a valid random number. This power consumption waveform is sometimes high power consumption 1 (the highest part in the figure) and sometimes low power consumption 0 (the lowest part in the figure). The power consumption is also high. The third power consumption waveform is the data processing method in the chip of the present application, that is, Figure 4 The power consumption waveform in (3) is the effective power consumption waveform after the initial key and the data to be encrypted are randomly encrypted and then encrypted according to the randomly encrypted data. Since the initial key is encrypted, that is, encrypted by a random number, and the random number is valid only after being latched by the random number latch, not all random numbers are valid at all times. Therefore, it is equivalent to that the encryption process does not always perform encryption calculations, so the power consumption in the encryption process is high and low. The random number encryption of the initial key and the data to be encrypted adopts the XOR processing mode, and its calculation power consumption is relatively low. Therefore, even if the encryption process is performed, it does not necessarily require the highest power consumption (such as, indicating high power consumption 1). Therefore, its overall power consumption is lower than that of the second waveform, achieving low power consumption.
[0067] In another embodiment of the present application, a data processing method is provided, which is applied to the chip described above. Figure 5 , the method may include the following steps:
[0068] S101. Latch the generated random number to obtain a first random number and a second random number.
[0069] S102: Perform XOR processing on the initial key based on the first random number to obtain a target key.
[0070] S103: Perform XOR processing on the data to be encrypted based on the second random number to obtain initial encrypted data.
[0071] S104: encrypt the initial encrypted data using the target key to obtain target encrypted data.
[0072] S105 . Perform random scrambling processing on the clock signal based on a random number to obtain a target clock signal, and input the target clock signal into the encryption module.
[0073] Optionally, the method further comprises:
[0074] Decrypting the target encrypted data based on the target key to obtain initial encrypted data;
[0075] The initial encrypted data is XOR-ed based on the second random number to obtain plaintext data.
[0076] Optionally, the method further comprises:
[0077] Generate a target control signal according to a time interval of latching the random number;
[0078] The random number is latched according to the target control signal to obtain a first random number or a second random number.
[0079] Optionally, latching the random number according to the target control signal to obtain a first random number includes:
[0080] Based on the length of the initial key, generating a first random number control signal in the target control signal, wherein the first random number control signal includes a first number of first control sub-signals;
[0081] latching the random numbers output by the random number generator based on each of the first control sub-signals to obtain a first random number set, wherein the number of first random numbers in the first random number set matches the first number, and the first number is related to the length of the initial key;
[0082] The step of performing XOR processing on the initial key based on the first random number to obtain the target key includes:
[0083] An XOR process is performed based on each first random number in the first random number set and the initial key to obtain a target key.
[0084] Optionally, latching the random number according to the target control signal to obtain a second random number includes:
[0085] Based on the length of the data to be encrypted, generating a second random number control signal in the target control signal, wherein the second random number control signal includes a second number of second control sub-signals;
[0086] latching the random numbers output by the random number generator based on each of the second control sub-signals to obtain a second random number set, wherein the number of second random numbers in the second random number set matches the second number, and the second number is related to the length of the data to be encrypted;
[0087] The step of performing XOR processing on the data to be encrypted based on the second random number to obtain initial encrypted data includes:
[0088] An XOR process is performed on each second random number in the second random number set and the data to be encrypted to obtain initial encrypted data.
[0089] Optionally, the method further comprises:
[0090] Inputting the target clock signal into the decryption module;
[0091] The target clock signal is input to the random number latch module.
[0092] It should be noted that the specific implementation of the data processing method in this embodiment can refer to the corresponding content in the previous text and will not be described in detail here.
[0093] In another embodiment of the present application, a readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the data processing method as described in any one of the above items is implemented.
[0094] In another embodiment of the present application, an electronic device is provided. The electronic device includes the chip as described above.
[0095] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0097] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0098] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A chip, comprising: Random number latch module, operation module, encryption module and clock scrambling module; The random number latch module is used to latch the generated random number to obtain a first random number and a second random number; The operation module is used to perform XOR processing on the initial key based on the first random number to obtain a target key; Performing XOR processing on the data to be encrypted based on the second random number to obtain initial encrypted data; The encryption module is used to encrypt the initial encrypted data using the target key to obtain target encrypted data; The clock scrambling module is used to perform random scrambling processing on the clock signal based on a random number to obtain a target clock signal, and input the target clock signal into the encryption module.
2. The chip according to claim 1, further comprising: Decryption module; The decryption module is used to decrypt the target encrypted data based on the target key to obtain initial encrypted data; The operation module is further used to perform XOR processing on the initial encrypted data based on the second random number to obtain plaintext data.
3. The chip according to claim 1, further comprising a control module and a random number generator; The random number generator is used to output a random number; The control module is used to generate a target control signal according to a time interval for latching a random number, and input the target control signal into the random number latch module; The random number latch module is used to latch the random number output by the random number generator according to the target control signal to obtain a first random number or a second random number.
4. The chip according to claim 3, wherein the control module is further used to: generate a first random number control signal in the target control signal based on the length of the initial key, wherein the first random number control signal includes a first number of first control sub-signals; The random number latch module is used to latch the random number output by the random number generator based on each of the first control sub-signals to obtain a first random number set, wherein the number of first random numbers in the first random number set matches the first number, and the first number is related to the length of the initial key; The operation module is further used to perform XOR processing on each first random number in the first random number set and the initial key to obtain a target key.
5. The chip according to claim 3, wherein the control module is further configured to: Based on the length of the data to be encrypted, generating a second random number control signal in the target control signal, wherein the second random number control signal includes a second number of second control sub-signals; The random number latch module is further used to latch the random number output by the random number generator based on each of the second control sub-signals to obtain a second random number set, wherein the number of second random numbers in the second random number set matches the second number, and the second number is related to the length of the data to be encrypted; The operation module is further used to perform XOR processing on each second random number in the second random number set and the data to be encrypted to obtain initial encrypted data. 6 . The chip according to claim 2 , wherein the clock scrambling module is further configured to input a target clock signal into the decryption module. 7 . The chip according to claim 1 , wherein the clock scrambling module is further configured to input the target clock signal into the random number latch module.
8. A data processing method, applied to the chip according to any one of claims 1 to 7, the method comprising: The generated random number is latched to obtain a first random number and a second random number; Performing XOR processing on the initial key based on the first random number to obtain a target key; Performing XOR processing on the data to be encrypted based on the second random number to obtain initial encrypted data; Using the target key to encrypt the initial encrypted data to obtain target encrypted data; The clock signal is randomly scrambled based on a random number to obtain a target clock signal, and the target clock signal is input into the encryption module.
9. The method according to claim 8, further comprising: Decrypting the target encrypted data based on the target key to obtain initial encrypted data; The initial encrypted data is XOR-ed based on the second random number to obtain plaintext data.
10. An electronic device comprising the chip according to any one of claims 1 to 7.