Dynamic precision management for integer deep learning primitives

Abstract

One embodiment provides a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising: a computing unit comprising a hardware logic unit having dynamic precision fixed point logic; a decode unit that decodes an instruction for execution by the compute unit, the instruction causing the compute unit to perform a matrix arithmetic operation on a set of dynamic fixed point tensors; and a dynamic precision manager that dynamically adjusts the precision of the calculation operation performed by the calculation unit during the matrix arithmetic operation, the dynamic precision manager adjusting that adjusts the precision of the calculation operation to prevent arithmetic overflow.

Description

[0001] This application is a divisional application of a patent application with the same name, filed on May 4, 2018, with application number 201810420883.X.

[0002] Cross-references

[0003] This application also claims the benefit of U.S. Provisional Patent Application No. 62 / 501,796, filed May 5, 2017, which is incorporated herein by reference in its entirety. Technical Field

[0004] Embodiments relate generally to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0005] Current parallel graphics data processing includes systems and methods developed to perform specific operations on image data (e.g., linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc.). Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0006] In order to further increase performance, graphics processors generally implement processing techniques, such as pipelines, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, several groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. A general overview of the software and hardware of the SIMT architecture can be found in Shane Cook's "CUDA Programming" (Chapter 3, 37-51 pages (2013)) and / or Nicholas Wilt's CUDA Handbook "A Comprehensive Guide to GPU Programming" (Chapter 2.6.2 to 3.1.2) (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order that the features of the present invention can be understood in detail, a more particular description of the present invention can be made by reference to embodiments, some of which are shown in the accompanying drawings. It should be noted, however, that the accompanying drawings only show typical embodiments and therefore should not be considered as limiting the scope of all embodiments.

[0008] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0009] Figure 2A-2D shows a parallel processor component according to an embodiment;

[0010] Figure 3A-3B is a block diagram of a graphics microprocessor according to an embodiment;

[0011] Figure 4A-4F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0012] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0013] Figure 6 illustrates a machine learning software stack according to an embodiment;

[0014] Figure 7 A highly parallel general purpose graphics processing unit is shown according to an embodiment;

[0015] Figure 8 A multi-GPU computing system according to an embodiment is shown;

[0016] Figure 9A-9B The layers of an exemplary deep neural network are shown;

[0017] Fig.10 An exemplary recurrent neural network is shown;

[0018] Fig.11 shows the training and deployment of a deep neural network;

[0019] Fig.12 is a block diagram illustrating distributed learning;

[0020] Fig.13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown;

[0021] Fig.14 shows a comparison between a floating point format and a dynamic fixed point format according to an embodiment;

[0022] Fig.15A shows dynamic fixed-point quantization according to an embodiment;

[0023] Fig. 15B Dequantization according to an embodiment is shown;

[0024] Fig.16A shows equations for arithmetic operations and down conversion according to embodiments described herein;

[0025] Fig. 16Bshows equations for hardware accelerated dynamic fixed-point primitives according to an embodiment;

[0026] Fig.17 Floating point to dynamic fixed point biased rounding according to an embodiment is shown;

[0027] Fig.18 shows a block diagram of a multi-processor unit according to an embodiment;

[0028] Figure 19A-19B shows a logic unit that may be configured with dynamic precision capability according to an embodiment;

[0029] Fig. 20 shows a block diagram of logic for implementing dynamic precision management for integer deep learning primitives according to an embodiment;

[0030] Figure 21A-Figure 21D shows closed dynamic fixed point and low precision floating point data according to embodiments described herein;

[0031] Fig. 22 is a block diagram of a processing system according to an embodiment;

[0032] Fig.23 is a block diagram of a processor according to an embodiment;

[0033] Fig.24 is a block diagram of a graphics processor according to an embodiment;

[0034] Fig.25 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0035] Fig.26 is a block diagram of a graphics processor provided by additional embodiments;

[0036] Fig. 27 shows thread execution logic including an array of processing elements employed in some embodiments;

[0037] Fig.28 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0038] Fig.29 is a block diagram of a graphics processor according to another embodiment;

[0039] Figure 30A-Figure 30B shows a graphics processor command format and command sequence according to some embodiments;

[0040] Fig.31 An exemplary graphics software architecture for a data processing system according to some embodiments is shown;

[0041] Fig.32 is a block diagram showing an IP core development system according to an embodiment;

[0042] Fig.33 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0043] Fig.34 is a block diagram illustrating an additional graphics processor according to an embodiment; and

[0044] Fig.35 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0045] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign jobs to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0046] In the following description, many specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments.

[0047] System Overview

[0048] Figure 11 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may implement a display controller that may be included in the one or more processors 102 to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0049] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system including a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0050] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform and various other devices that may be added via one or more accessory devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0051] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. The use of the I / O hub 107 may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express) or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect) or interconnect protocol known in the art. Figure 1 The communication paths that interconnect the various components in a

[0052] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general processing while maintaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated on a single integrated circuit with one or more other systems. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0053] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology may be modified as desired, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is directly connected to the processor 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor 102. In other optional topologies, the parallel processors 112 are connected to the I / O hub 107 or directly connected to one of the one or more processors 102 rather than being connected to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple slots, and the slots may be coupled to two or more instances of the parallel processor 112.

[0054] Some of the specific components described herein are optional and may not be included in all implementations of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to the Figure 1Different terminology is used for similar components shown. For example, in some architectures memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0055] Figure 2A 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices (e.g., a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA)). According to an embodiment, the parallel processor 200 shown is Figure 1 Variations of the one or more parallel processors 112 are shown.

[0056] In one embodiment, parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I / O unit 204, which enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations, and memory cross switch 216 receives commands related to performing memory operations.

[0057] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 may direct job operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other job items to the processing cluster array 212. In one embodiment, before tasks are distributed to the processing clusters of the processing cluster array 212, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and job distribution operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software may prove a workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed throughout the processing array 212 by the logic of the scheduler 210 within the scheduler microcontroller.

[0058] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or job allocation algorithms to allocate jobs to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or calculation. The scheduling may be dynamically manipulated by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be allocated for processing different types of programs or for performing different types of calculations.

[0059] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0060] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0061] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better achieve the distribution of graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0062] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands specifying the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data) as well as state parameters and commands specifying how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to fetch an index corresponding to a task, or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0063] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), each of which may be coupled to a portion (e.g., memory cells) of the parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding second memory cell 224B, and an Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0064] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Render targets (such as frame buffers or texture maps) may be stored in the memory units 224A-224N, allowing the partitioning units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, it may be advantageous to utilize a unified memory design of system memory in conjunction with local cache memory and eliminate local instances of the parallel processor memory 222.

[0065] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 may process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 may be configured to transmit the output of each cluster 214A-214N to any of the partition units 220A-220N or another cluster 214A-214N, which may perform additional processing operations on the output. Each cluster 214A-214N may communicate with a memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, and has a connection to a local instance of the parallel processor memory 222, enabling the processing units within different processing clusters 214A-214N to communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0066] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems that incorporate one or more instances of row processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0067] Figure 2B is a block diagram of the division unit 220 according to an embodiment. In one embodiment, the division unit 220 is Figure 2A 2 is an example of one of the partition units 220A-220N of FIG. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 is coupled to one of the memory units in the parallel processor memory (e.g., the memory units 224A-224N of FIG. 2 (e.g., within the parallel processor memory 222)).

[0068] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stencil printing, z-testing, blending, etc.). ROP 226 then outputs the processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic using one or more of a plurality of compression algorithms. The type of compression performed by ROP 226 can be changed based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0069] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., Figure 1 100), is routed for further processing by the processor 102, or is routed for further processing by the processor 102. Figure 2A A process in a processing entity within parallel processor 200.

[0070] Figure 2C It is a block diagram of a processing cluster 214 in a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of Figure 2. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, a single instruction multiple data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of threads that are usually synchronized using a common instruction unit, and the common instruction unit is configured to issue instructions to a group of processing engines in each of the processing clusters. Different from the SIMD execution regime (wherein all processing engines generally execute the same instruction), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0071] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of a plurality of possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying the destination of the processed data distributed via the data crossbar 240.

[0072] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In one embodiment, the same function-unit hardware may be employed to perform different operations, and any combination of function units may exist.

[0073] The instructions sent to the processing cluster 214 constitute threads. A group of threads executed on this set of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread in the thread group can be assigned to a different processing engine in the graphics multiprocessor 234. The thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle when that thread group is being processed. The thread group may also include more threads than the number of processing engines in the graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing may be performed during continuous clock cycles. In one embodiment, multiple thread groups may be executed simultaneously on the graphics multiprocessor 234.

[0074] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 may abandon the internal cache and use the cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 also accesses the L2 cache within the partition unit (e.g., partition unit 220A-220N of Figure 2) shared among all processing clusters 214, and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, embodiments can share common instructions and data that can be stored in the L1 cache 308.

[0075] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may be present in the memory interface 218 of Figure 2. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally cache line indexes. The MMU 245 may include an address translation buffer (TLB) or a cache or L1 cache or processing cluster 214 that may be present in the graphics multiprocessor 234. The physical address is processed to distribute the surface data access location to allow valid requests to be interleaved among the partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0076] In graphics and computing applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A pre-ROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to the ROP unit, and may be located with a partition unit (e.g., partition units 220A-220N of FIG. 2 ) as described herein. The units of pre-ROP 242 may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0077] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, pre-ROP 242, etc.) may be included within a processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include instances of any number of processing clusters 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0078] Figure 2DA graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache memory interconnect 268.

[0079] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. Instructions are cached in the instruction cache 252 and scheduled for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0080] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 234. Register file 258 provides temporary storage of operands for data paths connected to the functional units of graphics multiprocessor 234 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is divided between each functional unit such that each functional unit is assigned a dedicated portion of register file 258. In one embodiment, register file 258 is divided between different warps executed by graphics multiprocessor 234.

[0081] Each of the GPGPU cores 262 may include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core 262 includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or implement variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0082] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. The SIMD instructions of GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0083] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so the data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data passed between the functional units and the texture unit 236. The shared memory 270 can also be used as a program managed cache. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0084] Figure 3A-3B Additional graphics multiprocessors are shown according to an embodiment. Graphics multiprocessors 325, 350 are shown as Figure 2C The illustrated graphics multiprocessors 320, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0085] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2D The graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple groups of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0086] The various components may communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0087] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A Execution resources 356A-356D may work in conjunction with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share multiple instances of instruction cache 354 and shared memory 362 as well as texture and / or data cache memories 358A-358B. The various components may be communicated with via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0088] Those skilled in the art will understand that Figure 1 , Figure 2A-2D and Figure 3A-3B The architecture described in is illustrative and not limiting with respect to the scope of the current embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core GPUs, one or more parallel processing units such as parallel processing unit 202 of FIG. 2 , and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein.

[0089] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe or NVLink). In another embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may distribute jobs to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0090] Technologies for GPU to host processor interconnect

[0091] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 are dependent on implementing a communication throughput that supports 4GB / s, 30GB / s, 80GB / s, or higher speeds. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink (e.g., NVLink 1.0, NVLink 2.0, or another Nvidia high-speed signaling interconnect (NVHS)). However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0092] Furthermore, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric) to implement the interconnection between the processors. Figure 4A All communications between the various system components are shown. However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0093] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM) and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0094] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed throughout the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0095] Figure 4B Additional details are shown for the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated with the processor 407 on the same package or chip.

[0096] The processor 407 shown includes a plurality of cores 460A-460D, each core having a bypass translation buffer 461A-461D and one or more caches 462A-462D. The core may include various other components (e.g., instruction fetching unit, branch prediction unit, decoder, execution unit, recorder buffer, etc.) for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by several groups of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 - 402 .

[0097] Coherence is maintained for data and instructions stored in the various caches 462A-460D, 456 and the system memory 441 via inter-core communication over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the invention.

[0098] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a core's peer. In particular, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0099] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 431, 432, N may include different types of graphics processing engines, media processing engines (e.g., video encoders / decoders), samplers, and blit engines within a GPU (e.g., a graphics execution unit). In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be separate GPUs integrated on a common package, line card, or chip.

[0100] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one embodiment, the accelerator integrated circuit 436 includes a fetch unit 491 to fetch commands, instructions, job descriptors, etc. that define operations to be performed. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433-434, N remain consistent with the core caches 462A-462D, 456 and the system memory 441. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates related to modifications / accesses of cache lines on processor caches 462A-462D, 456 to cache 438 and receiving updates from cache 438).

[0101] A set of registers 449 stores context data for threads executed by the graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switch, context management circuitry 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon return to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0102] In one implementation, virtual / effective addresses from the graphics processing engine 431 are converted by the MMU 439 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407 or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0103] Thus, the accelerator integrated circuit acts as a bridge to the system for graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0104] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space visible to the host processor 407, any host processor can directly use the effective address values ​​to manipulate these resources. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0105] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-Ram.

[0106] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that data stored in graphics memory 433-434, M is data that is most frequently used by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, N) within the cores' caches 462A-462D, 456 and system memory 411.

[0107] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the high-speed link 440 via the interface 437 and the interface 435 (which again can utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operation as described, but possibly at higher throughput, assuming it is in close proximity to the coherency bus 462 and caches 462A-462D, 456.

[0108] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0109] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can send other application requests to virtualized graphics processing engines 431-432, N provided within a VM / partition.

[0110] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VMs or application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single-partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0111] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and is addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (that is, calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0112] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specific portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the process state of the corresponding application 480. The job descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a queue of jobs. In the latter case, the WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0113] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0114] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process at the time when the graphics acceleration module 446 is allocated.

[0115] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of a job completed by one of the graphics processing engines of the graphics acceleration module 446. The data from the WD 484 may be stored in registers 449 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a fragment / page walk circuit for accessing a fragment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 may process an interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is converted into a real address by the MMU 439.

[0116] In one embodiment, the same set of registers 449 is repeated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these repeated registers can be included in an accelerator integrated slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0117] Table 1 - Registers initialized by the hypervisor

[0118]

[0119]

[0120] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0121] Table 2 - Registers initialized by the operating system

[0122] 1 Process and thread identification 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual address (VA) storage segment table pointer 5 Permission shielding 6 Job Descriptor

[0123] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information that the graphics processing engine 431-432, N needs to complete its job, or it may be a pointer to a memory location of a command queue where the application has established jobs to be completed.

[0124] Figure 4E Additional details of one embodiment of the sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine of the operating system 495.

[0125] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics pointer sharing.

[0126] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization through the hypervisor 496, the graphics acceleration module 446 may adhere to the following requirements: 1) The application's job requests must be autonomous (that is, state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed by the graphics acceleration module 446 to be completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) The graphics acceleration module 446 must be guaranteed fairness between processes when operating in a direct sharing programming model.

[0127] In one embodiment, for the shared model, the application 480 needs to use the graphics acceleration module 446 type, the job descriptor (WD), the permission mask register (AMR) value and the context save / restore region pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can describe the job to be completed by the graphics acceleration module 446 in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user permission mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current privilege mask override register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 449 that contains the effective address of an area in the address space 482 of the application of the graphics acceleration module 446 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. The context save / restore area may be fixed system memory.

[0128] When the system call is received, the operating system 495 can verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0129] Table 3 - OS to Hypervisor Call Parameters

[0130] 1 Job Descriptor (WD) 2 The value of the authority mask register (AMR) (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual pointer to the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0131] When the hypervisor call is received, the hypervisor 496 verifies that the operating system 495 has been registered and given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in a linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0132] Table 4 - Process element information

[0133] 1 Job Descriptor (WD) 2 The value of the authority mask register (AMR) (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual pointer to the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table obtained from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 12 Storage Descriptor Register (SDR)

[0134] In one embodiment, the hypervisor initializes the plurality of registers 449 of the accelerator integrated slice 490 .

[0135] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual address space, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPU 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 401-402 and GPU memory 40-423, allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0136] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between the caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4FMultiple instances of bias / consistency management circuits 494A- 494E are shown in , but the bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0137] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the general performance drawbacks associated with full system cache coherence. The ability of GPU-attached memory 420-423 to be accessed as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to establish operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead may be critical to the execution time of offloaded calculations. In the case of a large amount of streaming write memory business, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 410-413. The efficiency of operand establishment, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0138] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure comprising 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU attached memories 420-423 with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0139] In one implementation, the bias table entries associated with each access to the GPU-attached memory 420-423 are accessed before the actual access to the GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 to find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU to find their pages in the host bias are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from processors 405 to find their requested pages in the host processor bias complete requests such as normal memory reads. Optionally, requests pointing to pages in the GPU bias may be forwarded to GPUs 410-413. If the GPU is not currently using a page, it can then convert the page to the host processor bias.

[0140] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of circumstances, by a purely hardware-based mechanism.

[0141] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, which directs it to change the bias state, and for some transitions, performs a cache flush operation in the host. The cache flush operation is required for a transition from the host processor 405 to the GPU bias, but not for the reverse transition.

[0142] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are pages that are needed by the GPU but not host processor 405, and vice versa.

[0143] Graphics processing pipeline

[0144] Figure 5 2. A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein (e.g., parallel processor 200 of FIG. 2), which in one embodiment is Figure 12 . Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 514. The functions of the data assembler 502, the primitive assemblers 506, 514, 516, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units for the functions. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 of FIG. 2 .

[0145] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, which illuminates and transforms vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0146] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0147] The tessellation control processing unit 508 processes the input vertices into control points for the geometry patch. The control points are transformed from an input representation from the patch (e.g., the basis of the patch) into a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to subdivide the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are sent to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0148] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0149] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for use in processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0150] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments, and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 may read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0151] Raster operations unit 526 is a processor that performs raster operations (including but not limited to stenciling, z-testing, blending, etc.) and outputs pixel data as processed graphics data to be stored in graphics memory (e.g., parallel processor memory 222 in FIG. 2 and / or in FIG. 3 ). Figure 1 Raster operations unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0152] Machine Learning Overview

[0153] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; given an input, a regression algorithm can output a numerical value; and pattern recognition algorithms can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0154] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as a non-periodic curve in which nodes are arranged in layers. In general, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "forward fed") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer in the network based on coefficients ("weights") associated with each edge connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0155] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem modeled by the network, and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize that error as the error signal propagates backward through the layers of the network. The network is considered "trained" when the error for each output generated according to an instance of the training data set is minimized.

[0156] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may require a significant amount of time on a conventional general purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suitable for parallel implementation. In particular, many machine learning algorithms and software applications are suitable for utilizing the parallel processing hardware within general purpose graphics processing devices.

[0157] Figure 6is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include training and reasoning capabilities for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, automatic navigation, speech synthesis, medical imaging, or language translation.

[0158] Hardware acceleration of the machine learning application 602 can be achieved via the machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, the developer of the machine learning algorithm would need to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when a new parallel processor is developed. Alternatively, the machine learning application can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pools, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms (e.g., matrix and vector operations).

[0159] The machine learning framework 604 may process input data received from the machine learning application 602 and generate appropriate inputs to the computation framework 606. The computation framework 606 may abstract the basic instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to have detailed knowledge of the architecture of the GPGPU hardware 610. Furthermore, the computation framework 606 may enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610.

[0160] GPGPU machine learning acceleration

[0161] Figure 7 A highly parallel general purpose graphics processing unit 700 is shown in accordance with an embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 may be configured to be particularly efficient at processing the type of computational workload associated with training deep neural networks. In addition, GPGPU 700 may be directly linked to other instances of GPGPU to create a multi-GPU cluster to increase the speed of training, in particular, deep neural networks.

[0162] GPGPU 700 includes a host interface 702 to enable connection to a host processor. In one embodiment, host interface 702 is a fast PCI interface. However, the host interface can also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with those commands to a group of computing clusters 706A-706H. Computing clusters 706A-706H share cache memory 708. Cache memory 708 can be used as a higher-level cache of cache memory within computing clusters 706A-706H.

[0163] GPGPU 700 includes memory 714A-714B coupled to computing clusters 706A-706H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0164] In one embodiment, each computing cluster 706A-706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessors of the compute clusters may be configured to perform multiple types of integer and floating point logic units with a range of precision suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating point units in each of the compute clusters 706A-706H may be configured to perform 16-bit or 32-bit floating point operations, although a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0165] Multiple instances of GPGPU 700 may be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange are different in all embodiments. In one embodiment, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 with a GPU link 710, and GPU link 710 implements direct connection with other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU to GPU bridge, which implements communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to send data to other GPGPUs or parallel processors and receive data. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via network devices accessible through host interface 702. In one embodiment, in addition to host interface 702 or as an alternative to host interface 702, GPU link 710 may be configured to implement connection to a host processor.

[0166] Although the illustrated configuration of GPGPU 700 may be configured to train a neural network, one embodiment provides an optional configuration of GPGPU 700 that may be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer of the compute clusters 706A-706H relative to the training configuration. In addition, the memory technology associated with memory 714A-714B may be different between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 700 may support inference specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions that are typically used during inference operations of a neural network for deployment.

[0167] Figure 8 800 according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 can communicate with the set of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be Figure 7 GPGPU 700 of FIG. 806A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected via dedicated GPU links (e.g., Figure 7 806D). The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-806D without the need to communicate through a host interface bus to which the processor 802 is connected. In the case where GPU-to-GPU traffic is directed to the P2P GPU link, the host interface bus remains available for access to system memory or for communication with other instances of the multi-GPU computing system 800, for example, via one or more network devices. Although in the illustrated embodiment, the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D.

[0168] Machine Learning Neural Network Implementation

[0169] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. Neural networks can be generalized as networks with functions that have curvilinear relationships. As is known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as described above.

[0170] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network for processing data (e.g., image data) with a known grid-like topology. Therefore, CNNs are commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors stimulated by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The calculation for a CNN includes applying a convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized type of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function used for convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as a feature map. For example, the input for a convolutional layer can be a multidimensional array of data defining the various color components of the input graphic. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process for the neural network.

[0171] A recurrent neural network (RNN) is a series of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequence data by sharing reference data among different parts of the neural network. The architecture of an RNN includes loops. A loop represents the effect of the current value of a variable on its own value at a future time, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature that language data can have.

[0172] The figures described below present exemplary feedforward, CNN, and RNN networks and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and not limiting of any particular embodiment described herein, and that the concepts shown can be generally applied to deep neural networks and machine learning techniques in general.

[0173] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. The deep neural network used in deep learning is an artificial neural network composed of multiple hidden layers, unlike shallow neural networks that only include a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

[0174] The deep neural network used in deep learning generally includes a front-end network to perform feature recognition coupled to a back-end network representing a mathematical model that can perform operations (such as object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without the need for hand-crafted feature engineering performed on the model. Alternatively, a deep neural network can learn features based on statistical structures or associations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0175] Once a neural network is constructed, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the expected output, and an error value is calculated for each neuron in the output layer. The error value is then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0176] Figure 9A-9B An exemplary convolutional neural network is shown. Fig.9A Various layers within a CNN are shown. As shown in Figure 9, an exemplary CNN for modeling image processing may receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from a plurality of convolutional layers may optionally be processed by a set of fully connected layers 908. The neurons in the fully connected layers have full connections with all activations in the previous layers, as described above for feed-forward networks. The output from the fully connected layers 908 may be used to generate output results according to the network. Matrix multiplication may be used instead of convolution to calculate the activations within the fully connected layers 908. Not all CNN implementations utilize fully connected layers 908. For example, in some implementations, convolutional layers 906 may generate outputs for CNN.

[0177] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the domain is input (rather than the corresponding state value of each node in the domain) to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs the convolution operation, and its output is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process larger images.

[0178] Fig. 9B Exemplary computational stages within a convolutional layer of a CNN are shown. The input to a convolutional layer 912 of the CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolutional stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a subsequent convolutional layer. The last convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for the input to the CNN.

[0179] The convolution stage 916 performs several convolutions in parallel to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be defined as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by the subsequent stages of the convolution layer 914.

[0180] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinearity of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the activation is thresholded at zero.

[0181] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with summary statistics of nearby outputs. Pooling functions can be used to introduce translation invariance into a neural network so that small translations of the input do not change the output of the pooling. Invariance to local translations may be useful in situations where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during pooling stage 920, which includes maximum pooling, average pooling, and 12 standard pooling. In addition, some CNN implementations do not include a pooling stage. Alternatively, such an implementation replaces an additional convolution stage with an increased stride relative to the previous convolution stage.

[0182] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Fig.9A The first convolutional layer 904 may output to the second convolutional layer 906 , and the second convolutional layer may output to the first layer of the fully connected layer 908 .

[0183] Fig.10An exemplary recurrent neural network 1000 is shown. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be constructed in various ways using various functions. The use of RNNs is usually based on mathematical models to predict the future based on previous sequences of inputs. For example, given a previous sequence of words, RNNs can be used to perform statistical language modeling to predict upcoming words. The RNN 1000 shown can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recursive function, a feedback mechanism 1005 that makes it possible to "memorize" the previous state, and an output layer 1006 for outputting a result. RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) may be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). A given state may be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. The function f is typically nonlinear, such as a hyperbolic tangent function (Tanh) or a variation of a corrector function f(x)=max(0,x). However, the specific mathematical function used in the hidden layer 1004 may vary depending on the specific implementation details of the RNN 1000.

[0184] In addition to the basic CNN and RNN networks described, variations on those networks may also be possible. An example RNN deformation is the long short-term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies that may be necessary for processing longer sequences of language. A deformation on CNN is a convolutional deep belief network, which has a similar structure to CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of random variables. Greedy unsupervised learning can be used to train DBN layer by layer. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the best initial set of weights for the neural network.

[0185] Fig.11 The training and deployment of a deep neural network is shown. Once a given network is constructed for a task, the neural network is trained using a training data set 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6The machine learning framework 604 may be configured as a training framework 604. The training framework 604 may be hooked into the untrained neural network 1106 and use the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1108.

[0186] To start the training process, initial weights can be chosen randomly or by pre-training using a deep belief network. A training cycle is then performed in a supervised or unsupervised manner.

[0187] Supervised learning is a learning method in which training is performed as an intermediate operation, such as when the training data set 1102 includes inputs paired with the expected outputs of the inputs, or where the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 1104 is adjustable to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 focuses on the following model, which is suitable for generating the correct answer based on the known input data. The training process occurs repeatedly when the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning algorithms.

[0188] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn the groupings within the unlabeled inputs and can determine how the individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1107 that can perform operations useful in reducing the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0189] Variations on supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variation of supervised learning in which input data is used continuously to further train the model. Incremental training enables a trained neural network 1108 to adapt to new data 1112 without forgetting the instructions instilled in the network during initial training.

[0190] Whether supervised or unsupervised, the training process for a particular deep neural network may be too computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to speed up the training process.

[0191] Fig.12 700 ). 1202 , data parallelism 1204 , or a combination of model and data parallelism 1204 .

[0192] In model parallelism 1202, different computing nodes in a distributed system may perform training computations for different parts of a single network. For example, each layer of a neural network may be trained by a different processing node of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Partitioning the computations associated with different layers of a neural network enables the training of very large neural networks, where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism may be particularly useful when performing unsupervised training of large neural networks. In another example of model parallelism, computations in one or more layers of a neural network model may be partitioned among multiple computing nodes spanning the dimension of a feature graph to reduce the size of the model parameters per node.

[0193] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from different nodes are then combined. Although different methods for data parallelism are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0194] Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0195] Distributed training increases overhead relative to training on a single machine. However, each of the parallel processors and GPGPUs described herein can implement various techniques to reduce the overhead of distributed training, including techniques to implement high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0196] Example Machine Learning Applications

[0197] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from replicating human visual capabilities (e.g., facial recognition) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in an object visible in a video. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than were previously feasible, and enables reasoning systems to be deployed using low-power parallel processors.

[0198] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0199] Parallel processor accelerated deep neural networks enable machine learning methods to be implemented into automatic speech recognition (ASR). ASR includes creating a function that computes the most likely speech sequence given a random sequence of inputs. Accelerated machine learning implementations using deep neural networks replace the Hidden Markov (HMM) and Gaussian Mixture Models (GMM) previously used for ASR.

[0200] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. The automated learning process can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0201] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 The highly parallel general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, the deployed machine learning platform typically includes lower-power parallel processors suitable for use in products (e.g., cameras, autonomous robots, and autonomous vehicles).

[0202] Fig.13 An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model is shown. The SOC 1300 may integrate processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 may further include an on-chip memory 1305 that implements a shared on-chip data pool accessible by each processing component. The processing components may be optimized for low-power operation to enable deployment to various machine learning platforms including autonomous vehicles and autonomous robots. For example, an implementation of the SOC 1300 may be used as part of a master control system for an autonomous vehicle. Where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to be compatible with the relevant functional safety standards of the deployment jurisdiction.

[0203] During operation, the media processor 1302 and the visual processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can implement low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and use the trained image recognition model to perform preparatory processing operations on the frames of the decoded video in preparation for processing the frames. For example, the visual processor 1304 can accelerate the convolution operations of a CNN for performing image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0204] The multi-core processor 1308 may include control logic to facilitate sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also be used as an application processor to execute software applications that may utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executed on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or computational workloads may be issued to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0205] GPGPU 1306 may include a compute cluster, such as a low-power configuration of compute clusters 706A-706H within a highly parallel general purpose graphics processing unit 700. The compute cluster within GPGPU 1306 may support instructions that are specifically optimized to perform inference computations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0206] Quantization framework for deep learning applications

[0207] Methods and apparatus for performing quantization and data representation of low-precision tensors in deep learning applications are described. Each low-precision tensor may contain a data buffer and associated metadata represented as a data structure. The metadata may contain information about the data type (integer, fixed point, floating point, or any other custom data type), precision, and shared exponent / scaling factors necessary to perform data conversions and arithmetic operations. The data buffer may be stored as one continuous block or many smaller blocks with many exponents / scaling factors corresponding to each block. Smaller blocks with fine-grained scaling can be used to capture a wider dynamic range (generally required for gradients during training), with each block scaled independently to fit the range and precision of the low-precision data type.

[0208] Embodiments described herein provide a dynamic fixed-point representation that can be used to store quantized floating-point data. Methods and apparatus for performing dynamic fixed-point quantization (DFPQ) to convert between floating-point numbers to integers with shared exponents are described. Dynamic fixed-point data representations are also described along with associated formulas for performing basic arithmetic operations. In one embodiment, a 16-bit dynamic fixed-point representation is used, which has a 1-bit sign, 15-bit amplitude, and uses an 8-bit shared exponent that is stored separately. However, the size of the shared exponent may vary in different fixed-point representations. For example, a 5-bit, 8-bit, 16-bit, or 32-bit shared exponent may be used. In one embodiment, a signed integer of any size may be used as a shared exponent, and the data may be represented by a signed or unsigned integer of any size. To convert from floating point to traditional fixed point, we may multiply the floating point value by 2 fb , where fb is the number of fractional bits of the target fixed-point representation (e.g., 28 for 24.8 fixed-point), and the result is rounded to the nearest integer. Optionally, some implementations use a lookup table or hash table to perform this conversion. However, these techniques can result in considerable data loss, depending on the dynamic range of the data to be converted. In addition, conventional systems typically use a single fixed-point format for a data set, rather than dynamically changing the representation of each data block (e.g., tensor, neural network layer, etc.). In some embodiments, data can be processed in blocks, each block having an associated shared exponent. Although a block-based dynamic fixed-point representation is described herein, the block-based data representation can also be used for any other standard or custom low-precision fixed or floating point data.

[0209] Fig.14 A comparison between floating point and dynamic fixed point formats according to an embodiment is shown. Quantization is supported for multiple floating point formats to multiple dynamic fixed point bit widths. Single precision (e.g., 32-bit) floating point 1410 to 16-bit dynamic fixed point 1420 is shown for exemplary purposes. IEEE-754 single precision encoding is shown, where the floating point value includes a sign bit 1411, an 8-bit exponent 1412, and a 23-bit explicit mantissa. An 8x8 tensor 1415 is shown, where 64 floating point values ​​are stored at 32 bits per entry.

[0210] The floating point representation 1410 may be quantized to a 16-bit dynamic fixed point representation 1420 with minimal data loss. The dynamic fixed point representation enables an 8x8 tensor 1415 of 32-bit floating point values ​​1414 to be stored in an 8x8 tensor 1425 of 16-bit integer values, each associated with an 8-bit shared exponent. The floating point sign bit 1411 is reserved as a fixed point sign bit 1421. The 32 bits of the exponent 1414 and mantissa 1413 (including explicit leading bits) may be stored using a 15-bit magnitude 1422 and a shared exponent 1423, which is used as a scaling factor for the entire 8x8 tensor 1425.

[0211] Fig.15ADynamic fixed point quantization according to an embodiment is shown. Dynamic fixed point quantization is performed based on the absolute maximum value within the tensor to be quantized. The quantization shown is performed as indicated by equation (1).

[0212]

[0213] The quantized value is associated with a shared scalar factor (SF) which serves as a shared exponent of the tensor. The SF is calculated as shown in equation (2).

[0214] SF={E abs_max -127} (2)

[0215] Equations (1) and (2) may be applied to quantize the values ​​within a tensor, where the tensor has an absolute maximum value of 318.00 1502 (f abs_max =318.00). The absolute maximum value 1502 is associated with an absolute maximum exponent 1504A and an absolute maximum mantissa 1504B. abs_max = 135. To quantize an exemplary floating point value 1512 (fx) having an exponent 1514A (Ex) and a mantissa 1514B (Mx), x =3.4667968), the mantissa 1514B is shifted right by the difference between the exponent 1514A and the absolute maximum exponent to create a magnitude integer 1524 (Ix), and the explicit leading bits 1513 (LB) are stored as explicit bits 1523 within the magnitude integer 1524. The sign bit 1520 (Sx) is maintained for the quantized fixed point value. The scaled exponent scaling factor 1522 (SF) is calculated as shown in equation (2) above.

[0216] Fig. 15B 1424 (Ix) is converted to a floating point value. The common scaling factor 1522 may be used to convert each magnitude integer 1425 (Ix) to a floating point value after rounding for fixed point calculations. The leading zero detector logic 1530 (LZD) is used to generate an LZD indicating the number of leading zeros in the magnitude integer 1524. x The value 1532 is used to convert the amplitude integer 1524 (I x ). Amplitude integer 1524 (I x ) Based on LZ x The value 1532 is shifted left by the shift logic and the explicitly stored leading bit is restored to the implicit leading bit 1533. As with the quantization, the sign bit 1520 is unchanged. The dequantized exponent 1534A (Ex) is calculated as described in equation (3).

[0217] E x ={127+SF+LZ x +1} (3)

[0218] A floating-point value may then be constructed based on the dequantized sign, exponent, and mantissa.

[0219] The general dynamic fixed-point formula is shown in the following equation. To convert a 32-bit floating-point tensor f tensor Convert to dfp tensor , where f tensor ={f0, f1, f2, ... f n}, the shared block index (eg scaling factor SF) is calculated via equation (4).

[0220] SF=SH exp =E(maxabs(f tensor ))-127 (4)

[0221] In addition, dfp tensor = {I tensor , SF}, where I tensor = {I0, I1, I2, ... I n ,}. Calculate I in equation (5) tensor elements.

[0222]

[0223] In equation (5), P is used to represent I x For example, for a 16-bit dynamic fixed-point value (dfp 16 ), P=16.

[0224] Fig.16A The equations for arithmetic operations (addition, multiplication) and down conversion are shown to support 16-bit dynamic fixed-point format input and output. Define the equation, where as well as are values ​​from two different 16-bit dfp tensors, then addition 1610, multiplication 1620, and down conversion 1630 may be defined as shown. The arithmetic operation of addition 1610 is defined as:

[0225] in

[0226]

[0227] The arithmetic operation of multiplication 1620 is defined as:

[0228] in

[0229] Is a 32-bit integer.

[0230] Down conversion 1630 arithmetic operation (dft32 →dft 16 ) is defined as:

[0231] in

[0232] and R shift =(16-LZC(I 32 )-1)

[0233] In the above equations, LZC refers to the leading zero count equation.

[0234] The embodiments described herein are not limited to calculations using 16-bit dynamic fixed-point data types. One embodiment provides calculation logic with support for hardware accelerated primitives to perform conversions between floating point and dynamic fixed-point data of varying sizes. Such embodiments may also provide support for hardware accelerated primitives to perform arithmetic operations on dynamic fixed-point data.

[0235] When converting a floating point tensor to dynamic fixed point, the shared exponent is obtained from the exponent of the absolute maximum value of the floating point tensor.

[0236] If F is a floating point tensor, then the exponent is the absolute maximum as expressed by equation (6).

[0237]

[0238] The value of the sharing index Es is a function of Efmax and the number of bits P used by the output integer tensor I, as shown in equation (7).

[0239] E s =E fmax -(P-2) (7)

[0240] The resulting DFP tensor <I-E s >is related to the input floating point tensor F as shown in equation (8).

[0241] where f n ∈F (8)

[0242] Based on the basic formula above, it can be described as follows and as in Fig. 16B The definitions shown in are for a set of dynamic fixed-point primitives used in neural network training.

[0243] Fig. 16B The equations for the hardware accelerated dynamic fixed point primitives according to an embodiment are shown. The operation of the primitive for addition 1640 may be defined as:

[0244] and index,

[0245] The operation of multiplication primitive 1650 may be defined as:

[0246] i ab =i a ×i b and index,

[0247] In one embodiment, when fused multiplication and addition operations are performed, all products may have the same shared exponent: Therefore the sum of such products has the same shared exponent.

[0248] Down-conversion can be performed to scale the higher precision dynamic floating point data output from one layer of a neural network to lower precision for input to subsequent layers. The data of an N-bit I tensor can be right-shifted by R s bits to fit into the lower precision tensor. The operation for downconverting primitive 1660 may be defined as:

[0249]

[0250] and index,

[0251] Although dynamic precision is described in this article with respect to fixed-point computations, dynamic precision operations can also be extended to floating-point, low-precision floating-point, and custom-defined floating-point data types. In particular, as in Figure 21A-Figure 21D Blocked dynamic-precision operations, described further in , may be generally applied to low-precision data types to enable computations on data having a larger dynamic range that could otherwise be supported by the low-precision data types.

[0252] Biased rounding for training low-precision integer neural networks

[0253] One embodiment provides a method and apparatus for biased rounding to improve training accuracy using low-precision integer networks. The biased rounding described herein achieves performance equal to or better than random rounding techniques in use in some implementations of low-precision training. The biased rounding technique avoids the requirement for a random number generator for computing random numbers used in random rounding, achieving reduced latency and power consumption relative to random rounding.

[0254] In one embodiment, when performing quantization from a 32-bit floating point value to a 16-bit dynamic fixed point value or when down-converting a 32-bit dynamic fixed point value to a 16-bit dynamic fixed point value, a biased rounding technique is performed. The biased rounding technique increases the likelihood that the quantized or down-converted data set has a data distribution similar to the data before quantization or down-conversion.

[0255] The biased rounding logic is configured to have a bias towards rounding up. In one embodiment, this bias is implemented with an extra bit representing 0.25ε as a bias bit, where ε is the minimum value representable in the target precision. The truth table for rounding precision for a single bias bit is shown in Table 5.

[0256] Table 5 - Biased rounding truth table

[0257] Rounding position Offset Rounding 0 0 down 1 0 up 0 1 up 1 1 up

[0258] The bias for rounding up is shown in Table 5, where rounding up is performed unless both the rounding bit and the bias bit are zero. The truth table of Table 5 is an example of an embodiment where a single rounding bit and a single bias bit exist. In one embodiment, two bias bits exist. In other embodiments, three or more bias bits exist. In such an embodiment, the bias can be adjusted based on the input data distribution.

[0259] Fig.17 FIG. 2 shows the floating point to dynamic fixed point biased rounding according to an embodiment. Fig.17 The quantization shown for biased rounding is similar to that shown in Fig.15A quantization as shown. In addition, rounding bits 1740 and bias bits 1742 are used to capture bits that would otherwise be lost during the right shift to generate an integer magnitude value. Based on the rounding bits 1740 and bias bits 1742 having values, a truth function or truth table is applied based on the rounding and bias bits, for example, Figure 5 The truth table is shown. A rounding margin 1744 may then be generated, which is rounded or not rounded based on the truth table.

[0260] Dynamic precision management for integer deep learning primitives

[0261] Overflow and / or saturation of accumulators during integer arithmetic operations introduces significant computational errors while performing long accumulation chains (e.g., GEMM or convolutions). One embodiment enables techniques to use dynamic fixed-point representation to dynamically adjust the effective precision of the input to prevent such errors with minimal impact on precision.

[0262] Fig.18 1 is a block diagram of a multiprocessor unit 1800 according to an embodiment. The multiprocessor unit 1800 may be Figure 2DThe multiprocessor unit 1800 includes a fetch and decode unit 1802, a branch unit 1804, a register file 1806, a thread manager 1808, a single instruction multithread unit (SIMT unit 1809), and a dynamic precision manager 1819. The fetch and decode unit 1802 may fetch instructions for execution by the multiprocessor unit 1800. The instructions may cause one or more computational units (e.g., computational unit 1810) of the SIMT unit 1809 to perform computational operations associated with a neural network as described herein. In one embodiment, the instructions cause the computational unit 1810 to perform dynamic precision computations using dynamic fixed-point data types as described herein. The branch unit 1804 may calculate instruction pointer adjustments based on executed jump instructions. The register file 1806 may store general and architectural registers used by the SIMT unit 1809. The thread manager 1808 may allocate and reallocate threads among the computational units of the SIMT unit 1809. In one embodiment, SIMT unit 1809 is configured to execute a single instruction as multiple threads, each thread of instruction being executed by a separate computing unit. In one embodiment, computing units 1811 to 1818 each include an integer ALU (e.g., ALU 1811A-1818A) and a floating point unit (e.g., FPU 1811B-1818B). The voltage and frequency of each computing unit 1811-1818 within SIMT unit 1809 can be dynamically managed by a voltage and frequency manager, which can increase or decrease the voltage and clock frequency supplied to the various computing units when components of the computing units are enabled and disabled.

[0263] In some previously enabled configurations, each computing unit can execute a single thread of integer instructions or floating-point instructions. If any of ALU 1811A-1818A is assigned the task of executing a thread of integer instructions, the corresponding FPU1811B-FPU1418B is unavailable for the thread for executing floating-point instructions, and can be power-gated during the operation of the corresponding ALU 1811A-ALU1818A. For example, although ALU 1811A can execute a thread of integer instructions, and FPU1813B executes a thread of floating-point instructions, FPU 1811B is power-gated, and ALU 1813A is active. The embodiments described herein overcome such limitations by, for example, enabling ALU 1811A to execute a thread of instructions while FPU 1811B executes threads of different instructions. In addition, one embodiment provides support for mixed precision or mixed data type operands, so that a single instruction can be performed simultaneously for instructions with floating-point and integer operands and / or operands with different precisions.

[0264] The embodiments described herein achieve increased computational throughput of a cluster of computing units by manufacturing all logic units within each computing unit available for performing calculations. In such embodiments, logic units within a computing unit designed to selectively perform calculations at one of multiple precisions or multiple data types can be configured to perform multiple simultaneous operations for each precision or data type supported by the computing unit. For a given computing unit 1811-1818, ALU 1811A-1818A can perform integer operations, while FPU 1811B-1818B performs floating point operations. These operations can be performed for a single instruction or for multiple instructions.

[0265] In one embodiment, the dynamic precision manager 1819 may be configured to dynamically adjust the precision of computational operations, for example to prevent overflow during an accumulation chain. Longer accumulation chains generally require longer accumulators. The number of extra bits required for the accumulator is ~log2 n, where n is the number of accumulations. Some embodiments described herein may be configured to dynamically adjust the "effective precision" of a computation. Such computations may be applied to input data and / or intermediate outputs of an ongoing accumulation chain. The intermediate data is "shifted" "right" by R before being passed through the next iteration of the computation. shift . R shift The value is calculated based on a heuristic and may be incremented or decremented to preserve as many bits of precision as possible while keeping overflow under control.

[0266] Figure 19A-19B 1920, 1940 are shown configured with dynamic precision capabilities according to an embodiment. In one embodiment, the logic units 1920, 1940 may be present in Fig.18 Within the computing unit 1810 in .

[0267] like Fig.19AAs shown, the logic unit 1920 can process input value 1921 by 16-bit multiplication-addition logic including 16bx16b multiplier 1924 and 32-bit adder 1926. The 32-bit adder 1926 can add the product 1925 of the multiplication operation with the accumulator value 1923 read from the accumulator 1934, which is a 32-bit integer register in one embodiment. The 32-bit adder 1926 can output an integer sum 1928 represented in dynamic fixed point. At various points within the logic, shifters (e.g., shift logic 1927, 1933, 1935) can be used to move the results to dynamically adjust the precision and prevent overflow. A shared exponent or scaling factor (SF) can be stored in the SF register 1930 to enable the inverse of the precision of the reserved shift to generate the output data. The scaling factor stored in SF register 1930 may be determined based on precision heuristic unit 1929, which may adjust the scaling factor to maintain as many bits of precision as possible without overflow. In one embodiment, precision heuristic unit 1929 may reside at least in part in Fig.18 Dynamic Precision Manager 1819.

[0268] In one embodiment, metadata 1932 may also be maintained along with the blocks of dynamic fixed-point data to track shared scaling factors for the data. Metadata 1932 may be stored in concert with the dynamic fixed-point data, or may be stored in a separate metadata structure that tracks scaling factors for multiple blocks of dynamic fixed-point data. In one embodiment, the metadata may be or may be derived from the scaling factor data stored in scaling factor registers 1930. In one embodiment, metadata for blocks of dynamic fixed-point data may be used by shift logic 1933 to shift the dynamic fixed-point data before storing the data in accumulator 1934. In one embodiment, leading bit detector 1931 may be used to detect leading ones or leading zeros in integer sum 1928. In such an embodiment, the number of leading zeros or leading ones may be used as a heuristic to determine whether to shift an intermediate output. In one embodiment, leading bit detector 1931 may be configured to detect only leading zeros when checking for absolute values.

[0269] Although in Figure 19A-19B 1924, adder 1926, and other logic described herein may vary in size in embodiments. In addition, the dynamic precision logic described herein is not limited to dynamic precision fixed point (e.g., integer) logic and data types.

[0270] Fig.19BDynamic precision calculations using combined dynamic fixed-point and floating-point operations are shown. A logic unit 1940, similar to logic unit 1920, may replace shift logic 1927, 1933 with floating-point logic elements that can calculate with a larger dynamic range. Logic unit 1940 may include an internal block 1942, which includes an N-bit x N-bit integer multiplier 1944, which outputs an integer product 1945 of a predetermined bit length based on the instruction or primitive to be executed, or a parameter provided to the instruction or primitive to be executed. An N-bit adder 1946 may add the product 1945 to an accumulator value 1943 read from an accumulator 1950, which may be an integer register of one of a plurality of predetermined sizes (e.g., 8 bits, 16 bits, 32 bits, 140 bits, etc.). Internal block 1942 may be configured to perform multiple passes of multiplication and accumulation on input data, where the number of passes is determined to be a number that does not overflow the bit length configured for internal block 1942. In one embodiment, the number of passes performed by internal block 1942 may be determined by Fig.18 The dynamic precision manager 1819 in is predetermined as input 1921 and configured via the precision heuristic module 1929.

[0271] Once a predetermined number of iterations are performed by the internal block 1942, the data may be converted from dynamic fixed point to floating point via a dynamic fixed point to floating point converter unit 1954. The conversion may be performed based on a pre-scaling factor for the output tensor stored as part of the metadata 1932. The converted output may then be accumulated to a floating point accumulator register 1956, which in one embodiment may be a 32-bit (FP32) register. In one embodiment, additional operations on the tensor data may be performed in floating point. The logic 1940 may be used to implement training for a data set that is executed at least in part in dynamic fixed point precision, enabling performance and efficiency gains during an earlier portion of training, reducing the overall training time of the neural network.

[0272] Fig. 20 2000 for implementing dynamic precision management for integer deep learning primitives, according to an embodiment. The logic 2000 may receive a set of dynamic fixed-point tensors as input, as shown at block 2002. The logic 2000 may then determine whether to shift the input, as shown at block 2003. If the input is to be shifted, the logic 2000 may calculate "rshift" (shift right) using the absolute maximum value and dynamic range of the tensor at block 2012. The logic 2000 may then right-shift the data based on the rshift value and increment the shared exponent, as shown at block 2014. If a shift is not required or after a shift is performed, the logic 2000 may then perform the necessary computation operations (e.g., MUL, ADD, MADD) at block 2004.

[0273] After performing the computational operation at block 2004, the logic 2000 may then check the leading zero count of the absolute maximum value of the output tensor at block 2006. If the leading zero count is above the overflow threshold at block 2007, the logic 2000 may adjust the precision of the output tensor based on the leading zero count. Adjusting the precision of the output tensor includes adjusting the rshift count of the shared index for the output. For example, the logic 2000 may increase the rshift count for the output, and if the leading count zero is above the overflow threshold at block 2016, the shared index is incremented. Otherwise, the logic 2000 may decrement the rshift count for the output and decrement the shared index at block 2008. Adjusting the rshift count may include adjusting an rshift counter configured to track the degree of right shift applied to the output tensor. Adjusting the right shift count may correspond to applying a right shift to the output data. After incrementing or decrementing the rshift counter and incrementing or decrementing the shared index, additional computational operations may be performed by returning to block 2004.

[0274] Figure 21A-Figure 21D Blocked dynamic multi-precision data operations are shown that can be performed according to the embodiments described herein. Blocked dynamic multi-precision data operations can be performed for dynamic fixed-point data, and can also be generalized to achieve block-level scaling for any low-precision data type. In a training scenario, some tensors may be blocked, while other tensors may be unblocked. For example, back propagation may require a larger dynamic range, so the calculation logic can be configured to use a smaller block size to block the tensor data. For forward propagation calculations, blocking may not be required.

[0275] In one embodiment, a variable block size may be used, with the block size and scaling factor maintained in metadata for the data block. When processing multi-precision tensor data in blocks, the compute logic may read the metadata for the block and configure the compute units to perform logical operations on the data block.

[0276] Fig.21A A memory map 2100 associated with blocked dynamic fixed point is shown according to an embodiment. Fig. 21B A block-based multi-dimensional fine-grained quantization tensor 2110 is shown according to an embodiment. Fig. 21C An exemplary set 2120 of 3x3 filters that may be represented in a blocked dynamic precision data type is shown. Fig.21D A process 2130 of performing block-wise dynamic fixed-point operations is shown according to an embodiment.

[0277] Higher function ranges require more bits of precision to represent the full range using integers. One solution is to partition the tensor into smaller blocks with independent shared exponents while maintaining the integer data at lower precision. This technique is useful for representing large matrix multiplication and convolution operations. Using smaller blocks within each block achieves higher effective precision and helps achieve better overall accuracy using lower precision calculations.

[0278] As in Fig.21A As shown in , a 64x64 tensor 2100 may be partitioned into four 32x32 blocks 2102, 2103, 2106, 2107. Each of the 32x3 blocks may have a separate shared exponent / scaling factor in metadata 2101, 2104, 2105, 2108 associated with each block. The metadata 2101, 2104, 2105, 2108 may be stored contiguously with each of the 32x32 blocks 2102, 2103, 2106, 2107, or may be stored in a separate area of ​​memory. In addition to the shared exponent or scaling factor data, the metadata may also include other items for data conversion (e.g., floating point to fixed point conversion or fixed point to floating point conversion). In addition, blocking may be performed for tensor data stored in a low precision or custom floating point format, with the data being shifted or the floating point format being adjusted to properly capture the dynamic range of the data within each block. Data used to track adjustments to data and data formats may be tracked via metadata 2101 , 2104 , 2105 , 2108 .

[0279] Although the 64x64 tensor 2100 is shown as having four 2x32 blocks 2102, 2103, 2106, 2107, embodiments are not limited to the tensor size and block size shown, and any tensor and block sizes may be used in various embodiments.

[0280] Fig. 21BA multi-dimensional fine-grained quantized tensor 2110 in blocks according to an embodiment is shown. The tensor 2110 may be partitioned into blocks along one or more dimensions, each block having a separate shared index (e.g., EXP1 2111, EXP2, 2112, etc.). Shared index data for the quantized tensor 2110 may be stored in metadata for the tensor. The metadata may maintain an exponential scaling factor for each block and a block size for each block. In one embodiment, partitioning with variable block sizes may be performed along all dimensions of the tensor. A data representation having variable size blocks in all dimensions of the tensor may be generated. For example, tensor data for use in a convolution operation may have N, C, H, and W dimensions of corresponding sample, color channel, width, and height dimensions. Partitioning with variable block sizes may be performed along all dimensions of the tensor. In addition, the GEMM (general matrix multiplication) kernel can have partitions along the M, N, and K dimensions, which specify the number of rows and columns of matrices A and B to be multiplied (e.g., M is the number of rows in matrix A, N is the number of columns in matrix B, and K is the number of columns in matrix A and C is the number of rows in matrix B). A variety of different types of blocking and clustering algorithms can be used to determine the block size of the tensor. In addition, the tensor data can be blocked in a continuous or non-continuous manner using variable or non-uniform block sizes. In addition, although a blocked dynamic fixed-point representation is described herein, the blocked data representation can also be used for low-precision floating-point data.

[0281] Fig. 21C An exemplary group 2140 of 3x3 filters that can be represented in a block-based dynamic precision data type is shown. The group 2140 of filters contains a (R x S) subset of n elements from consecutive filters along the C dimension. The exemplary subset 2140 can be described by equation 2142, which states i=1...N,j=1...(RxS). N filters 2144A-21444N (w0...w N ) contains three groups of weights derived based on the full precision weights. For each group 2140 of 3x3 filters, there is a 3x3 filter containing a scaling factor 2146 (α) for each element in the filter. The hardware logic can be configured to perform low precision calculations using blocked dynamic precision data. In one embodiment, the filter data can be quantized to a blocked dynamic precision format that requires a reduced number of bits to store the data, while shifting the scaling factors in a fine-grained manner to avoid data loss. The activations at each layer can be quantized to a low precision format, such as a dynamic fixed point or a blocked low precision floating point format.

[0282] As in Fig.21DAs shown in , a computation logic 2130 for performing a process implementing dynamic fixed point into blocks may receive an input tensor associated with a matrix operation performed on the computation logic, as shown at block 2132. The computation logic may then divide the input tensor into a plurality of blocks, as shown at block 2134. For each of the plurality of blocks, the computation logic may determine a shared index (e.g., a scaling factor) for each of the plurality of blocks and coordinate each block to a dynamic fixed point, as shown at block 2136. The computation logic may then store metadata for the plurality of blocks to indicate a data format for the shared index for the plurality of blocks, as shown at block 2138. In one embodiment, the metadata for the plurality of blocks is stored in a separate metadata segment in a memory. In one embodiment, the metadata for each of the plurality of blocks is attached to or adjacent to each block.

[0283] Once the input tensor is written for the metadata, the computation logic can then use the partitioned dynamic fixed-point input tensor to perform matrix operations, as shown at block 2139. In some embodiments, the computation logic includes hardware support for dynamic fixed-point. In one embodiment, metadata describing the data format of a block of input tensors is stored at a predetermined memory location relative to the tensor data. The hardware can automatically read the metadata for the block of tensors and configure the logic units of the hardware to process the tensor data at the specified dynamic fixed-point configuration. For example, as shown at Fig.19A The logic unit 1920 in Fig.19B The logic unit 1940 or similar logic unit in may be configured to process tensor data in a dynamic fixed-point format.

[0284] Mixed precision training can be performed using low-precision dynamic fixed-point data types to train neural networks with precision similar to that of 32-bit floating-point. One embodiment provides a 16-bit dynamic fixed-point implementation that is tested in training relative to training performed using FP32. Training is performed for several state-of-the-art ImageNet-class CNNs using a variant of the Berkeley Vision and Learning Center (BVLC) Caffe framework, one variant modifies the additive DFP16 data type support. Using hardware acceleration of DFP16 compute primitives, an average 1.8X speedup in training throughput is achieved relative to baseline FP32 performance, with accuracy results as shown in Table 6 below.

[0285] Table 6 - Training configuration and ImageNet-1K classification accuracy

[0286]

[0287] As shown in Table 6 above, ImageNet-1K networks trained with DFP16 achieve state-of-the-art accuracy, with some models exceeding the accuracy of FP32 baselines. Convergence for DFP16 training closely tracks FP32 training, while achieving as much potential as 2x savings in compute, communication, and storage. Although CNN training is shown, the techniques described herein can also be applied to other types of neural networks, such as RNNs, LSTMs, and GANs (Generative Adversarial Networks).

[0288] Additional Exemplary Graphics Processing Systems

[0289] Details of the embodiments described above may be incorporated into the graphics processing systems and devices described below. Figure 22-Figure 35 The graphics processing systems and devices illustrate optional systems and graphics processing hardware that can implement any and all of the techniques described above.

[0290] Fig. 22 2200 is a block diagram of a processing system 2300 according to an embodiment. In various embodiments, the system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and may be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2202 or processor cores 2207. In one embodiment, the system 2200 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0291] Embodiments of system 2200 may include or be incorporated in the following items: a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 2200 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 2200 may also include, be coupled with, or be integrated in the following items: a wearable device such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 2200 is a television or set-top box device having one or more processors 2202 and a graphics interface generated by one or more graphics processors 2208.

[0292] In some embodiments, each of the one or more processors 2202 includes one or more processor cores 2207 to process instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 2207 is configured to process a specific instruction set 2209. In some embodiments, the instruction set 2209 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC) or computing via very long instruction set words (VLIW). Each of the multiple processor cores 2207 may process different instruction sets 2209, which may include instructions that facilitate the simulation of other instruction sets. The processor core 2207 may also include other processing devices, such as a digital signal processor (DSP).

[0293] In some embodiments, the processor 2202 includes a cache memory 2204. Depending on the architecture, the processor 2202 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 2202. In some embodiments, the processor 2202 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown)), which can be shared among the processor core 2207 using known cache coherence techniques. In addition, a register file 2206 is included in the processor 2202, and the processor 2202 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 2202.

[0294] In some embodiments, the processor 2202 is coupled to the processor bus 2210 to send communication signals, such as address, data, or control signals, between the processor 2202 and other components in the system 2200. In one embodiment, the system 2200 uses an exemplary "hub" system architecture, including a memory controller hub 2216 and an input output (I / O) controller hub 2230. The memory controller hub 2216 facilitates communication between memory devices and other components of the system 2200, while the I / O controller hub (ICH) 2230 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2216 is integrated within the processor.

[0295] The memory device 2220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties for use as process memory. In one embodiment, the memory device 2220 may operate as system memory for the system 2200 to store data 2222 and instructions 2221 for use when one or more processors 2202 execute applications or processes. The memory controller hub 2216 is also coupled to an optional external graphics processor 2212, which may communicate with one or more graphics processors 2208 in the processor 2202 to perform graphics and media operations.

[0296] In some embodiments, the ICH 2230 enables peripheral devices to connect to the memory device 2220 and the processor 2202 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 2246, a firmware interface 2228, a wireless transceiver 2226 (e.g., Wi-Fi, Bluetooth), a data storage device 2224 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 2240 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2242 connect input devices, such as a combination of a keyboard and mouse 2244. A network controller 2234 may also be coupled to the ICH 2230. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2210. It will be appreciated that the system 2200 shown is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 2230 may be integrated within one or more of the processors 2202 , or the memory controller hub 2216 and the I / O controller hub 2230 may be integrated into a discrete external graphics processor (eg, external graphics processor 2212 ).

[0297] Fig.23 2300 having one or more processor cores 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. Elements having the same reference numerals (or names) as elements of any other figure herein Fig.23 Those elements of the processor 2300 may operate or run in any manner similar to that described elsewhere herein, but are not limited thereto. The processor 2300 may include additional cores, and includes an additional core 2302N represented by a dashed box. Each of the processor cores 2302A-2302N includes one or more internal cache units 2302A-2304N. In some embodiments, each processor core also accesses one or more shared cache units 2306.

[0298] Internal cache units 2304A-2304N and shared cache unit 2306 represent a cache memory hierarchy within processor 2300. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 2306 and 2304A-2304N.

[0299] In some embodiments, the processor 2300 may also include a set of one or more bus controller units 2316 and a system agent core 2310. The one or more bus controller units 2316 manage a set of peripheral buses, such as one or more peripheral component internet buses (e.g., PCI, PCI Express). The system agent core 2310 provides management functions for various processor components. In some embodiments, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0300] In some embodiments, one or more of the processor cores 2302A-2302N include support for simultaneous multithreading. In such embodiments, the system agent core 2310 includes components for coordinating and operating the cores 2302A-2302N during multithreaded processing. The system agent core 2310 may additionally include a power control unit (PCU) that includes logic and components to regulate the power state of the processor cores 2302A-2302N and the image processor 2308.

[0301] In some embodiments, the processor 2300 additionally includes a graphics processor 2308 to perform graphics processing operations. In some embodiments, the graphics processor 2308 is coupled to the set of shared cache units 2306 and a system agent core 2310 including one or more integrated memory controllers 2314. In some embodiments, a display controller 2311 is coupled to the graphics processor 2308 to output graphics processing to one or more coupled displays. In some embodiments, the display controller 2311 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2308 or the system agent core 2310.

[0302] In some embodiments, a ring-based interconnect unit 2312 is used to couple the internal components of the processor 2300. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 2308 is coupled to the ring interconnect 2312 via an I / O link 2313.

[0303] Exemplary I / O link 2313 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect, that facilitates communication between various processor components and high-performance embedded memory module 2318 (e.g., eDRAM module). In some embodiments, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared last level cache.

[0304] In some embodiments, the processor cores 2302A-2302N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2302A-2302N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2302A-2302N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with relatively low power consumption. In addition, the processor 2300 may be implemented on one or more chips or as a SoC integrated circuit also having the components, etc.

[0305] Fig.24 24 is a block diagram of a graphics processor 2400, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into the processor memory. In some embodiments, the graphics processor 2400 includes a memory interface 2414 to access memory. The memory interface 2414 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0306] In some embodiments, the graphics processor 2400 also includes a display controller 2402 to drive display output data to a display device 2420. The display controller 2402 includes hardware for one or more overlay planes for display and composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2400 includes a video codec engine 2406 to encode, decode or transcode media to, from or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0307] In some embodiments, graphics processor 2400 includes a block image transfer (BLIT) engine 2404 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2410. In some embodiments, GPE 2410 is a computational engine for performing graphics operations including three-dimensional (3D) graphics operations and media operations.

[0308] In some embodiments, GPE 310 includes a 3D pipeline 2412 for performing 3D operations (e.g., rendering three-dimensional images and scenes) using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2412 includes programmable and fixed function elements that perform various tasks within the elements and / or generate execution threads for 3D / media subsystem 2415. While 3D pipeline 2412 can be used to perform media operations, embodiments of GPE 2410 also include a media pipeline 2416 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0309] In some embodiments, the media pipeline 2416 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of the video codec engine 2406. In some embodiments, the media pipeline 2416 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1415. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 2415.

[0310] In some embodiments, the 3D / media subsystem 2415 includes logic for executing threads generated by the 3D pipeline 2412 and the media pipeline 2416. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating various requests and dispatching various requests to available thread execution resources. The execution resources include an array of graphics execution units to handle 3D and media threads. In some embodiments, the 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and store output data.

[0311] Exemplary Additional Graphics Processing Engine

[0312] Fig.25 is a block diagram of a graphics processing engine 2510 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2510 is Fig.24 The GPE 2410 shown in FIG. 2 is a version of the GPE 2410 shown in FIG. 2. Elements having the same reference numerals (or names) as elements of any other figure herein Fig.25 The elements of may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Fig.24 2412 and media pipeline 2416. The media pipeline 2416 is optional in some embodiments of the GPE 2510 and may not be explicitly included in the GPE 2510. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2510.

[0313] In some embodiments, the GPE 2510 is coupled to or includes a command stream sender 2503, which provides a command stream to the 3D pipeline 2412 and / or the media pipeline 2416. In some embodiments, the command stream sender 2503 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command stream sender 2503 receives commands from the memory and sends the commands to the 3D pipeline 2412 and / or the media pipeline 2416. The commands are taken directly from a ring buffer, which stores commands for the 3D pipeline 2412 and the media pipeline 2416. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 2412 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2412 and / or image data and memory objects for the media pipeline 2416. The 3D pipeline 2412 and the media pipeline 2416 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2514.

[0314] In various embodiments, the 3D pipeline 2412 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2514. The graphics core array 2514 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 2514 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0315] In some embodiments, graphics core array 2514 also includes execution logic to perform media functions, such as video and / or image processing. In one embodiment, the execution units additionally include general purpose logic that can be programmed to perform parallel general purpose computing operations in addition to performing graphics processing operations. The general purpose logic can be combined in parallel or in Fig. 22 Processor core 2207 or as in Fig.23 The general logic within cores 2302A-2302N performs processing operations.

[0316] Output data generated by threads executing on graphics core array 2314 may output data to memory in unified return buffer (URB) 2518. URB 2518 may store data for multiple threads. In some embodiments, URB 2518 may be used to send data between different threads executing on graphics core array 2514. In some embodiments, URB 2518 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 2520.

[0317] In some embodiments, graphics core array 2514 is scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance level of GPE 2510. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0318] The graphics core array 2514 is coupled to shared function logic 2520, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 2520 are hardware logic units that provide specialized supplemental functions to the graphics core array 2514. In various embodiments, the shared function logic 2520 includes, but is not limited to, samplers 2521, math 2522, and inter-thread communication (ITC) 2523 logic. In addition, some embodiments implement one or more caches 2525 within the shared function logic 2520. The shared functions are implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array 2514. Alternatively, a single instantiation of that specialized function is implemented as an independent entity in the shared function logic 2520 and shared among the execution resources within the graphics core array 2514. The exact set of functions that are shared between the graphics core array 2514 and included within the graphics core array 2514 varies between embodiments.

[0319] Fig.26 is a block diagram of a graphics processor 2600 provided by an additional embodiment. Elements having the same reference numerals (or names) as elements of any other figure herein Fig.26 The elements of may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0320] In some embodiments, graphics processor 2600 includes ring interconnect 2602, pipeline front end 2604, media engine 2637, and graphics cores 2680A-2680N. In some embodiments, ring interconnect 2602 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0321] In some embodiments, the graphics processor 2600 receives batches of commands via a ring interconnect 2602. Incoming commands are interpreted by a command streamer 2603 in a pipeline front end 2604. In some embodiments, the graphics processor 2600 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2680A-2680N. For 3D geometry processing commands, the command streamer 2603 supplies the commands to a geometry pipeline 2636. For at least some media processing commands, the command streamer 2603 supplies the commands to a video front end 2634, which is coupled to a media engine 2637. In some embodiments, the media engine 2637 includes a video quality engine (VQE) 2630 for video and graphics post-processing and a multi-format encoding / decoding (MFX) 2633 for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2636 and the media engine 2637 each generate execution threads for thread execution resources provided by at least one graphics core 2680A.

[0322] In some embodiments, the graphics processor 2600 includes scalable thread execution resources featuring modular cores 2680A-2680N (sometimes referred to as core slices), each modular core having multiple sub-cores 2650A-550N, 2660A-2660N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2600 may have any number of graphics cores 2680A to 2680N. In some embodiments, the graphics processor 2600 includes a graphics core 2680A having at least a first sub-core 2650 and a second sub-core 2660A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2650A). In some embodiments, the graphics processor 2600 includes multiple graphics cores 2680A-2680N, each graphics core including a group of first sub-cores 2650A-2650N and a group of second sub-cores 2660A-2660N. Each sub-core in the set of first sub-cores 2650A-2650N includes at least a first set of execution units 2652A-2652N and a media / texture sampler 2654A-2654N. Each sub-core in the set of second sub-cores 2660A-2660N includes at least a second set of execution units 2662A-2662N and a sampler 2664A-2664N. In some embodiments, each sub-core 2650A-2650N, 2660A-2660N shares a set of shared resources 2670A-2670N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0323] Additional Exemplary Execution Units

[0324] Fig. 27 Thread execution logic 2700 is shown including an array of processing elements employed in some embodiments. Elements having the same reference numerals (or names) as elements of any other figure herein Fig. 27 The elements of may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0325] In some embodiments, thread execution logic 2700 includes a shader processor 2702, a thread scheduler 2704, an instruction cache 2706, a scalable execution unit array including a plurality of execution units 2708A-2708N, a sampler 2710, a data cache 2712, and a data port 2714. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2708A, 2708B, 2708C, 2708D to 2708N-1 and 2708N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure linked to each of the components. In some embodiments, thread execution logic 2700 includes one or more interconnects to a memory (e.g., system memory or cache memory) through one or more of the instruction cache 2706, the data port 2714, the sampler 2710, and the execution units 2708A-2708N. In some embodiments, each execution unit (e.g., 2708A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements for each thread in parallel. In various embodiments, the array of execution units 2708A-2708N is scalable to include any number of separate execution units.

[0326] In some embodiments, execution units 2708A-2708N are primarily used to execute shader programs. Shader processor 2702 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2704. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more of execution units 2708A-2708N. For example, geometry pipelines (e.g., Fig.26 2636) can dispatch vertex, tessellation or geometry shaders to thread execution logic 2700 ( Fig. 27 ) for processing. In some embodiments, thread dispatcher 2704 may also process runtime thread generation requests from executing shader programs.

[0327] In some embodiments, execution units 2708A-2708N support the following instruction set, which includes inherent support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (such as Direct 3D and OpenGL) are executed with minimal conversion. The execution unit supports vertex and geometry processing (such as vertex programs, geometry programs, vertex shaders), pixel processing (such as pixel shaders, fragment shaders) and general processing (such as calculation and media shaders). Each execution unit 2708A-2708N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations face high latency memory access to achieve an effective execution environment. Each hardware thread in each execution unit has a dedicated high-bandwidth register file and an associated independent thread state. Execution is multi-issue per clock for pipelines capable of integer, single and double precision floating point operations, SIMD branching capabilities, logical operations, transcendental operations and other tessellation operations. When waiting for data from memory or one of the shared functions, dependency logic within execution units 2708A-2708N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources can be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0328] Each execution unit in execution units 2708A-2708N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for an instruction. An execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, execution units 2708A-2708N support integer and floating point data types.

[0329] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as encapsulated data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit encapsulated data elements (quad word (QW) size data elements), eight separate 32-bit encapsulated data elements (double word (DW) size data elements), sixteen separate 16-bit encapsulated data elements (word (W) size data elements) or thirty-two separate 8-bit encapsulated data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0330] One or more internal instruction caches (e.g., 2706) are included in the thread execution logic 2700 to cache thread instructions for the instruction unit. In some embodiments, one or more data caches (e.g., 2712) are included to cache thread data during thread execution. In some embodiments, a sampler 2710 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2710 includes a dedicated texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0331] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2700 via thread generation and dispatch logic. Once a set of geometric objects are processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2702 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes interpolated on the rasterized object. In some embodiments, the pixel processor logic within the shader processor 2702 then executes the pixel or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 2702 dispatches the thread to the execution unit (e.g., 2708A) via the thread dispatcher 2704. In some embodiments, the pixel shader 2702 uses the texture sampling logic in the sampler 2710 to access the texture data stored in the texture map in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels for further processing.

[0332] In some embodiments, data port 2714 provides a memory access mechanism for thread execution logic 2700 to output processed data to memory for execution on the graphics processor output pipeline. In some embodiments, data port 2714 includes or is coupled to one or more cache memories (e.g., data cache 2712) to cache data via the data port for memory access.

[0333] Fig.282800 is a block diagram illustrating a graphics processor instruction format 2800 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2800 described and illustrated are macroinstructions in that they are instructions that are supplied to the execution unit, as opposed to micro-operations that are generated from instruction decode once the instruction is processed.

[0334] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 2810. Based on the selected instruction, instruction options, and the number of operands, a 64-bit compressed instruction format 2830 is available for some instructions. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 2830. The native instructions available in the 64-bit format 2830 vary according to the embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in the index field 2813. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions in the 128-bit instruction format 2810.

[0335] For each format, the instruction opcode 2812 defines the operation that the execution unit will perform. The execution unit executes each instruction in parallel among multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs simultaneous addition operations on each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction on all data channels of the operand. In some embodiments, the instruction control field 2814 implements control by certain execution options (such as channel selection (such as prediction) and data channel order (such as swizzle)). For instructions in the 128-bit instruction format 2810, the exec size field 2816 limits the number of data channels that will be executed in parallel. In some embodiments, the exec size field 2816 is not available for use in the 64-bit compressed instruction format 2830.

[0336] Some execution unit instructions have up to three operands, including two source operands src0 2820, src1 2822, and one destination 2818. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implied. Data manipulation instructions may have a third source operand (e.g., SRC2 2824), where the instruction opcode 2812 determines the number of source operands. The last source operand of an instruction may be an immediate (hard-coded) value passed along with the instruction.

[0337] In some embodiments, the 128-bit instruction format 2810 includes an access / address mode field 2816 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0338] In some embodiments, the 128-bit instruction format 2810 includes an access / address mode field 2826 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0339] In one embodiment, the address mode portion of the access / address mode field 2826 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0340] In some embodiments, instructions are grouped based on the opcode 2812 bit field to simplify opcode decoding 2840. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is just an example. In some embodiments, the move and logic opcode group 2842 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2842 shares five most significant bits (MSBs), where the move (mov) instruction is in the form of 0000xxxxb, and the logic instruction is in the form of 0001xxxxb. The flow control instruction group 2944 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The tessellation instruction group 2846 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2848 includes component-by-component arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2848 performs arithmetic operations in parallel on the data paths. The vector math group 2850 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0341] Additional Exemplary Graphics Pipeline

[0342] Fig.29 2900 is a block diagram of another embodiment of a graphics processor. Elements having the same reference numerals (or names) as elements of any other figure herein Fig.29 The elements of may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0343] In some embodiments, the graphics processor 2900 includes a graphics pipeline 2920, a media pipeline 2930, a display engine 2940, a thread execution logic 2950, ​​and a rendering output pipeline 2970. In some embodiments, the graphics processor 2900 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2900 through the ring interconnect 2902. In some embodiments, the ring interconnect 2902 couples the graphics processor 2900 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2902 are interpreted by a command stream sender 2903, which supplies instructions to individual components of the graphics pipeline 2920 or the media pipeline 2930.

[0344] In some embodiments, command streamer 2903 directs the operation of vertex fetcher 2905, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2903. In some embodiments, vertex fetcher 2905 provides vertex data to vertex shader 2907, which performs coordinate space transformation and lighting operations for each vertex. In some embodiments, vertex fetcher 2905 and vertex shader 2907 execute vertex processing instructions by dispatching execution threads to execution units 2952A-2952B via thread dispatcher 2931.

[0345] In some embodiments, execution units 2952A-2952B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2952A-2952B have an attached L1 cache 2951 that is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0346] In some embodiments, the graphics pipeline 2920 includes a tessellation component to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operation. A programmable domain shader 817 provides back-end evaluation of the tessellation output. The refiner 2913 operates at the direction of the hull shader 2911 and contains dedicated logic to generate a set of detailed geometric objects based on a coarse geometric model provided as input to the graphics pipeline 2920. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 2911, refiner 2913, and domain shader 2917) may be bypassed.

[0347] In some embodiments, the complete geometric object may be processed by the geometry shader 2919 via one or more threads dispatched to execution units 2952A-2952B, or may proceed directly to the slicer 2929. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2919 receives input from the vertex shader 2907. In some embodiments, if the tessellation unit is disabled, the geometry shader 2919 is programmable by a geometry shader program to perform geometry tessellation.

[0348] Prior to rasterization, a limiter 2929 processes the vertex data. The limiter 2929 may be a fixed function limiter or a programmable limiter with limit and geometry shader functionality. In some embodiments, a rasterizer and depth test component 2973 in a render output pipeline 2970 dispatches a pixel shader to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2950. In some embodiments, an application may bypass the rasterizer and depth test component 2973 and access unrasterized vertex data via a stream output unit 2923.

[0349] The graphics processor 2900 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to pass through the main components of the processor. In some embodiments, the execution units 2952A-2952B and associated caches 2951, texture and media samplers 2954, and texture / sampler caches 2958 are interconnected via data ports 2956 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the samplers 2954, caches 2951, 2958, and execution units 2952A-2952B each have separate memory access paths.

[0350] In some embodiments, the render output pipeline 2970 includes a rasterizer and depth test component 2973 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit to perform fixed-function triangle and line rasterization. In some embodiments, an associated render cache 2978 and depth cache 2979 are also available. A pixel operation component 2977 performs pixel-based operations on data, although in some instances, pixel operations associated with 2D operations (e.g., using hybrid bit-block image transfers) are performed by the 2D engine 2941, or are replaced by the display controller 2943 using an overlay display plane at display time. In some embodiments, a shared L3 cache 2975 is available for all graphics components, allowing sharing of data without using main system memory.

[0351] In some embodiments, the graphics processor media pipeline 2930 includes a media engine 2937 and a video front end 2934. In some embodiments, the video front end 2934 receives pipeline commands from the command stream sender 2903. In some embodiments, the media pipeline 2930 includes a separate command stream sender. In some embodiments, the video front end 2934 processes the media commands before sending the commands to the media engine 2937. In some embodiments, the media engine 2937 includes a thread generation function to generate threads for dispatching to the thread execution logic 2950 via the thread dispatcher 2931.

[0352] In some embodiments, the graphics processor 2900 includes a display engine 2940. In some embodiments, the display engine 2940 is external to the graphics processor 2900 and is coupled to the graphics processor via a ring interconnect 2902 or some other interconnect bus or structure. In some embodiments, the display engine 2940 includes a 2D engine 2941 and a display controller 2943. In some embodiments, the display engine 2940 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2943 is coupled to a display device (not shown), which can be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0353] In some embodiments, graphics pipeline 2920 and media pipeline 2930 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, the driver software for graphics processor converts API calls that are unique to specific graphics or media libraries into commands that can be processed by graphics processor. In some embodiments, support is provided for open graphics library (OpenGL), open computing voice (OpenCL) and / or Vulkan graphics and computing APIs all from Khronos Group. In some embodiments, support for Direct3D library from Microsoft Corporation can also be provided. In some embodiments, the combination of these libraries can be supported. Support for open source computing vision library (OpenCV) can also be provided. If a mapping from the pipeline of future API to the pipeline of graphics processor can be made, future APIs with compatible 3D pipelines will also be supported.

[0354] Additional Example Graphics Pipeline Programming

[0355] Fig. 30A is a block diagram illustrating a graphics processor command format 3000 according to some embodiments. Fig. 30B is a block diagram illustrating a graphics processor command sequence 3010 according to an embodiment. Fig. 30A The solid-line boxes in show components that are typically included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig. 30A An exemplary graphics processor command format 3000 includes a data field to identify the target client of the command 3002, a command operation code (opcode) 3004, and associated data for the command 3006. A sub-opcode 3005 and a command size 3008 are also included in some commands.

[0356] In some embodiments, client 3002 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 3004, and if present, the sub-opcode 3005 determines the operation to be performed. The client unit uses the information in the data field 3006 to execute the command. For some commands, the explicit command size 3008 is expected to be the size of the specified command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the opcode. In some embodiments, the command is aligned via multiple double words.

[0357] Fig. 30B An exemplary graphics processor command sequence 3010 is shown in the flowchart of FIG. 3010. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of a command sequence that is shown to establish, execute, and terminate a set of graphics operations. For purposes of example only, a sample command sequence is shown and described, as embodiments are not limited to these particular commands or this command sequence. Moreover, commands may be issued as batch commands in a command sequence so that the graphics processor will process a sequence of commands that are at least partially concurrent.

[0358] In some embodiments, the graphics processor command sequence 3010 may begin with a pipeline refresh command 3012 to cause any active graphics pipeline to complete currently pending commands for the pipeline. In some embodiments, the 3D pipeline 3022 and the media pipeline 3024 do not operate concurrently. A pipeline refresh is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline refresh, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be flushed to memory. In some embodiments, the pipeline refresh command 3012 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0359] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 3013 is used. In some embodiments, a pipeline select command 3013 is only required once within an execution context before issuing a pipeline command, unless the context is used to issue commands for two pipelines. In some embodiments, a pipeline flush command 3012 is required immediately before a pipeline switch is made via a pipeline select command 3013.

[0360] In some embodiments, pipeline control commands 3014 configure the graphics pipeline for operation and are used to program the 3D pipeline 3022 and the media pipeline 3024. In some embodiments, pipeline control commands 3014 configure the pipeline state for the active pipeline. In one embodiment, pipeline control commands 3014 are used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

[0361] In some embodiments, the return buffer state command 3016 is used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during the processor operation. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 3016 includes selecting the size and number of return buffers for a set of pipeline operations.

[0362] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 3020 , the command sequence is tailored to either the 3D pipeline 3022 starting at the 3D pipeline state 3030 or the media pipeline 3024 starting at the media pipeline state 3040 .

[0363] The commands for configuring the 3D pipeline state 3030 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are configured before 3D primitive commands are processed. The values ​​of these commands are determined based at least in part on the specific 3D API in use. In some embodiments, the 3D pipeline state 3030 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0364] In some embodiments, 3D primitive 3032 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3032 commands are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 3032 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 3032 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 3022 dispatches the shader execution thread to the graphics processor execution unit.

[0365] In some embodiments, the 3D pipeline 3022 is triggered via an execution 3034 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger the command execution to refresh the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric object is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0366] In some embodiments, the graphics processor command sequence 3010 follows the media pipeline 3024 path when performing media operations. Generally, the specific use and manner of programming for the media pipeline 3024 depends on the media or computing operations to be performed. Specific media decoding operations can be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0367] In some embodiments, the media pipeline 3024 is configured in a similar manner to the 3D pipeline 3022. A set of commands for configuring the media pipeline state 3040 are dispatched or placed into a command queue before the media object commands 3024. In some embodiments, the media pipeline state commands 3040 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic (e.g., encoding or decoding formats) within the media pipeline. In some embodiments, the media pipeline state commands 3040 also support the use of one or more pointers to "indirect" state elements that contain batch state settings.

[0368] In some embodiments, media object command 3042 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 3042. Once the pipeline state is configured and media object command 3042 is queued, media pipeline 3042 is triggered via execution command 3044 or an equivalent execution event (e.g., register write). The output from media pipeline 3042 can then be post-processed by the operations provided by 3D pipeline 3022 or media pipeline 3024. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0369] Additional Exemplary Graphics Software Architecture

[0370] Fig.31 An exemplary graphics software architecture for data processing system 3100 is shown in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3110, an operating system 3120, and at least one processor 3130. In some embodiments, processor 3130 includes a graphics processor 3132 and one or more general purpose processor cores 3134. Graphics application 3110 and operating system 3120 each execute in system memory 3150 of the data processing system.

[0371] In some embodiments, the 3D graphics application 3110 includes one or more shader programs that include shader instructions 3112. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 3114 in a machine language suitable for execution by the general purpose processor core 3134. The application also includes graphics objects 3116 defined by vertex data.

[0372] In some embodiments, operating system 3120 is from Microsoft Corporation Operating system, dedicated UNIX-like operating system or open source UNIX-like operating system using a deformation of the Linux kernel. Operating system 3120 can support graphics API 3122, such as Direct3D API, OpenGL API or Vulkan API. When using Direct3D API, operating system 3120 uses front-end shader compiler 3224 to compile any shader instruction 3112 in HLSL into a lower-level shader language. Compilation can be just-in-time (JIT) compilation or application of executable shader precompilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of 3D graphics operation 3110. In some embodiments, shader instructions 3112 are provided in an intermediate form (for example, a version of the standard portable intermediate representation (SPIR) used by Vulkan API).

[0373] In some embodiments, the user mode graphics driver 3126 includes a backend shader compiler 3127 to convert shader instructions 3112 into hardware specific representations. When using the OpenGL API, shader instructions 3112 in the GLSL high level language are passed to the user mode graphics driver 3126 for compilation. In some embodiments, the user mode graphics driver 3126 uses the operating system kernel mode functions 3128 to communicate with the kernel mode graphics driver 3129. In some embodiments, the kernel mode graphics driver 3129 communicates with the graphics processor 3132 to dispatch commands and instructions.

[0374] Additional Example IP Core Implementations

[0375] One or more aspects of at least one embodiment may be implemented by representative code representing and / or defining logic within an integrated circuit (e.g., a processor) stored on a machine-readable medium. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic to perform the techniques described herein. Such representations, referred to as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations associated with any of the embodiments described herein.

[0376] Fig.3232 is a block diagram showing an IP core development system 3200 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 3200 can be used to generate modular, reusable designs that can be incorporated into a larger design, or for constructing an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 3230 can generate a software simulation 3210 of the IP core design in a high-level programming language (e.g., C++). The software simulation 3210 can be used to design, test, and verify the behavior of the IP core using a simulation model 3212. The simulation model 3212 may include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3215 can then be created or synthesized based on the simulation model 3312. The RTL design 3215 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including associated logic executed using the modeled digital signals). In addition to the RTL design 3215, a lower-level design at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can be changed.

[0377] The RTL design 3215 or equivalent may be further synthesized by the design facility into a hardware model 3220, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 3240 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 3265. Optionally, the IP core design may be sent (e.g., via the Internet) via a wired connection 3250 or a wireless connection 3260. The manufacturing facility 3265 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0378] Additional Exemplary System-on-Chip Integrated Circuits

[0379] Figure 33-Figure 35 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, and general-purpose processor cores.

[0380] Fig.333300 is an example system-on-chip integrated circuit 3300 that can be manufactured using one or more IP cores according to an embodiment. The example integrated circuit 3300 includes one or more application processors 3305 (e.g., CPUs), at least one graphics processor 3310, and may additionally include an image processor 3315 and / or a video processor 3320, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3300 includes peripheral or bus logic, which includes a USB controller 3325, a UART controller 3330, an SPI / SDIO controller 3335, and an I 2 S / I 2 The integrated circuits may include a display device 3345 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3350 and a mobile industry processor interface (MIPI) display interface 3355. Storage may be provided by a flash subsystem 3360 including flash memory and a flash controller. A memory interface may be provided via a memory controller 3365 for accessing SDRAM or SRAM memory devices. In addition, some integrated circuits include an embedded security engine 3370.

[0381] Fig.34 FIG. 34 is an exemplary graphics processor 3410 illustrating a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3410 may be Fig.33 A variation of the graphics processor 3310 of FIG. The graphics processor 3410 includes a vertex processor 3405 and one or more fragment processors 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D to 3415N-1 and 3415N). The graphics processor 3410 may execute different shader programs via separate logic, such that the vertex processor 3405 is optimized to perform operations for a vertex shader program, while one or more fragment processors 3415A-3415N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. The vertex processor 3405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processors 3415A-3415N use the primitives and vertex data generated by the vertex processor 3405 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processors 3415A-3415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0382] In addition, the graphics processor 3410 includes one or more memory management units (MMUs) 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B. The one or more MMUs 3420A-3420B provide a virtual physical address mapping for the graphics processor 3410 (including for the vertex processor 3405 and / or the fragment processors 3415A-3415N), which can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 3425A-3425B. In one embodiment, the one or more MMUs 3420-3430B can be synchronized with other MMUs within the system, including with Fig.33 One or more MMUs associated with one or more application processors 3305, image processors 3315, and / or video processors 3320 enable each processor 3305-3320 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3430A-3430B enable the graphics processor 3410 to communicate with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0383] Fig.35 is a block diagram illustrating an additional exemplary graphics processor 3510 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3510 may be Fig.33 A variation of the graphics processor 3310. The graphics processor 3510 includes Fig.34 One or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B of the integrated circuit 3400.

[0384] The graphics processor 3510 includes one or more shader cores 3515A-3515N (e.g., 3515A, 3515B, 3515C, 3515D, 3515E, 3515F to 3515N-1 and 3515N) that provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code that implements vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary among embodiments and implementations. In addition, the graphics processor 3510 includes an inter-core task manager 3505 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3515A-3515N and a tiling unit 3518 for accelerating tiling operations for tile-based rendering, wherein rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0385] The statements and / or examples below belong to a specific embodiment or examples thereof. In one or more embodiments, the details in the examples may be used anywhere. The various features of different embodiments or examples may be combined with some included features and other excluded features to suit various applications. Examples may include the subject matter of the embodiments and examples described herein, such as methods, modules for performing actions of the methods, at least one machine-readable medium including instructions, which, when executed by a machine, cause the machine to perform the actions of the methods, or the actions of a device or system. Various components may be units for performing the operations or functions.

[0386] Other embodiments provide a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising: a compute unit including a hardware logic unit having dynamic precision fixed-point logic; a decode unit that decodes instructions for execution by the compute unit, the instructions being used to cause the compute unit to perform matrix arithmetic operations on a set of dynamic fixed-point tensors; and a dynamic precision manager that dynamically adjusts the precision of computational operations performed by the compute unit during the matrix arithmetic operations, the dynamic precision manager adjusting the precision of the computational operations to prevent arithmetic overflow.

[0387] In one embodiment, the dynamic precision fixed-point logic of the computation unit includes an integer computation unit. The integer computation unit may include a multiplier, an adder and an accumulator, a shifter, and a register. The register may be configured to store a dynamic fixed-point scaling factor. In one embodiment, instructions for execution by the computation unit cause the computation unit to perform a matrix operation for a convolution operation of input data for a neural network. The matrix operation may include an addition or a multiplication operation. The matrix operation may also include a multiplication and accumulation operation. In one embodiment, a dynamic precision manager may be configured to dynamically adjust the precision of the computation operation to prevent arithmetic overflow of the accumulator.

[0388] One embodiment provides a method comprising: receiving a set of dynamic fixed-point tensors; calculating a right shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors; right shifting data values ​​within the set of dynamic fixed-point tensors to prevent loss of precision during calculations; incrementing a shared exponent associated with the set of dynamic fixed-point tensors; and performing a computational operation on the set of dynamic fixed-point tensors.

[0389] One embodiment provides a data processing system comprising a non-transitory machine-readable medium storing instructions; and one or more processors including at least one graphics processor, wherein the at least one graphics processor includes a compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit being used to perform matrix arithmetic operations on a set of dynamic fixed-point tensors; and a dynamic precision manager being used to dynamically adjust the precision of computational operations performed by the compute unit on the set of dynamic fixed-point tensors during the matrix arithmetic operations, the dynamic precision manager being used to prevent arithmetic overflow during the computational operations.

[0390] The embodiments described herein refer to a specific configuration of hardware (e.g., an application specific integrated circuit (ASIC)) that is configured to perform certain operations or have predetermined functions. Such electronic devices generally include a group of one or more processors coupled to one or more other components (e.g., one or more storage devices (non-temporary machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connections). The coupling of this group of processors and other components is generally through one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying the network service represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device generally stores code and / or data for execution on this group of one or more processors of that electronic device.

[0391] Of course, different combinations of software, firmware and / or hardware can be used to implement one or more parts of the embodiment. Throughout this specific embodiment, for the purpose of explanation, a lot of specific details have been set forth to provide a thorough understanding of the present invention. However, it is apparent to those skilled in the art that embodiments can be put into practice without some of these specific details. In some instances, known structures and functions are not described in detail to avoid blurring the creative subject of the embodiment. Therefore, the scope and spirit of the present invention should be judged according to the following claims.

Claims

1. A graphics processing unit for performing computations associated with a neural network, the graphics processing unit comprising: A computation unit comprising a hardware logic unit with dynamic precision fixed-point logic, the computation unit being configured to: Receives a set of dynamic fixed-point tensors; computing, by the dynamic precision fixed-point logic, a right-shifted value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors; right shifting data values ​​within the set of dynamic fixed-point tensors based on the right shift value; incrementing a shared exponent associated with the set of dynamic fixed-point tensors based on the right shift value; performing a computational operation on the set of dynamic fixed-point tensors; as well as An output tensor is generated by performing the computation on the set of dynamic fixed-point tensors.

2. The graphics processing unit of claim 1, wherein the dynamic precision fixed-point logic of the computation unit comprises an integer computation unit, wherein the integer computation unit comprises a multiplier, an adder, an accumulator, a shifter, and a register.

3. The graphics processing unit according to claim 2, wherein: The register is used to store shared exponents associated with the set of dynamic fixed-point tensors.

4. The graphics processing unit according to claim 1, wherein the computing unit is further configured to: determining whether the leading zero count of the absolute maximum value of the output tensor is above a threshold; and A precision associated with the output tensor is adjusted in response to determining whether the leading zero count is above the threshold.

5. The graphics processing unit according to claim 4, wherein: Adjusting the precision associated with the output tensor includes adjusting a right shift value within a right shift counter and adjusting a shared exponent for the output tensor.

6. The graphics processing unit according to claim 4, wherein: Adjusting the precision associated with the output tensor includes increasing a right shift value within a right shift counter and incrementing a shared exponent in response to determining that the leading zero count is above the threshold.

7. The graphics processing unit according to claim 4, wherein: Adjusting the precision associated with the output tensor includes decreasing a right shift value within a right shift counter and decrementing a shared exponent in response to determining that the leading zero count is below the threshold.

8. The graphics processing unit according to claim 4, wherein the computing unit is further configured to: performing an additional computational operation, the additional computational operation having an input comprising the output tensor; and A precision associated with the output tensor is adjusted based on the additional computational operations.

9. A method comprising: Receives a set of dynamic fixed-point tensors; computing a right shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors; Right shifting data values ​​within the set of dynamic fixed-point tensors; incrementing a shared exponent associated with the set of dynamic fixed-point tensors based on an amount of a right shift applied to data values ​​within the set of dynamic fixed-point tensors; as well as A computation operation is performed on the set of dynamic fixed-point tensors.

10. The method of claim 9, wherein: Performing the computation operation on the set of dynamic fixed-point tensors includes: generating an output tensor by performing the computation on the set of dynamic fixed-point tensors; determining whether the leading zero count of the absolute maximum value of the output tensor is above a threshold; and A precision associated with the output tensor is adjusted in response to determining whether the leading zero count is above the threshold.

11. The method according to claim 10, wherein: Adjusting the precision associated with the output tensor includes adjusting a right shift counter and a shared exponent for the output tensor.

12. The method of claim 10, wherein: Adjusting the precision associated with the output tensor includes increasing a right shift counter and incrementing a shared exponent in response to determining that the leading zero count is above the threshold.

13. The method of claim 10, wherein: Adjusting the precision associated with the output tensor includes decrementing a right shift counter and decrementing a shared exponent in response to determining that the leading zero count is below the threshold.

14. The method of claim 10, further comprising: Use the output tensor to perform additional computational operations; as well as A precision associated with the output tensor is adjusted based on the additional computational operations.

15. A data processing system comprising: A memory for storing a set of dynamic fixed-point tensors; as well as One or more processors, including at least one graphics processor, the at least one graphics processor including a compute unit, the compute unit including a hardware logic unit with dynamic precision fixed-point logic, the compute unit configured to: receiving the set of dynamic fixed-point tensors; computing, by the dynamic precision fixed-point logic, a right-shifted value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors; right shifting data values ​​within the set of dynamic fixed-point tensors based on the right shift value; incrementing a shared exponent associated with the set of dynamic fixed-point tensors based on the right shift value; performing a computational operation on the set of dynamic fixed-point tensors; as well as An output tensor is generated by performing the computation on the set of dynamic fixed-point tensors.

16. The data processing system according to claim 15, wherein the computing unit is further configured to: determining whether the leading zero count of the absolute maximum value of the output tensor is above a threshold; and A precision associated with the output tensor is adjusted in response to determining whether the leading zero count is above the threshold.

17. The data processing system according to claim 16, wherein: Adjusting the precision associated with the output tensor includes adjusting a right shift value within a right shift counter and adjusting a shared exponent for the output tensor.

18. The data processing system according to claim 16, wherein: Adjusting the precision associated with the output tensor includes increasing a right shift value within a right shift counter and incrementing a shared exponent in response to determining that the leading zero count is above the threshold.

19. The data processing system of claim 16, wherein: Adjusting the precision associated with the output tensor includes decreasing a right shift value within a right shift counter and decrementing a shared exponent in response to determining that the leading zero count is below the threshold.

20. The data processing system according to claim 16, wherein the computing unit is further configured to: performing an additional computational operation, the additional computational operation having an input comprising the output tensor; and A precision associated with the output tensor is adjusted based on the additional computational operations.

Images