Semiconductor memory device performing program operation

Abstract

The invention relates to a semiconductor memory device performing a program operation. A page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. During a program operation of a selected memory cell, a supply voltage is applied to a bit line connection transistor to set a voltage of a bit line connected with a memory cell having a threshold voltage greater than a main verify voltage to a program inhibit voltage. In addition, a second program enable voltage less than the program disable voltage is applied to the bit line connection transistor. In addition, a first program enable voltage less than the second program enable voltage is applied to the gate of the bit line connection transistor.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor memory device that performs a program operation. Background Art

[0002] The semiconductor memory device may be formed as a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate or a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. A three-dimensional memory device is a memory device designed to solve the integration limitation of a two-dimensional memory device and may include a plurality of memory cells stacked in a vertical direction on a semiconductor substrate.

[0003] During a programming operation of a selected memory cell, a plurality of programming loops for the selected memory cell are performed. Each programming loop may include a first auxiliary verification operation, a second auxiliary verification operation, and a main verification operation. The first auxiliary verification operation includes an operation of sensing the threshold voltage of a memory cell using a first auxiliary verification voltage that is less than the main verification voltage used in the main verification operation. The second auxiliary verification operation includes an operation of sensing the threshold voltage of a memory cell using a second auxiliary verification voltage that is less than the first auxiliary verification voltage used in the first auxiliary verification operation. By differently controlling the bit line voltage of a memory cell having a threshold voltage corresponding to each segment in a segment divided by the first auxiliary verification voltage and the second auxiliary verification voltage and the main verification voltage, the threshold voltage distribution characteristics of the memory cell formed by the programming operation can be improved. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor memory device includes a memory cell array, a plurality of page buffers, and control logic. The memory cell array includes a plurality of memory cells. The plurality of page buffers are respectively connected to the plurality of memory cells through bit lines. The control logic controls a programming operation of each of the plurality of page buffers. Each of the plurality of page buffers includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. The bit line connection transistor is connected to a corresponding bit line. The internal operation circuit is connected to the bit line connection transistor through a first node. The plurality of latch circuits are connected to the internal operation circuit through a second node. During a programming operation of a selected memory cell among a plurality of memory cells, the control logic controls the plurality of page buffers to set a voltage of a bit line connected to a memory cell having a threshold voltage greater than a main verification voltage corresponding to a target programming state among the plurality of memory cells to a programming inhibition voltage by applying a power supply voltage to a gate of a bit line connection transistor included in each of the plurality of page buffers, controls the plurality of page buffers to set a voltage of a bit line connected to a memory cell having a threshold voltage greater than a first auxiliary verification voltage corresponding to the target programming state and less than the main verification voltage among the plurality of memory cells to a second programming inhibition voltage by applying a second programming enable voltage less than the programming enable voltage to a gate of a bit line connection transistor included in each of the plurality of page buffers, and controls the plurality of page buffers to set a voltage of a bit line connected to a memory cell having a threshold voltage greater than a first auxiliary verification voltage corresponding to the target programming state and less than the first auxiliary verification voltage among the plurality of memory cells to a first programming enable voltage by applying a first programming enable voltage less than the second programming enable voltage to a gate of a bit line connection transistor included in each of the plurality of page buffers.

[0005] According to another embodiment of the present disclosure, a semiconductor memory device includes a memory cell, a page buffer, and control logic. The memory cell stores N bits. Here, N is a natural number greater than or equal to 2. In addition, the page buffer is connected to the memory cell through a bit line. The control logic controls the programming operation of the page buffer. The page buffer includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. The bit line connection transistor is connected to the bit line. The internal operation circuit is connected to the bit line connection transistor through a first node. The plurality of latch circuits are connected to the internal operation circuit through a second node. The memory cell is programmed to a first programming state to a second programming state. N-1) A target programming state among programming states. During a programming operation of a memory cell, the control logic controls the page buffer to perform a verification operation using a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage corresponding to the target programming state, respectively. After the verification operation on the memory cell, the control logic controls the page buffer to set the voltage of the bit line according to the threshold voltage of the memory cell by sequentially applying a power supply voltage, a second programming enable voltage, and a first programming enable voltage to the gate of the bit line connection transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 2 is a diagram illustrating a threshold voltage distribution of a multi-level cell (MLC), and a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage used to form the threshold voltage distribution.

[0008] Figure 3 is a diagram illustrating a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage corresponding to a first program state, and sections of threshold voltages of memory cells distinguished by the main verification voltage, the first auxiliary verification voltage, and the second auxiliary verification voltage.

[0009] Figure 4 is an example of Figure 3 Graph of bit line voltage settings for memory cells corresponding to the segments shown in FIG.

[0010] Figure 5 is a block diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0011] Figure 6 yes Figure 5 An example circuit diagram of the internal operating circuit is shown in FIG.

[0012] Figure 7 yes Figure 5 An example circuit diagram of a first latch circuit is shown in FIG.

[0013] Figure 8 yes Figure 5 An example circuit diagram of a second latch circuit is shown in FIG.

[0014] Fig. 9 yes Figure 5 An example circuit diagram of a third latch circuit is shown in FIG.

[0015] Fig.10 yes Figure 5 An example circuit diagram of a fourth latch circuit is shown in FIG.

[0016] Fig.11yes Figure 5 An example circuit diagram of a fifth latch circuit is shown in FIG.

[0017] Fig.12 is a timing diagram illustrating the operation of the semiconductor memory device according to an embodiment of the present disclosure.

[0018] Fig.13 is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment of the present disclosure.

[0019] Fig.14 yes Figure 5 Another example circuit diagram of the second latch circuit is shown in FIG. DETAILED DESCRIPTION

[0020] The specific structural or functional description of the embodiments of the concepts disclosed in this specification or this application is only exemplified for describing the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0021] Embodiments of the present disclosure may relate to a semiconductor memory device that sets a bit line voltage to perform first and second auxiliary verification operations and a main verification operation. The present technology may relate to a semiconductor memory device that sets a bit line voltage to perform first and second auxiliary verification operations and a main verification operation.

[0022] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read / write circuit 130 , a control logic 140 , and a voltage generator 150 .

[0024] The memory cell array 110 includes a plurality of memory blocks BLKa to BLKz. The plurality of memory blocks BLKa to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLKa to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLKa to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells may be configured as nonvolatile memory cells.

[0025] Figure 1 2 shows a structure of a memory block BLKa among a plurality of memory blocks BLKa to BLKz included in a memory cell array. Figure 1, a plurality of word lines WL1 to WLn arranged in parallel with each other may be connected between a drain selection line DSL and a source selection line SSL. More specifically, a memory block BLKa may include a plurality of strings ST connected between bit lines BL1 to BLm and a common source line CSL. The bit lines BL1 to BLm may be connected to corresponding strings ST, respectively, and the common source line CSL may be connected to the strings ST in common. Since the strings ST may be configured identically to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

[0026] The string ST may include a source select transistor SST, a plurality of memory cells MC1 to MCn, and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include at least one source select transistor SST and at least one drain select transistor DST.

[0027] The source of the source select transistor SST may be connected to a common source line CSL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MCn may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, the gates of the drain select transistors DST may be connected to the drain select line DSL, and the gates of the memory cells MC1 to MCn may be connected to a plurality of word lines WL1 to WLn. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Therefore, the memory block BLKi may include a page PG of the number of word lines WL1 to WLn.

[0028] One memory cell can store one bit of data. This is generally referred to as a single-level cell (SLC). In this case, one physical page PG can store one logical page (LPG) of data. One logical page (LPG) of data can include the same number of data bits as the number of cells included in one physical page PG.

[0029] In addition, one memory cell can store two or more bits of data. In this case, one physical page PG can store two or more logical pages (LPG) of data.

[0030] exist Figure 1 In FIG. 1 , a two-dimensional storage block structure is shown, but the present disclosure is not limited thereto. That is, Figure 1 Each of the memory blocks BLKa to BLKz may be configured as a three-dimensional memory block.

[0031] The address decoder 120, the read / write circuit 130, and the voltage generator 150 operate as a peripheral circuit for driving the memory cell array 110. The peripheral circuit can perform a read operation, a write operation, and an erase operation on the memory cell array 110 based on the control of the control logic 140. The address decoder 120 is connected to the memory cell array 110 through the word line WL. The address decoder 120 is configured to operate in response to the control of the control logic 140. Specifically, the control logic 140 transmits an address decoding control signal CTRL to the address decoder 120. AD , and the address decoder 120 decodes the control signal CTRL based on the address AD Perform a decode operation.

[0032] In addition, during a program operation, the address decoder 120 applies a program voltage VPGM generated by the voltage generator 150 to a selected word line and applies a program pass voltage to the remaining unselected word lines. In addition, during a program verification operation, the address decoder 120 applies a verification voltage Vvf generated by the voltage generator 150 to a selected word line and applies a verification pass voltage to the remaining unselected word lines.

[0033] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 may operate as a “read circuit” during a read operation of the memory cell array 110, and may operate as a “write circuit” during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. The read / write circuit 130 responds to a page buffer control signal CTRL output from the control logic 140. PB The received data DATA is programmed. Figure 5 An implementation of the page buffer 131 among the plurality of page buffers PB1 to PBm is described.

[0034] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, and the voltage generator 150. The control logic 140 may receive a command CMD from the outside. The control logic 140 may control the address decoder 120, the read / write circuit 130, and the voltage generator 150 to perform an operation corresponding to the received command CMD. That is, the control logic 140 may generate a control signal CTRL through a voltage. VG To control the operation of the voltage generator 150. In addition, the control logic 140 can decode the control signal CTRL by address AD To control the operation of the address decoder 120. In addition, the control logic 140 can control the operation of the address decoder 120 through the page buffer control signal CTRL PBTo control the operation of the page buffers PB1 to PBm in the read / write circuit 130. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0035] The voltage generator 150 may generate a control signal CTRL in response to a voltage output from the control logic 140. VG The voltage generator 150 may generate various operation voltages. For example, the voltage generator 150 may generate a program voltage VPGM for a program operation and a verification voltage Vvf for a program verification operation. In addition, the voltage generator 150 may generate a program pass voltage and a verification pass voltage.

[0036] Figure 2 is a diagram illustrating a threshold voltage distribution of a multi-level cell (MLC), and a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage used to form the threshold voltage distribution.

[0037] Reference Figure 2 , as an example, shows the threshold voltage distribution of the target state corresponding to the MLC. The MLC stores two-bit data including the most significant bit (MSB) and the least significant bit (LSB). Figure 2 In the example of , memory cells corresponding to the erase state E may store a data pattern of "1 1", memory cells corresponding to the first programming state PV1 may store a data pattern of "1 0", memory cells corresponding to the second programming state PV2 may store a data pattern of "0 0", and memory cells corresponding to the third programming state PV3 may store a data pattern of "0 1". In order to read data of the MLC, the first read voltage R1 to the third read voltage R3 may be used.

[0038] In order to store two bits of data respectively, the MLC may have a threshold voltage corresponding to the erase state E and any one of the first to third programming states PV1 to PV3 after programming. In order to read the data of the MLC, the first to third read voltages R1 to R3 may be used. In addition, the pass voltage Vpass may be applied to the unselected word lines.

[0039] During a programming verification operation, main verification voltages Vvf1, Vvf2, and Vvf3, first auxiliary verification voltages Vvf1', Vvf2', and Vvf3', and second auxiliary verification voltages Vvf1", Vvf2", and Vvf3" may be used. The corresponding first auxiliary verification voltages Vvf1', Vvf2', and Vvf3' are smaller than the corresponding main verification voltages Vvf1, Vvf2, and Vvf3, and the corresponding second auxiliary verification voltages Vvf1", Vvf2", and Vvf3" are smaller than the corresponding first auxiliary verification voltages Vvf1', Vvf2', and Vvf3'.

[0040] Reference Figure 3 A programming method using main verification voltages Vvf1 , Vvf2 , and Vvf3 , first auxiliary verification voltages Vvf1 ′, Vvf2 ′, and Vvf3 ′, and second auxiliary verification voltages Vvf1 ″, Vvf2 ″, and Vvf3 ″ is described.

[0041] Figure 3 is a diagram illustrating a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage corresponding to a first program state PV1, and sections of threshold voltages of memory cells distinguished by the main verification voltage, the first auxiliary verification voltage, and the second auxiliary verification voltage. Figure 4 is an example of Figure 3 1 is a diagram of the bit line voltage settings of the memory cells corresponding to the segments shown in FIG. Figure 3 and Figure 4 Control of a voltage of a bit line connected to a memory cell to be programmed to a first program state PV1 during a program operation is described.

[0042] Reference Figure 3 , shows the threshold voltage distribution of the memory cell to be programmed to the first programming state PV1 during the programming operation. In addition, Figure 3 1 shows a main verification voltage Vvf1, a first auxiliary verification voltage Vvf1′, and a second auxiliary verification voltage Vvf1″ corresponding to a first programming state PV1. Memory cells to be programmed to the first programming state PV1 may be divided into four groups A to D by the main verification voltage Vvf1, the first auxiliary verification voltage Vvf1′, and the second auxiliary verification voltage Vvf1″. That is, a memory cell D having a threshold voltage greater than the main verification voltage Vvf1 is programmed to the first programming state PV1. Therefore, as Figure 4 As shown, in a subsequent program loop, a program inhibition voltage Vinh may be applied to a bit line BL connected to a memory cell D having a threshold voltage higher than a main verification voltage Vvf1. D In an implementation, the program inhibit voltage may be a power supply voltage.

[0043] On the other hand, the memory cells A, B, and C having a threshold voltage less than the main verification voltage Vvf1 have not been programmed to the first program state PV1. Therefore, in a subsequent programming loop, a program enable voltage less than the program inhibit voltage may be applied to the bit lines BL connected to the memory cells A, B, and C having a threshold voltage less than the main verification voltage Vvf1. A BL B and BL C .

[0044] In addition, the programming speed of the memory cells that have not yet been programmed to the first programming state PV1 can be adjusted using the first auxiliary verification voltage Vvf1′ and the second auxiliary verification voltage Vvf1″. That is, the threshold voltage distribution width of the first programming state PV1 can be narrowed by reducing the threshold voltage movement width of the memory cells near the main verification voltage Vvf1.

[0045] More specifically, the ground voltage VSS may be applied to the bit line BL connected to the memory cell A having a threshold voltage less than the second auxiliary verification voltage Vvf1″ among the memory cells to be programmed to the first program state PV1. A In addition, the first program enable voltage VREF1 is applied to the bit line BL connected to the memory cell B having a threshold voltage greater than the second auxiliary verification voltage Vvf1″ and less than the first auxiliary verification voltage Vvf1′ among the memory cells to be programmed to the first program state PV1. B In an embodiment, the first program enable voltage VREF1 may be a voltage greater than the ground voltage VSS and less than the program inhibit voltage Vinh. In addition, the second program enable voltage VREF2 is applied to the bit line BL connected to the memory cell C having a threshold voltage greater than the first auxiliary verification voltage Vvf1' and less than the main verification voltage Vvf1 among the memory cells to be programmed to the first program state PV1. C In an embodiment, the second program permission voltage VREF2 may be a voltage greater than the first program permission voltage VREF1 and less than the program inhibition voltage Vinh.

[0046] When the program voltage is applied to the selected word line, the threshold voltage of the memory cell connected to the bit line to which the program inhibition voltage is applied is maintained. In addition, when the program voltage is applied to the selected word line, the bit line BL connected to which the second program enable voltage VREF2 is applied is C The threshold voltage shift width of the memory cell C is smaller than the bit line BL connected to the bit line BL to which the first program enable voltage VREF1 is applied. B In addition, when the program voltage is applied to the selected word line, the bit line BL connected to the bit line BL to which the first program enable voltage VREF1 is applied isB The threshold voltage shift width of the memory cell B is smaller than that of the bit line BL connected to the ground voltage VSS. A The threshold voltage shift width of memory cell A.

[0047] Therefore, the threshold voltage distribution width of the memory cells programmed to the first program state PV1 may be narrowed by controlling the threshold voltage shift width of the memory cells A, B, and C, in which programming has not been completed, for each segment.

[0048] Although the first program state PV1 is described above as an example, program operations for the second program state PV2 and the third program state PV3 may also be performed by the same method.

[0049] Hereinafter, for ease of discussion, a semiconductor memory device and an operating method thereof according to the present disclosure are described based on a program operation for MLC. However, the present disclosure is not limited thereto and is applicable to programming of single-level cells (SLC), triple-level cells (TLC), etc.

[0050] Figure 5 is a block diagram illustrating a page buffer according to an embodiment of the present disclosure. Figure 5 As an example, the Figure 1 1 is a block diagram of a page buffer 131 connected to a first bit line BL1.

[0051] Reference Figure 5 , the page buffer 131 may include a bit line connection transistor 201, an internal operation circuit 205, and a plurality of latch circuits 210, 220, 230, 240, and 250. For example, Figure 5 The page buffer 131 shown in FIG. 1 may include a first latch circuit (LAT1) 210, a second latch circuit (LAT2) 220, a third latch circuit (LAT3) 230, a fourth latch circuit (LAT4) 240, and a fifth latch circuit (LAT5) 250. However, this is only an example, and the number of latch circuits included in the page buffer 131 may vary as needed.

[0052] The bit line connection transistor 201 is connected between the first bit line BL1 and the internal operation circuit 205. Specifically, the bit line connection transistor 201 is connected to the internal operation circuit 205 through the node CSO. The bit line connection transistor 201 can be controlled by the control signal PB_SENSE, and controls the connection between the first bit line BL1 and the internal operation circuit 205. In an embodiment, the bit line connection transistor 201 can be implemented as a first NMOS transistor N1. When the first NMOS transistor N1 is turned on, the first bit line BL1 can be connected to the internal operation circuit 205 through the node CSO. The signal PB_SENSE can be output from the control logic 140 and input to the bit line connection transistor 201.

[0053] In addition, the latch circuits 210, 220, 230, 240, and 250 are connected to the internal operation circuit 205 through the node SO. The bit data received from the outside can be stored in at least a part of the latch circuits 210, 220, 230, 240, and 250 for programming operations. For example, the page buffer 131 may include a latch circuit for storing two bits for programming the MLC. For example, among the latch circuits 210, 220, 230, 240, and 250, the LSB can be stored in the fourth latch circuit 240, and the MSB can be stored in the fifth latch circuit 250.

[0054] For example, in the case where data bits indicating a logic value of “1” are respectively stored in the fourth latch circuit 240 and the fifth latch circuit 250 , this means that the threshold voltage of the memory cell connected to the corresponding page buffer needs to maintain the erase state E.

[0055] As another example, in the case where a data bit indicating a logic value of "0" is stored in the fourth latch circuit 240 and a data bit indicating a logic value of "1" is stored in the fifth latch circuit 250, this means that the memory cell connected to the corresponding page buffer is a memory cell to be programmed to the first programming state PV1.

[0056] As yet another example, when data bits indicating a logic value of '0' are respectively stored in the fourth latch circuit 240 and the fifth latch circuit 250 , this means that memory cells connected to the corresponding page buffer are memory cells to be programmed to the second program state PV2 .

[0057] As another example, when a data bit indicating a logic value of "1" is stored in the fourth latch circuit 240 and a data bit indicating a logic value of "0" is stored in the fifth latch circuit 250, this means that the memory cell connected to the corresponding page buffer is a memory cell to be programmed to the third programming state PV3.

[0058] However, this is an example, and the page buffer 131 may include a latch circuit for storing three bits for programming TLC. In this case, in addition to the fourth and fifth latch circuits for storing LSB and MSB, the page buffer 131 may further include a sixth latch circuit for storing a middle significant bit CSB.

[0059] Hereinafter, a case where a data bit indicating a logic value of “0” is stored in the fourth latch circuit 240 and a data bit indicating a logic value of “1” is stored in the fifth latch circuit 250, that is, a case where the target programming state of the memory cell connected to the first bit line BL1 is the first programming state PV1 is described as an example.

[0060] As mentioned above Figure 2 and Figure 3 As described, the page buffer 131 may include three latch circuits to store bits indicating whether each threshold voltage of each memory cell is greater than the main verification voltage, the first auxiliary verification voltage, and the second auxiliary verification voltage during the programming process. When the target programming state of the memory cell connected to the first bit line BL1 is the first programming state PV1, a bit indicating whether the threshold voltage of the corresponding memory cell is greater than the main verification voltage Vvf1 may be stored in the first latch circuit 210. For example, when the threshold voltage of the memory cell is greater than the main verification voltage Vvf1, a data bit having a logic value of "0" may be stored in the first latch circuit 210, and when the threshold voltage of the memory cell is less than the main verification voltage Vvf1, a data bit having a logic value of "1" may be stored in the first latch circuit 210.

[0061] In addition, a bit indicating whether the threshold voltage of the memory cell is greater than the first auxiliary verification voltage Vvf1′ may be stored in the second latch circuit 220. For example, when the threshold voltage of the memory cell is greater than the first auxiliary verification voltage Vvf1′, a data bit having a logic value of “0” may be stored in the second latch circuit 220, and when the threshold voltage of the memory cell is less than the first auxiliary verification voltage Vvf1′, a data bit having a logic value of “1” may be stored in the second latch circuit 220.

[0062] In addition, a bit indicating whether the threshold voltage of the memory cell is greater than the second auxiliary verification voltage Vvf1” can be stored in the third latch circuit 230. For example, when the threshold voltage of the memory cell is greater than the second auxiliary verification voltage Vvf1”, a data bit with a logic value of “0” can be stored in the third latch circuit 230, and when the threshold voltage of the memory cell is less than the second auxiliary verification voltage Vvf1”, a data bit with a logic value of “1” can be stored in the third latch circuit 230.

[0063] To summarize the above, Figure 3 In the page buffer connected to the memory cells of group A shown in FIG. 1 , data bits “1”, “1”, and “1” may be stored in the first to third latch circuits 210, 220, and 230, respectively. In addition, in the page buffer connected to the memory cells of group B, data bits “1”, “1”, and “0” may be stored in the first to third latch circuits 210, 220, and 230, respectively. In addition, in the page buffer connected to the memory cells of group C, data bits “1”, “0”, and “0” may be stored in the first to third latch circuits 210, 220, and 230, respectively. Finally, in the page buffer connected to the memory cells of group D, data bits “0”, “0”, and “0” may be stored in the first to third latch circuits 210, 220, and 230, respectively. The page buffer 131 may be configured to store data bits based on the data bits stored in the first to third latch circuits 210, 220, and 230. Figure 4 The voltages to be applied to the bit lines for subsequent programming cycles are set as shown.

[0064] The internal operation circuit 205 and the first to fifth latch circuits 210, 220, 230, 240, and 250 may be designed in various ways as needed. Figure 6 and Fig.11 Example implementations of the internal operation circuit 205 and the first to fifth latch circuits 210 , 220 , 230 , 240 , and 250 are described.

[0065] Figure 6 yes Figure 5 An example circuit diagram of the internal operating circuit 205 is shown in FIG.

[0066] The internal operation circuit 205 may operate in response to signals output from the control logic 140. Signals SA_PRE, SA_CSOC, SA_PRECH_N, SA_SENSE, and SA_DISCH described below may be signals output from the control logic 140. A detailed description of the internal operation circuit 205 is as follows.

[0067] Reference Figure 6 , the internal operation circuit 205 may include second to sixth NMOS transistors N2 to N6 and first and second PMOS transistors P1 and P2. The second NMOS transistor N2 is connected between the node CSO and the node SAN and is controlled by the signal SA_CSOC. The third NMOS transistor N3 is connected between the power supply voltage VCORE and the node SAN and is controlled by the signal SA_PRE. The first PMOS transistor P1 is connected between the power supply voltage VCORE and the node SAN and is controlled by the voltage of the node QS. Figure 7Describes the node QS.

[0068] The second PMOS transistor P2 is connected between the node SAN and the node SO, and is controlled by the signal SA_PRECH_N. The fourth NMOS transistor N4 is connected between the node SO and the node CSO, and is controlled by the signal SA_SENSE.

[0069] The fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected in series between the node SO and the ground voltage. The fifth NMOS transistor N5 is controlled by the signal SA_DISCH, and the sixth NMOS transistor N6 is controlled by the voltage of the node QS.

[0070] As mentioned above Figure 5 As described, the first NMOS transistor N1 may be connected between the node CSO and the first bit line BL1.

[0071] Figure 7 yes Figure 5 An example circuit diagram of the first latch circuit 210 is shown in FIG.

[0072] Reference Figure 7 The first latch circuit 210 may include a latch LS connected between nodes QS and QS_N, a seventh NMOS transistor N7 connected between the node QS and the node COM1, an eighth NMOS transistor N8 connected between the node QS_N and the node COM1, a ninth NMOS transistor N9 connected between the node COM1 and the ground voltage, and a tenth NMOS transistor N10 and an eleventh NMOS transistor N11 connected in series between the node SO and the ground voltage.

[0073] The seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 may be controlled by signals RST_S, SET_S, PBRST, and TRANS_N, respectively. In addition, the eleventh NMOS transistor N11 may be controlled by a voltage value of the node QS_N.

[0074] The voltage value of the node QS of the latch LS and the voltage value of the node QS_N may be a logically inverted value. That is, when the voltage value of the node QS is a logic-high voltage value, the voltage value of the node QS_N becomes a logic-low voltage value. Conversely, when the voltage value of the node QS is a logic-low voltage value, the voltage value of the node QS_N becomes a logic-high voltage value. The bit stored in the first latch circuit 210 may be represented by the voltage value of the node QS or the node QS_N.

[0075] In an embodiment, it can be determined that when the voltage value of the node QS is a logic-high voltage value and the voltage value of the node QS_N is a logic-low voltage value, the first latch circuit 210 stores a value "0", and when the voltage value of the node QS is a logic-low voltage value and the voltage value of the node QS_N is a logic-high voltage value, the first latch circuit 210 stores a value "1".

[0076] On the contrary, it can be determined that when the voltage value of the node QS is a logic-high voltage value and the voltage value of the node QS_N is a logic-low voltage value, the first latch circuit 210 can store the value "1", and when the voltage value of the node QS is a logic-low voltage value and the voltage value of the node QS_N is a logic-high voltage value, the first latch circuit 210 stores the value "0".

[0077] For ease of discussion, in this specification, the present disclosure is described based on an implementation in which the first latch circuit 210 stores a value "1" when the voltage value of the node QS is a logic-high voltage value and the voltage value of the node QS_N is a logic-low voltage value, and the first latch circuit 210 stores a value "0" when the voltage value of the node QS is a logic-low voltage value and the voltage value of the node QS_N is a logic-high voltage value.

[0078] Figure 8 yes Figure 5 An example circuit diagram of the second latch circuit 220 is shown in FIG.

[0079] Reference Figure 8 The second latch circuit 220 may include a twelfth NMOS transistor N12 and a thirteenth NMOS transistor N13 connected in series between the node SO and the ground voltage, a latch LM connected between the nodes QM and QM_N, a fourteenth NMOS transistor N14 connected between the node QM and the node COM1, a fifteenth NMOS transistor N15 connected between the node QS_N and the node COM1, a sixteenth NMOS transistor N16 connected between the node COM1 and the ground voltage, and a seventeenth NMOS transistor N17 and an eighteenth NMOS transistor N18 connected in series between the node SO and the power supply voltage.

[0080] The twelfth NMOS transistor N12, the fourteenth NMOS transistor N14, the fifteenth NMOS transistor N15, and the seventeenth NMOS transistor N17 may be controlled by signals TRNM, RST_M, SET_M, and TRANM_N, respectively. The thirteenth NMOS transistor N13 may be controlled by the voltage value of the node QM, the sixteenth NMOS transistor N16 may be controlled by the voltage value of the node SO, and the eighteenth NMOS transistor N18 may be controlled by the voltage value of the node QM_N.

[0081] For ease of discussion, in this specification, the present disclosure is described based on an implementation in which the second latch circuit 220 stores a value "1" when the voltage value of the node QM is a logic-high voltage value and the voltage value of the node QM_N is a logic-low voltage value, and stores a value "0" when the voltage value of the node QM is a logic-low voltage value and the voltage value of the node QM_N is a logic-high voltage value.

[0082] Fig. 9 yes Figure 5 An example circuit diagram of the third latch circuit 230 is shown in FIG.

[0083] Reference Fig. 9 The third latch circuit 230 may include a nineteenth NMOS transistor N19 and a twentieth NMOS transistor N20 connected in series between the node SO and the ground voltage, a latch LT connected between the nodes QT and QT_N, a twenty-first NMOS transistor N21 connected between the node QT and the node COM2, a twenty-second NMOS transistor N22 connected between the node QT_N and the node COM2, and a twenty-third NMOS transistor N23 connected between the node COM2 and the ground voltage.

[0084] The nineteenth NMOS transistor N19, the twenty-first NMOS transistor N21, and the twenty-second NMOS transistor N22 may be controlled by signals TRANT, RST_T, and SET_T, respectively. The twentieth NMOS transistor N20 may be controlled by a voltage value of a node QT, and the twenty-third NMOS transistor N23 may be controlled by a voltage value of a node SO.

[0085] For ease of discussion, in this specification, the present disclosure is described based on an implementation in which the third latch circuit 230 stores a value "1" when the voltage value of the node QT is a logic-high voltage value and the voltage value of the node QT_N is a logic-low voltage value, and stores a value "0" when the voltage value of the node QT is a logic-low voltage value and the voltage value of the node QT_N is a logic-high voltage value.

[0086] Fig.10 yes Figure 5 An example circuit diagram of the fourth latch circuit 240 is shown in FIG.

[0087] Reference Fig.10The fourth latch circuit 240 may include a twenty-fourth NMOS transistor N24 and a twenty-fifth NMOS transistor N25 connected in series between the node SO and the ground voltage, a latch LA connected between the nodes QA and QA_N, a twenty-sixth NMOS transistor N26 connected between the node QA and the node COM3, a twenty-seventh NMOS transistor N27 connected between the node QA_N and the node COM3, and a twenty-eighth NMOS transistor N28 connected between the node COM3 and the ground voltage.

[0088] The twenty-fourth, twenty-sixth and twenty-seventh NMOS transistors N24, N26 and N27 may be controlled by signals TRANA, RST_A and SET_A, respectively. The twenty-fifth NMOS transistor N25 may be controlled by a voltage value of a node QA, and the twenty-eighth NMOS transistor N28 may be controlled by a voltage value of a node SO.

[0089] For ease of discussion, in this specification, the present disclosure is described based on an implementation in which the fourth latch circuit 240 stores a value "1" when the voltage value of the node QA is a logic-high voltage value and the voltage value of the node QA_N is a logic-low voltage value, and stores a value "0" when the voltage value of the node QA is a logic-low voltage value and the voltage value of the node QA_N is a logic-high voltage value.

[0090] Fig.11 yes Figure 5 An example circuit diagram of the fifth latch circuit 250 is shown in FIG.

[0091] Reference Fig.11 , the fifth latch circuit 250 may include a latch LB connected between the nodes QB and QB_N, a twenty-ninth NMOS transistor N29 connected between the nodes SO and QB, a thirtieth NMOS transistor N30 connected between the nodes SO and QB_N, and a thirty-first NMOS transistor N31 connected between the node QB and the ground voltage. The twenty-ninth NMOS transistor N29, the thirtieth NMOS transistor N30, and the thirty-first NMOS transistor N31 may be controlled by signals TRANB, TRANSB_N, and CRST, respectively.

[0092] For ease of discussion, in this specification, the present disclosure is described based on an implementation in which the fifth latch circuit 250 stores a value "1" when the voltage value of the node QB is a logic-high voltage value and the voltage value of the node QB_N is a logic-low voltage value, and the fifth latch circuit 250 stores a value "0" when the voltage value of the node QB is a logic-low voltage value and the voltage value of the node QB_N is a logic-high voltage value.

[0093] Fig.12 is a timing diagram illustrating the operation of the semiconductor memory device according to an embodiment of the present disclosure.

[0094] Reference Fig.12 , shows a timing diagram for setting a bit line voltage immediately before a programming voltage is applied to a selected word line during a programming operation of a semiconductor memory device. Fig.12 Before time t1 shown in FIG. 1 , data bits indicating verification results using the main verification voltage Vvf1 , the first auxiliary verification voltage Vvf1 ′, and the second auxiliary verification voltage Vvf1 ″ may be stored in the first to third latch circuits 210 , 220 , and 230 of the page buffer 131 .

[0095] From time t1 to time t2, a first bit line setting operation is performed. Specifically, the signal SA_PRECH_N is activated to a low voltage at time t1. Therefore, the second PMOS transistor P2 is turned on at time t1.

[0096] In addition, the signals SA_SENSE, SA_DISCH, and PB_SENSE are activated to a high voltage at time t1. Therefore, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the first NMOS transistor N1 are turned on at time t1.

[0097] Refer to Figure 5 The first NMOS transistor N1 and Figure 6 According to the internal operation circuit 205 , since the second PMOS transistor P2 , the fourth NMOS transistor N4 , and the fifth NMOS transistor N5 are turned on at time t1 , the voltage of the bit line may be differently set according to the data stored in the first latch circuit 210 .

[0098] More specifically, when the threshold voltage of the memory cell is greater than the main verification voltage Vvf1, a data bit having a logic value of "0" may be stored in the first latch circuit 210. In this case, the voltage value of the node QS may be a logic-low voltage value. Therefore, the first PMOS transistor P1 is turned on and the sixth NMOS transistor N6 is turned off. Therefore, the bit line is connected to the power supply voltage through a path including the first PMOS transistor P1, the second PMOS transistor P2, the fourth NMOS transistor N4, and the first NMOS transistor N1. That is, at time t1, the bit line BL connected to the memory cell of group D is D The voltage starts to increase to the power supply voltage VCORE.

[0099] In addition, when the threshold voltage of the memory cell is less than the main verification voltage Vvf1, a data bit having a logic value of "1" may be stored in the first latch circuit 210. In this case, the voltage value of the node QS may be a logic-high voltage value. Therefore, the first PMOS transistor P1 is turned off and the sixth NMOS transistor N6 is turned on. Therefore, the bit line is connected to the ground voltage through a path including the sixth NMOS transistor N6, the fifth NMOS transistor N5, the fourth NMOS transistor N4, and the first NMOS transistor N1. That is, the bit line BL connected to the memory cells of the groups A to C A BL B and BL C The voltage of may not increase at time t1 and remain at the ground voltage.

[0100] Thereafter, from time t2 to time t5, the TPGM data is moved. The TPGM data is data indicating whether the threshold voltage of the memory cell is greater than the second auxiliary verification voltage Vvf1″, and is data stored in the third latch circuit 230. During the period t2 to t5, the data stored in the third latch circuit 230 is moved to the first latch circuit 210.

[0101] The operation of moving the data stored in the third latch circuit 230 to the first latch circuit 210 may be performed by transferring the voltage value of the node QT to the node QS. The step of transferring the voltage value of the node QT to the node QS is performed by the following process.

[0102] First, by initialization, the node QS has a high value indicating "1", that is, a power supply voltage value. This can be performed by turning on the eighth NMOS transistor N8 and the ninth NMOS transistor N9 via the signals PBRST and SET_S. In addition, by initialization, the node SO has a high value indicating "1", that is, a power supply voltage value. This can be performed by activating the signal SA_PRE to a high value to turn on the third NMOS transistor N3 and by activating the signal SA_PRECH_N to a low value to turn on the second PMOS transistor P2. Fig.12 , the signal SA_PRECH_N is activated to a low value at time t3.

[0103] In this state, when the signal TRANT applied to the gate of the nineteenth NMOS transistor N19 is activated to a high value, the nineteenth NMOS transistor N19 is turned on. In addition, the twentieth NMOS transistor N20 may be selectively turned on according to the value of the node QT to selectively change the value of the node SO.

[0104] For example, when the voltage value of the node QT is high, the twentieth NMOS transistor N20 is turned on, so the voltage of the node SO changes to the ground voltage. Conversely, when the voltage value of the node QT is low, the twentieth NMOS transistor N20 is turned off, so the voltage of the node SO remains high.

[0105] Because the node SO is connected to the gate of the sixteenth NMOS transistor N16, the sixteenth NMOS transistor N16 is selectively turned on according to the voltage value of the node SO. Thereafter, the signal RST_S is activated to a high value to turn on the seventh NMOS transistor N7.

[0106] When the voltage of the node SO is the ground voltage, the sixteenth NMOS transistor N16 maintains a turned-off state. Therefore, even if the seventh NMOS transistor N7 is turned on by activating the signal RST_S to a high value, the voltage of the node QS maintains a high value indicating "1".

[0107] In contrast, when the voltage of the node SO is high, the sixteenth NMOS transistor N16 is turned on. Therefore, when the seventh NMOS transistor N7 is turned on by activating the signal RST_S to a high value, the node QS is electrically connected to the ground voltage and thus changes to a low value indicating "0".

[0108] Through the above process, the data stored in the third latch circuit 230 may be transferred to the first latch circuit 210 . Fig.12 Node SO is shown to initialize a high value indicating "1" by activating signal SA_PRECH_N to a low value at time t3. Between time t4 and time t5, an operation of selectively changing the voltage value of node SO according to the voltage value of node QT to selectively change the voltage value of node QS may be performed.

[0109] Thereafter, from time t5 to time t6, a second bit line setting operation is performed. Specifically, at time t5, signals SA_SENSE, SA_DISCH, and PB_SENSE are activated to a high voltage. Therefore, at time t5, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the first NMOS transistor N1 are turned on.

[0110] In addition, at time t5, the signal SA_CSOC is activated to the first programming enable voltage VREF1. Therefore, the second NMOS transistor N2 of the internal operation circuit 205 is turned on. In addition, through the TPGM data shift operation during the period t2 to t5, the verification result using the second auxiliary verification voltage Vvf1" is stored in the first latch circuit 210. When the threshold voltage of the memory cell is greater than the second auxiliary verification voltage Vvf1", a data bit with a logic value of "0" can be stored in the first latch circuit 210. In this case, because the voltage value of the node QS is a logic-low voltage value, the first PMOS transistor P1 is turned on. Therefore, the voltage of the node CSO can start to increase at time t5. However, because the first programming enable voltage VREF1 is applied to the gate of the second NMOS transistor N2 instead of the power supply voltage VCORE, the voltage of the node CSO can also increase to the first programming enable voltage VREF1. Because the first NMOS transistor N1 is turned on, the bit line voltage also increases to the first programming enable voltage VREF1. As a result, at time t5, the bit line BL connected to the memory cell of group B B The voltage starts to increase to the first programming enable voltage VREF1.

[0111] In addition, at time t5, the signal TRANM_N is activated to the second programming enable voltage VREF2. Therefore, the seventeenth NMOS transistor N17 of the second latch circuit 220 is turned on. As described above, the verification result using the first auxiliary verification voltage Vvf1' is stored in the second latch circuit 220. When the threshold voltage of the memory cell is greater than the first auxiliary verification voltage Vvf1', a data bit with a logic value of "0" can be stored in the second latch circuit 220. In this case, the voltage value of the node QM can be a logic-low voltage value, and the voltage value of the node QM_N can be a logic-high voltage value. Therefore, the eighteenth NMOS transistor N18 is turned on. Therefore, at time t5, the voltage of the node SO can begin to increase. However, because the second programming enable voltage VREF2 is applied to the gate of the seventh NMOS transistor N17 instead of the power supply voltage VCORE, the voltage of the node SO can also increase to the second programming enable voltage VREF2. Because the fourth NMOS transistor N4 and the first NMOS transistor N1 are turned on, the bit line voltage is also increased to the second programming enable voltage VREF2. As a result, at time t5, the bit line BL connected to the memory cells of group C is C The voltage starts to increase to the second programming enable voltage VREF2.

[0112] Through the above process, the bit lines BL connected to the memory cells belonging to the groups A to D can be respectively set. A BL B BL C and BLD In addition, after time t6, in a state in which the corresponding bit line voltage is set, a program pass voltage may be applied to the unselected word line, and a program voltage may be applied to the selected word line. Therefore, the threshold voltages of the memory cells included in the groups A to C may be moved, and the threshold voltages of the memory cells included in the group D may be maintained.

[0113] Specifically, since the bit lines BL connected to the memory cells included in the group D D The voltage of φ is a power supply voltage corresponding to a program inhibition voltage, and thus even if a program voltage is applied to a selected word line, the threshold voltages of the memory cells included in the group D may not increase.

[0114] In addition, the bit lines BL connected to the memory cells included in the group B B The voltage VREF1 is greater than the bit line BL connected to the memory cells included in the group A. A and the bit line BL connected to the memory cells included in the group C C The voltage VREF2 is greater than the bit line BL connected to the memory cells included in the group B. B In addition, the threshold voltage shift width of the memory cells included in group A may be the largest, the threshold voltage shift width of the memory cells included in group B may be smaller than the threshold voltage shift width of the memory cells included in group A, and the threshold voltage shift width of the memory cells included in group C may be smaller than the threshold voltage shift width of the memory cells included in group B.

[0115] Reference Fig.12 In the method of operating a semiconductor memory device shown in FIG. 1 , during a first bit line setting period, a bit line BL connected to a memory cell belonging to a group D is set. D The voltage of is set to the program inhibition voltage, and during the second bit line setting period, the bit line BL connected to the memory cells belonging to the groups B and C is B and BL C The voltages of the bit lines are set simultaneously. In addition, during the second bit line setting period, the first programming enable voltage VREF1 is applied to the gate of the second NMOS transistor N2 in the internal operation circuit 205, and the second programming enable voltage VREF2 is applied to the seventeenth NMOS transistor N17 of the second latch circuit 220. According to the above method, the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 need to set the bit line BL according to the DPGM data (that is, the result data of the verification operation using the first auxiliary verification voltage Vvf1'). CThe number of page buffers may be equal to the number m of bit lines BL1 to BLm connected to the memory block. Therefore, a total of 2m NMOS transistors are required to include the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 for each page buffer. As the number m of bit lines BL1 to BLm connected to one memory block increases, the bit lines BL C The total number of NMOS transistors additionally required to set to the second program enable voltage VREF2 also increases.

[0116] According to a method of operating a semiconductor memory device according to another embodiment of the present disclosure, a bit line BL connected to a memory cell belonging to a group D D , bit lines BL connected to memory cells belonging to group C C and the bit lines BL connected to the memory cells belonging to group B B In addition, according to the method of operating a semiconductor memory device according to another embodiment of the present disclosure, when the bit line BL connected to the memory cell belonging to group B is set B When the voltage of the first programming enable voltage VREF1 is applied to the gate of the bit line connection transistor 201, and when the bit line BL connected to the memory cell belonging to the group C is set C When the voltage of the first programming enable voltage VREF1 is reached, the second programming enable voltage VREF2 greater than the first programming enable voltage VREF1 is applied to the gate of the bit line connection transistor 201. Therefore, without the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 of the second latch circuit 220, the bit line BL C The second program enable voltage VREF2 may be set according to the DPGM data (that is, result data of the verification operation using the first auxiliary verification voltage Vvf1′). Fig.13 The present disclosure is described.

[0117] Fig.13 is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment of the present disclosure. Fig.12 Contents describing similar or overlapping contents are omitted.

[0118] Reference Fig.13 , shows another timing diagram for setting a bit line voltage immediately before a programming voltage is applied to a selected word line during a programming operation of a semiconductor memory device. Fig.13Before time t11 shown in FIG. 1 , data bits indicating verification results using the main verification voltage Vvf1 , the first auxiliary verification voltage Vvf1 ′, and the second auxiliary verification voltage Vvf1 ″ may be stored in the first to third latch circuits 210 , 220 , and 230 of the page buffer 131 .

[0119] From time t11 to time t12, the first bit line setting operation is performed. Because the first bit line setting operation performed during the period t11 to t12 can be performed with the first bit line setting operation performed during the period t11 to t12, the first bit line setting operation can be performed with the first bit line setting operation performed during the period t11 to t12. Fig.12 The first bit line setting operation performed during the period t1 to t2 of the first bit line setting operation is substantially the same, so the overlapping description is omitted. By the first bit line setting operation, at time t11, the bit line BL connected to the memory cell of group D D The voltage of the bit line BL connected to the memory cells of groups A to C begins to increase to the power supply voltage VCORE. A BL B and BL C The voltage of may not increase at time t11 and may be maintained at the ground voltage.

[0120] Thereafter, during the period t12 to t15, the DPGM data is moved. The DPGM data is data indicating whether the threshold voltage of the memory cell is greater than the first auxiliary verification voltage Vvf1', and is data stored in the second latch circuit 220. During the period t12 to t15, the data stored in the second latch circuit 220 is moved to the first latch circuit 210. The method of moving the data stored in the second latch circuit 220 to the first latch circuit 210 can be performed by a method substantially the same as the method of moving the data stored in the third latch circuit 230 to the first latch circuit 210. Because the above reference Fig.12 A method of moving data stored in the third latch circuit 230 to the first latch circuit 210 is described, so an overlapping description is omitted. Fig.13 Node SO is shown to initialize a high value indicating "1" by activating signal SA_PRECH_N to a low value at time t13. Between time t14 and time t15, an operation of selectively changing the voltage value of node SO and thus selectively changing the voltage value of node QS according to the voltage value of node QM may be performed.

[0121] From time t15 to time t16, a second bit line setting operation is performed. During the period t15 to t16, the bit line BL connected to the memory cells of group C is set based on the DPGM data stored in the first latch circuit 210. C voltage.

[0122] Specifically, when the threshold voltage of the memory cell is greater than the first auxiliary verification voltage Vvf1', the DPGM data stored in the first latch circuit 210 may be a data bit having a logic value of "0". In this case, the voltage value of the node QS may be a logic-low voltage value. Therefore, the first PMOS transistor P1 is turned on and the sixth NMOS transistor N6 is turned off. Therefore, the bit line is connected to the power supply voltage through a path including the first PMOS transistor P1, the second PMOS transistor P2, the fourth NMOS transistor N4, and the first NMOS transistor N1. That is, the bit line BL connected to the memory cell of group C C The voltage of starts to increase at time t15. However, because the second program enabling voltage VREF2 is applied to the gate of the bit line connection transistor (that is, the first NMOS transistor N1) instead of the power supply voltage VCORE, the bit line BL C The voltage of can also be increased to the second programming enable voltage VREF2.

[0123] Thereafter, the data stored in the third latch circuit 230 is moved to the first latch circuit 210 through the TPGM data shift operation performed during the period t16 to t19. Fig.12 A method of moving data stored in the third latch circuit 230 to the first latch circuit 210 is described, so an overlapping description is omitted. Fig.13 Node SO is shown to initialize a high value indicating "1" by activating signal SA_PRECH_N to a low value at time t17. Between time t18 and time t19, an operation of selectively changing the voltage value of node SO and thus selectively changing the voltage value of node QS according to the voltage value of node QT may be performed.

[0124] Thereafter, from time t19 to time t20, a third bit line setting operation is performed. During the period t19 to t20, the bit line BL connected to the memory cells of group B is set based on the TPGM data stored in the first latch circuit 210. B voltage.

[0125] Specifically, when the threshold voltage of the memory cell is greater than the second auxiliary verification voltage Vvf1", the TPGM data stored in the first latch circuit 210 may be a data bit having a logic value of "0". In this case, the voltage value of the node QS may be a logic-low voltage value. Therefore, the first PMOS transistor P1 is turned on, and the sixth NMOS transistor N6 is turned off. Therefore, the bit line is connected to the power supply voltage through a path including the first PMOS transistor P1, the second PMOS transistor P2, the fourth NMOS transistor N4, and the first NMOS transistor N1. That is, the bit line BL connected to the memory cell of group BB The voltage of starts to increase at time t19. However, because the first program enable voltage VREF1 is applied to the gate of the bit line connection transistor (that is, the first NMOS transistor N1) instead of the power supply voltage VCORE, the bit line BL B The voltage of can also be increased to the first program enable voltage VREF1.

[0126] Through the above process, the bit lines BL connected to the memory cells belonging to the groups A to D can be respectively set. A BL B BL C and BL D In addition, after time t20, in a state in which the corresponding bit line voltage is set, a program pass voltage may be applied to the unselected word line, and a program voltage may be applied to the selected word line. Therefore, the threshold voltages of the memory cells included in the groups A to C may be moved, and the threshold voltages of the memory cells included in the group D may be maintained.

[0127] As reference Fig.13 As described, according to the method of operating a semiconductor memory device according to another embodiment of the present disclosure, the bit lines BL corresponding to the groups D, C, and B D BL C and BL B The voltage of is sequentially set during three periods. In addition, when the bit lines BL corresponding to groups C and B C and BL B When the voltage of the bit line connection transistor 201 is set, the second program enable voltage VREF2 or the first program enable voltage VREF1 is applied to the gate of the bit line connection transistor 201. Therefore, the semiconductor memory device according to another embodiment of the present disclosure does not need Figure 8 The seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 are shown in FIG. This is because the bit line BL corresponding to the group C C The voltage of is set by applying the second program enable voltage VREF2 to the gate of the bit line connection transistor 201 after moving the DPGM data to the first latch circuit 210 instead of applying the second program enable voltage VREF2 to the gate of the seventeenth NMOS transistor N17 in a state in which the DPGM data is stored in the second latch circuit 220.

[0128] Fig.14 yes Figure 5 Another example circuit diagram of the second latch circuit is shown in FIG.

[0129] As mentioned above, according to Fig.13 In another embodiment of the present disclosure described in the timing diagram shown in FIG. Figure 8 17 NMOS transistor N17 and 18 NMOS transistor N18 are shown in FIG. Therefore, the second latch circuit 220′ may only include the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 connected in series between the node SO and the ground voltage, the latch LM connected between the nodes QM and QM_N, the fourteenth NMOS transistor N14 connected between the node QM and the node COM1, the fifteenth NMOS transistor N15 connected between the node QS_N and the node COM1, and the sixteenth NMOS transistor N16 connected between the node COM1 and the ground voltage. Except that the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 are not included, Fig.14 The second latch circuit 220' shown in FIG. Figure 8 The second latch circuit 220 has the same configuration as shown in FIG.

[0130] Fig.14 The second latch circuit 220′ shown in FIG. Figure 8 17th NMOS transistor N17 and 18th NMOS transistor N18 shown in FIG. ... Fig.14 In the case of the second latch circuit 220' shown, with the use of Figure 8 Compared with the case of the second latch circuit 220 shown in FIG. 1 , the total number of 2m NMOS transistors can be reduced. Therefore, the size of a chip required to manufacture the semiconductor memory device 100 can be reduced. As a result, the manufacturing cost of the semiconductor memory device can be reduced.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application claims the priority of Korean Patent Application No. 10-2023-0076157 filed in the Korean Intellectual Property Office on June 14, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; a plurality of page buffers, the plurality of page buffers being respectively connected to the plurality of memory cells through bit lines; as well as a control logic that controls a program operation of each of the plurality of page buffers, Wherein, each of the plurality of page buffers comprises: a bit line connection transistor connected to a corresponding bit line; an internal operation circuit connected to the bit line connection transistor through a first node; and a plurality of latch circuits connected to the internal operation circuit via a second node, wherein during a programming operation of a selected memory cell among the plurality of memory cells, the control logic: controlling the plurality of page buffers to set a voltage of a bit line connected to a memory cell having a threshold voltage greater than a main verification voltage corresponding to a target program state among the plurality of memory cells to a program inhibition voltage by applying a power supply voltage to a gate of the bit line connection transistor included in each of the plurality of page buffers, controlling the plurality of page buffers to set a voltage of a bit line connected to a memory cell having a threshold voltage greater than a first auxiliary verification voltage corresponding to the target program state and less than the main verification voltage among the plurality of memory cells to the second program permission voltage by applying a second program permission voltage less than the program inhibition voltage to the gate of the bit line connection transistor included in each of the plurality of page buffers, and The multiple page buffers are controlled by applying a first programming enable voltage less than the second programming enable voltage to the gate of the bit line connection transistor included in each of the multiple page buffers to set the voltage of the bit line connected to the memory cell among the multiple memory cells having a threshold voltage greater than the second auxiliary verification voltage corresponding to the target programming state and less than the first auxiliary verification voltage to the second programming enable voltage.

2. The semiconductor memory device according to claim 1, wherein The plurality of latch circuits included in each of the plurality of page buffers include: a first latch circuit storing first verification data indicating whether a threshold voltage of a corresponding memory cell is greater than the main verification voltage; a second latch circuit storing second verification data indicating whether a threshold voltage of the memory cell is greater than the first auxiliary verification voltage; and A third latch circuit stores third verification data indicating whether a threshold voltage of the memory cell is greater than the second auxiliary verification voltage.

3. The semiconductor memory device according to claim 2, wherein: The semiconductor memory device is configured such that: during the period when the control logic applies the power supply voltage to the gate of the bit line connection transistor included in each of the plurality of page buffers, the voltage of the first node is selectively set to the power supply voltage or the ground voltage according to the first verification data stored in the first latch circuit.

4. The semiconductor memory device according to claim 2, wherein: The semiconductor memory device is configured such that: after the voltage of the bit line connected to the memory cell having a threshold voltage greater than the main verification voltage is set to the program inhibition voltage, each of the page buffers moves the second verification data stored in the second latch circuit to the first latch circuit.

5. The semiconductor memory device according to claim 4, wherein: The semiconductor memory device is configured such that: during the period in which the control logic applies the second programming enable voltage to the gate of the bit line connection transistor included in each of the plurality of page buffers, the voltage of the first node is selectively set to a power supply voltage or a ground voltage according to the second verification data stored in the first latch circuit.

6. The semiconductor memory device according to claim 2, wherein: The semiconductor memory device is configured such that: after the voltage of the bit line connected to the memory cell having a threshold voltage greater than the first auxiliary verification voltage and less than the main verification voltage is set to the second programming enable voltage, each of the page buffers moves the third verification data stored in the third latch circuit to the first latch circuit.

7. The semiconductor memory device according to claim 6, wherein: The semiconductor memory device is configured such that: during the period in which the control logic applies the first programming enable voltage to the gate of the bit line connection transistor included in each of the plurality of page buffers, the voltage of the first node is selectively set to a power supply voltage or a ground voltage according to the third verification data stored in the first latch circuit.

8. A semiconductor memory device, comprising: A memory cell, wherein the memory cell stores N bits, where N is a natural number greater than or equal to 2; a page buffer connected to the memory cell via a bit line; as well as a control logic for controlling a programming operation of the page buffer, Wherein, the page buffer comprises: a bit line connection transistor connected to the bit line; an internal operation circuit connected to the bit line connection transistor through a first node; and a plurality of latch circuits connected to the internal operation circuit via a second node, wherein the memory cell is programmed to a first programming state to a second programming state; N -1) a target programming state among the programming states, during the programming operation of the memory cell, the control logic controls the page buffer to perform a verification operation using a main verification voltage, a first auxiliary verification voltage, and a second auxiliary verification voltage corresponding to the target programming state, respectively, and after the verification operation on the memory cell, the control logic controls the page buffer to set the voltage of the bit line according to the threshold voltage of the memory cell by sequentially applying a power supply voltage, a second programming enable voltage, and a first programming enable voltage to the gate of the bit line connection transistor.

9. The semiconductor memory device according to claim 8, wherein: The second program enable voltage is lower than the power supply voltage, and the first program enable voltage is lower than the second program enable voltage.

10. The semiconductor memory device according to claim 9, wherein: The semiconductor memory device is configured so that: when a threshold voltage of the memory cell is greater than the main verification voltage, as the power supply voltage is applied to the gate of the bit line connection transistor, a voltage of the bit line is set to a program inhibition voltage.

11. The semiconductor memory device according to claim 9, wherein: The semiconductor memory device is configured such that: when a threshold voltage of the memory cell is less than the main verification voltage and greater than the first auxiliary verification voltage, as the second programming enable voltage is applied to the gate of the bit line connection transistor, the voltage of the bit line is set to the second programming enable voltage.

12. The semiconductor memory device according to claim 9, wherein: The semiconductor memory device is configured such that: when a threshold voltage of the memory cell is less than the first auxiliary verification voltage and greater than the second auxiliary verification voltage, as the first programming enable voltage is applied to the gate of the bit line connection transistor, the voltage of the bit line is set to the first programming enable voltage.

13. The semiconductor memory device according to claim 9, wherein: When the threshold voltage of the memory cell is less than the second auxiliary verification voltage, the voltage of the bit line is set to a ground voltage.

14. The semiconductor memory device according to claim 8, wherein: The plurality of latch circuits include: a first latch circuit storing first verification data indicating whether a threshold voltage of the memory cell is greater than the main verification voltage; a second latch circuit storing second verification data indicating whether a threshold voltage of the memory cell is greater than the first auxiliary verification voltage; and A third latch circuit stores third verification data indicating whether a threshold voltage of the memory cell is greater than the second auxiliary verification voltage.

15. The semiconductor memory device according to claim 14, wherein: The control logic controls the page buffer to move the second verification data stored in the second latch circuit to the first latch circuit after the power supply voltage is applied to the gate of the bit line connection transistor and before the second program enable voltage is applied to the gate of the bit line connection transistor.

16. The semiconductor memory device according to claim 14, wherein: The control logic controls the page buffer to move the third verification data stored in the third latch circuit to the first latch circuit after the second program enable voltage is applied to the gate of the bit line connection transistor and before the first program enable voltage is applied to the gate of the bit line connection transistor.

17. The semiconductor memory device according to claim 14, wherein: The bit line connection transistor is a first NMOS transistor, and The internal operating circuit comprises: a second NMOS transistor connected between the first node and a third node; a third NMOS transistor connected between the power supply voltage and the third node; a fourth NMOS transistor connected between the first node and the second node; a fifth NMOS transistor and a sixth NMOS transistor, wherein the fifth NMOS transistor and the sixth NMOS transistor are connected in series between the second node and a ground voltage; a first PMOS transistor connected between the power supply voltage and the third node; and A second PMOS transistor is connected between the second node and the third node.

18. The semiconductor memory device according to claim 17, wherein: The first latch circuit comprises: a first latch connected between a fourth node having a logic-inverted voltage value and a fifth node; a seventh NMOS transistor, the seventh NMOS transistor being connected between the fourth node and the sixth node; an eighth NMOS transistor connected between the fifth node and the sixth node; a ninth NMOS transistor connected between the sixth node and the ground voltage; and a tenth NMOS transistor and an eleventh NMOS transistor, wherein the tenth NMOS transistor and the eleventh NMOS transistor are connected in series between the second node and the ground voltage, wherein each of the gate of the first PMOS transistor and the gate of the sixth NMOS transistor is connected to the fourth node, and Wherein, the gate of the eleventh NMOS transistor is connected to the fifth node.

19. The semiconductor memory device according to claim 18, wherein: The second latch circuit comprises: a second latch connected between a seventh node having a logic-inverted voltage value and an eighth node; a twelfth NMOS transistor and a thirteenth NMOS transistor, wherein the twelfth NMOS transistor and the thirteenth NMOS transistor are connected in series between the second node and the ground voltage; a fourteenth NMOS transistor, the fourteenth NMOS transistor being connected between the seventh node and the sixth node; a fifteenth NMOS transistor connected between the eighth node and the sixth node; and a sixteenth NMOS transistor, the sixteenth NMOS transistor being connected between the sixth node and the ground voltage, wherein the gate of the thirteenth NMOS transistor is connected to the seventh node, and Wherein, the gate of the sixteenth NMOS transistor is connected to the second node.

20. The semiconductor memory device according to claim 19, wherein The third latch circuit comprises: a third latch connected between a ninth node and a tenth node having a logic-inverted voltage value; a seventeenth NMOS transistor and an eighteenth NMOS transistor, wherein the seventeenth NMOS transistor and the eighteenth NMOS transistor are connected in series between the second node and the ground voltage; a nineteenth NMOS transistor, the nineteenth NMOS transistor being connected between the ninth node and the eleventh node; a twentieth NMOS transistor connected between the tenth node and the eleventh node; and a twenty-first NMOS transistor, the twenty-first NMOS transistor being connected between the eleventh node and the ground voltage, wherein the gate of the eighteenth NMOS transistor is connected to the ninth node, and Wherein, a gate of the twenty-first NMOS transistor is connected to the second node.

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