Polycrystalline silicon back etching method
By forming shallow trench isolation and polysilicon layers in the Hipower platform and using photolithography technology to form grooves in overlapping areas, the problem of polysilicon columns or silicon deep pits in polysilicon back etching is solved, and the polysilicon columns or silicon deep pits is achieved is achieved to avoid polysilicon columns or silicon deep The effect of pit.
Patent Information
- Application Number
- CN202411204663.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-17
AI Technical Summary
In Hipower platform, due to the existence of BCD and SGT regions, polysilicon back-etching requires two separate etchings, resulting in the overlapping position of polysilicon columns or silicon pits.
By forming shallow trench isolation with a width X on the substrate and forming a polysilicon layer on the gate dielectric layer, the polysilicon layer is retained in the first device region using photolithography and extending over the shallow trench isolation. Then, grooves of Y width are formed on the gate polysilicon layer and the shallow trench isolation to avoid the occurrence of polysilicon columns or silicon pits.
The polysilicon column or silicon pit in the overlapping area of the polysilicon back-etching of the two device areas is effectively avoided, and the window for lithography engraving is improved.
Smart Images
Figure CN119153329A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a polysilicon etching back method. Background Art
[0002] The Hipower platform has both BCD (bipolar-CMOS-DMOS device) and SGT (shallow trench gate device) areas, which means that polysilicon back etching needs to be done twice. After the two etchings, the polysilicon in all surface areas needs to be removed. In order to increase the window for photolithography, the two areas will overlap to a certain extent. Generally, there are two situations:
[0003] 1. The overlapped position of the two areas is not etched twice - there is always a 8k angstrom polysilicon column retained at the junction;
[0004] 2. The overlapping positions of the two areas are etched twice - the second etching results in a Si deep pit of about 1um at the junction.
[0005] In order to solve the above problems, a new polysilicon etching back method needs to be proposed. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for polysilicon back etching, which is used to solve the problem of polysilicon columns or silicon deep pits existing at the overlapping positions of two areas in the prior art during two polysilicon back etchings.
[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for etching back polysilicon, comprising:
[0008] Step 1, providing a substrate, the substrate comprising adjacent first and second device regions, forming a shallow trench isolation with a width of X at the junction of the first and second device regions, forming a trench gate structure on the second device region, forming a gate dielectric layer on the substrate, and forming a gate polysilicon layer on the gate dielectric layer;
[0009] Step 2: patterning the gate polysilicon layer by photolithography and first polysilicon etch-back, so that the gate polysilicon layer remains on the first device region, and one end portion of the remaining gate polysilicon layer extends to above the shallow trench isolation;
[0010] Step 3, forming a photoresist layer covering the gate dielectric layer and the gate polysilicon layer, and patterning the photoresist layer by photolithography, wherein the photoresist layer after photolithography is retained on the second device region, and one end portion of the photoresist layer extends to above the shallow trench isolation, so that the distance between the gate polysilicon layer and the photoresist layer is Y, and Y<X;
[0011] Step 4: utilizing etching with a high selectivity ratio of the gate polysilicon layer relative to the gate dielectric layer and the shallow trench isolation to remove the gate polysilicon layer, and forming a groove with a width of Y on the gate dielectric layer and the shallow trench isolation.
[0012] Preferably, in step 1, the first device region is a BCD device region, and the second device region is a SGT device region.
[0013] Preferably, the material of the gate dielectric layer in step 1 is silicon dioxide.
[0014] Preferably, the material of the shallow trench isolation in step 1 is silicon dioxide.
[0015] Preferably, the first polysilicon etching back method in step 2 is dry etching.
[0016] Preferably, in step 2, a first mask is used to define a reserved area of the gate polysilicon layer.
[0017] Preferably, the etching method in step 4 is dry etching.
[0018] Preferably, in step 4, a second mask is used to define a reserved area of the photoresist, a width of an overlapping area between the first and second masks is Y, and the overlapping area is located in an area of the shallow trench isolation.
[0019] Preferably, in step 2, the distance from one end portion of the remaining gate polysilicon layer extending to the shallow trench isolation is (XY) / 2; in step 4, the distance from one end portion of the photoresist layer extending to the shallow trench isolation is (XY) / 2.
[0020] Preferably, in step 4, after removing the gate polysilicon layer, if the photoresist layer remains, the remaining photoresist layer needs to be removed.
[0021] As described above, the polysilicon etching back method of the present invention has the following beneficial effects:
[0022] The present invention can avoid the polysilicon pillars or silicon deep pits that may appear in the overlapping areas of the polysilicon back etching of two device regions. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0024] Figure 2 Shown are schematic diagrams of the first and second photomasks of the present invention;
[0025] Figure 3 It is a schematic diagram showing the back etching area of the polysilicon layer defined by photolithography according to the present invention;
[0026] Figure 4 Shown is a schematic diagram of the first polysilicon etch back of the present invention;
[0027] Figure 5 It is a schematic diagram of forming a photoresist layer according to the present invention;
[0028] Figure 6 It is a schematic diagram of the second polysilicon etch back of the present invention. DETAILED DESCRIPTION
[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0030] See also Figure 1 The present invention provides a method for polysilicon back etching, comprising:
[0031] Step 1, providing a substrate 101, the substrate 101 includes adjacent first and second device areas (A1, A2), forming a shallow trench isolation 105 with a width of X at the junction of the first and second device areas (A1, A2), forming a trench gate structure on the second device area A2, forming a gate dielectric layer 102 on the substrate 101, and forming a gate polysilicon layer 103 on the gate dielectric layer 102;
[0032] In some embodiments, the first device region A1 in step 1 is a BCD device region, and the second device region A2 is a SGT device region. It should be noted that the first and second device regions (A1, A2) may also be other well-known device regions.
[0033] In some embodiments, the material of the gate dielectric layer 102 in step 1 is silicon dioxide.
[0034] In some embodiments, the material of the shallow trench isolation 105 in step 1 is silicon dioxide.
[0035] Step 2: Use photolithography and the first polysilicon etch back method to pattern the gate polysilicon layer 103 so that it remains on the first device area A1, and one end of the remaining gate polysilicon layer 103 extends to the top of the shallow trench isolation 105, forming a Figure 4 Specifically, a photoresist layer 104 is formed on the gate polysilicon layer 103, and then the photoresist layer 104 is patterned by photolithography. After the gate polysilicon layer 103 is patterned by etching back, the photoresist layer 104 can be removed by ashing and wet cleaning methods;
[0036] In some embodiments, the first polysilicon etch back in step 2 is performed by dry etching.
[0037] In some embodiments, in step 2, a first mask is used to define a reserved region of the gate polysilicon layer 103 .
[0038] Step 3: forming a photoresist layer 106 covering the gate dielectric layer 102 and the gate polysilicon layer 103, and patterning the photoresist layer 106 by photolithography. The photoresist layer 106 after photolithography is retained on the second device area A2, and one end of the photoresist layer 106 extends to the top of the shallow trench isolation 105, so that the distance between the gate polysilicon layer 103 and the photoresist layer 106 is Y, Y<X, forming Figure 5 The structure shown;
[0039] Step 4: Remove the gate polysilicon layer 103 by etching with a high selectivity ratio relative to the gate dielectric layer 102 and the shallow trench isolation 105, and form a groove with a width of Y on the gate dielectric layer 102 and the shallow trench isolation 105, so as to form a Figure 6 The structure shown.
[0040] In some embodiments, the etching method in step 4 is dry etching.
[0041] In some embodiments, see Figure 2 In step 4, a second mask is used to define a reserved area of the photoresist. The width of the overlapping area of the first and second masks is Y, and the overlapping area is located in the shallow trench isolation 105 area.
[0042] In some embodiments, the distance from one end of the remaining gate polysilicon layer 103 extending to the shallow trench isolation 105 in step 2 is (XY) / 2; the distance from one end of the photoresist layer 106 extending to the shallow trench isolation 105 in step 4 is (XY) / 2. It should be noted that the distance can also be appropriately adjusted according to the actual process.
[0043] In some embodiments, after the gate polysilicon layer 103 is removed in step 4, if a photoresist layer 106 remains, the remaining photoresist layer 106 needs to be removed.
[0044] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0045] In summary, the present invention can avoid the polysilicon pillars or silicon pits that may appear in the overlapping areas of the polysilicon back etching of the two device regions. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.
[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for etching back polysilicon, characterized in that: At least: Step 1, providing a substrate, the substrate comprising adjacent first and second device regions, forming a shallow trench isolation with a width of X at the junction of the first and second device regions, forming a trench gate structure on the second device region, forming a gate dielectric layer on the substrate, and forming a gate polysilicon layer on the gate dielectric layer; Step 2: patterning the gate polysilicon layer by photolithography and first polysilicon etch-back, so that the gate polysilicon layer remains on the first device region, and one end portion of the remaining gate polysilicon layer extends to above the shallow trench isolation; Step 3, forming a photoresist layer covering the gate dielectric layer and the gate polysilicon layer, and patterning the photoresist layer by photolithography, wherein the photoresist layer after photolithography is retained on the second device region, and one end portion of the photoresist layer extends to above the shallow trench isolation, so that the distance between the gate polysilicon layer and the photoresist layer is Y, and Y<X; Step 4: utilizing etching with a high selectivity ratio of the gate polysilicon layer relative to the gate dielectric layer and the shallow trench isolation to remove the gate polysilicon layer, and forming a groove with a width of Y on the gate dielectric layer and the shallow trench isolation.
2. The polysilicon etching back method according to claim 1, characterized in that: In step 1, the first device area is a BCD device area, and the second device area is a SGT device area.
3. The polysilicon etching back method according to claim 1, characterized in that: The material of the gate dielectric layer in step 1 is silicon dioxide.
4. The polysilicon etching back method according to claim 1, characterized in that: The material of the shallow trench isolation in step 1 is silicon dioxide.
5. The polysilicon etching back method according to claim 1, characterized in that: The first polysilicon etching back method in step 2 is dry etching.
6. The polysilicon etching back method according to claim 1, characterized in that: In step 2, a first photomask is used to define a reserved area of the gate polysilicon layer.
7. The polysilicon etching back method according to claim 1, characterized in that: The etching method in step 4 is dry etching.
8. The polysilicon etching back method according to claim 6, characterized in that: In step 4, a second mask is used to define a reserved area of the photoresist, the width of the overlapping area of the first and second masks is Y, and the overlapping area is located in the shallow trench isolation area.
9. The polysilicon etching back method according to claim 1, characterized in that: In step 2, the distance from one end of the remaining gate polysilicon layer to the shallow trench isolation is (XY) / 2; in step 4, the distance from one end of the photoresist layer to the shallow trench isolation is (XY) / 2.
10. The polysilicon etching back method according to claim 1, characterized in that: In step 4, after removing the gate polysilicon layer, if the photoresist layer remains, the remaining photoresist layer needs to be removed.