Integrated chip and forming method thereof

Abstract

Various embodiments of the present disclosure are directed to an integrated chip including a thin film resistor (TFR) layer overlying a semiconductor substrate. The first conductive structure is disposed on an outer region of the TFR layer. The first conductive structure includes a lateral portion adjacent to a vertical portion. The vertical portion is higher than the transverse portion. A cover structure is disposed on the intermediate region of the TFR layer and adjoins the vertical portion of the first conductive structure. The embodiment of the invention also relates to an integrated chip and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated chip and a method for forming the same. Background Art

[0002] Modern integrated chips use a wide range of devices to achieve varying functions. Typically, integrated chips include active devices and passive devices. Active devices include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), while passive devices include inductors, capacitors, and resistors. Resistors are widely used in many applications, such as resistor-capacitor (RC) circuits, power drivers, power amplifiers, radio frequency (RF) applications, etc. Summary of the invention

[0003] Some embodiments of the present application provide an integrated chip, comprising: a thin film resistor (TFR) layer located on a semiconductor substrate; a first conductive structure arranged on an outer area of ​​the thin film resistor layer, wherein the first conductive structure includes a lateral portion adjacent to a vertical portion, wherein a height of the vertical portion is greater than a height of the lateral portion; and a covering structure arranged on a middle area of ​​the thin film resistor layer and adjacent to the vertical portion of the first conductive structure.

[0004] Other embodiments of the present application provide an integrated chip, comprising: a first dielectric layer, located on a semiconductor substrate; a resistor structure, located on the first dielectric layer, wherein the resistor structure includes a thin film resistor (TFR) layer and a pair of conductive structures, wherein the thin film resistor layer includes an intermediate region extending between a pair of external regions, wherein the conductive structure is located on the external regions; a second dielectric layer, located on the thin film resistor layer and extending around the thin film resistor layer; and a covering structure, disposed on the intermediate region of the thin film resistor layer and extending between the conductive structures, wherein a lower surface of the second dielectric layer is vertically spaced apart from the thin film resistor layer by the covering structure.

[0005] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a thin film resistor (TFR) layer over a semiconductor substrate; forming a covering structure over a middle region of the thin film resistor layer; depositing a conductive layer and an etch stop layer over the thin film resistor layer and the covering structure; and performing a first patterning process on the conductive layer and the etch stop layer to define a pair of conductive structures on an outer region of the thin film resistor layer, wherein, during the first patterning process, the covering structure is disposed on the thin film resistor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip including a resistor structure including a capping structure overlying a thin film resistor (TFR) layer are shown.

[0008] Figure 2 Cross-sectional views of some embodiments of an integrated chip having a resistor structure disposed within an interconnect structure are shown.

[0009] Figure 3 A top view of some embodiments of the resistor structure taken along line AA' is shown.

[0010] FIG. 4A to FIG. 4D Shows Figure 2 Cross-sectional views of some other embodiments of integrated chips.

[0011] FIG. 5A to FIG. 5B to FIG. 13A to FIG. 13B Various views of some embodiments of methods for forming an integrated chip having a resistor structure including a capping structure located above a TFR layer are shown.

[0012] Fig.14 A flow chart illustrating some embodiments of a method for forming an integrated chip having a resistor structure including a capping structure located above a TFR layer. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for realizing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Some integrated chips have passive devices arranged above / inside the semiconductor substrate. The passive devices may include, for example, inductors, resistors, capacitors, diodes, etc. One type of resistor used in an integrated chip is a thin film resistor (TFR) arranged above the semiconductor substrate. The TFR includes a TFR layer (e.g., a resistor layer) and a conductive structure pair. The TFR layer includes an intermediate region extending continuously between the outer region pairs. The conductive structure is located directly above the corresponding outer region of the TFR layer, wherein the intermediate region of the TFR layer extends continuously between the conductive structures. The resistance of the TFR layer is based on the material and thickness of the TFR layer.

[0016] A method for forming a plurality of TFRs above a semiconductor substrate (e.g., a semiconductor wafer) includes depositing a TFR film on a lower dielectric layer located above the semiconductor substrate. A conductive layer is deposited on the TFR film. A first dry etch is performed on the TFR film and the conductive layer to define a plurality of TFR layers for corresponding TFRs above the semiconductor substrate. Each TFR layer includes an intermediate region extending continuously between a pair of outer regions. A second dry etch is performed on the conductive layer to reduce the thickness of the conductive layer above each intermediate region of the TFR layer. Subsequently, a wet etching process is performed on the conductive layer to remove a portion of the conductive layer from above each intermediate region of the TFR layer. This forms a conductive structure pair above the outer region of each TFR layer. During the wet etching process, the semiconductor substrate is immersed in and / or exposed to a wet etchant (e.g., hydrogen peroxide) for removing a portion of the conductive layer. The wet etchant contacts a portion of the TFR layer (e.g., the intermediate region of each TFR layer) and damages the portion of the TFR layer and / or reduces the thickness of the portion of the TFR layer. This may result in each of the TFR layers having a higher total thickness variation (TTV) and / or a non-uniform thickness, thereby reducing the performance or reliability of the TFR (e.g., due to damage to the TFR layer by the wet etchant). For example, the non-uniform thickness may cause sheet resistance variations across different regions of the TFR layer (e.g., along a middle region of the TFR layer), thereby reducing the overall performance of the TFR and / or causing the TFR to fail to meet design specifications (e.g., the TFR has a resistance that does not fall within the design specifications).

[0017] In addition, due to the method of applying the wet etchant and the etching rate of the TFR layer during the wet etching process, the wet etchant does not uniformly reduce the thickness of the TFR layer across the semiconductor substrate. Therefore, the first thickness of the TFR layer in the central region of the semiconductor substrate is substantially different from the second thickness of the TFR layer in the peripheral region of the semiconductor substrate. This produces a TFR with a relatively high resistance variation across the semiconductor substrate. The resistance variation of the TFR reduces the performance of the integrated chip and / or may result in failure to pass the wafer acceptance test (WAT), thereby reducing the device yield.

[0018] Therefore, the present disclosure is directed to an integrated chip including a resistor structure having a TFR layer and a corresponding manufacturing method configured to reduce the thickness variation of the TFR layer. The TFR layer is located on a semiconductor substrate including an intermediate region extending continuously between a pair of outer regions. The conductive structure pair is located on the outer region pair of the TFR layer. The covering structure is located above the intermediate region of the TFR layer and extends continuously between the conductive structure pair. During the manufacture of the resistor structure, the covering structure is arranged on the TFR layer, and a wet etching process is performed on the conductive layer to form and / or define the conductive structure. The covering structure is configured to protect the TFR layer from the influence of a wet etchant (e.g., hydrogen peroxide) used during the wet etching process. Therefore, the removal of the TFR layer during wet etching and / or damage to the TFR layer is minimized, so that the TFR layer has a uniform thickness, reduced TTV and increased reliability. In addition, this alleviates the non-uniform removal of the TFR layer across the semiconductor substrate, thereby increasing the uniformity of the resistance of the resistor structure across the semiconductor substrate. Therefore, the overall performance and device yield of the integrated chip are improved.

[0019] Figure 1 A cross-sectional view 100 of some embodiments of an integrated chip including a resistor structure 104 including a capping structure 112 located above a thin film resistor (TFR) layer 106 is shown.

[0020] The integrated chip includes a dielectric structure 118 located above a semiconductor substrate 102. A resistor structure 104 is disposed within the dielectric structure 118. A plurality of conductive vias 120 are disposed within the dielectric structure 118 and located above the resistor structure 104. The conductive vias 120 are electrically coupled to the resistor structure 104.

[0021] The resistor structure 104 includes a TFR layer 106, a pair of conductive structures 108 disposed on the TFR layer 106, and a capping structure 112 on the TFR layer 106. In some embodiments, the capping structure 112 and the conductive structure 108 directly contact the top surface of the TFR layer 106. The etch stop layer 110 is located above the conductive structure 108. The TFR layer 106 may be, for example, or include silicon chromium, nickel chromium, etc. However, other materials for the TFR layer 106 are also feasible. The conductive structure 108 is configured to electrically couple the TFR layer 106 to a plurality of conductive vias 120. The resistor structure 104 is configured to resist (e.g., reduce) the flow of current between the conductive structures 108. The resistance of the resistor structure 104 is based at least in part on the material and thickness of the TFR layer 106. In some embodiments, the resistor structure 104 may be, for example, used in a resistor-capacitor (RC) circuit, a power driver, a power amplifier, an RF application, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), other suitable electronic devices, or any combination of the foregoing.

[0022] The TFR layer 106 includes a middle region 106m extending continuously between the pair of outer regions 106o1, 106o2. The conductive structure 108 is directly located above the outer regions 106o1, 106o2 of the TFR layer 106. The cover structure 112 is directly located above the middle region 106m of the TFR layer 106 and extends continuously laterally between the pair of conductive structures 108. In some embodiments, the cover structure 112 directly contacts the conductive structure 108. The conductive structures 108 respectively include a first portion 108p1 adjacent to a second portion 108p2, wherein the height of the first portion 108p1 is less than the height of the second portion 108p2. In various embodiments, the cover structure 112 includes a first cover layer 114 disposed on the TFR layer 106 and a second cover layer 116 located above the first cover layer 114.

[0023] Because the capping structure 112 is directly located above the middle region 106m of the TFR layer 106, the thickness of the TFR layer 106 can be maintained during the manufacture of the resistor structure 104 and / or the total thickness variation (TTV) of the TFR layer 106 can be reduced. For example, during the manufacture of the resistor structure 104, the capping structure 112 is disposed on the TFR layer 106 while an etching process (e.g., a wet etching process) is performed on the conductive layer to form and / or define the conductive structure 108. The capping structure 112 is configured to protect the TFR layer 106 from the etchant (e.g., hydrogen peroxide) utilized during the etching process. Therefore, the removal of the TFR layer 106 during the etching process is prevented and / or mitigated, so that the thickness of the TFR layer 106 is maintained during and / or after the etching process. This reduces the TTV of the TFR layer 106 and facilitates the resistor structure 104 to have a predetermined resistance that meets the design specifications. Furthermore, the capping structure 112 prevents damage to the TFR layer 106 during the etching process, thereby increasing the reliability of the TFR layer 106 .

[0024] Furthermore, the presence of other capping structures (not shown) over other TFR layers (not shown) across the semiconductor substrate 102 mitigates the non-uniform reduction in thickness of other TFR layers across the semiconductor substrate 102 during the etching process. Thus, the uniformity of the resistance of the resistor structure across the semiconductor substrate 102 is increased. This mitigates the chance that the integrated chip may fail to pass the WAT and increases device yield.

[0025] Figure 2 A cross-sectional view 200 of some embodiments of an integrated chip including a resistor structure 104 disposed within an interconnect structure 202 is shown. In some embodiments, the resistor structure 104 is configured as follows: Figure 1 As shown and / or described in.

[0026] The interconnect structure 202 is located on the semiconductor substrate 102. The semiconductor substrate 102 may be, for example, or include silicon, germanium, silicon germanium, a bulk silicon substrate, one or more epitaxial layers, a silicon-on-insulator (SOI) substrate, or another suitable substrate material. The interconnect structure 202 includes a plurality of conductive vias 120 and a plurality of conductive lines 218 disposed within a dielectric structure. The dielectric structure includes a plurality of dielectric layers 214 and a plurality of dielectric cap layers 216. The plurality of conductive vias 120 and the plurality of conductive lines 218 are configured to electrically couple devices disposed within and / or above the semiconductor substrate 102 to each other. The plurality of dielectric layers 214 include a first dielectric layer 214a and a second dielectric layer 214b disposed above the first dielectric layer 214a.

[0027] The plurality of dielectric layers 214 may be, for example, or include silicon dioxide, a low-k dielectric material such as undoped quartz glass, carbon-doped silicon dioxide, some other suitable dielectric material, or any combination of the foregoing materials. The plurality of dielectric cap layers 216 may be, for example, or include silicon carbide, silicon nitride, etc. The conductive vias 120 and the conductive lines 218 may be, for example, or include copper, aluminum, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination of the foregoing materials.

[0028] A plurality of semiconductor devices 204 are disposed within and / or on the semiconductor substrate 102. In some embodiments, the semiconductor devices 204 are configured as transistors. In such embodiments, the semiconductor devices 204 each include a source / drain region 206, a gate dielectric layer 208, a gate electrode 210, and a sidewall spacer structure 212. The gate electrode 210 is located above the gate dielectric layer 208, and the source / drain region 206 is disposed within the semiconductor substrate 102 on the opposite side of the gate electrode 210. The source / drain region may refer to a source or a drain, individually or collectively depending on the context.

[0029] The resistor structure 104 is disposed above the first dielectric layer 214a. The resistor structure 104 includes a TFR layer 106, a pair of conductive structures 108 disposed on opposite sides of the TFR layer 106, and a cover structure 112 on the TFR layer 106 between the pairs of conductive structures 108. The first dielectric layer 214a includes a top surface 214ts disposed above the upper surface 214us. In some embodiments, the bottom surface of the TFR layer 106 directly contacts the top surface 214ts of the first dielectric layer 214a, and the outer sidewalls of the TFR layer 106 are aligned with the opposite sidewalls of the first dielectric layer 214a. The cover structure 112 is located above the middle region 106m of the TFR layer 106 and directly contacts the middle region 106m of the TFR layer 106. The conductive structure 108 is located above the outer regions 106o1, 106o2 of the TFR layer 106 and directly contacts the outer regions 106o1, 106o2 of the TFR layer 106. In some embodiments, the thickness 220 of the TFR layer 106 is in the range of about 40 to 70 angstroms or some other suitable value. The conductive structure 108 may be, for example, or include titanium nitride, tantalum nitride, titanium, tantalum, some other conductive material, or any combination of the foregoing materials. In some embodiments, the thickness of the conductive structure 108 may be, for example, in the range of about 500 to 1000 angstroms.

[0030] The conductive structures 108 include first portions 108p1 adjacent to the second portions 108p2, respectively. In some embodiments, the height of the first portions 108p1 is less than the height of the second portions 108p2. The covering structure 112 extends continuously between the second portions 108p2 of the first conductive structure in the conductive structure 108 and the second portions 108p2 of the second conductive structure in the conductive structure 108. In various embodiments, the first portion 108p1 includes a curved sidewall, and the second portion 108p2 includes a sidewall having a curved section 226 above the straight section 224. In some embodiments, the height of the curved section 226 is greater than the height of the straight section 224. In further embodiments, the height of the straight section 224 is equal to the height of the covering structure 112. In yet further embodiments, the height of the curved section 226 is equal to or greater than the height of the curved sidewall of the first portion 108p1. In addition, the length of the first portion 108p1 is greater than the length of the second portion 108p2. In a further embodiment, the height of the conductive structures 108 discretely increases from the corresponding outer sidewalls of the TFR layer 106 in a direction toward the middle region 106 m .

[0031] An etch stop layer 110 is disposed above the conductive structure 108. In some embodiments, the etch stop layer 110 extends continuously from the top surface of the first portion 108p1 along the sidewall of the second portion 108p2 to the top surface of the second portion 108p2. The etch stop layer 110 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, etc. In some embodiments, the thickness of the etch stop layer 110 is in the range of about 300 to 500 angstroms or some other suitable value. In further embodiments, the thickness of the etch stop layer 110 is less than the thickness of the conductive structure 108.

[0032] The covering structure 112 is directly located above the middle region 106m of the TFR layer 106. In some embodiments, the covering structure 112 includes a first covering layer 114 on the TFR layer 106 and a second covering layer 116 on the first covering layer 114. In various embodiments, the outer sidewall of the first covering layer 114 is aligned with the outer sidewall of the second covering layer 116. The covering structure 112 is configured to prevent damage to the TFR layer 106 during the manufacture of the resistor structure 104. For example, the covering structure 112 is formed before the conductive structure 108 and is configured to protect the TFR layer 106 during the etching process for forming and / or defining the conductive structure 108. Therefore, damage and / or non-uniform removal of a portion (e.g., the middle region 106m) of the TFR layer 106 during manufacture is reduced. This partially reduces the TTV of the TFR layer 106 and / or reduces damage to the TFR layer 106 (e.g., delamination), thereby improving the reliability and overall performance of the resistor structure 104. In addition, since other capping structures (not shown) are disposed over other TFR layers (not shown) across the semiconductor substrate 102, non-uniform reduction of other TFR layers during manufacturing is reduced. Therefore, the uniformity of the resistance of the resistor structure across the semiconductor substrate 102 is increased, thereby increasing the device yield of the integrated chip.

[0033] The first capping layer 114 may be, for example, or include an oxide such as silicon dioxide or some other suitable dielectric material. In various embodiments, the thickness of the first capping layer 114 is in the range of about 100 to 200 angstroms or some other suitable value. The second capping layer 116 may be, for example, or include silicon nitride, silicon carbide, some other suitable dielectric material, or any combination of the foregoing materials. In various embodiments, the thickness of the second capping layer 116 is in the range of about 100 to 200 angstroms or some other suitable value. In some embodiments, the thickness of the first capping layer 114 is equal to the thickness of the second capping layer 116. In further embodiments, the thickness of the first capping layer 114 and the second capping layer 116 are respectively greater than the thickness of the TFR layer 106. In yet further embodiments, the capping structure 112 directly contacts the entire top surface of the middle region 106m of the TFR layer 106. In various embodiments, the lower surface 222 of the second dielectric layer 214b is vertically spaced apart from the top surface of the TFR layer 106 by the capping structure 112.

[0034] Figure 3 Shows Figure 2 The cross-sectional view 200 is a top view 300 of some embodiments taken along line AA′.

[0035] like Figure 3As shown in FIG. 3 , the width 302 of the middle region 106m of the TFR layer 106 is smaller than the width 304 of the outer regions 106o1, 106o2 of the TFR layer 106. Figure 2 The width of the conductive structure 108 is equal to the width 304 of the outer regions 106o1, 106o2.

[0036] Figure 4A Shows the corresponding Figure 2 In some embodiments of the integrated chip, the sidewalls of the first portion 108p1 and the second portion 108p2 are straight. In some embodiments, independent sidewalls of each of the opposite sidewalls of the conductive structure 108 are aligned with the corresponding outer sidewalls of the TFR layer 106.

[0037] Figure 4B Shows the corresponding Figure 4A Other embodiments of the integrated chip of the cross-sectional view 400b of some embodiments of the integrated chip, in which the second cover layer ( Figure 4A In some embodiments, the cover structure 112 includes a single dielectric layer (eg, Figure 4A The first covering layer 114).

[0038] Figure 4C Shows the corresponding Figure 4A Other embodiments of the integrated chip of the cross-sectional view 400c of some embodiments of the integrated chip, in which the second cover layer ( Figure 4A 116), and the second portion 108p2 of the conductive structure 108 includes a sidewall having a curved segment 226 above the straight segment 224. In some embodiments, the capping structure 112 includes a single dielectric layer (e.g., Figure 4A In some embodiments, the height of the straight segment 224 is equal to the height of the covering structure 112.

[0039] Figure 4D Shows the corresponding Figure 4A 400d of some embodiments of the integrated chip of other embodiments of the integrated chip, wherein the plurality of conductive vias 120 and the plurality of conductive wires 218 respectively include a conductor 404 and a diffusion barrier layer 402. The diffusion barrier layer 402 wraps around the conductor 404 and is disposed along the lower surface of the conductor 404. The conductor 404 may be, for example, or include copper, aluminum, tungsten, or any combination of the foregoing materials. The diffusion barrier layer 402 may be, for example, or include titanium, tantalum, titanium nitride, tantalum nitride, or any combination of the foregoing materials. In some embodiments, the diffusion barrier layer 402 and the conductive structure 108 include a first material (e.g., titanium nitride, tantalum nitride, etc.).

[0040] FIG. 5A to FIG. 5B to FIG. 13A to FIG. 13B Various views of some embodiments of a method for forming an integrated chip having a resistor structure including a capping structure located above a TFR layer are shown. The figures with an "A" suffix show cross-sectional views of the integrated chip during various formation processes. The figures with a "B" suffix show corresponding top views taken along line AA' of the figures with an "A" suffix. Although the method of forming an integrated chip is described with reference to FIG. 5A to FIG. 5B to FIG. 13A to FIG. 13B The various views shown in FIG. 1 , however, it should be understood that FIG. 5A to FIG. 5B to FIG. 13A to FIG. 13B The structure shown in is not limited to the formation method but can exist independently of the method.

[0041] like Figure 5A and Figure 5B As shown in the cross-sectional view 500a and the top view 500b of , a semiconductor substrate 102 is provided, and a dielectric protection layer 216, a first dielectric layer 214a, a TFR film 502, a first capping layer 114 and a second capping layer 116 are formed over the semiconductor substrate 102. The semiconductor substrate 102 may be, for example, or include silicon, germanium, silicon germanium, epitaxial silicon, a silicon-on-insulator (SOI) substrate, some other suitable semiconductor material, etc. The dielectric protection layer 216, the first dielectric layer 214a, the TFR film 502, the first capping layer 114 and the second capping layer 116 may be formed over the semiconductor substrate 102 by corresponding deposition processes, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or some other suitable growth or deposition process. In some embodiments, the TFR film 502, the first capping layer 114 and the second capping layer 116 are formed by separate CVD processes, respectively.

[0042] The TFR film 502 may be, for example, or include silicon chromium, nickel chromium, or the like. In some embodiments, the TFR film 502 is formed to a thickness in the range of about 40 to 70 angstroms or some other suitable value. The first capping layer 114 may be, for example, or include an oxide such as silicon dioxide or some other suitable dielectric material. In various embodiments, the first capping layer 114 is formed to a thickness in the range of about 100 to 200 angstroms or some other suitable value. The second capping layer 116 may be, for example, or include silicon nitride, silicon carbide, some other suitable dielectric material, or any combination of the foregoing materials. In some embodiments, the second capping layer 116 is formed to a thickness in the range of about 100 to 200 angstroms or some other suitable value.

[0043] like Fig. 6A and Figure 6BAs shown in the cross-sectional view 600a and the top view 600b, the first dielectric layer 214a, the TFR film ( Figure 5A 502), the first capping layer 114 and the second capping layer 116 are subjected to a first patterning process to define and / or form the TFR layer 106. The TFR layer 106 includes an intermediate region 106m extending continuously between the pair of outer regions 106o1, 106o2, wherein the width of the intermediate region 106m is smaller than the width of the outer regions 106o1, 106o2. In some embodiments, the first patterning process includes: forming a first masking layer 602 above the second capping layer 116; and performing a first etching process (e.g., dry etching, such as plasma etching, reactive ion etching, etc.) based on the first masking layer 602. In various embodiments, the first masking layer 602 is removed by a removal process (e.g., a photoresist stripping process, an ash removal process, etc.) (not shown) during the first patterning process or after the first patterning process. In some embodiments, the first etching process includes removing the first dielectric layer 214a, the TFR film ( Figure 5A 502), unmasked areas of the first capping layer 114 and the second capping layer 116 are exposed to a first dry etchant (eg, a carbon-based etchant such as carbon tetrafluoride).

[0044] like Fig. 7A and Figure 7B As shown in the cross-sectional view 700a and the top view 700b of , a second patterning process is performed on the second capping layer 116. In some embodiments, the second patterning process includes: forming a second masking layer 702 above the second capping layer 116; and performing a second etching process (e.g., dry etching, such as plasma etching, reactive ion etching, etc.) according to the second masking layer 702. In various embodiments, the second masking layer 702 is removed by a removal process (e.g., a photoresist stripping process, an ash removal process, etc.) (not shown) during the second patterning process or after the second patterning process. In a further embodiment, the second etching process over-etches into the first capping layer 114, thereby reducing the thickness of the first capping layer 114 in the area offset relative to the second masking layer 702. In a further embodiment, the second etching process includes exposing the second capping layer 116 to a second dry etchant (e.g., difluoromethane and / or oxygen). In various embodiments, during the second patterning process, the second capping layer 116 is etched at a higher rate than the first capping layer 114.

[0045] like Fig. 8A and Figure 8BAs shown in the cross-sectional view 800a and the top view 800b of FIG. 1 , a third etching process is performed on the first capping layer 114, thereby defining and / or forming a capping structure 112 over the middle region 106m of the TFR layer 106. The capping structure 112 includes the first capping layer 114 and the second capping layer 116. In various embodiments, the third etching process is a wet etching process, which includes exposing the exposed area of ​​the first capping layer 114 and / or the TFR layer 106 to a first wet etchant (e.g., diluted hydrofluoric acid). In some embodiments, the second capping layer 116 is configured as a masking layer (e.g., a hard mask layer) during the third etching process.

[0046] During the third etching process, the first capping layer 114 is etched at a first etching rate, and the TFR layer 106 is etched at a second etching rate that is less than the first etching rate. In some embodiments, during the third etching process, the first etching rate of the first capping layer 114 is about 5000 times greater than the second etching rate of the TFR layer 106. Thus, a reduction in the thickness of the TFR layer 106 is substantially minimized, so that the TFR layer 106 and other TFR layers (not shown) disposed across the semiconductor substrate 102 maintain a uniform thickness during and / or after the third etching process. In some embodiments, during the third etching process, the first etching rate of the first capping layer 114 is, for example, about 492 angstroms per minute (A / min), and the second etching rate of the TFR layer 106 is, for example, about 0.0225 A / min.

[0047] like Fig. 9A and Fig. 9B As shown in the cross-sectional view 900a and the top view 900b of FIG. 1 , a conductive layer 902 and an etch stop film 904 are formed over the semiconductor substrate 102. The conductive layer 902 may be formed over the semiconductor substrate 102 by, for example, CVD, PVD, ALD, or some other suitable growth or manufacturing process. The conductive layer 902 may be, for example, or include titanium nitride, tantalum nitride, titanium, tantalum, some other conductive material, or any combination of the foregoing materials. In some embodiments, the conductive layer 902 is formed to a thickness of about 500 to 1000 angstroms or some other suitable value. The etch stop film 904 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, some other dielectric material, or any combination of the foregoing materials. In some embodiments, the etch stop film 904 is formed to a thickness of about 300 to 500 angstroms or some other suitable value. In various embodiments, the thickness of the conductive layer 902 is greater than the thickness of the etch stop film 904. In a further embodiment, the conductive layer 902 and the etch stop film 904 are formed by separate CVD processes.

[0048] like Fig. 10A and Fig. 10B As shown in the cross-sectional view 1000a and the top view 1000b, the etching stop film ( Fig. 9A and Fig. 9B 904) and the conductive layer 902 are subjected to a third patterning process, thereby defining and / or forming an etch stop layer 110 over the outer regions 106o1, 106o2 of the TFR layer 106. In some embodiments, the third patterning process includes: forming a third masking layer 1002 over the semiconductor substrate 102; and performing a fourth etching process (e.g., dry etching, such as plasma etching, reactive ion etching, etc.) based on the third masking layer 1002. In various embodiments, the third masking layer 1002 is removed by a removal process (e.g., a photoresist stripping process, an ash removal process, etc.) (not shown) during or after the third patterning process. In further embodiments, the fourth etching process reduces the thickness of the conductive layer 902 over the middle region 106m of the TFR layer 106 to a thickness 1006 of about 200 angstroms or in a range of about 100 to 200 angstroms. Since at least a portion of the conductive layer 902 remains over the middle region 106 m of the TFR layer 106 after the third patterning process, damage to the TFR layer 106 by the fourth etching process is reduced and / or a reduction in thickness of the TFR layer 106 is mitigated or prevented during the fourth etching process.

[0049] like Fig.11A and Fig. 11B As shown in the cross-sectional view 1100a and the top view 1100b, the conductive layer ( Fig. 10A 902) performs a fifth etching process to define and / or form a pair of conductive structures 108 on opposite sides of the TFR layer 106 and the resistor structure 104. In some embodiments, the process for forming the pair of conductive structures 108 includes FIG. 9A to FIG. 9B to FIG. 11A to FIG. 11B In various embodiments, the fifth etching process is a wet etching process, which includes etching the conductive layer ( Fig. 10A 902) is exposed to a second wet etchant (e.g., hydrogen peroxide). In various embodiments, the fifth etching process is Fig. 8A and Figure 8BThe conductive structure 108 includes a first portion 108p1 adjacent to a second portion 108p2, respectively, wherein the height of the first portion 108p1 is less than the height of the second portion 108p2. In some embodiments, due to the second wet etchant removing the lateral portion of the conductive structure 108, the first portion 108p1 and the second portion 108p2 each include at least one curved sidewall segment. In yet further embodiments, the fifth etching process is a dry etching process (e.g., blanket dry etching, plasma etching, reactive ion etching, etc.). In such an embodiment, the outer sidewall of the conductive structure 108 is straight (e.g., as shown in FIG. 1 ). Figure 4A In some embodiments, during the fifth etching process, the etch stop layer 110 is configured as a masking layer (eg, a hard mask layer).

[0050] Since the capping structure 112 is located above the TFR layer 106 during the fifth etching process, damage to the TFR layer 106 is mitigated and / or a reduction in the thickness of the TFR layer 106 is prevented during the fifth etching process. This, in part, facilitates the TFR layer 106 to maintain a low TTV and mitigates non-uniform removal of other TFR layers (not shown) across the semiconductor substrate 102. Thus, the uniformity of the resistance of the resistor structure 104 and other resistor structures (not shown) disposed across the semiconductor substrate 102 is increased, thereby increasing the overall performance and device yield of the integrated chip. In yet a further embodiment, during the fifth etching process, the conductive layer ( Fig. 10A 902).

[0051] like Fig. 12A and Fig. 12B As shown in the cross-sectional view 1200a and the top view 1200b of FIG. 1200, a second dielectric layer 214b is formed over the resistor structure 104. It should be understood that for ease of description, Fig. 12B The top view 1200b omits the second dielectric layer 214b. The second dielectric layer 214b may be formed over the resistor structure 104, for example, by CVD, PVD, ALD, or some other suitable growth or deposition process. In some embodiments, the first dielectric layer 214a and the second dielectric layer 214b include the same material.

[0052] like Fig.13A and Fig. 13B As shown in the cross-sectional view 1300a and the top view 1300b of FIG. 1300, a plurality of conductive vias 120 are formed in the second dielectric layer 214b and over the conductive structure 108. It should be understood that for ease of description, Fig. 13BThe top view 1300b omits the second dielectric layer 214b. In some embodiments, the process for forming the plurality of conductive vias 120 includes: patterning the second dielectric layer 214b to form a plurality of openings above the conductive structure 108; depositing (e.g., by CVD, PVD, ALD, electroplating, chemical plating, etc.) one or more conductive materials (e.g., copper, aluminum, ruthenium, titanium, titanium nitride, tantalum nitride, etc.) in the openings; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the one or more conductive materials.

[0053] Fig.14 A flow chart of some embodiments of a method 1400 for forming an integrated chip having a resistor structure including a covering structure located above a TFR layer is shown. Although method 1400 is shown and / or described as a series of steps of events, it should be understood that the method is not limited to the order or steps shown. Therefore, in some embodiments, the steps may be performed in an order different from that shown and / or may be performed simultaneously. In addition, in some embodiments, the steps or events shown may be subdivided into multiple steps or events, which may be performed at different times or simultaneously with other steps or sub-steps. In some embodiments, some of the steps or events shown may be omitted, and other steps or events not shown may be included.

[0054] In step 1402, a first dielectric layer, a TFR film, a first capping layer, and a second capping layer are formed over a semiconductor substrate. Figure 5A and Figure 5B Various views corresponding to some embodiments of step 1402 are shown.

[0055] In step 1404, the first and second capping layers and the TFR film are patterned to define a TFR layer having an intermediate region between the pair of outer regions. Fig. 6A and Figure 6B Various views corresponding to some embodiments of step 1404 are shown.

[0056] In step 1406 , the first capping layer and the second capping layer are patterned to form a capping structure over the middle region of the TFR layer. Fig. 7A , Figure 7B , Fig. 8A and Figure 8B Various views corresponding to some embodiments of step 1406 are shown.

[0057] In step 1408, a conductive layer and an etch stop film are deposited over the capping structure and the TFR layer. Fig. 9A and Fig. 9B Various views corresponding to some embodiments of step 1408 are shown.

[0058] In step 1410 , the etch stop film and the conductive layer are patterned to form the etch stop layer over the outer region of the TFR layer and to reduce the thickness of the conductive layer over the middle region of the TFR layer. Fig. 10A and Fig. 10B Various views corresponding to some embodiments of step 1410 are shown.

[0059] In step 1412, the conductive layer is etched to form a pair of conductive structures over an outer region of the TFR layer and to define a resistor structure, wherein a capping structure is disposed on the TFR layer while the conductive layer is etched. Fig.11A and Fig. 11B Various views corresponding to some embodiments of step 1412 are shown.

[0060] In step 1414, a second dielectric layer is formed over the resistor structure. Fig. 12A and Fig. 12B Various views corresponding to some embodiments of step 1414 are shown.

[0061] In step 1416 , a plurality of conductive vias are formed in the second dielectric layer and over the conductive structure. Fig.13A and Fig. 13B Various views corresponding to some embodiments of step 1416 are shown.

[0062] Therefore, in some embodiments, the disclosed embodiments are directed to a resistor structure including a TFR layer, a pair of conductive structures disposed on opposite sides of the TFR layer, and a capping structure on the TFR layer between the pair of conductive structures.

[0063] In some embodiments, the present application provides an integrated chip, comprising: a thin film resistor (TFR) layer, located on a semiconductor substrate; a first conductive structure, arranged on an outer region of the TFR layer, wherein the first conductive structure includes a lateral portion adjacent to the vertical portion, wherein the height of the vertical portion is greater than the height of the lateral portion; and a covering structure, arranged on a middle region of the TFR layer, and adjacent to the vertical portion of the first conductive structure. In an embodiment, the covering structure directly contacts the first sidewall of the vertical portion. In an embodiment, the first sidewall of the vertical portion includes a curved segment above the straight segment. In an embodiment, the second sidewall of the lateral portion is curved. In an embodiment, the height of the second sidewall is greater than the height of the straight segment of the first sidewall. In an embodiment, the integrated chip further comprises: an etch stop layer, arranged on the first conductive structure, wherein the etch stop layer extends along the top surface of the lateral portion and along the sidewall and top surface of the vertical portion; and a conductive via, extending through the etch stop layer to the first conductive structure. In an embodiment, the width of the first conductive structure is greater than the width of the middle region of the TFR layer. In an embodiment, the first sidewall of the vertical portion is straight.

[0064] In some embodiments, the present application provides an integrated chip, comprising: a first dielectric layer, located on a semiconductor substrate; a resistor structure, located on the first dielectric layer, wherein the resistor structure includes a thin film resistor (TFR) layer and a conductive structure pair, wherein the TFR layer includes an intermediate region extending between a pair of outer regions, wherein the conductive structure is located on the outer region; a second dielectric layer, located on the TFR layer and extending around the TFR layer; and a covering structure, disposed on the intermediate region of the TFR layer and extending between the conductive structures, wherein the lower surface of the second dielectric layer is vertically spaced from the TFR layer by the covering structure. In an embodiment, the bottom surface of the second dielectric layer is disposed below the top surface of the TFR layer. In an embodiment, the covering structure includes a first covering layer on the TFR layer and a second covering layer on the first covering layer, wherein the first covering layer includes a first material and the second covering layer includes a second material different from the first material. In an embodiment, the second dielectric layer includes a first material. In an embodiment, the thickness of each of the first covering layer and the second covering layer is greater than the thickness of the TFR layer. In an embodiment, the conductive structures each include a first portion adjacent to a second portion, wherein the second portion is spaced apart between the cover structure and the first portion, wherein a height of the first portion is greater than a height of the cover structure. In an embodiment, a width of the cover structure is less than a width of the conductive structure pair, wherein a length of the cover structure is greater than a length of a first conductive structure in the conductive structure pair.

[0065] In some embodiments, the present application provides a method for forming an integrated chip, comprising: forming a thin film resistor (TFR) layer over a semiconductor substrate; forming a capping structure over a middle region of the TFR layer; depositing a conductive layer and an etch stop layer over the TFR layer and the capping structure; and performing a first patterning process on the conductive layer and the etch stop layer to define a conductive structure pair on an outer region of the TFR layer, wherein during the first patterning process, the capping structure is disposed on the TFR layer. In an embodiment, the first patterning process comprises: performing a first etching on the conductive layer and the etch stop layer, wherein the first etching reduces the thickness of a portion of the conductive layer located above the middle region of the TFR layer; and performing a second etching on the conductive layer to remove a portion of the conductive layer located above the middle region of the TFR layer, wherein the first etching is different from the second etching. In an embodiment, the first etching is a dry etching, and the second etching is a wet etching. In an embodiment, forming the capping structure comprises: depositing a first capping layer and a second capping layer on the TFR layer; performing a dry etching on the second capping layer; and performing a wet etching on the first capping layer, wherein during the wet etching, a first etching rate of the first capping layer is greater than a second etching rate of the TFR layer. In an embodiment, the method further includes depositing an upper dielectric layer over the TFR layer, wherein the upper dielectric layer contacts outer sidewalls of the TFR layer, and wherein the capping structure is disposed directly between a lower surface of the upper dielectric layer and a top surface of the TFR layer.

[0066] Some embodiments of the present application provide an integrated chip, comprising: a thin film resistor (TFR) layer located on a semiconductor substrate; a first conductive structure arranged on an outer area of ​​the thin film resistor layer, wherein the first conductive structure includes a lateral portion adjacent to a vertical portion, wherein a height of the vertical portion is greater than a height of the lateral portion; and a covering structure arranged on a middle area of ​​the thin film resistor layer and adjacent to the vertical portion of the first conductive structure.

[0067] In some embodiments, the capping structure directly contacts the first sidewall of the vertical portion.

[0068] In some embodiments, the first sidewall of the vertical portion includes a curved segment above a straight segment.

[0069] In some embodiments, the second sidewall of the lateral portion is curved.

[0070] In some embodiments, the height of the second sidewall is greater than the height of the straight section of the first sidewall.

[0071] In some embodiments, the integrated chip further comprises:

[0072] an etch stop layer disposed on the first conductive structure, wherein the etch stop layer extends along a top surface of the lateral portion and along a sidewall and a top surface of the vertical portion; and

[0073] A conductive via extends through the etch stop layer to the first conductive structure.

[0074] In some embodiments, the width of the first conductive structure is greater than the width of the middle region of the thin film resistor layer.

[0075] In some embodiments, the first sidewall of the vertical portion is straight.

[0076] Other embodiments of the present application provide an integrated chip, comprising: a first dielectric layer, located on a semiconductor substrate; a resistor structure, located on the first dielectric layer, wherein the resistor structure includes a thin film resistor (TFR) layer and a pair of conductive structures, wherein the thin film resistor layer includes an intermediate region extending between a pair of external regions, wherein the conductive structure is located on the external regions; a second dielectric layer, located on the thin film resistor layer and extending around the thin film resistor layer; and a covering structure, disposed on the intermediate region of the thin film resistor layer and extending between the conductive structures, wherein a lower surface of the second dielectric layer is vertically spaced apart from the thin film resistor layer by the covering structure.

[0077] In some embodiments, a bottom surface of the second dielectric layer is disposed below a top surface of the thin-film resistor layer.

[0078] In some embodiments, the cover structure includes a first cover layer on the thin film resistor layer and a second cover layer on the first cover layer, wherein the first cover layer includes a first material and the second cover layer includes a second material different from the first material.

[0079] In some embodiments, the second dielectric layer includes the first material.

[0080] In some embodiments, each of the thicknesses of the first cover layer and the second cover layer is greater than the thickness of the thin film resistor layer.

[0081] In some embodiments, the conductive structures respectively include a first portion adjacent to a second portion, wherein the second portion is spaced apart between the covering structure and the first portion, and wherein a height of the first portion is greater than a height of the covering structure.

[0082] In some embodiments, the width of the covering structure is smaller than the width of the pair of conductive structures, wherein the length of the covering structure is greater than the length of a first conductive structure in the pair of conductive structures.

[0083] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a thin film resistor (TFR) layer over a semiconductor substrate; forming a covering structure over a middle region of the thin film resistor layer; depositing a conductive layer and an etch stop layer over the thin film resistor layer and the covering structure; and performing a first patterning process on the conductive layer and the etch stop layer to define a pair of conductive structures on an outer region of the thin film resistor layer, wherein, during the first patterning process, the covering structure is disposed on the thin film resistor layer.

[0084] In some embodiments, the first patterning process includes: performing a first etching on the conductive layer and the etch stop layer, wherein the first etching reduces the thickness of a portion of the conductive layer located above the middle region of the thin film resistor layer; and performing a second etching on the conductive layer to remove the portion of the conductive layer located above the middle region of the thin film resistor layer, wherein the first etching is different from the second etching.

[0085] In some embodiments, the first etch is a dry etch and the second etch is a wet etch.

[0086] In some embodiments, forming the covering structure includes: depositing a first covering layer and a second covering layer on the thin film resistor layer; performing dry etching on the second covering layer; and performing wet etching on the first covering layer, wherein, during the wet etching, a first etching rate of the first covering layer is greater than a second etching rate of the thin film resistor layer.

[0087] In some embodiments, the method further includes: depositing an upper dielectric layer above the thin film resistor layer, wherein the upper dielectric layer contacts the outer side wall of the thin film resistor layer, and wherein the covering structure is directly disposed between the lower surface of the upper dielectric layer and the top surface of the thin film resistor layer.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated chip, comprising: a thin film resistor (TFR) layer located on the semiconductor substrate; a first conductive structure disposed on an outer region of the thin film resistor layer, wherein the first conductive structure includes a lateral portion adjacent to a vertical portion, wherein a height of the vertical portion is greater than a height of the lateral portion; and A capping structure is disposed on the middle region of the thin film resistor layer and is adjacent to the vertical portion of the first conductive structure.

2. The integrated chip according to claim 1, wherein: The cover structure directly contacts the first sidewall of the vertical portion.

3. The integrated chip according to claim 2, wherein: The first side wall of the vertical portion includes a curved section above a straight section.

4. The integrated chip according to claim 3, wherein: The second side wall of the lateral portion is curved.

5. The integrated chip according to claim 4, wherein: The height of the second side wall is greater than the height of the straight section of the first side wall.

6. The integrated chip according to claim 1, further comprising: an etch stop layer disposed on the first conductive structure, wherein the etch stop layer extends along a top surface of the lateral portion and along a sidewall and a top surface of the vertical portion; and A conductive via extends through the etch stop layer to the first conductive structure.

7. The integrated chip according to claim 1, wherein: The width of the first conductive structure is greater than the width of the middle region of the thin film resistor layer.

8. The integrated chip according to claim 1, wherein: The first side wall of the vertical portion is straight.

9. An integrated chip, comprising: A first dielectric layer is disposed on the semiconductor substrate; a resistor structure located above the first dielectric layer, wherein the resistor structure includes a thin film resistor (TFR) layer and a pair of conductive structures, wherein the thin film resistor layer includes an intermediate region extending between a pair of outer regions, wherein the conductive structure is located above the outer regions; a second dielectric layer overlying and extending around the thin film resistor layer; and A cover structure is disposed on the middle region of the thin film resistor layer and extends between the conductive structures, wherein a lower surface of the second dielectric layer is vertically spaced apart from the thin film resistor layer by the cover structure.

10. A method for forming an integrated chip, comprising: forming a thin film resistor (TFR) layer over the semiconductor substrate; forming a capping structure over a middle region of the thin film resistor layer; depositing a conductive layer and an etch stop layer over the thin film resistor layer and the capping structure; as well as A first patterning process is performed on the conductive layer and the etch stop layer to define a pair of conductive structures on an outer region of the thin film resistor layer, wherein the capping structure is disposed on the thin film resistor layer during the first patterning process.

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