Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a tunable component. The tunable component is coupled to the pixel circuit. The pixel circuit includes a storage capacitor, a first scan transistor, and a second scan transistor. The first scan transistor is coupled to the storage capacitor. The second scan transistor is coupled to the storage capacitor. The electronic device can effectively drive the tunable component.

Description

Technical Field

[0001] The present disclosure relates to a device; in particular, to an electronic device. Background Art

[0002] A general beam-steerable directional antenna is composed of multiple antenna units, and each of the antenna units may include a tunable component (e.g., a varactor diode) and a pixel circuit. The resonant frequency of each of the antenna units can be tuned by a control signal of the tunable component, which is driven by the pixel circuit. Although a wider voltage range of the control signal can expand the tuning range, it causes reliability issues, especially due to the drain-avalanche hot carrier (DAHC) stress that causes the on-current of the scanning transistor of the pixel circuit to degrade. Summary of the invention

[0003] The electronic device of the present disclosure includes a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a tunable component. The tunable component is coupled to the pixel circuit. The pixel circuit includes a storage capacitor, a first scanning transistor, and a second scanning transistor. The first scanning transistor is coupled to the storage capacitor. The second scanning transistor is coupled to the storage capacitor.

[0004] Based on the above, according to the electronic device of the present disclosure, the electronic device can effectively drive the tunable component by controlling at least two scanning transistors.

[0005] In order to make the foregoing content more understandable, several embodiments of the drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0007] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 is a schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure;

[0009] Figure 3 Based on Figure 2 A timing diagram of relevant signals of an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure;

[0011] Figure 5 Based on Figure 4 A timing diagram of relevant signals of an embodiment of the present invention;

[0012] Figure 6 is a schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure;

[0013] Figure 7 Based on Figure 6 A timing diagram of relevant signals of an embodiment of the present invention;

[0014] Figure 8 is a schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure;

[0015] Fig. 9 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure;

[0016] Fig.10 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0017] Description of Figure Numbers

[0018] 110, 210, 410, 610, 810: pixel circuit;

[0019] 120, 220, 420, 620, 820: tunable components;

[0020] 811, 911, 1011: driving circuit;

[0021] Cst: storage capacitor;

[0022] CVL: common voltage line;

[0023] CVL_m: pre-charge data line;

[0024] DL_m: data line;

[0025] DP1: driving cycle;

[0026] DP2: next driving cycle;

[0027] DPS_m: precharge data signal;

[0028] DS_m: data signal;

[0029] OP: Operational amplifier;

[0030] P(1,1), P(m,n): electronic unit;

[0031] P1: circuit node;

[0032] PCP1: pre-charge cycle;

[0033] PCP2: next pre-charge cycle;

[0034] Pin: input node;

[0035] Pout: output node;

[0036] R1: resistor;

[0037] SP_n: pre-scan signal;

[0038] SS_(n-1): first scanning signal;

[0039] SS_n: second scanning signal;

[0040] t1, t2, t3, t4, t5, t6, t7, t8: time;

[0041] Td, Td': driving transistor;

[0042] Ts1: first scanning transistor;

[0043] Ts2: second scanning transistor;

[0044] Vdata(m,n): voltage;

[0045] Vdata1, Vdata2: data voltage;

[0046] VDD: first operating voltage;

[0047] VGH: high voltage level;

[0048] VGL: low voltage level;

[0049] Vmax: maximum voltage;

[0050] Vmin: minimum voltage;

[0051] Vpc, Vpc': pre-charge voltage;

[0052] VSS: second operating voltage. DETAILED DESCRIPTION

[0053] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like components.

[0054] Throughout the specification and appended claims of this disclosure, specific terms are used to refer to specific components. It will be appreciated by those skilled in the art that electronic device manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but have different names. In the following description and claims, words such as "include" and "comprising" are open-ended terms and should be interpreted as "including but not limited to...".

[0055] The term "coupling (or connection)" used throughout the entire specification (including the attached claims) of this application may refer to any direct or indirect connection member. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device by other devices or some connecting members. The terms "first", "second" and similar terms mentioned in the entire specification (including the attached claims) of this application are only used to name discrete elements or to distinguish between different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limit of the number of elements and should not be used to limit the arrangement order of elements. In addition, where possible, the elements / components / steps with the same figure numbers in the drawings and embodiments represent the same or similar parts. The same figure numbers can be used in different embodiments or the same terms can be used to refer to the relevant descriptions of the elements / components / steps.

[0056] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1 , the electronic device 100 includes a plurality of electronic units P(1,1) to P(m,n), and the electronic units P(1,1) to P(m,n) can be as follows Figure 1 , where m and n are positive integers. Each of the electronic units P(1,1) to the electronic units P(m,n) includes a pixel circuit 110 and a tunable component 120, and the pixel circuit 110 is coupled to the tunable component 120. In an embodiment of the present disclosure, the tunable component 120 may be a voltage-controlled component (e.g., a variable capacitor, a varactor diode, or a micro-electromechanical system (MEMS)), but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the tunable component 120 may be a capacitive tunable component. In an embodiment of the present disclosure, the electronic device 100 may be an active matrix device. In one embodiment of the present disclosure, the electronic device 100 may be an antenna device (e.g., a directional antenna device with a steerable beam), and the antenna device may be a liquid crystal antenna or a varactor diode antenna.

[0057] Figure 2Schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure. Figure 2 , Figure 1 The pixel circuit 110 and the tunable component 120 of each of the electronic units P(1,1) to the electronic units P(m,n) may be implemented as Figure 2 The pixel circuit 210 and the tunable component 220 of the present disclosure are provided. In an embodiment of the present disclosure, the pixel circuit 210 includes a first scanning transistor Ts1, a second scanning transistor Ts2, and a storage capacitor Cst. The first end of the first scanning transistor Ts1 is coupled to the common voltage line CVL to receive the precharge voltage Vpc. The common voltage line CVL (i.e., a dedicated voltage line) can be coupled to all pixels, a row in the pixel array, or a column in the pixel array. In other words, the common voltage line CVL can be shared with multiple electronic units on the same row and / or the same column. The second end of the first scanning transistor Ts1 is coupled to the circuit node P1. The control end of the first scanning transistor Ts1 receives the first scanning signal SS_(n-1) from the scanning line of the previous row of the pixel array. The first end of the second scanning transistor Ts2 is coupled to the data line DL_m corresponding to the current column of the pixel array to receive the data signal DS_m. The second end of the second scanning transistor Ts2 is coupled to the circuit node P1. The control end of the second scanning transistor Ts2 receives the second scanning signal SS_n from the scanning line of the current row of the pixel array. A first end of the capacitor Cst is coupled to the circuit node P1. A second end of the capacitor Cst is coupled to a reference voltage, such as a ground voltage. The tunable component 220 is coupled to the circuit node P1. In an embodiment of the present disclosure, the first scanning transistor Ts1 and the second scanning transistor Ts2 may be n-type transistors, but the present disclosure is not limited thereto.

[0058] In an embodiment of the present disclosure, the first scan transistor Ts1 and the second scan transistor Ts2 are turned on at different times according to the first scan signal SS_(n-1) and the second scan signal SS_n. When the first scan transistor Ts1 is turned on, the first scan transistor Ts1 transmits the precharge voltage Vpc to the storage capacitor Cst through the circuit node P1. The second scan transistor Ts2 receives the data voltage of the data signal DS_m, and when the second scan transistor Ts2 is turned on, the data voltage is transmitted to the storage capacitor Cst through the circuit node P1. In an embodiment of the present disclosure, the storage capacitor Cst can be precharged by the precharge voltage Vpc, and then the storage capacitor Cst can be further charged by the data voltage of the data signal DS_m. Therefore, the drain avalanche hot carrier (DAHC) stress of the first scan transistor Ts1 and the second scan transistor Ts2 can be effectively alleviated by sharing the amount of charge to be transmitted to the storage capacitor Cst and the drain-source voltage.

[0059] Figure 3 Based on Figure 2The timing diagram of the relevant signals of the embodiment is shown in FIG. Figure 2 and Figure 3 During the precharge period PCP1 from time t1 to time t2, the first scan signal SS_(n-1) may provide a high voltage level VGH, and the second scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The first scan transistor Ts1 may transmit the precharge voltage Vpc to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed to the precharge voltage Vpc. During the driving period DP1 from time t3 to time t4, the first scan signal SS_(n-1) may provide a low voltage level VGL, and the second scan signal SS_n may provide a high voltage level VGH. The data signal DS_m may provide a data voltage Vdata1. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The second scan transistor Ts2 may transmit the data voltage Vdata1 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc to the data voltage Vdata1. Therefore, the storage capacitor Cst may maintain the data voltage Vdata1 as a control signal (i.e., control voltage) of the tunable component 220 after time t4. The tunable component 220 may be controlled by the control signal corresponding to the data voltage Vdata1.

[0060] Similarly, during the next precharge period PCP2 from time t5 to time t6, the first scan signal SS_(n-1) may provide a high voltage level VGH, and the second scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The first scan transistor Ts1 may transmit the precharge voltage Vpc to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed from the previous data voltage Vdata1 to the precharge voltage Vpc. During the next drive period DP2 from time t7 to time t8, the first scan signal SS_(n-1) may provide a low voltage level VGL, and the second scan signal SS_n may provide a high voltage level VGH. The data signal DS_m may provide another data voltage Vdata2. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The second scan transistor Ts2 may transmit the data voltage Vdata2 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc to the data voltage Vdata2. Therefore, the storage capacitor Cst may maintain the data voltage Vdata2 as a control signal of the tunable component 220 after time t8. The tunable component 220 may be controlled by the control signal corresponding to the data voltage Vdata2.

[0061] In an embodiment of the present disclosure, the precharge voltage Vpc may be defined as an appropriate voltage for alleviating the DAHC stress of the first scan transistor Ts1 and the second scan transistor Ts2 during the charging process of the storage capacitor Cst (i.e., during the precharge period and the driving period). In an embodiment of the present disclosure, the precharge voltage Vpc may be a fixed voltage. The precharge voltage Vpc may be within a first preset range corresponding to the center of the voltage range of the data voltage of the data signal DS_m. In addition, the precharge voltage Vpc may be equal to or less than the maximum voltage Vmax of the data voltage of the data signal DS_m, and the precharge voltage Vpc may be equal to or greater than the minimum voltage Vmin of the data voltage of the data signal DS_m.

[0062] In an embodiment of the present disclosure, the storage capacitor Cst can be charged in two stages (i.e., a precharge period and a drive period), so the first scanning transistor Ts1 and the second scanning transistor Ts2 can share the amount of charge used to charge the storage capacitor Cst. Therefore, the DAHC stress of the first scanning transistor Ts1 and the second scanning transistor Ts2 can be effectively alleviated during the charging process of the storage capacitor Cst.

[0063] Figure 4 Schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure. Figure 4 , Figure 1 The pixel circuit 110 and the tunable component 120 of each of the electronic units P(1,1) to the electronic units P(m,n) may be implemented as Figure 4 A pixel circuit 410 and a tunable component 420 are provided. In an embodiment of the present disclosure, the pixel circuit 410 includes a first scanning transistor Ts1, a second scanning transistor Ts2, and a storage capacitor Cst. A first end of the first scanning transistor Ts1 is coupled to a data line DL_m corresponding to a current column of a pixel array to receive a precharge voltage provided by a data signal DS_m. A second end of the first scanning transistor Ts1 is coupled to a circuit node P1. A control end of the first scanning transistor Ts1 receives a pre-scan signal SP_n from a pre-scan line of a current row of the pixel array. A first end of the second scanning transistor Ts2 is coupled to the data line DL_m to receive a data voltage provided by the data signal DS_m. A second end of the second scanning transistor Ts2 is coupled to the circuit node P1. A control end of the second scanning transistor Ts2 receives a scan signal SS_n from a scan line of a current row of the pixel array. A first end of the capacitor Cst is coupled to the circuit node P1. A second end of the capacitor Cst is coupled to a reference voltage, such as a ground voltage. The tunable component 420 is coupled to the circuit node P1. In an embodiment of the present disclosure, the first scan transistor Ts1 and the second scan transistor Ts2 may be n-type transistors, but the present disclosure is not limited thereto.

[0064] In an embodiment of the present disclosure, the data line DL_m may provide a precharge voltage and a data voltage of the data signal DS_m in a time-sharing manner. The first scan transistor Ts1 and the second scan transistor Ts2 are turned on at different times according to the pre-scan signal SP_n and the scan signal SS_n. The first scan transistor Ts1 receives the precharge voltage, and when the first scan transistor Ts1 is turned on, the precharge voltage is transmitted to the storage capacitor Cst through the circuit node P1. The second scan transistor Ts2 receives the data voltage, and when the second scan transistor Ts2 is turned on, the data voltage is transmitted to the storage capacitor Cst through the circuit node P1. In an embodiment of the present disclosure, the storage capacitor Cst may be precharged by the precharge voltage, and then the storage capacitor Cst may be further charged by the data voltage. Therefore, the DAHC stress of the first scan transistor Ts1 and the second scan transistor Ts2 may be effectively alleviated by sharing the amount of charge to be transmitted to the storage capacitor Cst and the drain-source voltage.

[0065] Figure 5 Based on Figure 4 The timing diagram of the relevant signals of the embodiment is shown in FIG. Figure 4 and Figure 5During the precharge period PCP1 from time t1 to time t2, the pre-scan signal SP_n may provide a high voltage level VGH, and the scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The data signal DS_m may provide a precharge voltage Vpc, and the first scan transistor Ts1 may transmit the precharge voltage Vpc to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed to the precharge voltage Vpc. During the driving period DP1 from time t3 to time t4, the pre-scan signal SP_n may provide a low voltage level VGL, and the scan signal SS_n may provide a high voltage level VGH. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The data signal DS_m may provide a data voltage Vdata1, and the second scan transistor Ts2 may transmit the data voltage Vdata1 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc to the data voltage Vdata1. Therefore, the storage capacitor Cst may maintain the data voltage Vdata1 as a control signal (i.e., control voltage) of the tunable component 420 after time t4. The tunable component 420 may be controlled by the control signal corresponding to the data voltage Vdata1.

[0066] Similarly, during the next precharge period PCP2 from time t5 to time t6, the pre-scan signal SP_n may provide a high voltage level VGH, and the scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The data signal DS_m may provide a precharge voltage Vpc', and the first scan transistor Ts1 may transmit the precharge voltage Vpc' to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed from the previous data voltage Vdata1 to the precharge voltage Vpc'. During the next drive period DP2 from time t7 to time t8, the pre-scan signal SP_n may provide a low voltage level VGL, and the scan signal SS_n may provide a high voltage level VGH. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The data signal DS_m may provide another data voltage Vdata2, and the second scan transistor Ts2 may transmit the data voltage Vdata2 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc' to the data voltage Vdata2. Therefore, the storage capacitor Cst may maintain the data voltage Vdata2 as a control signal of the tunable component 420 after time t8. The tunable component 420 may be controlled by the control signal corresponding to the data voltage Vdata2.

[0067] In an embodiment of the present disclosure, the precharge voltage Vpc and the precharge voltage Vpc' may be defined as appropriate voltages for relieving the DAHC stress of the first scan transistor Ts1 and the second scan transistor Ts2 during the charging process of the storage capacitor Cst (i.e., during the precharge period and the driving period). In an embodiment of the present disclosure, the precharge voltage Vpc and the precharge voltage Vpc' may be non-fixed voltages. During the precharge period PCP2, the precharge voltage Vpc' may be within a second preset range corresponding to the center of the voltage range of the first voltage, and the first voltage may be the current data voltage Vdata2 plus the previous data voltage Vdata1 divided by 2. In addition, the definition of the precharge voltage Vpc may be similarly inferred.

[0068] In an embodiment of the present disclosure, the storage capacitor Cst can be charged in two stages (i.e., a precharge period and a drive period), so the first scan transistor Ts1 and the second scan transistor Ts2 can share the amount of charge used to charge the storage capacitor Cst. Therefore, the DAHC stress of the first scan transistor Ts1 and the second scan transistor Ts2 can be effectively alleviated during the charging process of the storage capacitor Cst. In addition, in Figure 5, the pre-scan signal SP_n and the scan signal SS_n show the pre-scan signal and the scan signal of the pixel circuit on the previous row as a reference.

[0069] Figure 6 Schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure. Figure 6 , Figure 1 The pixel circuit 110 and the tunable component 120 of each of the electronic units P(1,1) to the electronic units P(m,n) may be implemented as Figure 6 A pixel circuit 610 and a tunable component 620. In an embodiment of the present disclosure, the pixel circuit 610 includes a first scan transistor Ts1, a second scan transistor Ts2, and a storage capacitor Cst. A first end of the first scan transistor Ts1 is coupled to a precharged data line CVL_m corresponding to a current column of the pixel array to receive a precharged data signal DPS_m. A second end of the first scan transistor Ts1 is coupled to a circuit node P1. A control end of the first scan transistor Ts1 receives a first scan signal SS_(n-1) from a scan line of a previous row of the pixel array. A first end of the second scan transistor Ts2 is coupled to a data line DL_m corresponding to a current column of the pixel array to receive a data signal DS_m. A second end of the second scan transistor Ts2 is coupled to the circuit node P1. A control end of the second scan transistor Ts2 receives a second scan signal SS_n from a scan line of a current row of the pixel array. A first end of the capacitor Cst is coupled to the circuit node P1. A second end of the capacitor Cst is coupled to a reference voltage, such as a ground voltage. The tunable component 420 is coupled to the circuit node P1. In an embodiment of the present disclosure, the first scan transistor Ts1 and the second scan transistor Ts2 may be n-type transistors, but the present disclosure is not limited thereto.

[0070] In an embodiment of the present disclosure, the first scan transistor Ts1 and the second scan transistor Ts2 are turned on at different times according to the first scan signal SS_(n-1) and the second scan signal SS_n. The first scan transistor Ts1 is configured to transmit the precharge voltage Vpc provided by the precharge data signal DPS_m to the storage capacitor Cst through the circuit node P1 when the first scan transistor Ts1 is turned on. The second scan transistor Ts2 receives the data voltage provided by the data signal DS_m, and is configured to transmit the data voltage to the storage capacitor Cst through the circuit node P1 when the second scan transistor Ts2 is turned on. In an embodiment of the present disclosure, the storage capacitor Cst can be precharged by the precharge voltage of the precharge data signal DPS_m, and then the storage capacitor Cst can be charged by the data voltage of the data signal DS_m. Therefore, the drain avalanche hot carrier (DAHC) stress of the first scan transistor Ts1 and the second scan transistor Ts2 can be effectively alleviated by sharing the amount of charge to be transmitted to the storage capacitor Cst and the drain-source voltage.

[0071] Figure 7 Based on Figure 6 The timing diagram of the relevant signals of the embodiment is shown in FIG. Figure 6 and Figure 7 During the precharge period PCP1 from time t1 to time t2, the first scan signal SS_(n-1) may provide a high voltage level VGH, and the second scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The precharge data signal DPS_m may provide a precharge voltage Vpc, and the first scan transistor Ts1 may transmit the precharge voltage Vpc to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed to the precharge voltage Vpc. During the driving period DP1 from time t3 to time t4, the first scan signal SS_(n-1) may provide a low voltage level VGL, and the second scan signal SS_n may provide a high voltage level VGH. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The data signal DS_m may provide a data voltage Vdata1, and the second scan transistor Ts2 may transmit the data voltage Vdata1 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc to the data voltage Vdata1. Therefore, the storage capacitor Cst may maintain the data voltage Vdata1 as a control signal (i.e., control voltage) of the tunable component 620 after time t4. The tunable component 620 may be controlled by a control signal corresponding to the data voltage Vdata1.

[0072] Similarly, during the next precharge period PCP2 from time t5 to time t6, the first scan signal SS_(n-1) may provide a high voltage level VGH, and the second scan signal SS_n may provide a low voltage level VGL. Therefore, the first scan transistor Ts1 may be turned on, and the second scan transistor Ts2 may be turned off. The precharge data signal DPS_m provides a precharge voltage Vpc', and the first scan transistor Ts1 may transmit the precharge voltage Vpc' to the circuit node P1 so as to precharge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may be changed from the previous data voltage Vdata1 to the precharge voltage Vpc'. During the next drive period DP2 from time t7 to time t8, the first scan signal SS_(n-1) may provide a low voltage level VGL, and the second scan signal SS_n may provide a high voltage level VGH. Therefore, the first scan transistor Ts1 may be turned off, and the second scan transistor Ts2 may be turned on. The data signal DS_m may provide another data voltage Vdata2, and the second scan transistor Ts2 may transmit the data voltage Vdata2 to the circuit node P1 so as to charge the storage capacitor Cst. The voltage Vdata(m,n) of the circuit node P1 may further change from the precharge voltage Vpc' to the data voltage Vdata2. Therefore, the storage capacitor Cst may maintain the data voltage Vdata2 as a control signal of the tunable component 620 after time t8. The tunable component 620 may be controlled by the control signal corresponding to the data voltage Vdata2.

[0073] In an embodiment of the present disclosure, the precharge voltage Vpc and the precharge voltage Vpc' may be defined as appropriate voltages for relieving the DAHC stress of the first scan transistor Ts1 and the second scan transistor Ts2 during the charging process of the storage capacitor Cst (i.e., during the precharge period and the driving period). In an embodiment of the present disclosure, the precharge voltage Vpc and the precharge voltage Vpc' may be non-fixed voltages. During the precharge period PCP2, the precharge voltage Vpc' may be within a second preset range corresponding to the center of the voltage range of the first voltage, and the first voltage may be the current data voltage Vdata2 plus the previous data voltage Vdata1 divided by 2. In addition, the definition of the precharge voltage Vpc may be similarly inferred.

[0074] In an embodiment of the present disclosure, the storage capacitor Cst can be charged in two stages (i.e., a precharge period and a drive period), so the first scanning transistor Ts1 and the second scanning transistor Ts2 can share the amount of charge used to charge the storage capacitor Cst. Therefore, the DAHC stress of the first scanning transistor Ts1 and the second scanning transistor Ts2 can be effectively alleviated during the charging process of the storage capacitor Cst.

[0075] Figure 8 Schematic diagram of a pixel circuit and a tunable component according to an embodiment of the present disclosure. Figure 8 , Figure 1 The pixel circuit 110 and the tunable component 120 of each of the electronic units P(1,1) to the electronic units P(m,n) may be implemented as Figure 8 The pixel circuit 810 and the tunable component 820 are provided. Figure 2 compared to, Figure 8 The pixel circuit 810 further includes a driving circuit 811, and the driving circuit 811 may be a voltage driver. Specifically, in an embodiment of the present disclosure, the pixel circuit 810 includes a first scanning transistor Ts1, a second scanning transistor Ts2, a storage capacitor Cst, and a driving circuit 811. The first end of the first scanning transistor Ts1 receives a precharge voltage Vpc. The second end of the first scanning transistor Ts1 is coupled to a circuit node P1. The control end of the first scanning transistor Ts1 receives a first scanning signal SS_(n-1) from a scanning line of a previous row of the pixel array. The first end of the second scanning transistor Ts2 is coupled to a data line DL_m to receive a data signal DS_m. The second end of the second scanning transistor Ts2 is coupled to the circuit node P1. The control end of the second scanning transistor Ts2 receives a second scanning signal SS_n from a scanning line of a current row of the pixel array. The first end of the capacitor Cst is coupled to the circuit node P1. The second end of the capacitor Cst is coupled to a reference voltage, such as a ground voltage. An input node Pin of the driver circuit 811 is coupled to the circuit node P1 , and an output node Pout of the driver circuit 811 is coupled to the tunable component 820 .

[0076] In an embodiment of the present disclosure, the driving circuit 811 includes a driving transistor Td and a resistor R1. The first end of the driving transistor Td is coupled to a first operating voltage VDD. The second end of the driving transistor Td is coupled to the output node Pout of the driving circuit 811 and the first end of the resistor R1. The control end of the driving transistor Td is coupled to the input node Pin of the driving circuit 811. The second end of the resistor R1 is coupled to the second operating voltage VSS. The first operating voltage VDD is higher than the second operating voltage VSS. In an embodiment of the present disclosure, the driving transistor Td may be an n-type transistor, but the present disclosure is not limited thereto. In an embodiment of the present disclosure, the driving circuit 811 may drive the tunable component 820 according to the voltage Vdata(m,n) of the circuit node P1. The driving circuit 811 can effectively enhance the driving capability of the pixel circuit 810. It should be noted that the driving circuit 811 can also be applied to Figure 4 and Figure 6 An embodiment to integrate into Figure 4 The pixel circuit 410 and Figure 6 In the pixel circuit 610.

[0077] Fig. 9 Schematic diagram of a driving circuit according to an embodiment of the present disclosure. Fig. 9 , in one embodiment of the present disclosure, Figure 8 The drive circuit 811 is available Fig. 9 The driving circuit 911 is replaced by the driving circuit 911. The driving circuit 911 includes an operational amplifier OP. The operational amplifier OP can be coupled to a first operating voltage VDD and a second operating voltage VSS. The non-inverting input terminal of the operational amplifier OP is coupled to an input node Pin of the driving circuit 911. The inverting input terminal of the operational amplifier OP is coupled to an output terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is further coupled to an output node Pout of the driving circuit 911. The driving circuit 911 can also effectively enhance Figure 8 The driving capability of the pixel circuit 810 is as follows.

[0078] Fig.10 Schematic diagram of a driving circuit according to an embodiment of the present disclosure. Fig.10 , in one embodiment of the present disclosure, Figure 8 The drive circuit 811 is available Fig.10 The driving circuit 1011 is replaced by a driving circuit 1011. The driving circuit 1011 may be a current driver, and the driving circuit 1011 includes a driving transistor Td'. A first end of the driving transistor Td' is coupled to an output node Pout of the driving circuit 1011. A second end of the driving transistor Td' is coupled to a second operating voltage VSS. A control end of the driving transistor Td' is coupled to an input node Pin of the driving circuit 1011. When the tunable component is a current control component, the driving circuit 1011 can effectively convert the data voltage into a corresponding current to control the tunable component.

[0079] In summary, the electronic device of the present disclosure can effectively alleviate the DAHC stress of the scan transistor in the pixel circuit by sharing the amount of charge to be transferred to the storage capacitor and the drain-source voltage through the scan transistor.

[0080] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure encompasses modifications and variations provided that the modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. An electronic device, characterized in that: include: a plurality of electronic units, wherein each of the plurality of electronic units comprises: pixel circuit; and a tunable component coupled to the pixel circuit, The pixel circuit comprises: Storage capacitors; a first scan transistor coupled to the storage capacitor; and A second scan transistor is coupled to the storage capacitor.

2. The electronic device according to claim 1, characterized in that: The first scanning transistor and the second scanning transistor receive a first scanning signal and a second scanning signal respectively. The first scanning transistor and the second scanning transistor are turned on at different times according to the first scanning signal and the second scanning signal.

3. The electronic device according to claim 1, characterized in that: The second scan transistor is configured to transfer a data voltage to the storage capacitor.

4. The electronic device according to claim 3, characterized in that: The second scan transistor is coupled to the data line to receive the data voltage.

5. The electronic device according to claim 3, characterized in that: The first scan transistor is configured to transfer a precharge voltage to the storage capacitor.

6. The electronic device according to claim 5, characterized in that: The precharge voltage is equal to or less than a maximum voltage of the data voltage, and the precharge voltage is equal to or greater than a minimum voltage of the data voltage.

7. The electronic device according to claim 6, characterized in that: The pre-charge voltage is a fixed voltage.

8. The electronic device according to claim 7, characterized in that: The precharge voltage is within a first preset range corresponding to a center of a voltage range of the data voltage.

9. The electronic device according to claim 6, characterized in that: The first scan transistor receives the precharge voltage from a common voltage line shared with the plurality of electronic cells on the same row and / or the same column.

10. The electronic device according to claim 6, characterized in that: The pre-charge voltage is within a second preset range corresponding to the center of the voltage range of the first voltage, The first voltage is the sum of the current data voltage and the previous data voltage divided by 2.

11. The electronic device according to claim 6, characterized in that: The first scan transistor and the second scan transistor are coupled to a data line.

12. The electronic device according to claim 3, characterized in that: The tunable component is controlled by a control signal corresponding to the data voltage.

13. The electronic device according to claim 12, characterized in that: The tunable component is a voltage controlled component.

14. The electronic device according to claim 12, characterized in that: The tunable component is a capacitive tunable component.

15. The electronic device according to claim 3, characterized in that: The pixel circuit further includes: A drive circuit is coupled to the tunable component.

16. The electronic device according to claim 15, characterized in that: The driving circuit is a voltage driver.

17. The electronic device according to claim 1, characterized in that: The electronic device is an active matrix device.

18. The electronic device according to claim 17, characterized in that: The electronic device is an antenna device.

19. The electronic device according to claim 18, characterized in that: The antenna device is a liquid crystal antenna.

20. The electronic device according to claim 18, characterized in that The antenna device is a varactor diode antenna.

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