Integrated circuit device and method of forming same

Abstract

An integrated circuit device includes a transistor having a plurality of stacked channels, each stacked channel extending between source / drain regions of the transistor. The transistor also includes a hard mask nanostructure over the highest channel and extending between the source / drain regions of the transistor. A gate dielectric and a gate metal surround the channel and the hard mask nanostructure. The embodiment of the invention also discloses a method for forming the integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing integrated circuits. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a transistor, comprising: a first source / drain region; a second source / drain region; a plurality of stacked channels, each stacked channel extending along a first lateral direction between the first source / drain region and the second source / drain region; a hard mask nanostructure of a dielectric material, directly located above the channel and extending along the first lateral direction between the first source / drain region and the second source / drain region; and a gate electrode surrounding each of the channel and the hard mask nanostructure.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a first transistor, comprising a plurality of stacked first channels, and a first hard mask nanostructure located above the first channels; a second transistor, comprising a plurality of stacked second channels, and a second hard mask nanostructure located above the second channels; a high-K gate dielectric layer surrounding the first channel, the first hard mask nanostructure, the second channel, and the second hard mask nanostructure; a first gate metal contacting the high-K gate dielectric layer at the first transistor and surrounding the first channel and the first hard mask nanostructure; and a second gate metal contacting the high-K gate dielectric layer at the second transistor and surrounding the second channel and the second hard mask nanostructure.

[0005] According to another aspect of an embodiment of the present application, a method for forming an integrated circuit device is provided, comprising: forming a plurality of stacked first channels of a first transistor; forming a first hard mask nanostructure of a dielectric material above the first channel; and forming a first gate electrode of the first transistor surrounding the first channel and the first hard mask nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A-Figure 2K is a cross-sectional view of an integrated circuit at various stages of processing according to some embodiments;

[0008] Figure 3 is a cross-sectional view of an integrated circuit according to some embodiments;

[0009] Figure 4 is a cross-sectional view of an integrated circuit according to some embodiments;

[0010] Figure 5 is a cross-sectional view of an integrated circuit according to some embodiments;

[0011] Figure 6 is a flow chart of a method for forming an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Terms indicating relative degrees, such as "about", "substantially", etc., should be interpreted as the understanding of one of ordinary skill in the art in the context of the current technical specifications.

[0015] The present invention generally relates to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active area spacing between nanostructured devices is typically uniform, the source / drain epitaxial structures are symmetrical, and the metal gate surrounds all four sides of the nanostructure (e.g., nanosheet). Due to the larger metal gate end caps and the increased source / drain epitaxial size, the gate-drain capacitance ("Cgd") increases.

[0016] In an embodiment of the nanostructure transistor disclosed herein, each nanostructure transistor includes a plurality of stacked channels. A hard mask nanostructure is positioned above the highest channel of each transistor. The gate metal of the transistor surrounds the channel and the hard mask nanostructure. The presence of the hard mask nanostructure helps prevent the loss of high-K gate dielectric from the top surface of the highest channel of each transistor. In addition, the presence of the hard mask nanostructure helps reduce the limitation of the gate width spacing. As a result, further scaling of critical polysilicon gate spacing and cell height can be achieved. As a result, the scaling of transistors can be improved while protecting and maintaining the electrical characteristics of the transistors. This results in improved wafer yields and better functioning electronic devices.

[0017] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with smaller spacing, for example, than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure transistor structure.

[0018] Figure 1A-Figure 2K is a cross-sectional view of an integrated circuit 100 at various stages of processing according to some embodiments. The fabrication process produces a plurality of semiconductor nanostructure transistors, which will be described in further detail below.

[0019] Figure 1A1 is a cross-sectional view of an integrated circuit 100 in an intermediate processing state according to some embodiments. Integrated circuit 100 includes substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of substrate 102 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide; or combinations thereof. Other substrates may be used, such as a single layer substrate, a multilayer substrate, or a gradient substrate.

[0020] The integrated circuit 100 includes a stack 104. The stack 104 includes a plurality of semiconductor layers 106 and sacrificial semiconductor layers 108 that alternate with each other. As will be described in further detail below, the semiconductor layers 106 will be patterned to form semiconductor nanostructures of a plurality of transistors. As will be described in more detail below, the sacrificial semiconductor layers 108 will eventually be completely removed and used to enable the formation of gate metal and other structures around the semiconductor nanostructures. The stack also includes a hard mask layer 110 on top of the highest sacrificial semiconductor layer 108.

[0021] In some embodiments, the semiconductor layer 106 may be formed by a first semiconductor material suitable for an n-type semiconductor nanostructure transistor, such as silicon, silicon carbide, etc.; the sacrificial semiconductor layer 108 may be formed by a second semiconductor material suitable for a p-type semiconductor nanostructure transistor, such as silicon germanium, etc. Each layer of the stack 104 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The hard mask layer 110 may include a dielectric material such as SiN, SiCN, SiC, SiOCN, or other suitable dielectric materials.

[0022] Three semiconductor layers 106 and four sacrificial semiconductor layers 108 are shown. In some embodiments, the multilayer stack 104 may include more or fewer semiconductor layers 106 and sacrificial semiconductor layers 108. Although the stack 104 is shown as including the sacrificial semiconductor layer 108 as the bottom layer of the multilayer stack 104, in some embodiments, the bottom layer of the multilayer stack 104 may be the semiconductor layer 106.

[0023] By virtue of the high etching selectivity between the materials of semiconductor layer 106 and sacrificial semiconductor layer 108 , the sacrificial semiconductor layer 108 of the second semiconductor material may be removed without significantly removing semiconductor layer 106 of the first semiconductor material, thereby allowing semiconductor layer 106 to be released to form a channel region of a semiconductor nanostructure transistor.

[0024] exist Figure 1B In the embodiment, the stack 104 is patterned to form a plurality of fins 112 . Figure 1B Only a single fin 112 is shown. The fin 112 extends along the X direction, that is, into and out of Figure 1B The fins 112 are separated from each other by grooves 114. In other words, the fins 112 are defined by forming grooves in the stack 104. The fins 112 can be defined by an etching process. Specifically, an etching process is implemented in conjunction with a photolithography mask to define the fins 112 from an initial single stack. The etching process may include an anisotropic etching process that etches in a downward direction. The etching process defines the fins 112 by forming grooves 114 that pass through the sacrificial semiconductor layer 108, the semiconductor layer 106, and the substrate 102.

[0025] After forming the trench 114, a trench isolation region (not shown) may be formed in the trench 114, which may be a shallow trench isolation (STI) region. The trench isolation region may be formed by depositing a dielectric material. In some embodiments, a dielectric material is formed over the substrate 102, the fins 112, and between adjacent fins 112. The dielectric material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not shown separately) may be first formed along the surface of the substrate 102 and the fins 112.

[0026] An etch back process is performed to lower the top surface of the trench isolation region to a level below the lowest sacrificial semiconductor layer 108. The etching process may include wet etching, dry etching, timed etching, or other types of etching processes that can recess the height of the shallow trench isolation region. As a result, the sidewalls of the semiconductor layer 106 and the sacrificial semiconductor layer 108 of the fin 112 are exposed.

[0027] Although Figure 1B Not shown, but appropriate wells (not shown separately) may also be formed in the fin 112 and / or trench isolation regions. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 102, and p-type impurity implantation may be performed in the n-type region of the substrate. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implant damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the stack 104 may avoid separate implantation, although in-situ doping and implantation doping may be used together.

[0028] Figure 1C According to some embodiments, Figure 1B The processing stage shown is a cross-sectional view of the integrated circuit 100 after several processing steps have been performed. Figure 1C The cross-section is taken along Figure 1B The cutting line X in corresponds to the view taken at line X, but after various processing steps.

[0029] exist Figure 1C In the embodiment, a sacrificial gate structure 116 is formed above the fin 112 and above the trench isolation region (not shown). Figure 1B The finite nature of the view of Figure 1C Only a single sacrificial gate structure 116 is shown in FIG. In practice, many other sacrificial gate structures 116 may be formed substantially parallel to the Figure 1C The sacrificial gate structure shown in is formed simultaneously with it.

[0030] The sacrificial gate structure 116 includes a sacrificial gate layer 122. The sacrificial gate layer 122 may include a material having a high etch selectivity relative to the trench isolation region. The sacrificial gate layer 122 may be a conductive, semiconductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 122 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. Although in Figure 1C The sacrificial gate structure 116 is shown as a single layer, but in practice, the sacrificial gate structure 116 may include multiple dielectric layers.

[0031] The sacrificial gate structure 116 is defined by a gate spacer layer 124. As will be described in more detail below, the sacrificial gate layer 122 will eventually be removed from between the gate spacer layers 124 for gate metal. The gate spacer layer 124 can be formed by PVD, CVD, ALD, or other suitable deposition processes. After forming the gate spacer layer 124, a horizontal portion of the gate spacer layer 124 (e.g., along the XY plane) can be removed to expose the upper surface of the fin 112 and the trench isolation region. The gate spacer layer 124 may include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0032] exist Figure 1C In some embodiments, after forming the gate spacer layer 124, one or more etching operations are performed to recess the fin 112 exposed by the gate spacer layer 124. The etching process forms source / drain trenches in the fin 112. Figure 1CIn the embodiment of the present invention, the trenches are filled with source / drain regions 118, which will be described in more detail below.

[0033] The etching process that forms the source / drain trenches in the fins 112 also results in the singulation of individual stacks of nanostructures. Each stack includes a plurality of channels 107, a plurality of sacrificial semiconductor nanostructures 109, and a hard mask nanostructure 111 located on top of the tallest sacrificial semiconductor nanostructure 109. The channels 107 are formed from the semiconductor layer 106. The sacrificial semiconductor nanostructures 109 are formed from the sacrificial semiconductor layer 108. The hard mask nanostructures 111 are formed from the hard mask layer 110. Figure 1C In the example of FIG. 1 , each stack includes three stacked channels 107 and four sacrificial semiconductor nanostructures 109. The stacked channels 107 of each stack will eventually correspond to the channel region of a corresponding transistor. Thus, a single transistor will be formed with each stack, Figure 1C Only a single stack is shown in FIG. Sacrificial semiconductor nanostructure 109 is an example of a sacrificial nanostructure. In some cases, the sacrificial semiconductor nanostructure can be replaced by a sacrificial nanostructure of dielectric material.

[0034] Channel 107 is a semiconductor nanostructure. The semiconductor nanostructure may include a semiconductor nanosheet, a semiconductor nanowire, or other types of semiconductor nanostructures. The hard mask nanostructure 111 is similar to the semiconductor nanostructure of channel 107 in shape and orientation. However, the hard mask nanostructure 111 is different from the semiconductor nanostructure of channel 107 in that the hard mask nanostructure is a dielectric material that does not carry current during operation of the transistor. The presence of the hard mask nanostructure 111 can obtain flexibility in scaling the gate width and the internal channel spacing.

[0035] After forming the source / drain trenches and before forming the source / drain regions 118, lateral ends of the channel 107, sacrificial semiconductor nanostructure 109, and hard mask nanostructure 111 are exposed. According to some embodiments, a selective etching process is performed to recess the exposed ends of the sacrificial semiconductor nanostructure 109 without substantially etching the channel 107 or the hard mask nanostructure 111. The material of the sacrificial semiconductor nanostructure 109 is selectively etchable relative to the material of the semiconductor channel 107. Therefore, the sacrificial semiconductor nanostructure 109 can be recessed without substantially etching the channel 107. The etching process causes a recess to be formed in the sacrificial semiconductor nanostructure 109.

[0036] exist Figure 1CIn the embodiment, the inner spacer 120 is already conformally located in the recess of the sacrificial semiconductor layer 109 before the source / drain regions 118 are formed. Initially, the dielectric material of the inner spacer 120 can be conformally deposited. The inner spacer 120 can include a dielectric material such as SiCN, SiOCN, etc. formed by a suitable deposition method such as physical vapor deposition (PVD), CVD, ALD, etc. Then an etching process can be performed to remove the dielectric material from all locations outside the recess. The result is as shown in FIG. Figure 1C 1. The internal spacers 120 are shown in FIG. As will be explained in more detail below, the presence of the internal spacers helps to electrically isolate the subsequently deposited gate metal from the source / drain regions 118.

[0037] According to some embodiments, after forming the inner spacer 120, a source / drain region 118 is formed in the source / drain trench. In the embodiment shown, the source / drain region 118 is epitaxially grown from an epitaxial material. The source / drain region 118 is grown on the channel 107 in the trench and the exposed portion of the substrate 102.

[0038] For each stack, there are two source / drain regions 118. Each source / drain region 118 is in direct contact with the side of the channel 107 of the corresponding stack. The channel 107 of each stack extends between the two source / drain regions 118 along the X direction.

[0039] The source / drain region 118 may include any acceptable material, such as suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source / drain region 118 includes a material that applies tensile strain in the channel region, such as Si, SiC, SiCP, SiP, etc. According to some embodiments, when a p-type device is formed, the source / drain region 118 includes a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 118 may have a surface that protrudes from the corresponding surface of the fin and may have a small facet. In some embodiments, adjacent source / drain regions 118 may be merged to form a single source / drain region above two adjacent fins of the fin 112.

[0040] The source / drain region 118 may be implanted with dopants and then subjected to an annealing process. The source / drain region 118 may have a thickness of about 10 19 cm -3 and about 10 21 cm -3 The N-type and / or p-type impurities used for the source / drain regions 118 may be any of the impurities discussed previously. In some embodiments, the source / drain regions 118 are doped in situ during growth.

[0041] exist Figure 1D In the embodiment of the present invention, an interlayer dielectric layer 126 is formed. Although not shown, a contact etch stop layer (CESL) may be formed before forming the interlayer dielectric layer 126. The CESL layer may include a thin dielectric layer that may be conformally deposited on exposed surfaces of the source / drain regions 118 and the trench isolation regions. The CESL layer may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The CESL may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0042] The dielectric layer 126 covers the CESL. The dielectric layer 126 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 126 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0043] exist Figure 1D , the sacrificial gate structure 116 is removed. Specifically, the sacrificial gate layer 122 is removed. As a result, there is a gap between the gate spacers 124. The sacrificial gate layer 122 can be removed by an etching process that selectively etches the sacrificial gate layer 122 relative to other exposed materials of the sacrificial gate layer 122.

[0044] After removing the sacrificial gate layer 122, an etching process is performed to completely remove the sacrificial semiconductor nanostructure 109 from each stack. This corresponds to releasing the channel 107. Since the sacrificial semiconductor nanostructure 109 is selectively etchable relative to the channel 107, the channel 107 is substantially not etched during the removal of the sacrificial semiconductor nanostructure 109. As a result, there is a gap between each channel 107 in each stack.

[0045] The sacrificial semiconductor nanostructure 109 can be removed by a selective etching process using an etchant that is selective to the material of the sacrificial semiconductor nanostructure 109, thereby removing the sacrificial semiconductor nanostructure 109 without substantially etching the channel 107. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, a combination thereof, etc. In some embodiments, the sacrificial semiconductor nanostructure 109 is removed, and the channel 107 is patterned to form the channel regions of the PFET and the NFET.

[0046] exist Figure 1DIn the embodiment of the present invention, an interfacial gate dielectric layer 128 is formed in contact with the exposed surface of the channel 107 and the substrate 102. The interfacial gate dielectric layer 128 may correspond to a native oxide that consumes the surface portion of the exposed semiconductor material. The interfacial gate dielectric layer 128 surrounds the channel 107. The interfacial gate dielectric layer 128 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial gate dielectric layer 128 may include a relatively low-K dielectric relative to a high-K dielectric such as hafnium oxide or other high-K dielectric materials that can be used for the gate dielectric of the transistor. The high-K dielectric may include a dielectric material having a dielectric constant higher than the dielectric constant of silicon oxide. The interfacial gate dielectric layer 128 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interfacial gate dielectric layer 128 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interfacial gate dielectric layer 128 without departing from the scope of the present invention.

[0047] Figure 1E is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 1E The view corresponds to the Figure 1D The position of the cutting line Y intercepts the Y cut.

[0048] exist Figure 1E In the embodiment of the present invention, a high-K gate dielectric layer 130 is deposited. The high-K gate dielectric layer 130 can be deposited in a conformal deposition process. The conformal deposition process deposits the high-K gate dielectric layer 130 on the interface gate dielectric layer 128 and on the sidewalls of the gate spacer layer 124. The high-K gate dielectric layer 130 surrounds the channel 107. The high-K gate dielectric layer 130 has a thickness between 1 nm and 3 nm. The high-K dielectric layer includes one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiO2, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The high-K gate dielectric layer 130 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-K gate dielectric layer 130 without departing from the scope of the present invention.

[0049] A high-K gate dielectric layer 130 surrounds each channel 107 and is separated from each channel 107 by an interfacial gate dielectric layer 127. The high-K gate dielectric layer 130 surrounds and is in direct contact with the hard mask nanostructure 111. The high-K gate dielectric layer 130 is located on the top surface of the trench isolation region 132. The trench isolation region 132 can be formed as previously described.

[0050] As will be described in more detail below, the total width of the hard mask nanostructure 111 along the Y direction is slightly greater than the total width of the channel 107 along the Y direction. The hard mask nanostructure 111 also has a greater thickness along the Z direction than the channel 107. This difference in thickness and width may be the result of an etching process that releases the channel 107 by removing the sacrificial semiconductor nanostructure 109. Although the etching process selectively etches the material of the sacrificial semiconductor nanostructure 109 relative to the material of the channel 107, the channel 107 is still etched to a relatively small extent. The hard mask nanostructure 111 is substantially unetched. As a result, the hard mask nanostructure 111 has a slightly larger size than the channel 107.

[0051] In the subsequent figures, many of the figures show two separate regions of the integrated circuit 100 according to some embodiments. Specifically, the subsequent figures may show a first region 101 and a second region 103. The first region 101 may correspond to a region of the integrated circuit 100 where an N-type transistor is to be formed. The second region 103 may correspond to a region where a P-type transistor is to be formed. Therefore, the first region 101 may correspond to an N-type region, and the second region 103 may correspond to a P-type region.

[0052] Figure 1F is a cross-sectional Y view of integrated circuit 100 according to some embodiments. Figure 1F The view can correspond to Figure 1E 1, except that both the first region 101 and the second region 103 are shown. Specifically, a stack of channels 107 is shown in each region 101 / 103. The stack of channels 107 in region 101 will eventually correspond to the channels of an N-type transistor. The stack of channels 107 in region 103 will eventually correspond to the channels of a P-type transistor.

[0053] exist Figure 1F In the embodiment of the present invention, according to some embodiments, a hard mask layer 134 is conformally deposited in region 101 and in region 103. Specifically, hard mask layer 134 is conformally deposited on high-K gate dielectric layer 130 at regions 101 and 103. Hard mask layer 134 surrounds channel 107 and hard mask nanostructure 111 in regions 101 and 103.

[0054] In some embodiments, the hard mask layer 134 includes aluminum oxide, AlN, TiO, or other suitable hard mask materials. The hard mask layer 134 may be formed by ALD, PVD, CVD, or other suitable deposition processes. The hard mask layer 134 may include other materials or deposition processes without departing from the scope of the present invention.

[0055] Figure 1GAccording to some embodiments, the integrated circuit 100 is Figure 1F A cross-sectional X-view of the processing stage shown in FIG. Figure 1G The view of FIG. 101 may be referred to as an upper X view because only the upper portion of the stack above the channel 107 is shown. Specifically, the upper X view shows the hard mask nanostructure 111, wherein the gate spacer 124 is located above the hard mask nanostructure 111. More specifically, the upper X view of the region 101 is along Figure 1F The upper X view of region 103 is taken along the cutting line Xn of region 101. Figure 1F The region 103 is intercepted by the cutting line Xp. Figure 1G The view of FIG. 1 shows the high-K gate dielectric layer and the hard mask layer present on the inner sidewalls of the gate spacers 124 and on the upper surface of the hard mask nanostructures 111 .

[0056] The following figures may show Figure 1F The Y view shown in Figure 1G The upper X-view shown in FIG. 1 does not show the subsequent processing stages. In these existing drawings, it is understood that the upper X-view is along a similar Figure 1F It is intercepted by the cutting line Xn and the cutting line Xp.

[0057] Figure 1H and Fig. 1I 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1H and Fig. 1I , a photoresist layer 136 is deposited at regions 101 and 103. The photoresist 136 fills the gaps between the trench 107 and the hard mask nanostructure 111, and between the gate spacers 124. The photoresist layer 136 may correspond to a bottom anti-reflective coating (BARC) layer.

[0058] Figure 1J and Figure 1K 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1J and Figure 1K, the photoresist layer 136 is patterned. In one example, the photoresist layer 136 can be patterned by a high power global etching process that etches along a vertical direction. The photoresist 136 is removed from all locations except those locations directly below the outer edge of the hard mask layer surrounding the hard mask nanostructure 111. The result is that the photoresist layer 136 remains between the channels 107 in the regions 101 and 103. The photoresist 136 is removed between the gate spacers 124. In some cases, the upper portion of the high K gate dielectric layer above the hard mask nanostructure 111 may be damaged by the high power bombardment of the etching process. After the etching process, the photoresist layer 136 does not cover the lateral sidewalls of the hard mask layer 134 on the hard mask nanostructure 111. The hard mask layer 134 surrounding the channel 107 remains fully covered.

[0059] Figure 1L and Figure 1M 1 and 12 are a Y view and an upper X view of the integrated circuit 100 according to some embodiments. An etching process is performed to remove the hard mask layer 134 from all locations not covered by the photoresist layer 136. As a result, the hard mask layer 134 is no longer present on the side and top surfaces of the high-K gate dielectric layer 130 around the hard mask nanostructures 111 or between the gate spacers 124. The hard mask layer 134 remains on the bottom of the high-K gate dielectric layer 130 on the hard mask nanostructures 111. The etching process may also partially etch the exposed portions of the high-K gate dielectric layer 130 on the hard mask nanostructures 111.

[0060] Figure 1N and Fig.1O 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1N and Fig.1O In the embodiment of the present invention, a hard mask layer 138 is deposited on the remaining portion of the hard mask layer 134 and on the exposed portion of the high-K gate dielectric layer 130. In some embodiments, the hard mask layer 138 is the same material as the hard mask layer 134. Figure 1N and Fig.1O , the hard mask layer 134 can be considered to be merged with the hard mask layer 138. Therefore, the hard mask layer 138 is thick enough between adjacent channels 107 and between the top channels 107 and the hard mask nanostructures 111 so that there is no remaining gap between adjacent channels 107 and between the top channels 107 and the hard mask nanostructures 111. The hard mask layer 138 can have the materials and deposition processes described with respect to the hard mask layer 134.

[0061] Figure 1P and Figure 1Q 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1P and Figure 1QIn the embodiment of the present invention, a photoresist layer 140 is deposited and patterned. Initially, the photoresist layer 140 covers the regions 101 and 103 , however, after patterning, the photoresist layer 140 only covers the region 101 .

[0062] exist Figure 1P and Figure 1Q , after patterning the layer of photoresist layer 140, an etching process is performed. The etching process completely removes the hard mask layer 138 (including the remaining portion of the hard mask layer 134) from the region 103. Since the hard mask layer 138 is covered by the photoresist layer 140 in the region 101, the hard mask layer 138 remains in the region 101. The high-K gate dielectric layer 130 on top of the hard mask nanostructure 111 of the region 103 may be damaged by the patterning process of the photoresist layer 140.

[0063] Figure 1R and Figure 1S 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1R and Figure 1S 1 , a layer of photoresist layer 140 is removed from region 101 by an ashing process or other type of removal process. After removing the layer of photoresist layer 140, an isotropic etching process is performed to remove the hard mask layer 138 from the side portions of the high-K gate dielectric layer 130 on the sides of the trenches 107. The hard mask layer 138 remains directly between the trenches 107 and between the top trenches 107 and the hard mask nanostructures 111 at region 101. The etching process may include timed etching, wet etching, or other types of etching processes.

[0064] Figure 1T and Figure 1U 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1T and Figure 1U , a gate metal 142 is deposited. The gate metal 142 is deposited on the exposed surface of the high-K gate dielectric layer 130 at regions 101 and 103, and on the exposed portion of the hard mask layer 138 at region 101. More specifically, the gate metal 142 is deposited on the sidewalls of the remaining hard mask layer 138. At region 103, the gate metal 142 is formed completely and quickly around the channels 107 and the hard mask nanostructures 111, so that gaps remain between the channels 107 at region 103 and between the top channels 107 and the hard mask nanostructures 111.

[0065] In some embodiments, the gate metal 142 includes TiN, WN, WCN, TaN, Ru, Co, W, or other suitable materials. The gate metal 142 may be deposited by ALD, PVD, CVD, or other suitable deposition processes.

[0066] Figure 1V and Figure 1W 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1V and Figure 1W In the embodiment of the present invention, a photoresist layer 144 is deposited. The photoresist layer 144 is deposited on the exposed surface of the gate metal 142. At the region 103, the photoresist layer 144 is positioned in the gap between the channel 107 and the hard mask nanostructure 111.

[0067] Figure 1X and Figure 1Y 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1X and Figure 1Y In the embodiment, a high power etching process is performed to remove the layer of photoresist layer 144 at all locations except between the channels 107 and between the top channels 107 and the hard mask nanostructures 111. The etching process may cause damage to the high K gate dielectric layer 130 above the hard mask nanostructures 111.

[0068] Figure 1Z and Figure 2A 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 1Z and Figure 2A In the embodiment, an etching process is performed to completely remove the gate metal 142 from the portion of the gate metal 142 not covered by the photoresist layer 144 in the region 103 and the region 101. More specifically, at the region 103, the gate metal 142 is removed from all sides of the channels 107 and the hard mask nanostructures 111. At the region 103, the gate metal 142 remains directly between the channels 107 and directly between the top channels 107 and the hard mask nanostructures 111.

[0069] After the etching process to remove a portion of the gate metal 142, the photoresist layer 144 is completely removed from the region 103. The remaining portion of the gate metal 142 may correspond to a work function gate metal for a P-type transistor to be formed at the region 103.

[0070] Figure 2B and Figure 2C 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 2B and Figure 2C, gate metal 146 is deposited. Gate metal 146 is deposited on all exposed surfaces at regions 101 and 103. As a result, at region 101, gate metal 146 is positioned on the sidewalls of high-K gate dielectric layer 130 and on the sidewalls of hard mask layer 138. At region 103, gate metal 146 is deposited on exposed portions of the remaining portions of high-K gate dielectric layer 130 and gate metal 142. As a result, at region 103, gate metal 146 fills the space between adjacent trenches 107 and between the top trench 107 and hard mask nanostructure 111.

[0071] In some embodiments, gate metal 146 includes TiN, WN, WCN, TaN, Ru, Co, W, or other suitable materials. Gate metal 146 may be deposited by ALD, PVD, CVD, or other suitable deposition processes. Gate metal 146 may be different from gate metal 142.

[0072] Figure 2D and Figure 2E 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 2D and Figure 2E In the embodiment of the present invention, a photoresist layer 148 is deposited and patterned. The photoresist layer 148 remains at the region 103 and is not present in the region 101.

[0073] Figure 2F and Figure 2G 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 2F and Figure 2G In FIG. 1 , an etching process is performed to remove the gate metal 146 from the region 101. Since the photoresist layer 148 exists at the region 103, the gate metal 146 at the region 103 is not removed.

[0074] Figure 2H and Fig.2I 1 and 2 are respectively a Y view and an upper X view of the integrated circuit 100 according to some embodiments. Figure 2H and Fig.2I , the photoresist layer 148 is removed from the region 103. The gate metal 150 is conformally deposited at the regions 101 and 103. At the region 101, the gate metal 150 is in direct contact with the high-K gate dielectric layer 130 and surrounds each of the channels 107 and the hard mask nanostructures 111. Thus, at the region 101, the gate metal 150 is positioned between adjacent channels 107 and between the top channels 107 and the hard mask nanostructures 111. At the region 103, the gate metal 150 is positioned in contact with the gate metal 146.

[0075] At region 103 , gate metal 150 does not extend between adjacent channels 107 and between the top channel 107 and hard mask nanostructure 111 . This is because at region 103 , gate metal 146 fills the gaps between adjacent channels 107 and between the hard mask nanostructure 111 and the top channel 107 .

[0076] In some embodiments, gate metal 150 is a work function metal for an N-type transistor at region 101. Gate metal 150 may include TiN, TaN, WN, WCN, Ru, Co, W, or other suitable materials. Gate metal 150 may be deposited by ALD, PVD, CVD, or other suitable deposition processes.

[0077] exist Figure 2H and Fig.2I , gate metal 152 is conformally deposited at regions 101 and 103. At region 101, gate metal 152 is in direct contact with gate metal 150 and surrounds each of channels 107 and hard mask nanostructures 111. Thus, at region 101, gate metal 152 is positioned between adjacent channels 107 and between the top channel 107 and hard mask nanostructure 111. At region 103, gate metal 150 is positioned in contact with gate metal 150.

[0078] At region 103 , gate metal 152 does not extend between adjacent channels 107 and between the top channel 107 and hard mask nanostructure 111 . This is because, at region 103 , gate metal 146 fills the gaps between adjacent channels 107 and between the hard mask nanostructure 111 and the top channel 107 .

[0079] In some embodiments, gate metal 152 includes a glue layer. Gate metal 152 may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaAl, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, or other suitable materials. Gate metal 152 may be deposited by ALD, PVD, CVD, or other suitable deposition processes. Gate metal 152 may completely fill all remaining gaps around channel 107 at regions 101 and 103. Alternatively, additional gate metal 154 may be deposited to fill any remaining gaps around channel 107 and between gate spacers 124. Gate metal 154 may be deposited at any of the gates 154. Fig.2I It is obvious in Figure 2H If gate metal 152 fills all remaining gaps, gate metal 154 will not exist. Gate metal 154 may include W or other suitable materials. Gate metal 154 may be deposited by ALD, PVD, CVD, or other suitable deposition processes.

[0080] After the gate metals 152 and 154 are deposited, a CMP process may be performed to remove any excess gate metal material on the top surface of the interlayer dielectric layer 126 .

[0081] exist Figure 2H and Fig.2I At the processing stage shown, processing of transistors at regions 101 and 103 may be substantially complete. Specifically, transistor 156a is formed at region 101, and transistor 156b is formed at region 103. In some embodiments, transistor 156a is an N-type transistor, and transistor 156b is a P-type transistor.

[0082] Figure 2J is an X-view of transistor 156 according to some embodiments, corresponding to Figure 1D The view shown in , but in Figure 2H and Fig.2I The processing stages shown in . Figure 2J 101 or 103. Transistor 156 of FIG. 102 may represent transistor 156 a or transistor 156 b. High-K gate dielectric layer 130 is present around channel 107 and over hard mask nanostructure 111. Gate electrode 160 surrounds channel 107 and hard mask nanostructure 111 and is present between gate spacers 124. Gate electrode 160 is shown as a single layer but represents all gate metals that may be present at regions 101 or 103. For P-type transistor 156 b, gate electrode 160 may include gate metals 142, 146, 150, 152, and 154. For N-type transistor 156 a, gate metal 160 may include gate metals 150, 152, and 154. Gate metals 142, 146, 150, 152, and 154 may also be referred to as gate metal layers.

[0083] Figure 2J 1 shows how the internal spacer 120 electrically isolates the gate metal 160 from the source / drain region 118. The gate metal 160 may be referred to as a gate electrode. Figure 2J 1 , source / drain contacts may be formed in the interlayer dielectric layer 126 to provide electrical contact to the source / drain regions 118. The transistor 156 is operated by applying a gate voltage to the gate electrode 160 and a source / drain voltage to the source / drain regions 118. When the transistor 156 is turned on, current flows through each channel 107 between the source / drain regions 118. When the transistor 156 is turned off, substantially zero current flows through the channel 107. Figure 2JIt is also shown how the hard mask nanostructure 111 extends between the source / drain regions 118 and has lateral sidewalls that are in direct contact with the source / drain regions 118. The transistor 156 may have other configurations without departing from the scope of the present invention.

[0084] Figure 2K According to some embodiments, the integrated circuit 100 is in Figure 2H Y view of the processing stage shown in . Figure 2K The high-K gate dielectric layer 130 is shown to have varying thicknesses around the hard mask nanostructures 111 at regions 101 and 103. Specifically, the high-K gate dielectric layer 130 has a first thickness D1 on the top surface of the hard mask nanostructures 111 and a second thickness D2 on the bottom surface of the hard mask nanostructures 111. Thickness D1 is less than thickness D2. This may be due to various etching processes that remove layers of photoresist and other layers throughout the processing at regions 101 and 103. In some embodiments, dimension D1 is between 0 nm and 0.5 nm. In some embodiments, dimension D2 is between 0.5 nm and 2 nm. Other values ​​for D1 and D2 may be used without departing from the scope of the present invention. The thickness of the high-K gate dielectric layer 130 around the channel 107 is substantially equal to D2 and is uniform around the channel 107.

[0085] Since the hard mask nanostructures 111 do not carry current and do not affect the threshold voltage of the transistor 156, the difference in the thickness of the gate dielectric layer 130 around the hard mask nanostructures 111 does not adversely affect the function of the transistor 156. The thickness of the high-K gate dielectric layer 130 around the channels 107 of the two transistors 156 is substantially uniform, and there is substantially no damage to the high-K gate dielectric layer 130 around the channels 107. The result is that the transistors 156a and 156b have very good electrical function.

[0086] Transistor 156a includes gate electrode 160a including gate metals 150 and 152. Transistor 156b includes gate electrode 160b including gate metals 142, 146, 150, and 152.

[0087] As previously described, the hard mask nanostructures 111 have a width dimension along the Y direction that is greater than the width dimension of the channel 107. Therefore, the lateral ends of the hard mask nanostructures 111 are suspended above the lateral ends of the channel 107 by a dimension D3 along the Y direction. In some embodiments, the dimension D3 is between 0 nm and 4 nm, but other values ​​may be used without departing from the scope of the present invention.

[0088] The hard mask nanostructure 111 has a thickness dimension D4 along the Z direction. In some embodiments, dimension D4 is between 1 nm and 10 nm, although other values ​​may be used without departing from the scope of the present invention.

[0089] Each transistor 156 has a dimension D5 that separates the gate spacers 124 along the X direction (see Fig.2I ). In some embodiments, dimension D5 is between 8 nm and 15 nm, but other values ​​may be used without departing from the scope of the present invention. In some embodiments, adjacent fins 112 are separated from each other by a distance between 20 nm and 60 nm, but other distances may be used without departing from the scope of the present invention.

[0090] Adjacent channels 107 are separated from each other by dimension D6 along the Z direction. In some embodiments, dimension D6 is between 5.5nm and 15nm, but other values ​​may be used without departing from the scope of the present invention. The presence of the hard mask nanostructure 111 allows a larger dimension D5. This in turn allows flexibility in dimension D6. Dimension D6 may be less than, equal to, or greater than dimension D5. In some possible solutions, scaling is limited by the proposition that the gate width should be greater than the vertical distance between adjacent channels of the transistor. However, embodiments of the present invention overcome the shortcomings of other possible solutions by providing a hard mask nanostructure that enables flexibility in the design of dimension D5 in D6. Specifically, dimension D6 may be less than, greater than, or equal to dimension D5. This may allow aggressive scaling of critical polysilicon gate spacing and cell height.

[0091] At the boundary between regions 101 and 103, there is a height mismatch between the top surfaces of gate metal 150 in regions 101 and 103. Specifically, the top surface of gate metal 150 at region 103 is higher by dimension D7 than the top surface of gate metal 150 at region 101. Dimension D7 may be between 0 nm and 5 nm.

[0092] At region 103, gate metal 146 has a thickness dimension D8 along the Y direction on the lateral surfaces of hard mask nanostructure 111 and channel 107. Gate metal 146 (combined with gate metal 142) between adjacent channels 107 has a thickness dimension D9. D9 is greater than D8. In some embodiments, D8 is between 0.5 nm and 5 nm, and D9 is between 3 nm and 10 nm, but other values ​​may be used without departing from the scope of the present invention.

[0093] In some embodiments, the hard mask nanostructure 111 has a width dimension D10 along the Y direction between 9 nm and 100 nm, but other values ​​may be used without departing from the scope of the present invention. In some embodiments, the channel 107 has a width dimension D11 along the Y direction between 6 nm and 100 nm, but other values ​​may be used without departing from the scope of the present invention. D11 is less than D10. In some embodiments, the channel 107 has a height dimension D12 along the Z direction between 3 nm and 10 nm, but other values ​​may be used without departing from the scope of the present invention. D12 is less than D4.

[0094] Figure 3 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3 The integrated circuit 100 and Figure 2K The processing stages shown in are essentially the same. However, in Figure 3 In the example of FIG. 1 , the high-K gate dielectric layer 130 has been completely removed from the top surface of the hard mask nanostructure 111 due to the various photoresist removal processes described previously. As a result, the gate metal 150 is in direct contact with the top surface of the hard mask nanostructure 111 at transistor 156a. The gate metal 146 is in direct contact with the top surface of the hard mask nanostructure 111 at transistor 156b. There is no such problem at the top surface of the channel 107. Therefore, the hard mask nanostructure 111 protects the overall function of the channel 107 and the transistor 156.

[0095] Figure 4 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4 The integrated circuit 100 and Figure 2K The processing stages shown in are essentially the same. However, in Figure 4 In the example of FIG. 1 , at transistor 156 b, gate metal 142 still exists on the lateral surface of high-K gate dielectric layer 130. This may be due to the overlapping nature of hard mask nanostructure 111, so that Figure 1X The layer of photoresist layer 144 at the gate metal 142 remains on the side. Figure 1Z During the described etching process, gate metal 142 may not be completely removed from the sides of channel 107 in region 103. As a result, Figure 4 The structure shown in .

[0096] Figure 5 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5 The integrated circuit 100 and Figure 2K The processing stages shown in are essentially the same. However, in Figure 5In the example of , a semiconductor layer 162 is formed on the gate metal 146 at region 103. In some embodiments, the semiconductor layer 162 includes silicon, but other semiconductor materials can be used without departing from the scope of the present invention. The semiconductor layer 162 can be formed by ALD, PVD, CVD, or epitaxy, but other processes can be used without departing from the scope of the present invention. One benefit of the presence of the semiconductor layer 162 is that material from the gate metal 150 (e.g., aluminum) cannot diffuse into the gate metal 146 at the transistor 156 b. This can help maintain the proper electrical function of the transistor 156 b.

[0097] Semiconductor layer 162 may be formed in the following manner. After depositing gate metal 146 and before forming photoresist layer 148, semiconductor layer 162 may be deposited at regions 101 and 103. Subsequently, the semiconductor layer 162 may be deposited as described above. Figure 2D and Figure 2E As described, a layer of photoresist layer 148 is formed and patterned so that semiconductor layer 162 is exposed at region 101 and not exposed at region 103. An etching process may then be performed to remove semiconductor layer 162 at region 101. Figure 2F and Figure 2G The etching process is described to remove gate metal 156 from region 101. Other processes may be used to form semiconductor layer 162 without departing from the scope of the present invention.

[0098] Figure 6 is a flow chart of a method 600 for forming an integrated circuit according to some embodiments. The method 600 may utilize Figure 1A-Figure 5 The structure, process, and system described herein. At 602, method 600 includes forming a first channel of a plurality of stacks of first transistors. An example of a first transistor is Figure 2J An example of a first channel of the stack is Figure 2J At 604, the method includes forming a first hard mask nanostructure of dielectric material over the first trench. An example of the first hard mask nanostructure is Figure 2J At 606, method 600 includes forming a first gate electrode of a first transistor surrounding the first channel and the first hard mask nanostructure. An example of the first gate electrode is Figure 2J The gate electrode 160 is provided.

[0099] In an embodiment of the nanostructure transistor disclosed herein, each nanostructure transistor includes a plurality of stacked channels. A hard mask nanostructure is positioned above the highest channel of each transistor. The gate metal of the transistor surrounds the channel and the hard mask nanostructure. The presence of the hard mask nanostructure helps prevent the loss of high-K gate dielectric from the top surface of the highest channel of each transistor. In addition, the presence of the hard mask nanostructure helps reduce the limitation of the gate width spacing. As a result, further scaling of critical polysilicon gate spacing and cell height can be achieved. As a result, the scaling of transistors can be improved while protecting and maintaining the electrical characteristics of the transistors. This results in improved wafer yields and better functioning electronic devices.

[0100] In one embodiment, an integrated circuit device includes a transistor. The transistor includes: a first source / drain region; a second source / drain region; and a plurality of stacked channels, each stacked channel extending along a first lateral direction between the first source / drain region and the second source / drain region. The transistor includes: a hard mask nanostructure of dielectric material directly above the channel and extending along the first lateral direction between the first source / drain region and the second source / drain region; and a gate electrode surrounding each of the channel and the hard mask nanostructure.

[0101] In some embodiments, an integrated circuit device includes a high-K gate dielectric layer located between a channel and a gate electrode, between a hard mask nanostructure and the gate electrode, and surrounding each of the channel and the hard mask nanostructure, the high-K gate dielectric layer having a first thickness on a top surface of the hard mask nanostructure and a second thickness less than the first thickness on a bottom surface of the hard mask nanostructure.

[0102] In some embodiments, the high-K gate dielectric layer has a uniform thickness over the channel that is equal to the second thickness.

[0103] In some embodiments, the hard mask nanostructure has a same length as the channel along a first lateral direction, wherein the hard mask nanostructure has a width dimension along a second lateral direction that is greater than a width of the channel along the second lateral direction.

[0104] In some embodiments, the gate electrode has a width along the first lateral direction over the hard mask nanostructure that is less than or equal to a vertical distance between adjacent channels.

[0105] In some embodiments, the transistor includes a high-K gate dielectric layer surrounding a channel, wherein the gate electrode includes a gate metal located on the high-K gate dielectric layer and has a first thickness on the sides of the channel and a second thickness greater than the first thickness between adjacent channels.

[0106] In some embodiments, the transistor includes a high-K gate dielectric layer surrounding a channel, wherein the gate electrode includes: a first gate metal directly contacting the high-K gate dielectric layer at the bottom of the channel; and a second gate metal directly contacting the high-K gate dielectric layer at the side of the channel and separated from the high-K gate dielectric layer at the bottom of the channel.

[0107] In some embodiments, the gate electrode includes a third gate metal on the second gate metal, wherein the third gate metal is not positioned between adjacent channels.

[0108] In some embodiments, the transistor includes a high-K gate dielectric layer surrounding the channel and located on the bottom surface of the hard mask nanostructure, wherein the gate electrode is separated from the bottom surface of the hard mask nanostructure by the high-K gate dielectric layer, and wherein the gate electrode is in direct contact with the top surface of the hard mask nanostructure.

[0109] In some embodiments, the transistor includes a high-K gate dielectric layer surrounding a channel, wherein the gate electrode includes: a first gate metal located on the high-K gate dielectric layer; a semiconductor layer located on the first gate metal; and a second gate metal located on the semiconductor layer.

[0110] In some embodiments, the gate electrode includes a third gate metal on the second gate metal.

[0111] In some embodiments, an integrated circuit device includes a first gate spacer and a second gate spacer on a hard mask nanostructure, with a gate electrode positioned between the first gate spacer and the second gate spacer over the hard mask nanostructure.

[0112] In one embodiment, an integrated circuit device includes: a first transistor including a plurality of stacked first channels, and a first hard mask nanostructure located above the first channel. The device includes: a second transistor including a plurality of stacked second channels, and a second hard mask nanostructure located above the second channel. The device includes: a high-K gate dielectric layer surrounding the first channel, the first hard mask nanostructure, the second channel, and the second hard mask nanostructure; a first gate metal contacting the high-K gate dielectric layer at the first transistor and surrounding the first channel and the first hard mask nanostructure; and a second gate metal contacting the high-K gate dielectric layer at the second transistor and surrounding the second channel and the second hard mask nanostructure.

[0113] In some embodiments, the second gate metal is positioned on a side of the first channel and is separated from the first channel by the first gate metal.

[0114] In some embodiments, an integrated circuit device includes a semiconductor layer between a first gate metal and a second gate metal at a first transistor.

[0115] In some embodiments, the first gate metal is not present at the first transistor.

[0116] In some embodiments, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0117] In one embodiment, a method of forming an integrated circuit device includes: forming a plurality of stacked first channels of a first transistor; forming a first hard mask nanostructure of a dielectric material over the first channel; and forming a first gate electrode of the first transistor surrounding the first channel and the first hard mask nanostructure.

[0118] In some embodiments, a method includes: before forming a gate electrode, removing a plurality of sacrificial nanostructures interleaved with the first channel; and forming a gate electrode replacing the sacrificial nanostructures.

[0119] In some embodiments, the method includes: forming a plurality of stacked second channels of a second transistor; forming a second hard mask nanostructure of a dielectric material above the second channel; and forming a second gate electrode of the second transistor surrounding the second channel and the second hard mask nanostructure, wherein: forming the first gate electrode includes forming a first gate metal surrounding the first channel and the second channel; and forming the second gate electrode includes removing the first gate metal around the second channel and depositing a second gate metal surrounding the second channel and contacting the first gate metal on a side of the first channel.

[0120] In one embodiment, an integrated circuit device includes a transistor. The transistor includes: a plurality of stacked channels; a source / drain region in contact with each stacked channel; and a gate metal surrounding the stacked channels and including an upper portion above the highest channel of the stacked channels. The transistor includes: an internal spacer including a gap above the highest channel and laterally between the upper portion of the gate metal and the source / drain region; and a dielectric cap structure located above the gap and in contact with the source / drain region.

[0121] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising: Transistors, including: a first source / drain region; a second source / drain region; a plurality of stacked channels, each of the stacked channels extending along a first lateral direction between the first source / drain region and the second source / drain region; a hard mask nanostructure of dielectric material directly over the channel and extending along the first lateral direction between the first source / drain region and the second source / drain region; and A gate electrode surrounds the channel and each of the hard mask nanostructures.

2. The integrated circuit device of claim 1 , comprising a high-K gate dielectric layer located between the channel and the gate electrode, between the hard mask nanostructure and the gate electrode, and surrounding the channel and each of the hard mask nanostructures, the high-K gate dielectric layer having a first thickness on a top surface of the hard mask nanostructure and a second thickness less than the first thickness on a bottom surface of the hard mask nanostructure.

3. The integrated circuit device according to claim 1, wherein: The hard mask nanostructure has the same length as the channel along the first lateral direction, wherein the hard mask nanostructure has a width dimension along a second lateral direction that is greater than a width of the channel along the second lateral direction.

4. The integrated circuit device according to claim 1, wherein: The gate electrode has a width along the first lateral direction over the hard mask nanostructure that is less than or equal to a vertical distance between adjacent channels.

5. The integrated circuit device according to claim 1, wherein: The transistor includes a high-K gate dielectric layer surrounding the channel, wherein the gate electrode includes a gate metal located on the high-K gate dielectric layer and has a first thickness on the sides of the channel and a second thickness between adjacent channels that is greater than the first thickness.

6. The integrated circuit device according to claim 1, wherein: The transistor comprises a high-K gate dielectric layer surrounding the channel, wherein the gate electrode comprises: a first gate metal directly contacting the high-K gate dielectric layer at the bottom surface of the channel; and A second gate metal directly contacts the high-K gate dielectric layer at a side surface of the channel and is separated from the high-K gate dielectric layer at a bottom surface of the channel.

7. The integrated circuit device according to claim 1, wherein: The transistor includes a high-K gate dielectric layer surrounding the channel and located on the bottom surface of the hard mask nanostructure, wherein the gate electrode is separated from the bottom surface of the hard mask nanostructure by the high-K gate dielectric layer, and wherein the gate electrode is in direct contact with the top surface of the hard mask nanostructure.

8. The integrated circuit device according to claim 1, wherein: The transistor comprises a high-K gate dielectric layer surrounding the channel, wherein the gate electrode comprises: A first gate metal is located on the high-K gate dielectric layer; a semiconductor layer, located on the first gate metal; and The second gate metal is located on the semiconductor layer.

9. An integrated circuit device comprising: A first transistor comprising a plurality of stacked first channels and a first hard mask nanostructure located above the first channels; a second transistor comprising a plurality of stacked second channels, and a second hard mask nanostructure located above the second channels; a high-K gate dielectric layer surrounding the first channel, the first hard mask nanostructure, the second channel, and the second hard mask nanostructure; a first gate metal in contact with the high-K gate dielectric layer at the first transistor and surrounding the first channel and the first hard mask nanostructure; as well as A second gate metal contacts the high-K gate dielectric layer at the second transistor and surrounds the second channel and the second hard mask nanostructure.

10. A method of forming an integrated circuit device, comprising: forming a plurality of stacked first channels of a first transistor; forming a first hard mask nanostructure of dielectric material over the first trench; as well as A first gate electrode of the first transistor is formed around the first channel and the first hard mask nanostructure.

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