Transistor, forming method thereof and method for forming gate stack of transistor

Abstract

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interface layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and / or surrounds the first semiconductor layer disposed over the second semiconductor layer. A gate dielectric and a work function layer (rather than a cap and / or bulk fill layer) fill the space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in the outer portion of the gate stack to oxygen in the inner portion of the gate stack may be from about 1 to about 1.25. A thickness of the work function layer at an inner portion of the gate stack may be less than a thickness of the work function layer at an outer portion of the gate stack. The embodiment of the invention also relates to a transistor, a method for forming the transistor and a method for forming a gate stack of the transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to transistors and methods of forming the same, and methods of forming gate stacks of transistors. Background Art

[0002] Multi-gate devices have been introduced to meet the semiconductor integrated circuit (IC) industry's growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. A multi-gate device has a gate that extends partially or completely around a channel region to provide access to the channel region on at least two sides. Exemplary multi-gate devices include fin field effect (FinFET) transistors, gate-all-around (GAA) transistors (e.g., transistors based on nanostructures (e.g., nanowires, nanosheets, or nanorods)), other three-dimensional (3D) transistors (e.g., fork-sheet transistors), or combinations thereof. Multi-gate devices enable aggressive scaling of IC technology and have been observed to improve gate control, increase gate-channel coupling, reduce off-state current, and reduce short channel effects (SCEs), while seamlessly integrating with conventional IC manufacturing processes.

[0003] However, as IC technology nodes continue to scale, it becomes challenging to manufacture gate stacks around the channel regions of multi-gate devices. For example, a gate stack of a multi-gate device is typically formed using a gate replacement process that includes removing a dummy gate to form a gate opening that exposes a channel layer and filling the gate opening with various gate layers (such as a gate dielectric and a gate electrode). Reducing device component size has led to a reduction in gate opening size and, therefore, a reduced gate stack volume. Therefore, a gate layer that wraps around a channel layer can easily fill the gate opening and / or the spacing between adjacent channel layers, which leaves limited space in the gate opening for precisely adjusting the threshold voltage (Vt) of a multi-gate device, for example, by using multiple work function layers and / or thicker work function layers. Various combinations and / or configurations of layers have been explored in gate stacks to maximize multi-gate device performance while minimizing performance mismatches (such as threshold voltage variations (σVt)) between multi-gate devices of an IC (such as those forming memories). Although existing gate stack configurations and methods of manufacturing the same for multi-gate devices have generally been adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a transistor, comprising: forming a first semiconductor layer and a second semiconductor layer over a substrate, wherein the first semiconductor layer is disposed over the second semiconductor layer and a gap is located between the first semiconductor layer and the second semiconductor layer; forming a gate dielectric over the first semiconductor layer and the second semiconductor layer, wherein the gate dielectric partially fills the gap between the first semiconductor layer and the second semiconductor layer; forming a work function layer on the gate dielectric, wherein the work function layer fills a remaining portion of the gap between the first semiconductor layer and the second semiconductor layer; and forming a cover over the work function layer.

[0005] Some other embodiments of the present application provide a method for forming a gate stack of a transistor, the method comprising: forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer, wherein the channel stack comprises the first channel layer disposed above the second channel layer, the first interface layer partially filling a gap between the first channel layer and the second channel layer, and the second interface layer partially filling the gap between the first channel layer and the second channel layer; forming a first high-k dielectric layer above the first interface layer and around the first channel layer and forming a second high-k dielectric layer above the second interface layer and around the second channel layer, wherein the first high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer; forming a work function layer around the first channel layer and the second channel layer, wherein the work function layer fills the gap between the first channel layer and the second channel layer. The work function layer is formed by depositing a work function material until a first portion of the work function material formed above the first high-k dielectric layer and around the first channel layer merges with a second portion of the work function material formed above the second high-k dielectric layer and around the second channel layer, wherein the first portion of the work function material merges with the second portion of the work function material in the space between the first channel layer and the second channel layer, and continuing to deposit the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material; and forming a cap over the work function layer, wherein the cap wraps around the channel stack, and forming the cap includes: forming a first metal nitride layer over the work function layer, and after breaking the vacuum, forming a second metal nitride layer over the first metal nitride layer, and forming a silicon-containing layer over the second metal nitride layer.

[0006] Some other embodiments of the present application provide a transistor, comprising: a first channel layer and a second channel layer; a gate stack, having: a gate dielectric, disposed around the first channel layer and the second channel layer, wherein the gate dielectric comprises an interface layer and a high-k dielectric layer disposed above the interface layer, and a gate electrode, disposed above the gate dielectric, wherein the gate electrode is located around the first channel layer and the second channel layer, and wherein the gate electrode comprises: a work function layer, disposed above the high-k dielectric layer, wherein the work function layer is located around the first channel layer and the second channel layer; and a cap, disposed on the work function layer. layer, wherein the cover includes a metal nitride layer disposed above the work function layer and a silicon layer disposed above the metal nitride layer; wherein the gate dielectric and the work function layer fill a gap between the first channel layer and the second channel layer; wherein an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, and a ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25; and wherein a first thickness of the work function layer in the outer region of the gate stack is greater than a second thickness of the work function layer in the inner region of the gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for fabricating part or all of a gate stack of a device according to various aspects of the disclosed embodiments.

[0009] Figure 2 A device (such as a transistor) according to various aspects of the present disclosure is provided in conjunction with a method (such as a gate stack) for manufacturing the device. Figure 1 A partial or whole stereoscopic view of a manufacturing stage related to the method).

[0010] FIG. 3A to FIG. 14A and FIG. 3B to FIG. 14B A device (such as a transistor) according to various aspects of the embodiments of the present disclosure is used to manufacture Figure 1 A partial or whole cross-sectional view of various manufacturing stages related to the method of manufacturing a gate stack.

[0011] Fig.15A and Fig. 15B is a device having a gate stack (which can be formed by Figure 1A cross-sectional view of part or all of a device (such as a transistor) manufactured by a method.

[0012] Fig.16A and Fig. 16B are energy dispersive x-ray spectroscopy (EDX) graphs of oxygen in inner and outer regions of gate stacks having different configurations according to various aspects of embodiments of the present disclosure.

[0013] Fig.17 is a cross-sectional view of a portion or the entirety of a stacked device structure according to various aspects of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The disclosed embodiments relate generally to integrated circuit (IC) devices, and more particularly, to gate stacks of transistors and methods of manufacturing the same.

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the disclosed embodiments. The specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to easily understand the relationship between one component and another component of the disclosed embodiments. Spatial relative terms are intended to cover different orientations of devices including components. The disclosed embodiments may also repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, when "about," "approximately," and the like are used to describe a value or a range of values, such terms are intended to encompass values ​​within a reasonable range taking into account variations that inherently occur during manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the values, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / -10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / -10%. In addition, in view of the differences inherent in any manufacturing process, when a device component is described as having "substantially" a property and / or feature, such terms are intended to capture the property and / or feature within the tolerance of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" component is intended to capture a component that is approximately vertical and horizontal - but not mathematically or perfectly vertical and horizontal - within a given tolerance of the manufacturing process used to manufacture such a component.

[0017] Multi-gate devices, such as fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, fork-sheet transistors, and other non-planar transistors, have gained popularity due to their enhanced performance compared to traditional planar transistors. As multi-gate device dimensions shrink to facilitate further IC technology node scaling, traditional multi-gate device manufacturing methods face challenges. For example, unintentional and / or undesired oxidation of gate stack layers, such as work function layers and / or gate dielectric layers, during the gate replacement process may result in performance degradation, such as slower device speed and / or threshold voltage (V t The problem is exacerbated for certain IC applications, such as static random access memory (SRAM) devices, where n-type transistor performance may be more important than p-type transistor performance.

[0018] To address these challenges, embodiments of the present disclosure propose gate stacks and corresponding gate stack manufacturing methods that reduce the oxygen difference between an inner portion (e.g., an inner film stack between channel layers) and an outer portion (e.g., an outer film stack not located between channel layers) of a gate stack. For example, the proposed gate stack omits a cap from its inner region, such as an off-site cap, configures its work function layer with different thicknesses in the inner region and the outer region, reduces the aluminum content of the work function layer, or a combination thereof. As described herein, because such a gate stack configuration takes into account and / or compensates for oxygen diffusion / migration that occurs during processing (such as this occurs when forming a cap), the oxygen difference between the inner region and the outer region of the proposed gate stack is reduced, thereby improving device reliability and / or performance, for example by providing faster device speeds and / or smaller threshold voltage variations. Details of an improved gate stack for a multi-gate device and methods for manufacturing and / or designing the same are described herein.

[0019] Figure 1 is a flow chart of a method 100 for fabricating a portion or all of a gate stack of a device according to various aspects of the disclosed embodiments. Figure 2 The device 200 according to various aspects of the embodiments of the present disclosure is used in conjunction with a method for manufacturing a gate stack (such as Figure 1 A perspective view of a portion or whole of a manufacturing stage associated with method 100). FIG. 3A to FIG. 14A and FIG. 3B to FIG. 14B The device 200 according to various aspects of the embodiments of the present disclosure is Figure 1 Partial or whole cross-sectional views of various manufacturing stages associated with method 100 . Figure 3A and Figure 3B The device 200 (eg, transistor) is Figure 2 The cross-sectional view of line AA and line BB, FIG. 4A to FIG. 14A The device 200 is Figure 1 The subsequent manufacturing stages of method 100 are along the Figure 2 A cross-sectional view of line AA, and FIG. 4B to FIG. 14B The device 200 is Figure 1 The subsequent manufacturing stages of method 100 are along the Figure 2 A cross-sectional view along line BB. Fig.15A and Fig. 15B is a device having a gate stack (which can be formed by Figure 1 The cross-sectional view of the device 200 with different configurations (manufactured by the method 100). For ease of description and understanding, this article also discusses Figure 1 , Figure 2 , FIG. 3A to FIG. 14A , FIG. 3B to FIG. 14B , Fig.15A and Fig. 15B. It has been simplified for clarity. Figure 1 , Figure 2 , FIG. 3A to FIG. 14A , FIG. 3B to FIG. 14B , Fig.15A and Fig. 15B , in order to better understand the inventive concept of the embodiments of the present disclosure. Figure 1 Additional steps are provided before, during, and after the method 100, and for Figure 1 In other embodiments of the method 100, some of the steps described may be moved, replaced, or eliminated. Additional components may be added to the device 200, and in other embodiments of the device 200, some of the components described below may be replaced, modified, or eliminated.

[0020] Go to Figure 1 , Figure 2 , Figure 3A and Figure 3B , method 100 includes, in box 105, forming a gate structure above the semiconductor stack. The gate structure includes a dummy gate and a gate spacer. This can include receiving and / or forming a device precursor, the device precursor including a substrate (wafer) 202, a semiconductor stack 210 (depicted as having a mesa 202' (i.e., a patterned, protruding portion of the substrate 202), a semiconductor layer 215, and a semiconductor layer 220), a substrate isolation structure 222, an internal spacer 224, a source / drain 225, a gate structure 230 (depicted as having a dummy gate 232 and a gate spacer 240), and a dielectric layer 250. The semiconductor stack 210 is located in a channel region C of the device 200, and the source / drain 225 is located in a source / drain region S / D of the device 200. In Figure 3A (e.g., XZ cross-sectional view), the semiconductor layer 220 and the mesa 202' extend along the X direction between the source / drain 225, the internal spacer 224 is located between the semiconductor layer 215 and the source / drain 225, and the gate structure 230 is disposed above the top of the semiconductor stack 210 and between the source / drain 225. Figure 3B (eg, YZ cross-sectional view), the gate structure 230 is located on the top and side of the semiconductor stack 210 , and the gate structure 230 wraps the semiconductor stack 210 .

[0021] The substrate 202 includes: an elemental semiconductor such as silicon and / or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In the depicted embodiment, the substrate 202 is a silicon substrate. In some embodiments, the substrate 202 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 202 (and the mesa 202') may include various doped regions such as a p-type doped region (e.g., a p-well), an n-type doped region (e.g., an n-well), or a combination thereof. The n-type doped region includes an n-type dopant such as phosphorus, arsenic, other n-type dopant, or a combination thereof. The p-type doped region includes a p-type dopant such as boron, indium, other p-type dopant, or a combination thereof. In some embodiments, the doped region includes a combination of a p-type dopant and an n-type dopant. The doped region can be formed directly on and / or in substrate 202, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, other suitable structures, or combinations thereof. In some embodiments, substrate 202, mesa 202', and semiconductor layers thereon include an n-well (such as where device 200 is a p-type transistor) or a p-well (such as where device 200 is an n-type transistor).

[0022] The semiconductor stack 210 extends along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. The semiconductor layer 215 and the semiconductor layer 220 are vertically stacked (e.g., along the z-direction) in a staggered and / or alternating configuration from the top surface of the substrate 202. The composition of the semiconductor layer 215 is different from the composition of the semiconductor layer 220 to achieve etching selectivity and / or different oxidation rates during subsequent processing. For example, the semiconductor layer 215 and the semiconductor layer 220 include different materials, component atomic percentages, component weight percentages, thicknesses, or combinations thereof to achieve desired etching selectivity during an etching process (such as an etching process implemented to form a suspended channel layer in the channel region C). In some embodiments, the semiconductor layer 215 includes silicon germanium, the semiconductor layer 220 includes silicon, and for a given etchant, the silicon etching rate of the semiconductor layer 220 is different from the silicon germanium etching rate of the semiconductor layer 215. In some embodiments, the semiconductor layer 215 and the semiconductor layer 220 include the same material but different component atomic percentages to achieve etching selectivity. For example, semiconductor layer 215 and semiconductor layer 220 include silicon germanium with different silicon atomic percentages and / or different germanium atomic percentages. The disclosed embodiments contemplate semiconductor layer 215 and semiconductor layer 220 having any combination of semiconductor materials that provide a desired etch selectivity, a desired oxidation rate difference, a desired performance characteristic (e.g., a material that maximizes current flow), or a combination thereof, including any of the semiconductor materials disclosed herein.

[0023] The substrate isolation structure 222 electrically isolates the active device regions and / or passive device regions of the device 200 from each other. For example, the substrate isolation structure 222 separates and electrically isolates the active region of the device 200 (e.g., its semiconductor stack 210 and / or source / drain 225) from other device regions and / or devices. The substrate isolation structure 222 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.), or a combination thereof. The substrate isolation structure 222 may have a multilayer structure. For example, the substrate isolation structure 222 may include a bulk dielectric (e.g., an oxide layer) located above a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride silicon, or a combination thereof). In another example, the substrate isolation structure 222 may include a dielectric layer located above a doped liner (such as a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The dimensions and / or characteristics of substrate isolation structure 222 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, substrate isolation structure 222 may be STI.

[0024] The internal spacer 224 is disposed below the gate spacer 240 and along the sidewall of the semiconductor layer 215. The internal spacer 224 is disposed between the semiconductor layer 215 and the source / drain 225 and separates the semiconductor layer 215 from the source / drain 225. The internal spacer 224 is also disposed between adjacent semiconductor layers 220 and between the bottommost semiconductor layer 220 and the mesa 202'. The internal spacer 224 includes a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxynitride carbon, and the like. In some embodiments, the internal spacer 224 includes a low-k dielectric material. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material, and the internal spacer 224 includes a doped dielectric material.

[0025] The source / drain 225 includes a semiconductor material and may be doped with an n-type dopant and / or a p-type dopant. When forming part of a p-type transistor, the source / drain 225 may include silicon germanium or germanium doped with boron, other p-type dopants, or a combination thereof. When forming part of an n-type transistor, the source / drain 225 may include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof. The source / drain 225 may include more than one semiconductor layer, wherein the semiconductor layers include the same or different materials and / or the same or different dopant concentrations. The source / drain 225 may include a material and / or dopant that achieves a desired tensile stress and / or compressive stress in the channel region C. In some embodiments, the source / drain 225 is formed using an epitaxial growth process, and the source / drain 225 may be referred to as an epitaxial source / drain. In some embodiments, a doped region (such as a heavily doped source / drain (HDD) region, a lightly doped source / drain (LDD) region, other doped regions, or a combination thereof) is disposed in the source / drain 225. In some embodiments, the doped region (such as the LDD region) may extend into the channel region C. As used herein, a source / drain region, a source / drain, a source / drain component, etc. may refer to a source of a device, a drain of a device, or a source and / or drain of multiple devices. In some embodiments, a bottom source / drain isolation structure may be formed between the substrate 202 and the source / drain 225.

[0026] The dummy gate 232 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the semiconductor stack 210. For example, the dummy gate 232 extends longitudinally along the y-direction, has a length along the y-direction, a width along the x-direction, and a height along the z-direction. Figure 3A In FIG. 2 , a dummy gate 232 is disposed on top of the semiconductor stack 210 . Figure 3BIn the embodiment of the present invention, the dummy gate 232 is disposed above the top and sidewalls of the semiconductor stack 210, and the dummy gate 232 wraps the semiconductor stack 210. The dummy gate 232 may include a dummy gate electrode and a dummy gate dielectric. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon (e.g., a polycrystalline gate), and the dummy gate dielectric includes a suitable dielectric material, such as silicon oxide (i.e., a dummy oxide). The dummy gate 232 may include additional layers, such as a hard mask layer (e.g., a nitride mask), other suitable layers, or combinations thereof.

[0027] The gate spacer 240 is adjacent to the sidewall of the dummy gate 232 and along the sidewall of the dummy gate 232. The gate spacer 240 may include a sealing spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, other suitable spacers, or a combination thereof. The gate spacer 240 may have a single-layer structure or a multi-layer structure. The gate spacer 240 includes a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable components, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, carbon oxynitride, etc.). For example, the gate spacer 240 may include silicon, oxygen, nitrogen, carbon, and hydrogen (i.e., the gate spacer 240 may be a SiONCH layer).

[0028] The dielectric layer 250 is disposed over the substrate 202, the substrate isolation structure 222, the source / drain 225, and the gate structure 230. The dielectric layer 250 may have a multi-layer structure, such as a contact etch stop layer (CESL) 252 and an interlayer dielectric (ILD) layer 254. The ILD layer 254 is formed over the CESL 252. The ILD layer 254 includes a dielectric material including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed by tetraethyl orthosilicate (TEOS), BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 254 includes a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k<3.9). In some embodiments, the ILD layer 254 includes a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low-k dielectric material), such as porous silicon oxide, silicon carbide, a carbon-doped oxide (e.g., a SiCOH-based material (having, for example, Si-CH3 bonds)), or a combination thereof. The CESL 252 includes a dielectric material different from the dielectric material of the ILD layer 254. For example, in the case where the ILD layer 254 includes silicon and oxygen (e.g., porous silicon oxide), the CESL 252 may include silicon and nitrogen, and the CESL 254 may be a silicon nitride layer, a silicon carbonitride layer, or a silicon carbon nitride oxide layer.

[0029] In some embodiments, the device precursor is received before and / or after the dielectric layer 250 is formed. The formation of the dielectric layer 250 may include: depositing dielectric material over the substrate 202, the substrate isolation structure 222, the source / drain 225, and the gate structure 230; and performing a planarization process, such as chemical mechanical polishing (CMP), on the dielectric material. The planarization process removes any dielectric material from over the gate structure 230. The dummy gate 232 may be used as a planarization stop layer, and the planarization process may be performed until the dummy gate 232 is reached. The planarization process may planarize the top surface of the dielectric layer 250 and the top surface of the gate structure 230. In some embodiments, the dielectric layer 250 is a device-level dielectric layer of a multi-layer interconnect (MLI) component that electrically connects devices (e.g., transistors, resistors, capacitors, inductors, etc.), components of a device (e.g., gates and / or source / drains), devices within an MLI component, components of an MLI component, or a combination thereof, so that the device and / or component can operate as specified by the design requirements.

[0030] Go to Figure 1 , Figure 4A and Figure 4B , the method 100 includes, in box 110, removing the dummy gate 232 to form a gate opening 255 exposing the semiconductor stack 210. The gate opening 255 has sidewalls formed by the gate spacer 240 and a bottom formed by the semiconductor stack 210 and / or the substrate isolation structure 222. In some embodiments, the etching process selectively removes the dummy gate 232 relative to the gate spacer 240, the dielectric layer 250, or a combination thereof. For example, the etching process etches the dummy gate 232 without (or negligibly) etching the gate spacer 240, the substrate isolation structure 222, the dielectric layer 250, or a combination thereof. The etchant of the etching process can etch polysilicon (i.e., the dummy gate 232) at a higher rate than the dielectric material (i.e., the gate spacer 240, the substrate isolation structure 222, the dielectric layer 250, etc.). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the patterned mask layer covers the dielectric layer 250 and / or the gate spacers 240 but exposes the dummy gate 232 during the etching process.

[0031] Go to Figure 1 , Figure 5A and Figure 5B, the method 100 may include, in block 115, performing a channel release process on the semiconductor stack to form a first channel layer disposed above the second channel layer. For example, the semiconductor layer 215 exposed by the gate opening 255 is selectively removed to form a gap 260 between the semiconductor layers 220 and between the semiconductor layers 220 and the mesas 202', thereby suspending the semiconductor layers 220 in the channel region C. In the depicted embodiment, three suspended semiconductor layers 220 are vertically stacked in the z direction (i.e., the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer that are vertically stacked and separated from each other by the gap 260), and the suspended semiconductor layers 220 provide three channels through which current can flow between the source / drain 225. Therefore, the suspended semiconductor layer 220 is hereinafter referred to as the channel layer 220'. The channel layer 220' has a width W along the y direction, a thickness T along the z direction, and a spacing S along the z direction. In some embodiments, the width W is about 10nm to about 60nm. In some embodiments, the thickness T is about 5 nm to about 10 nm. In some embodiments, the spacing S is about 5 nm to about 15 nm.

[0032] In some embodiments, the channel release process includes an etching process that selectively removes the semiconductor layer 215 relative to the semiconductor layer 220, the mesa 202', the gate spacer 240, the internal spacer 224, the substrate isolation structure 222, the dielectric layer 250, or a combination thereof. For example, the etching process etches the semiconductor layer 215, while not (or negligibly) etching the semiconductor layer 220, the mesa 202', the gate spacer 240, the internal spacer 224, the substrate isolation structure 222, the dielectric layer 250, or a combination thereof. The etchant of the etching process can etch silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220) and dielectric materials (i.e., the gate spacer 240, the internal spacer 224, the substrate isolation structure 222, the dielectric layer 250, etc.). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, before the etching process is performed, the oxidation process converts the semiconductor layer 215 into a semiconductor oxide component (e.g., silicon germanium oxide), and then the etching process removes the semiconductor oxide component. In some embodiments, during and / or after the semiconductor layer 215 is removed, an etching process is performed to modify the profile of the semiconductor layer 220 to achieve a target size and / or target shape for the channel layer 220', such as a cylindrical channel layer (e.g., nanowire), a rectangular channel layer (e.g., nanorod), a sheet-shaped channel layer (e.g., nanosheet), etc.

[0033] Go to Figure 1 , FIG. 6A to FIG. 14A and FIG. 6B to FIG. 14B, the method 100 includes, in block 120, forming a gate stack in the gate opening 255. The gate stack includes a gate dielectric 230A (e.g., at least one dielectric gate layer) and a gate electrode 230B (e.g., at least one conductive gate layer, such as a work function layer and / or a bulk / fill metal layer). The gate stack fills the gate opening 255 and, in the depicted embodiment, fills the air gap 260 (see FIG. 2 ). Fig.14A and Fig. 14B For example, the gate stack is disposed between the channel layers 220' and between the channel layers 220' and the mesas 202'. In the XZ plane ( Fig.14A ), the gate stack is disposed between the gate spacers 240 and between the inner spacers 224. In the YZ plane ( Fig. 14B ), the gate stack at least partially surrounds (eg, surrounds) the channel layer 220 ′. The gate stack may include more or fewer layers than depicted and described herein. The gate stack and gate spacer 240 may be collectively referred to as a gate structure 230.

[0034] refer to Figure 1 , Fig. 6A and Figure 6B The method 100 includes forming an interfacial layer 262 in the gate opening 255 in block 125. The interfacial layer 262 partially fills the gate opening 255 and partially fills the gap 260 (ie, the spacer) between the channel layers 220'. The interfacial layer 262 includes a dielectric material such as SiO2, SiGeO x , HfSiO, SiON, other dielectric materials, or combinations thereof. In some embodiments, the interfacial layer 262 is formed on semiconductor surfaces (e.g., channel layer 220' and mesa 202'), but not on dielectric surfaces (e.g., internal spacers 224, substrate isolation structures 222, gate spacers 240, and dielectric layer 250), such as depicted. For example, the interfacial layer 262 can be formed by an oxidation process, such as thermal oxidation and / or chemical oxidation, in which oxygen reacts with the semiconductor surface to form a semiconductor oxide (i.e., the interfacial layer 262), but does not react with the dielectric surface. Fig. 6A In the embodiment, the interface layer 262 covers the top surface of the channel layer 220', the bottom surface of the channel layer 220' and the top surface of the mesa 202'. Figure 6B In some embodiments, the interface layer 262 surrounds the channel layer 220' and wraps around the mesa 202'. In some embodiments, the interface layer 262 is formed by atomic layer deposition (ALD) and / or other suitable methods. In some embodiments, the interface layer 262 has a substantially uniform thickness, such as depicted. In some embodiments, the interface layer 262 has a thickness of about to about Thickness.

[0035] refer to Figure 1 , Fig. 7A and Figure 7B , the method 100 includes, in block 130, forming a high-k dielectric layer 264 over the interface layer 262. The high-k dielectric layer 264 partially fills the gate opening 255 and partially fills the gap 260 (i.e., the spacer) between the channel layers 220'. The high-k dielectric layer 264 can be formed over the gate spacer 240, the inner spacer 224, the substrate isolation structure 222, and the dielectric layer 250 (e.g., when formed by a conformal deposition process). The high-k dielectric layer 264 includes a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3P4, HfO2-Al2O3, other high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a dielectric constant greater than the dielectric constant of silicon dioxide (k≈3.9). For example, high-k dielectric layer 264 is a hafnium-based oxide (e.g., HfO2) layer or a zirconium-based oxide (e.g., ZrO2) layer. In Fig. 7A In FIG. 2 , the high-k dielectric layer 264 has a u-shaped profile in the top portion of the gate opening 255 and has a rectangular profile in the bottom portion of the gate opening 255 (ie, in the gap 260 ). Figure 7B In the embodiment, the high-k dielectric layer 264 surrounds the channel layer 220' and wraps the mesa 202'. The high-k dielectric layer 264 is formed by ALD, CVD, physical vapor deposition (PVD), other suitable processes, or combinations thereof. The thickness of the high-k dielectric layer 264 is greater than the thickness of the interface layer 262. In some embodiments, the thickness of the high-k dielectric layer 264 is about to about In some embodiments, high-k dielectric layer 264 has a substantially uniform thickness, such as depicted.

[0036] refer to Figure 1 , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B, the method 100 includes, at block 135, forming a work function layer 272 on the high-k dielectric layer 264. The work function layer 272 partially fills the gate opening 255 and fills the remaining portion (i.e., the spacing) of the gap 260 between the channel layers 220'. In the depicted embodiment, the gaps 260 between the channel layers 220' and between the bottommost channel layer 220' and the mesa 202' are thus filled with the work function layer 272 and the gate dielectric 230A (e.g., the high-k dielectric layer 264 and the interfacial layer 262). Fig.9A In FIG. 2 , the work function layer 272 has a u-shaped profile in the top portion of the gate opening 255 and has a rectangular profile in the bottom portion of the gate opening 255 (ie, in the gap 260 ). Fig. 9B In the embodiment of the present invention, the work function layer 272 surrounds the channel layer 220 ′ and wraps the mesa 202 ′.

[0037] The work function layer 272 is formed by ALD, CVD, PVD, other suitable processes, or combinations thereof. In the depicted embodiment, the work function layer 272 is formed by: depositing a work function material in the gate opening 255 (including the gap 260) to form a work function layer 272' around the channel layer 220', the work function layer 272' merges together and fills the remaining portion of the gap 260 ( Fig. 8A and Figure 8B ); and continuing to deposit work function material in the gate opening 255 to increase the thickness of the outer region of the work function layer 272' (ie, those portions not located between the channel layers 220') and increase the merging of the work function layer 272' ( Fig.9A and Fig. 9B ), so that the work function layer 272' around the channel layer 220' is combined to form the work function layer 272. Fig. 8A and Figure 8B When merged between the channel layers 220' and filling the remaining portion of the gap 260, the work function layer 272' has a thickness t1. In some embodiments, the thickness t1 is about to about In some embodiments, the thickness t1 is about 1 / 2 of the spacing S between the channel layers 220'. Fig.9A and Fig. 9B In the embodiment, the thickness of the outer region of the work function layer 272' is increased by a thickness t2. In some embodiments, the thickness t2 is about to about In some embodiments, thickness t2 is less than thickness t1. In some embodiments, thickness t2 is greater than thickness t1. In some embodiments, thickness t2 is approximately equal to thickness t1. In some embodiments, work function layer 272' is formed by a conformal deposition process, and work function layer 272' has a substantially uniform thickness. For example, thickness t1 of each of work function layers 272' may be the same along the top, bottom, and both sidewalls of corresponding channel layer 220'.

[0038] The thickness of the outer region of the work function layer 272 (i.e., those portions along the sidewalls of the channel layer 220' and along the top of the top channel layer 220') is therefore greater than the thickness of the inner region of the work function layer 272 (i.e., those portions between the channel layers 220' and between the bottom channel layer 220' and the mesa 202'). For example, the portion of the work function layer 272 located around the top channel layer 220' has an outer thickness T O and the inner thickness T I , and the outer thickness T O Greater than the inner thickness T I The portion of the work function layer 272 has an outer thickness T along the top and sidewalls of the top channel layer 220 ′. O , and a portion of the work function layer 272 has an inner thickness T along the bottom of the top channel layer 220 ′. I In the depicted embodiment, the outer thickness T O is the sum of thickness t1 and thickness t2, and the inner thickness T I is the thickness t1. In some embodiments, the outer thickness T O About to about In some embodiments, the inner thickness T I About to about In some embodiments, the inner thickness T I is about 1 / 2 of the interval S between the channel layers 220 ′. In addition, a portion of the work function layer 272 located around the middle channel layer 220 ′ may have an outer thickness T along the sidewall of the middle channel layer 220 ′. O and the inner thickness T along the top and bottom of the middle channel layer 220 ′ I , and a portion of the work function layer 272 located around the bottom channel layer 220 ′ may have an outer thickness T along the sidewall of the bottom channel layer 220 ′. O and the inner thickness T along the top and bottom of the bottom channel layer 220 ′ I .

[0039] The work function layer 272 is a conductive layer adjusted to have a desired work function. The work function layer 272 may be an n-type work function metal (N-WFM) layer, a p-type work function metal (P-WFM) layer, or a combination thereof. The N-WFM layer (also referred to as an n-metal layer) includes an n-type work function material, which generally refers to a conductive material adjusted to have an n-type work function, and the p-WFM layer (also referred to as a p-metal layer) includes a p-type work function material, which generally refers to a conductive material adjusted to have a p-type work function. The n-type work function material may include a metal having a sufficiently low effective work function, such as aluminum, titanium, tantalum, zirconium, other n-metals, their alloys, or a combination thereof. In some embodiments, the N-WFM layer is a titanium aluminum layer, a titanium aluminum carbide layer, a tantalum carbide layer, a tantalum carbonitride layer, or a tantalum silicon nitride layer. The p-type work function material may include a metal having a sufficiently high effective work function, such as titanium, tantalum, ruthenium, molybdenum, tungsten, platinum, other p-metals, their alloys, or a combination thereof. In some embodiments, the P-WFM layer is a titanium nitride layer, a titanium carbide layer, a titanium silicon nitride layer, a tantalum nitride layer, a tungsten carbonitride layer, or a molybdenum layer. In some embodiments, the work function layer has a multilayer structure, such as more than one N-WFM layer, more than one P-WFM layer, or an N-WFM layer and a P-WFM layer. In some embodiments, the work function layer 272 is adjusted to have an n-type work function or a p-type work function, depending on the type of transistor to which it belongs. For example, when the device 200 is configured as an n-type transistor, the work function layer 272 can be an N-WFM layer, and when the device 200 is configured as a p-type transistor, the work function layer 272 can be a P-WFM layer.

[0040] In the depicted embodiment, the work function layer 272 is an N-WFM layer formed by ALD, such as a titanium aluminum carbide (TiAlC) layer or a titanium aluminide (TiAl) layer. For example, the work function layer 272 includes titanium, aluminum, and carbon. In another example, the work function layer 272 includes titanium and aluminum. The aluminum concentration / content in the work function layer 272 depends on the thickness of the work function layer 272. For example, the aluminum content in the work function layer 272 is inversely proportional to the thickness of the work function layer 272, and in order to maintain a desired threshold voltage, the aluminum content in the work function layer 272 can be increased or decreased, depending on the thickness of the work function layer 272. Therefore, if the desired threshold voltage corresponds to a work function layer having a given thickness and a given aluminum content, and the work function layer 272 is configured to have a thickness less than the given thickness, the aluminum content can be configured to be greater than the given aluminum content to maintain the desired threshold voltage (i.e., the aluminum content increases as the thickness decreases). Furthermore, if the work function layer 272 is configured to have a thickness greater than a given thickness, the aluminum content of the work function layer 272 can be configured to be less than a given aluminum content to maintain a desired threshold voltage (i.e., the aluminum content decreases as the thickness increases). In the depicted embodiment, because the thickness of the work function layer 272 increases to fill the remaining portion of the gap 260 (i.e., the work function layer 272 is thicker), the work function layer 272 can be configured to have a lower aluminum content to obtain a given threshold voltage. For example, having less than about (For example, to about ) of the work function layer 272 (which will not fill the remainder of the gap 260 between the channel layers 220') can have an aluminum content greater than 33 atomic percent (at%) (e.g., about 40 at%) to obtain a desired threshold voltage, and in the depicted embodiment, greater than (For example, about to about ) of a total thickness of about 25 at % to about 33 at % aluminum content to obtain the same desired threshold voltage. A thicker work function layer 272 having an aluminum content of less than about 25 at % may not maintain the desired threshold voltage, while a thicker work function layer 272 having an aluminum content of greater than about 33 at % may undesirably increase gate resistance. Configuring the work function layer 272 to have a lower aluminum content (e.g., about 25 at % to about 33 at %) reduces gate resistance, particularly gate resistance associated with inner portions of the gate stack, such as those portions that fill the gaps 260 between the channel layers 220' and / or the gaps 260 between the channel layers 220' and the mesas 202'.

[0041] refer to Figure 1 , FIG. 10A to FIG. 12A and FIG. 10B to FIG. 12B , the method 100 includes, at block 140, forming a cap 274 over the work function layer 272. Fig. 12A and Fig. 12B In the embodiment, the cap 274 includes a capping layer 276 and a capping layer 278, and the composition of the capping layer 276 is different from the composition of the capping layer 278. For example, the capping layer 276 is a metal-containing layer, such as a metal nitride layer, and the capping layer 278 is a semiconductor-containing layer, such as a silicon layer. In some embodiments, block 140 includes: forming a metal nitride layer (e.g., capping layer 276) over the work function layer 272 (see Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B ); and forming a silicon-containing layer (eg, capping layer 278) over the metal nitride layer (see Fig. 12A and Fig. 12B In some embodiments, forming the capping layer 276 includes: forming a first portion of the capping layer 276 (eg, a capping sublayer 276A thereof) above the work function layer 272 ( Fig. 10A and Fig. 10B ); and after breaking the vacuum, forming a second portion of the covering layer 276 (eg, its covering sublayer 276B) ( Fig.11A and Fig. 11B ). In the depicted embodiment, because capping layer 276 is a metal nitride layer, capping sublayer 276A and capping sublayer 276B are metal nitride sublayers. In some embodiments, capping layer 276 has more than two sublayers, wherein the vacuum may be broken after forming each sublayer, or the vacuum may be broken after forming some sublayers but not after forming other sublayers. In some embodiments, capping layer 278 has a multilayer structure. In some embodiments, lid 274 has more than two capping layers.

[0042] refer to Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B , a capping sublayer 276A is formed over the work function layer 272 and partially fills a top portion of the gate opening 255 ( Fig. 10A , Fig. 10B ), and a capping sublayer 276B is formed over the capping sublayer 276A and partially fills a top portion of the gate opening 255 ( Fig.11A , Fig. 11B ). Because the work function layer 272 fills the remaining portion of the bottom portion of the gate opening 255 (i.e., the gap 260), the capping sublayer 276A and the capping sublayer 276B are not formed in the space between the adjacent channel layers 220'. The capping sublayer 276A and the capping sublayer 276B are formed by ALD, CVD, PVD, other suitable processes, or combinations thereof. Fig. 10A and Fig.11A In FIG. 1 , the cover sublayer 276A and the cover sublayer 276B have a U-shaped profile. Fig. 10B and Fig. 11B In the embodiment, the capping sublayer 276A and the capping sublayer 276B wrap the channel layer 220 ′.

[0043] As noted, the capping sublayer 276A and the capping sublayer 276B are metal nitride layers, which may include TiN, TiSiN, TaSiN, TaN, TaCN, WN, WCN, other metal nitrides, or combinations thereof. In some embodiments, the capping sublayer 276A and the capping sublayer 276B include the same metal nitride material. For example, the capping sublayer 276A and the capping sublayer 276B include titanium and nitrogen, and the capping sublayer 276A and the capping sublayer 276B are TiN sublayers. In some embodiments, the capping sublayer 276A and the capping sublayer 276B include different metal nitride materials. The thickness of the capping sublayer 276A may be greater than the thickness of the capping sublayer 276B. In some embodiments, the thickness of the capping sublayer 276A is about to about In some embodiments, the thickness of the cover sublayer 276B is about to about In some embodiments, the total thickness of the cover layer 276 (eg, the sum of the thickness of the cover sublayer 276A and the thickness of the cover sublayer 276B) is about 1000 Å. to about In some embodiments, the thickness of the cover sub-layer 276A is less than the thickness of the cover sub-layer 276B. In some embodiments, the thickness of the cover sub-layer 276A is the same as the thickness of the cover sub-layer 276B.

[0044] The capping sublayer 276B and the capping sublayer 276A are formed "ex situ," which generally refers to breaking vacuum between processes. For example, when forming the capping sublayer 276A and forming the capping sublayer 276B, the device 200 is contained in an environment under vacuum conditions, but between forming the capping sublayer 276A and forming the capping sublayer 276B, the device 200 is not maintained under vacuum conditions (i.e., the device 200 may be exposed to oxygen). In other words, the vacuum is broken between forming the capping sublayer 276A and forming the capping sublayer 276B, such that the device 200 is exposed to air (e.g., atmospheric oxygen) between these process steps. In some embodiments, the capping sublayer 276A and the capping sublayer 276B are formed in the same process chamber, and the vacuum is broken between forming the capping sublayer 276A and forming the capping sublayer 276B. In some embodiments, the capping sublayer 276A and the capping sublayer 276B are formed in different process chambers of a semiconductor process tool and / or a semiconductor process system, and the vacuum is broken when the device 200 is transferred from the process chamber for forming the capping sublayer 276A to the process chamber for forming the capping sublayer 276B. In some embodiments, the capping sublayer 276A and the capping sublayer 276B are formed in different semiconductor process tools and / or different semiconductor process systems, and the vacuum is broken when the device 200 is transferred between semiconductor process tools and / or semiconductor process systems.

[0045] Because the vacuum is broken when the capping layer 276 is formed, the capping layer 276 is referred to as an ex-situ capping layer, and the cap 274 may be referred to as an ex-situ cap. In some embodiments, before forming the capping sublayer 276B, breaking the vacuum exposes the capping sublayer 276A to an oxygen environment. For example, when the vacuum is broken (i.e., the device 200 is no longer in an environment with vacuum conditions), the capping sublayer 276A is exposed to air (e.g., atmospheric oxygen), and the capping sublayer 276A may absorb oxygen from the oxygen environment, which may combine with the metal and thus provide the capping sublayer 276A with a metal-oxygen bond. As the capping sublayer 276A absorbs oxygen, the exposed surface of the capping sublayer 276A may be converted into a thin metal oxide layer and / or a thin metal oxynitride layer, which is depicted as an oxidized surface 276O (also referred to as an oxide layer 276O). The oxide layer 276O may include metal-oxygen bonds, metal-nitrogen bonds, metal-oxygen-nitrogen bonds, or combinations thereof. In some embodiments, the oxide layer 276O of the capping sublayer 276A has a thickness of about 0.1 nm to about 0.2 nm. In embodiments where the capping sublayer 276A includes metal-oxygen bonds before breaking the vacuum, such as in embodiments where the capping sublayer 276A includes oxygen during processing of the device 200 and / or embodiments where oxygen has diffused into the capping sublayer 276A, the metal-oxygen bonds of the capping sublayer 276A can increase as the capping sublayer 276A absorbs oxygen from an oxygen environment. Forming and / or increasing metal-oxygen bonds in the capping sublayer 276A can reduce and / or repair oxygen vacancies therein, which can mitigate oxygen diffusion from the cap 274 and / or subsequently formed layers to the work function layer 272 and / or the gate dielectric 230A during fabrication of the device 200, thereby reducing unintended oxidation and minimizing threshold voltage changes and / or other device performance changes (e.g., reductions in speed and / or mobility) caused by such oxidation. In addition, reducing and / or repairing oxygen vacancies can reduce gate resistance. In the depicted embodiment, where the capping sublayer 276A is a TiN sublayer, the TiN sublayer may absorb oxygen from an oxygen environment, which forms and / or increases Ti-O bonds of the TiN sublayer. In such an embodiment, the oxide layer 276O and / or the capping sublayer 276A may include Ti-N bonds, Ti-O bonds, Ti-ON bonds, or combinations thereof.

[0046] refer to Fig. 12A and Fig. 12B , a capping layer 278 is formed over the capping layer 276 (e.g., over the capping sublayer 276B thereof). The capping layer 278 partially fills the top portion of the gate opening 255. Because the work function layer 272 fills the remaining portion of the bottom portion of the gate opening 255 (i.e., the gap 260), the capping layer 278 is not formed in the space between adjacent channel layers 220'. Fig. 12A In FIG. 2 , the capping layer 278 has a U-shaped profile in the top portion of the gate opening 255 . Fig. 12BIn the embodiment, the capping layer 278 wraps the channel layer 220 ′.

[0047] The capping layer 278 includes a material with a strong oxygen affinity, which can prevent oxygen from diffusing into the work function layer 272 and mitigate threshold voltage drift that may be caused by oxidation of the work function metal. For example, the capping layer 278 is a silicon-containing layer that can include silicon, polysilicon, amorphous silicon, or a combination thereof. In some embodiments, the thickness of the capping layer 278 is about 1000 Å. to about In the depicted embodiment, the thickness of capping layer 278 is less than the thickness of capping layer 276. In some embodiments, the thickness of capping layer 278 is greater than the thickness of capping layer 276. In some embodiments, the thickness of capping layer 278 is the same as the thickness of capping layer 276. Capping layer 278 is formed by ALD, CVD, PVD, other suitable processes, or combinations thereof. In some embodiments, capping layer 278 is formed ex situ (e.g., vacuum is broken between forming capping sublayer 276B and capping layer 278). In some embodiments, capping layer 278 is implemented in situ (e.g., vacuum is not broken between forming capping sublayer 276B and capping layer 278).

[0048] refer to Figure 1 , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B , the method 100 includes, at block 145, forming a bulk (fill) layer 280 over the cap 274. The bulk / fill layer 280 fills the remaining portion of the gate opening 255. Fig.14A In FIG. 2 , the bulk layer 280 has a U-shaped profile in the top portion of the gate opening 255 . Fig. 14B In the embodiment of the present invention, the bulk layer 280 wraps around the channel layer 220'. Because the work function layer 272 fills the remaining portion of the bottom portion of the gate opening 255 (ie, the gap 260), the bulk / filling layer 280 is not formed in the space between adjacent channel layers 220'.

[0049] The bulk / filling layer 280 includes a conductive material such as Al, W, Cu, Ti, Ta, polysilicon, other suitable metals and / or alloys thereof or combinations thereof. Fig.13A and Fig. 13B, a conductive material is deposited (e.g., by ALD, CVD, PVD, other suitable processes, or combinations thereof) over dielectric layer 250 and fills gate opening 255. In some embodiments, bulk layer 280 is a tungsten layer formed by PVD or CVD. In some embodiments, bulk layer 280 is a fluorine-free tungsten (FFW) layer. In some embodiments, bulk layer 280 is formed ex situ (e.g., vacuum is broken between forming capping layer 278 and bulk layer 280). In some embodiments, bulk layer 280 is implemented in situ (e.g., vacuum is not broken between forming capping layer 278 and bulk layer 280).

[0050] In some embodiments, the bulk layer 280 has a multi-layer structure, such as a glue layer and a metal filling layer, such as a tungsten layer. The glue layer may include a material that promotes adhesion between adjacent layers (such as between the work function layer 272 / cover 274 and the subsequently formed metal filling layer) and / or prevents or eliminates diffusion and / or reaction of components between adjacent layers. For example, the glue layer may include a metal and nitrogen, such as TiN, TaN, W2N, TiSiN, TaSiN, other suitable metal nitride materials, or a combination thereof. The glue may be formed ex situ (e.g., vacuum is broken between forming the cover layer 278 and the glue layer) or in situ (e.g., vacuum is not broken between forming the cover layer 278 and the glue layer). The metal filling layer may be formed ex situ (e.g., vacuum is broken between forming the glue layer and the metal filling layer) or in situ (e.g., vacuum is not broken between forming the glue layer and the metal filling layer).

[0051] refer to Fig.14A and Fig. 14B , a planarization process is performed to remove excess gate material, such as those disposed above the dielectric layer 250. For example, the CMP process removes portions of the bulk layer 280, the cap 274 (e.g., the cap layer 276 and the cap layer 278), the work function layer 272, and the high-k dielectric layer 264 disposed above the dielectric layer 250. The CMP process may be performed until the top surface of the dielectric layer 250 is reached and / or exposed. In some embodiments, the CMP process may continue to reduce the thickness of the dielectric layer 250, and correspondingly, reduce the height of the gate structure 230 (e.g., of its gate stack). In the depicted embodiment, the top of the gate structure 230 is substantially flush with the top of the dielectric layer 250 after the planarization process, and the remaining portion of the gate material (which fills the gate opening 255) forms the gate stack of the gate structure 230.

[0052] Thus, the method 100 provides a device 200 having a gate stack having a gate dielectric 230A (e.g., an interface layer 262 and a high-k dielectric layer 264) and a gate electrode 230B (e.g., a bulk / filling layer 280, a cap 274 (e.g., a cap layer 276 and a cap layer 278), and a work function layer 272). Because the gate dielectric 230A includes the high-k dielectric layer 264, the gate stack can be referred to as a high-k / metal gate. As noted above, introducing a vacuum break when forming the cap layer 276 (and thus introducing oxygen into the gate stack) can improve the performance of the device by reducing oxidation, minimizing threshold voltage variation, increasing its speed and / or mobility, or a combination thereof. However, it has been observed that when the capping layer 276 is incorporated and / or formed in the inner region of the gate stack (i.e., those regions between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202'), the amount of oxygen in the outer region of the gate stack (e.g., those regions not located between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202') is greater than the amount of oxygen in the inner region of the gate stack, which causes an undesirable threshold voltage change. The disclosed gate stack reduces the oxygen difference between the inner region and the outer region by filling the spaces between adjacent channel layers 220' and / or between the bottom channel layer 220' and the mesa 202' with the work function layer 272, so that the capping layer 276 is not incorporated and / or formed in the inner region of the gate stack.

[0053] refer to Fig.16A and Fig. 16B , Fig.16A is an energy dispersive x-ray spectroscopy (EDX) graph 300A of oxygen in the inner and outer regions of a gate stack having a cap (eg, portion of cap layer 276) in the inner region according to various aspects of embodiments of the present disclosure, and Fig. 16B300B is an EDX graph of oxygen in the inner and outer regions of a gate stack without a cap in the inner region, such as the gate stack of device 200, according to various aspects of embodiments of the present disclosure. Each of EDX graph 300A and EDX graph 300B has a y-axis representing oxygen concentration (in arbitrary units) and an x-axis representing position within the gate stack (in nanometers (nm)). EDX graph 300A and EDX graph 300B provide outer oxygen distributions obtained from outer film stacks of their respective gate stacks, such as outer film stack 302A and outer film stack 302B, and the outer oxygen distributions are represented by curves 304A and curves 304B, respectively. The outer film stack may include an interface (IL) layer (e.g., interface layer 262), a high-k dielectric (HK) layer (e.g., high-k dielectric layer 264), a work function (WF) layer (e.g., work function layer 272), and a cap layer formed by cap 1 (e.g., cap layer 276) and cap 2 (e.g., cap layer 278). The outer film stack 302A and the outer film stack 302B may be portions of the gate stack that are disposed along the sidewalls of the corresponding channel layers or disposed above the top of the corresponding topmost channel layers. The outer film stack 302A is different from the outer film stack 302B. For example, the thickness of the WF layer of the outer film stack 302A is less than the thickness of the WF layer of the outer film stack 302B, and the total thickness of the caps (e.g., cap 1 and cap 2) of the outer film stack 302A is greater than the thickness of the caps of the outer film stack 302B.

[0054] EDX graphs 300A and 300B also provide internal oxygen distributions obtained from the internal film stacks of their corresponding gate stacks (such as internal film stacks 310A and internal film stacks 310B), and the internal oxygen distributions are represented by curves 312A and curves 312B, respectively. The internal film stack may include an IL layer (e.g., an interface layer 262) and a HK layer (e.g., a high-k dielectric layer 264). The internal film stack 310A is different from the internal film stack 310B. For example, the internal film stack 310A also includes a WF layer (e.g., a work function layer 272) and a portion of a capping layer, such as a portion of the cover 1 (e.g., a capping layer 276), while the internal film stack 310B also includes a WF layer (e.g., a work function layer 272), but does not include a portion of a capping layer. The internal film stack 310A and the internal film stack 310B may be portions of the gate stack located between adjacent channel layers (such as between the corresponding topmost channel layer and the corresponding intermediate channel layer). Thus, the gate stack corresponding to the EDX map 300B does not include a cap between adjacent channel layers and may be configured like the gate stack of the device 200 described herein.

[0055] For the gate stack corresponding to the EDX map 300A, the region 320A of the EDX map 300A corresponds to the gate electrode portion of the gate stack that forms a portion of the outer film stack 302A and the inner film stack 310A. As shown by the curves 304A and 312A, in the region 320A, the outer oxygen concentration and the inner oxygen concentration are substantially similar (i.e., the difference between them is relatively small) until the WF layer reaches a thickness t, at which point the outer oxygen concentration begins to increase and the inner oxygen concentration begins to decrease. Therefore, the oxygen content of the upper portion of the WF layer in the outer film stack 302A is greater than the oxygen content of the upper portion of the WF layer in the inner film stack 310A, and the oxygen content of the lower portion of the cap 1 in the outer film stack 302A is greater than the oxygen content of the lower portion of the cap 1 in the inner film stack 310A. In some examples, it has been observed that a gate stack configured as a gate stack corresponding to EDX map 300A has a ratio of oxygen in the outer region to oxygen in the inner region of about 1.3 to about 1.5 (e.g., about 1.4). Such oxygen differences and / or oxygen ratios may undesirably increase the threshold voltage, for example, to about 70 millivolts (mV) to about 80 mV.

[0056] In contrast, as shown by curves 304B and 312B in region 320B of EDX map 300B, which corresponds to the gate electrode portion of the gate stack that forms a portion of the outer film stack 302B and the inner film stack 310B, the outer oxygen concentration and the inner oxygen concentration are substantially similar (i.e., the difference between them is relatively small) for the entire thickness of region 320B. Therefore, although the oxygen content of the outer film stack 302B may be slightly greater than the oxygen content of the inner film stack 310B, the difference between them is significantly less than the difference provided when both the cap 1 and the WF layer form the remainder of the inner film stack (such as the inner film stack 310A). Therefore, a gate stack configured as a gate stack corresponding to EDX map 300B (such as disclosed herein) can reduce the ratio of oxygen in the outer region of the gate stack to oxygen in the inner region. In some examples, a gate stack configured as a gate stack corresponding to EDX map 300B, such as the gate stack of device 200, has a ratio of oxygen in the outer region to oxygen in the inner region of about 1.0 to about 1.25 (e.g., about 1.1). Such an oxygen difference and / or oxygen ratio can reduce the threshold voltage, for example, to about 40 mV to about 50 mV, which can improve performance.

[0057] In addition, relative to the thickness of the WF layer in the inner film stack 310B (eg, T I ) Increase the thickness of the WF layer in the outer film stack 302B (e.g., T O) can reduce oxygen migration and / or diffusion into the inner film stack 310B. For example, the WF layer of the gate stack corresponding to the EDX map 300B is configured to have a sacrificial / buffer portion (i.e., a portion of the WF layer deposited / grown after filling the space between the adjacent channel layers (e.g., having a thickness t2)), which can compensate for the oxygen diffusion and / or migration into the WF layer that occurs when the cap 1 and / or other subsequently deposited gate stack layers are formed. In other words, the outer film stack 302B is configured to take into account the diffusion of oxygen into the WF layer and provide a greater distance between the cap 1 and the portion of the WF layer belonging to the inner film stack 310B. Therefore, as shown by curve 304B in the area of ​​the EDX map 300B corresponding to the sacrificial portion of the WF layer, the oxygen content of the sacrificial portion of the WF layer begins to increase, and the oxygen content of the WF layer of the outer film stack 302B decreases from a first oxygen concentration to a second oxygen concentration, and then increases from the second oxygen concentration to a third oxygen concentration that is less than the first oxygen concentration.

[0058] Reference again Fig.14A and Fig. 14B The disclosed gate stack having an inner film stack formed of a gate dielectric and a low aluminum content work function layer (e.g., less than about 33 at %) and methods of manufacturing the same provide several advantages. When compared to a device having a gate stack configured with an inner film stack having a gate dielectric, a high aluminum content work function layer (e.g., greater than 33 at % to compensate for its thinness), and an ex situ cap (e.g., a portion of a metal nitride layer), the gate stack of device 200 (with the cap omitted from its inner film stack) can reduce gate induced leakage current (I gi ) is about 0.5x to about 0.8x, subthreshold leakage current (I sb ), total gate resistance (R g ) (in some instances, up to 40%), improved time dependent dielectric breakdown (TDDB), or a combination thereof. Such improvements may be achieved while maintaining and / or reducing a desired threshold voltage and / or reducing a threshold voltage variation between an inner film stack and an outer film stack of a gate stack. Different embodiments may have different advantages, and no particular advantage is required of any embodiment.

[0059] refer to Fig.15A and Fig. 15B In some embodiments, when the reference Fig. 8A and Figure 8BWhen the work function material 272' is deposited as described, the portion of the work function material 272' along the sidewall of the channel layer 220' can merge together at the end of the gap 260 before completely filling the middle of the gap 260, so that an air gap 290 (also referred to as a void) can be formed within the work function layer 272 in the interval between the channel layers 220'. In such an embodiment, a corresponding air gap 290 is formed between a portion of the work function material 272' formed along the bottom of the first of the channel layers 220' and a portion of the work function material 272' formed along the top of the second of the channel layers 220'. The air gap 290 can have a variety of shape profiles, and in some embodiments, more than one air gap can be formed in the interval between adjacent channel layers 220'. In the depicted embodiment, the length of the air gap 290 is greater than or equal to the width of the channel layer 220'. In some embodiments, the length of the air gap 290 is less than the width of the channel layer 220'.

[0060] In some embodiments, the process may further include: etching back the gate electrode 230B and / or the gate dielectric 230A; and forming a hard mask, such as a self-aligned cap (SAC), over the etched back gate electrode 230B and / or the gate dielectric 230A. The hard mask may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium oxide aluminum, hafnium oxide, other suitable dielectric materials, or combinations thereof.

[0061] In some embodiments, processing may also include forming interconnects, such as gate contacts and / or source / drain contacts. In some embodiments, forming source / drain contacts includes: forming source / drain contact openings in dielectric layer 250 that expose epitaxial source / drain (e.g., epitaxial source / drain 225); and forming at least one conductive layer (e.g., metal) in the source / drain contact openings. In some embodiments, the source / drain contact openings are formed by forming a patterned mask layer (e.g., an etch mask) over dielectric layer 250 and etching exposed portions of dielectric layer 250. In some embodiments, forming at least one conductive layer in the source / drain contact openings includes: forming a metal silicide layer over the epitaxial source / drain; depositing a barrier / liner layer partially filling the source / drain contact openings; depositing a metal layer over the barrier / liner layer filling the remaining portion of the source / drain contact openings; and performing a planarization process to remove portions of the barrier / liner layer and / or the metal layer disposed over the top of the dielectric layer 250 and / or the gate structure 230. In some embodiments, one or more insulating layers may be formed and processed in the source / drain contact openings to form contact spacers, such as dielectric layers and / or air gaps, along sidewalls of the conductive portions of the source / drain contacts (e.g., barrier layers and / or bulk metal layers).

[0062] In some embodiments, device 200 is an n-type transistor, and portions of the gate stack are formed simultaneously with the p-type transistor. For example, processing may include: forming interfacial layer 262 and high-k dielectric layer 264 simultaneously with the interfacial layer and high-k dielectric layer of the gate stack of the p-type transistor; masking the p-type device region including the p-type transistor with a first mask layer (e.g., a hard mask layer and / or a photoresist layer), and forming work function layer 272, cap layer 276, and cap layer 278; removing the first mask layer; masking the n-type device region including the n-type transistor (e.g., device 200) with a second mask layer (e.g., a hard mask layer and / or a photoresist layer), and forming work function layer (e.g., P-WFM layer) and / or cap of the gate stack of the p-type transistor; removing the second mask layer; and forming bulk layer 282 simultaneously with the bulk layer of the p-type transistor (e.g., forming the bulk layer (e.g., bulk layer 282) in the p-type device region and the n-type device region). In such an embodiment, the work function layer and the cap of the n-type transistor are formed before the work function layer of the p-type transistor. In some embodiments, the work function layer and the cap of the n-type transistor are formed after the work function layer of the p-type transistor. For example, processing can include: forming the interface layer 262 and the high-k dielectric layer 264 simultaneously with the interface layer and the high-k dielectric layer of the gate stack of the p-type transistor; masking the n-type device region including the n-type transistor (e.g., device 200) with a first mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming the work function layer (e.g., a P-WFM layer) and / or the cap of the gate stack of the p-type transistor; removing the first mask layer; masking the p-type device region including the p-type transistor with a second mask layer (e.g., a hard mask layer and / or a photoresist layer) and forming the work function layer 272, the cap layer 276, and the cap layer 278; removing the second mask layer; and forming the bulk layer 282 simultaneously with the bulk layer of the p-type transistor. The disclosed embodiments consider various process flows in which the gate manufacturing method is implemented.

[0063] The present disclosure provides many different embodiments. The gate stack disclosed herein can be implemented in a variety of device types. For example, the gate stack described herein is suitable for planar field effect transistors (FETs), multi-gate transistors such as FinFETs, GAA transistors, omega gate (Ω gate) devices, pi gate (π gate) devices, fork gate devices, or combinations thereof, as well as strained semiconductor devices, silicon on insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, other devices, or combinations thereof. The gate stack described herein is also suitable for stacked transistor devices, such as complementary field effect transistors (CFETs).

[0064] Fig.17is a cross-sectional view of a portion or all of a stacked device structure 400 that can implement the gate stack described herein according to various aspects of the embodiments of the present disclosure. The stacked device structure 400 includes a device stack 412A and a device stack 412B. The device stack 412A and the device stack 412B each include a corresponding upper device 414U vertically stacked above a corresponding lower device 414L. The device 414U and the device 414L are disposed above a substrate 415, and an isolation structure 416 is disposed between the device 414U and the device 414L and separates the device 414U and the device 414L. The isolation structure 416 includes an isolation structure 417 and an isolation structure 418. In some embodiments, the device 414U and the device 414L are stacked back to front. For example, the back side of the device 414U is bonded and / or attached to the front side of the device 414L. For clarity, the device 414U has been simplified. Fig.17 To better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the stacked device structure 400 , and some of the components described below may be replaced, modified, or eliminated in other embodiments of the stacked device structure 400 .

[0065] Device 414U and device 414L include at least one electrically functional device. For example, device stack 412A is a transistor stack having an upper transistor 420U-1 and a lower transistor 420L-1, and device stack 412B is a transistor stack having an upper transistor 420U-2 and a lower transistor 420L-2. Transistor 420U-1 can be separated and / or electrically isolated from transistor 420L-1 by isolation structure 416, and transistor 420U-2 can be separated and / or electrically isolated from transistor 420L-2 by isolation structure 416. In the depicted embodiment, transistor 420U-1 and transistor 420L-1 have opposite conductivity types, and transistor 420U-2 and transistor 420L-2 have opposite conductivity types. For example, transistor 420U-1 and transistor 420U-2 are n-type transistors, and transistor 420L-1 and transistor 420L-2 are p-type transistors, and vice versa. In such an embodiment, transistor 420U-1 and transistor 420L-1 form a first CFET, and transistor 420U-2 and transistor 420L-2 form a second CFET. In some embodiments, transistor 420U-1 and transistor 420L-1 have the same conductivity type, and / or transistor 420U-2 and transistor 420L-2 have the same conductivity type. For example, transistor 420U-1 and transistor 420L-1 and / or transistor 420U-2 and transistor 420L-2 are both n-type transistors or both p-type transistors.

[0066] The device 414U includes various features and / or components, such as semiconductor layer 426U, semiconductor layer 426M, gate spacers 444, inner spacers 454, epitaxial source / drain 462U, CESL 470U, ILD layer 472U, gate dielectrics (e.g., gate dielectric 478U-1 and gate dielectric 478U-2), gate electrodes (e.g., gate electrode 480U-1 and gate electrode 480U-2), and hard mask 492. Gate dielectric 478U-1 and gate electrode 480U-1 together form an upper gate stack 490U-1, and gate dielectric 478L-1 and gate electrode 480L-1 together form a lower gate stack 490L-1. The gate stack 490U-1 and the gate stack 490L-1 are collectively referred to as the gate 490A of the device stack 412A, and the gate 490A can provide a metal gate or a high-k / metal gate of the first CFET. The gate stack 490U-1 is separated from the gate stack 490L-1 by a corresponding isolation structure 417 (and the semiconductor layer 426M in the depicted embodiment), and the epitaxial source / drain 462U of the device 414U is separated from the epitaxial source / drain 462L of the device 414L by the isolation structure 418.

[0067] The device 414L includes various components and / or elements, such as a mesa 415′ (e.g., an extension of the substrate 415), a semiconductor layer 426L, a semiconductor layer 426M, a substrate isolation structure 428, an internal spacer 454, an epitaxial source / drain 462L, a CESL 470L, an ILD layer 472L, a gate dielectric (e.g., a gate dielectric 478L-1 and a gate dielectric 478L-2), and a gate electrode (e.g., a gate electrode 480L-1 and a gate electrode 480L-2). The gate dielectric 478L-2 and the gate electrode 480L-2 together form an upper gate stack 490U-2, and the gate dielectric 478L-2 and the gate electrode 480L-2 together form a lower gate stack 490L-2. The gate stack 490U-2 and the gate stack 490L-2 are collectively referred to as the gate 490B of the device stack 412B, and the gate 490B can provide a metal gate or a high-k / metal gate of the second CFET. The gate stack 490U-2 is separated from the gate stack 490L-2 by a corresponding isolation structure 417 (and semiconductor layer 426M), and the epitaxial source / drain 462L of the device 414L is separated from the epitaxial source / drain 462U of the device 414L by an isolation structure 418.

[0068] Transistor 420L-1 and transistor 420L-2 are configured as GAA transistors. For example, each of transistor 420L-1 and transistor 420L-2 has two channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by a semiconductor layer 426L (also referred to as a channel layer or channel), which is suspended above substrate 415 and extends between corresponding sources / drains (such as epitaxial source / drain 462L). In some embodiments, transistor 420L-1 and / or transistor 420L-2 include more or fewer channels (and therefore more or fewer semiconductor layers 426L). Transistor 420L-1 has a gate stack 490L-1 disposed above its semiconductor layer 426L and between its epitaxial source / drain 462L, and transistor 420L-2 has a gate stack 490L-2 disposed above its semiconductor layer 426L and between its epitaxial source / drain 462L. In the gate lateral direction, the gate stack 490L-1 and the gate stack 490L-2 are located above the corresponding top semiconductor layer 426L, between the corresponding semiconductor layers 426L, and between the corresponding bottom semiconductor layer 426L and the substrate 415 (e.g., its mesa 415'). In the gate longitudinal direction, the gate stack 490L-1 and the gate stack 490L-2 can wrap and / or surround the corresponding semiconductor layer 426L. During operation of the GAA transistor, current can flow through the corresponding semiconductor layer 426L and between the corresponding epitaxial source / drain 462L. In the depicted embodiment, the transistor 420L-1 and the transistor 420L-2 have a common epitaxial source / drain 462L, such as an intermediate epitaxial source / drain 462L. In some embodiments, the transistor 420L-1 and the transistor 420L-2 do not have a common epitaxial source / drain 462L. Each of transistor 420L-1 and transistor 420L-2 also has a semiconductor layer 426M (also referred to as a dummy channel layer or dummy channel) suspended above substrate 415 and extending between corresponding isolation structures 418. A corresponding isolation structure 417 is disposed between the semiconductor layers 426M of transistor 420L-1 and transistor 420U-1, and a corresponding isolation structure 417 is disposed between the semiconductor layers 426M of transistor 420L-2 and transistor 420U-2. In addition, each of transistor 420L-1 and transistor 420L-2 has an internal spacer 454 disposed between its gate stack (e.g., gate stack 490L-1 or gate stack 490L-2) and its epitaxial source / drain 462L.

[0069] Transistor 420U-1 and transistor 420U-2 are also configured as GAA transistors. For example, each of transistor 420U-1 and transistor 420U-2 has two channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by a semiconductor layer 426U (also referred to as a channel layer or channel), which is suspended above substrate 415 and extends between corresponding sources / drains (such as epitaxial source / drain 462U). In some embodiments, transistor 420U-1 and / or transistor 420U-2 include more or fewer channels (and therefore more or fewer semiconductor layers 426U). Transistor 420U-1 has a gate stack 490U-1 disposed above its semiconductor layer 426U and between its epitaxial source / drain 462U, and transistor 420U-2 has a gate stack 490U-2 disposed above its semiconductor layer 426U and between its epitaxial source / drain 462U. In the gate lateral direction, the gate stack 490U-1 and the gate stack 490U-2 are located above the corresponding top semiconductor layer 426U, between the corresponding semiconductor layers 426U, and between the corresponding bottom semiconductor layer 426U and the corresponding semiconductor layer 426M. In the gate longitudinal direction, the gate stack 490U-1 and the gate stack 490U-2 can wrap and / or surround the corresponding semiconductor layer 426U. During operation of the GAA transistor, current can flow through the corresponding semiconductor layer 426U and between the corresponding epitaxial source / drain 462U. In the depicted embodiment, the transistor 420U-1 and the transistor 420U-2 have a common epitaxial source / drain 462U, such as an intermediate epitaxial source / drain 462U. In some embodiments, the transistor 420U-1 and the transistor 420U-2 do not have a common epitaxial source / drain 462U. In addition, each of transistor 420U-1 and transistor 420U-2 has a gate spacer 444 disposed along the sidewalls of an upper portion of its gate stack (e.g., gate stack 490U-1 or gate stack 490U-2), an internal spacer 454 disposed between its gate stack and its epitaxial source / drain 462U, and a hard mask 492 disposed over its gate stack and between its gate spacers 444. Hard mask 492 may be considered part of the gate stack.

[0070] Isolation structure 416 has isolation structure 417 and isolation structure 418 between the channel region and source / drain region of device 414L and device 414U, respectively. For example, isolation structure 417 is located between the channel region of the lower transistor (e.g., transistor 420L-1) and the channel region of the upper transistor (e.g., transistor 420U-1) (e.g., between their channels and / or gates), and isolation structure 418 is located between the source / drain region of the lower transistor (e.g., transistor 420L-1) and the source / drain region of the upper transistor (e.g., transistor 420U-1). In the depicted embodiment, isolation structure 417 is located between semiconductor layer 426M of the lower transistor and the upper transistor, and isolation structure 418 is located between epitaxial source / drain 462L of the lower transistor and epitaxial source / drain 462U of the upper transistor. Thus, isolation structure 417 can provide electrical isolation of the channel and / or gate of the stacked device, and isolation structure 418 can provide electrical isolation of the source / drain of the stacked device. Isolation structure 417 and isolation structure 418 may include a single layer or multiple layers. Isolation structure 417 and isolation structure 418 include a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or combinations thereof). Isolation structure 417 and isolation structure 418 may include the same or different materials and / or configurations. In the depicted embodiment, the thickness of isolation structure 417 is less than the thickness of isolation structure 418, and the configuration of isolation structure 417 is different from the configuration of isolation structure 418. In some embodiments, isolation structures 418 include CESL 470L and ILD layer 472L, such as depicted (ie, each isolation structure 418 is formed by a respective portion of CESL 470L and a respective portion of ILD layer 472L).

[0071] The substrate 415 may be similar to the substrate 202 described above, the mesa 415' may be similar to the mesa 202' described above, and the semiconductor layer 426U, the semiconductor layer 426M, and the semiconductor layer 426L may be similar to the semiconductor layers 220, 220' described above. For example, in the depicted embodiment, the substrate 415, the mesa 415', the semiconductor layer 426U, the semiconductor layer 426M, and the semiconductor layer 426L include silicon. In some embodiments, the semiconductor layer 426U and the semiconductor layer 426L include different semiconductor materials, such as silicon and silicon germanium, respectively, or vice versa. In such an embodiment, the semiconductor layer 426M of the upper transistor and the semiconductor layer 426M of the lower transistor may include different materials. For the convenience of description herein, the semiconductor layer 426U, the semiconductor layer 426M, and the semiconductor layer 426L may be collectively referred to as the semiconductor layer 426.

[0072] The gate spacer 444 is disposed along the sidewalls of the top portion of the upper gate stack (e.g., gate stack 490U-1 and gate stack 490U-2), the internal spacer 454 is disposed below the gate spacer 444 along the sidewalls of the upper gate stack 490U and / or the lower gate stack (e.g., gate stack 490L-1 and gate stack 490L-2), and the fin / mesa spacer may be disposed along the sidewalls of the mesa 415'. The internal spacer 454 is located between the semiconductor layers 426U, between the semiconductor layers 426L, between the bottom semiconductor layer 426U and the semiconductor layer 426M, between the top semiconductor layer 426L and the semiconductor layer 426M, and between the bottom semiconductor layer 426L and the mesa 415'. The gate spacer 444 may be similar to the gate spacer 240 described above, and the internal spacer 454 may be similar to the internal spacer 224 described above.

[0073] Each of gate 490A and gate 490B is disposed between corresponding epitaxial source / drain stacks. Each epitaxial source / drain stack includes a corresponding epitaxial source / drain 462U, a corresponding epitaxial source / drain 462L, and a corresponding isolation structure 418 therebetween. Epitaxial source / drain 462L and epitaxial source / drain 462U may be similar to epitaxial source / drain 225 described above. Epitaxial source / drain 462L and epitaxial source / drain 462U may have the same or different compositions and / or materials, depending on the configuration of their corresponding transistors. For example, in the case where the upper transistor is an NFET and the lower transistor is a PFET, such as in the depicted embodiment, epitaxial source / drain 462U may include silicon doped with phosphorus and / or carbon, and epitaxial source / drain 462L may include silicon germanium doped with boron.

[0074] The ILD layer 472U and the ILD layer 472L can be similar to the ILD layer 254 described above, and the CESL 470L and the CESL 470U can be similar to the CESL 252 described above. The gate dielectric 478U-1, the gate dielectric 478L-1, the gate dielectric 478U-2, and the gate dielectric 478L-2 each include at least one dielectric gate layer, such as an interfacial layer and / or a high-k dielectric layer, which is further described below. The gate electrode 480U-1, the gate electrode 480L-1, the gate electrode 480U-2, and the gate electrode 480L-2 each include at least one conductive gate layer, such as a work function layer, a metal fill (bulk) layer, an additional layer (e.g., a barrier layer and / or one or more capping layers), or a combination thereof. The gate dielectric 478U-1, the gate dielectric 478L-1, the gate dielectric 478U-2, the gate dielectric 478L-2, or a combination thereof can be similar to the gate dielectric 230A described above. Gate electrode 480U-1, gate electrode 480L-1, gate electrode 480U-2, gate electrode 480L-2, or a combination thereof may be similar to gate electrode 230B described above. In some embodiments, the composition and / or configuration of gate dielectric 478U-1 and gate dielectric 478U-2 are different from the composition and / or configuration of gate dielectric 478L-1 and gate dielectric 478L-2. In some embodiments, the composition and / or configuration of gate electrode 480U-1 and gate electrode 480U-2 are different from the composition and / or configuration of gate electrode 480L-1 and gate electrode 480L-2. For example, gate electrode 480U-1 and gate electrode 480U-2 may be configured as gate electrode 230B, and gate electrode 480L-1 and gate electrode 480L-2 may be configured differently from gate electrode 230B. In some embodiments, the work function layer of gate electrode 480U-1 and gate electrode 480U-2 may be an n-type work function layer, and the work function layer of gate electrode 480L-1 and gate electrode 480L-2 may be a p-type work function layer. In some embodiments, gate electrode 480U-1, gate electrode 480L-1, gate electrode 480U-2, and gate electrode 480L-2 have the same type of work function layer (e.g., n metal or p metal). In some embodiments, gate electrode 480U-1 and gate electrode 480U-2 each include a first work function layer, and gate electrode 480L-1 and gate electrode 480L-2 each include a second work function layer. The first work function layer and the second work function layer may include different types of work function layers (e.g., p metal and n metal, respectively).

[0075] The hard mask 492 includes a material different from the ILD layer 472U and / or a subsequently formed ILD layer to achieve etching selectivity during a subsequent etching process. In some embodiments, the hard mask 492 includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the hard mask 492 includes a metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HFO2), zirconium aluminum oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or combinations thereof.

[0076] The exemplary method includes forming a first semiconductor layer and a second semiconductor layer over a substrate. The first semiconductor layer is disposed over the second semiconductor layer, and a gap is located between the first semiconductor layer and the second semiconductor layer. The method also includes forming a gate dielectric over the first semiconductor layer and the second semiconductor layer. The gate dielectric partially fills the gap between the first semiconductor layer and the second semiconductor layer. The method also includes forming a work function layer on the gate dielectric. The work function layer fills the remaining portion of the gap between the first semiconductor layer and the second semiconductor layer. The method also includes forming a cap over the work function layer. In some embodiments, the method also includes forming a metal fill layer over the cap.

[0077] In some embodiments, an air gap is formed in the work function layer in the space between the first semiconductor layer and the second semiconductor layer. In some embodiments, forming the work function layer includes depositing a conductive material, the conductive material including titanium, aluminum, and carbon. In some embodiments, forming the work function layer provides a first portion of the work function layer having a first thickness along a bottom of the first semiconductor layer, the first thickness being less than about twice a second thickness of a second portion of the work function layer along a top of the first semiconductor layer.

[0078] In some embodiments, forming the cap includes: forming a metal nitride layer above the work function layer; and forming a silicon-containing layer above the metal nitride layer. In some embodiments, forming the metal nitride layer includes: forming a first metal nitride sublayer above the work function layer; and after breaking the vacuum, forming a second metal nitride sublayer. In some embodiments, the first semiconductor layer and the second semiconductor layer form a channel stack; along the first direction, the cap is disposed above the top of the channel stack; and along the second direction, the cap wraps around the channel stack.

[0079] In some embodiments, forming the work function layer includes: depositing a conductive material having a thickness around the first semiconductor layer and the second semiconductor layer. In a space between the first semiconductor layer and the second semiconductor layer, the conductive material having a thickness around the first semiconductor layer merges with the conductive material having a thickness around the second semiconductor layer. In such an embodiment, forming the work function layer also includes: continuing the deposition to increase the thickness of the conductive material along the sidewalls of the first semiconductor layer, the sidewalls of the second semiconductor layer, and the top of the first semiconductor layer.

[0080] In some embodiments, the method includes removing the dummy gate to form a gate opening exposing the semiconductor stack; and performing a channel release process to remove the third semiconductor layer from the semiconductor stack, thereby suspending the first semiconductor layer above the second semiconductor layer and suspending the second semiconductor layer above the substrate.

[0081] An exemplary method for forming a gate stack of a transistor includes forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer. The channel stack includes a first channel layer disposed above the second channel layer. The first interface layer partially fills the gap between the first channel layer and the second channel layer, and the second interface layer partially fills the gap between the first channel layer and the second channel layer. The method includes forming a first high-k dielectric layer above the first interface layer and around the first channel layer and forming a second high-k dielectric layer above the second interface layer and around the second channel layer. The first high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer. The method includes forming a work function layer around the first channel layer and the second channel layer. The work function layer fills the remaining portion of the gap between the first channel layer and the second channel layer.

[0082] The work function layer can be formed by: depositing a work function material until a first portion of the work function material formed above the first high-k dielectric layer and around the first channel layer merges with a second portion of the work function material formed above the second high-k dielectric layer and around the second channel layer. The first portion of the work function material merges with the second portion of the work function material in the gap between the first channel layer and the second channel layer. The work function layer can also be formed by: continuing to deposit the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material. In some embodiments, in the gap between the first channel layer and the second channel layer, the ends of the first portion of the work function material and the second portion of the work function material merge before their centers, thereby forming an air gap between the first portion of the work function material and the second portion of the work function material in the gap between the first channel layer and the second channel layer. In some embodiments, the work function layer is a titanium aluminum carbide layer, and the aluminum content of the work function layer is about 25at% to about 33at%.

[0083] The method also includes forming a cap over the work function layer. The cap wraps around the channel stack. Forming the cap may include forming a first metal nitride layer over the work function layer and forming a second metal nitride layer over the first metal nitride layer. The second metal nitride layer may be formed after breaking the vacuum. Forming the cap may also include forming a silicon-containing layer over the second metal nitride layer. In some embodiments, the first metal nitride layer is a first titanium nitride layer, and the second metal nitride layer is a second titanium nitride layer. In some embodiments, after forming the cap, an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, a ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25, the inner region of the gate stack fills the gap between the first channel layer and the second channel layer, and the outer region of the gate stack is not located in the gap between the first channel layer and the second channel layer.

[0084] In some embodiments, the gate opening exposes the first channel layer and the second channel layer, and the first interface layer, the first high-k dielectric layer, the work function layer, and the cover partially fill the top of the gate opening above the first channel layer. In such an embodiment, the method may also include forming a bulk / filling layer above the cover. The bulk / filling layer can fill the remaining portion of the top of the gate opening, and the bulk / filling layer wraps the channel stack. In some embodiments, the transistor is an n-type transistor, and the work function layer is an n-type work function metal layer.

[0085] An exemplary transistor includes a first channel layer, a second channel layer, and a gate stack. The gate stack includes a gate dielectric disposed around the first channel layer and the second channel layer. The gate dielectric includes an interface layer and a high-k dielectric layer disposed above the interface layer. The gate stack also includes a gate electrode disposed above the gate dielectric. The gate electrode is located around the first channel layer and the second channel layer. The gate electrode includes a work function layer disposed above the high-k dielectric layer. The work function layer is located around the first channel layer and the second channel layer. The gate electrode also includes a cap disposed above the work function layer. The cap includes a metal nitride layer disposed above the work function layer and a silicon layer disposed above the metal nitride layer. The gate dielectric and the work function layer fill the gap between the first channel layer and the second channel layer. The outer region of the gate stack has a first oxygen content, the inner region of the gate stack has a second oxygen content, and the ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25. In addition, the first thickness of the work function layer in the outer region of the gate stack is greater than the second thickness of the work function layer in the inner region of the gate stack. In some embodiments, the work function layer includes titanium, aluminum, and carbon. In some embodiments, the aluminum content of the work function layer is about 25 atomic percent (at%) to about 33 at%. In some embodiments, the air gap is located in the work function layer.

[0086] Some embodiments of the present application provide a method for forming a transistor, comprising: forming a first semiconductor layer and a second semiconductor layer over a substrate, wherein the first semiconductor layer is disposed over the second semiconductor layer and a gap is located between the first semiconductor layer and the second semiconductor layer; forming a gate dielectric over the first semiconductor layer and the second semiconductor layer, wherein the gate dielectric partially fills the gap between the first semiconductor layer and the second semiconductor layer; forming a work function layer on the gate dielectric, wherein the work function layer fills a remaining portion of the gap between the first semiconductor layer and the second semiconductor layer; and forming a cover over the work function layer.

[0087] In some embodiments, forming the work function layer comprises depositing a conductive material, the conductive material comprising titanium, aluminum, and carbon. In some embodiments, forming the work function layer provides a first portion of the work function layer having a first thickness along a bottom portion of the first semiconductor layer, the first thickness being less than about twice a second thickness of a second portion of the work function layer along a top portion of the first semiconductor layer. In some embodiments, forming the cap comprises: forming a metal nitride layer over the work function layer; and forming a silicon-containing layer over the metal nitride layer. In some embodiments, forming the metal nitride layer comprises: forming a first metal nitride sublayer over the work function layer; and after breaking the vacuum, forming a second metal nitride sublayer. In some embodiments, the method further comprises forming a metal fill layer over the cap. In some embodiments, forming the work function layer includes: depositing a conductive material having a thickness around the first semiconductor layer and the second semiconductor layer, wherein the conductive material having the thickness around the first semiconductor layer merges with the conductive material having the thickness around the second semiconductor layer in the space between the first semiconductor layer and the second semiconductor layer; and continuing to deposit to increase the thickness of the conductive material along the first sidewall of the first semiconductor layer, the second sidewall of the second semiconductor layer, and the top of the first semiconductor layer. In some embodiments, an air gap is formed in the work function layer in the space between the first semiconductor layer and the second semiconductor layer. In some embodiments, the method further includes: removing a dummy gate to form a gate opening exposing a semiconductor stack; and performing a channel release process to remove a third semiconductor layer from the semiconductor stack, thereby suspending the first semiconductor layer above the second semiconductor layer and suspending the second semiconductor layer above the substrate. In some embodiments, the first semiconductor layer and the second semiconductor layer form a channel stack; along the first direction, the cap is disposed above the top of the channel stack; and along the second direction, the cap wraps the channel stack.

[0088] Some other embodiments of the present application provide a method for forming a gate stack of a transistor, the method comprising: forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer, wherein the channel stack comprises the first channel layer disposed above the second channel layer, the first interface layer partially filling a gap between the first channel layer and the second channel layer, and the second interface layer partially filling the gap between the first channel layer and the second channel layer; forming a first high-k dielectric layer above the first interface layer and around the first channel layer and forming a second high-k dielectric layer above the second interface layer and around the second channel layer, wherein the first high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills the gap between the first channel layer and the second channel layer; forming a work function layer around the first channel layer and the second channel layer, wherein the work function layer fills the gap between the first channel layer and the second channel layer. The work function layer is formed by depositing a work function material until a first portion of the work function material formed above the first high-k dielectric layer and around the first channel layer merges with a second portion of the work function material formed above the second high-k dielectric layer and around the second channel layer, wherein the first portion of the work function material merges with the second portion of the work function material in the space between the first channel layer and the second channel layer, and continuing to deposit the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material; and forming a cap over the work function layer, wherein the cap wraps around the channel stack, and forming the cap includes: forming a first metal nitride layer over the work function layer, and after breaking the vacuum, forming a second metal nitride layer over the first metal nitride layer, and forming a silicon-containing layer over the second metal nitride layer.

[0089] In some embodiments, in the interval between the first channel layer and the second channel layer, ends of the first portion of the work function material and the second portion of the work function material merge before the centers of the first portion and the second portion, thereby forming an air gap between the first portion of the work function material and the second portion of the work function material in the interval between the first channel layer and the second channel layer. In some embodiments, forming the work function layer includes forming a titanium aluminum carbide layer, wherein the aluminum content of the work function layer is about 25 atomic percent (at%) to about 33 atomic percent. In some embodiments, after forming the cap, an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, a ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25, the inner region of the gate stack fills the interval between the first channel layer and the second channel layer, and the outer region of the gate stack is not located in the interval between the first channel layer and the second channel layer. In some embodiments, the gate opening exposes the first channel layer and the second channel layer; the first interface layer, the first high-k dielectric layer, the work function layer, and the cover partially fill the top of the gate opening above the first channel layer; and the method further includes forming a bulk / filling layer above the cover, wherein the bulk / filling layer fills the remaining portion of the top of the gate opening, wherein the bulk / filling layer encapsulates the channel stack. In some embodiments, forming the first metal nitride layer includes forming a first titanium nitride layer, and forming the second metal nitride layer includes forming a second titanium nitride layer. In some embodiments, the transistor is an n-type transistor, and the work function layer is an n-type work function metal layer.

[0090] Some other embodiments of the present application provide a transistor, comprising: a first channel layer and a second channel layer; a gate stack, having: a gate dielectric, disposed around the first channel layer and the second channel layer, wherein the gate dielectric comprises an interface layer and a high-k dielectric layer disposed above the interface layer, and a gate electrode, disposed above the gate dielectric, wherein the gate electrode is located around the first channel layer and the second channel layer, and wherein the gate electrode comprises: a work function layer, disposed above the high-k dielectric layer, wherein the work function layer is located around the first channel layer and the second channel layer; and a cap, disposed on the work function layer. layer, wherein the cover includes a metal nitride layer disposed above the work function layer and a silicon layer disposed above the metal nitride layer; wherein the gate dielectric and the work function layer fill a gap between the first channel layer and the second channel layer; wherein an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, and a ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25; and wherein a first thickness of the work function layer in the outer region of the gate stack is greater than a second thickness of the work function layer in the inner region of the gate stack.

[0091] In some embodiments, the work function layer includes titanium, aluminum, and carbon, wherein the aluminum content of the work function layer is about 25 atomic percent (at%) to about 33 atomic percent. In some embodiments, an air gap is located in the work function layer in the space between the first channel layer and the second channel layer.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a transistor, include: Forming a first semiconductor layer and a second semiconductor layer over a substrate, wherein the first semiconductor layer is disposed over the second semiconductor layer and is spaced between the first semiconductor layer and the second semiconductor layer; forming a gate dielectric over the first semiconductor layer and the second semiconductor layer, wherein the gate dielectric partially fills the space between the first semiconductor layer and the second semiconductor layer; forming a work function layer on the gate dielectric, wherein the work function layer fills a remaining portion of the space between the first semiconductor layer and the second semiconductor layer; and A cap is formed over the work function layer.

2. The method according to claim 1, in, Forming the work function layer includes depositing a conductive material, the conductive material including titanium, aluminum, and carbon.

3. The method according to claim 1, in, Forming the work function layer along a bottom portion of the first semiconductor layer provides a first portion of the work function layer having a first thickness that is less than about twice a second thickness of a second portion of the work function layer along a top portion of the first semiconductor layer.

4. The method according to claim 1, in, Forming the cover includes: forming a metal nitride layer over the work function layer; and A silicon-containing layer is formed over the metal nitride layer.

5. The method according to claim 4, in, Forming the metal nitride layer comprises: forming a first metal nitride sublayer over the work function layer; and After breaking the vacuum, a second metal nitride sub-layer is formed. The method of claim 1 , further comprising forming a metal fill layer over the cap.

7. The method according to claim 1, in, Forming the work function layer comprises: depositing a conductive material having a thickness around the first semiconductor layer and the second semiconductor layer, wherein the conductive material having the thickness around the first semiconductor layer merges with the conductive material having the thickness around the second semiconductor layer in the space between the first semiconductor layer and the second semiconductor layer; and Deposition continues to increase the thickness of the conductive material along a first sidewall of the first semiconductor layer, a second sidewall of the second semiconductor layer, and a top of the first semiconductor layer.

8. The method according to claim 1, in, An air gap is formed in the work function layer in the space between the first semiconductor layer and the second semiconductor layer.

9. A method for forming a gate stack of a transistor, the method comprising: include: forming a first interface layer around a first channel layer and forming a second interface layer around a second channel layer, wherein the channel stack includes the first channel layer disposed above the second channel layer, the first interface layer partially fills a space between the first channel layer and the second channel layer, and the second interface layer partially fills the space between the first channel layer and the second channel layer; forming a first high-k dielectric layer over the first interface layer and around the first channel layer and forming a second high-k dielectric layer over the second interface layer and around the second channel layer, wherein the first high-k dielectric layer partially fills the space between the first channel layer and the second channel layer, and the second high-k dielectric layer partially fills the space between the first channel layer and the second channel layer; A work function layer is formed around the first channel layer and the second channel layer, wherein the work function layer fills a remaining portion of the interval between the first channel layer and the second channel layer, wherein the work function layer is formed by the following steps: depositing a work function material until a first portion of the work function material formed over the first high-k dielectric layer and around the first channel layer merges with a second portion of the work function material formed over the second high-k dielectric layer and around the second channel layer, wherein the first portion of the work function material merges with the second portion of the work function material in the space between the first channel layer and the second channel layer, and continuing to deposit the work function material to increase the thickness of the first portion of the work function material and the second portion of the work function material; and Forming a cap over the work function layer, wherein the cap wraps around the channel stack, and forming the cap comprises: forming a first metal nitride layer above the work function layer, After breaking the vacuum, forming a second metal nitride layer over the first metal nitride layer, and A silicon-containing layer is formed over the second metal nitride layer.

10. A transistor, include: a first channel layer and a second channel layer; A gate stack having: a gate dielectric disposed around the first channel layer and the second channel layer, wherein the gate dielectric comprises an interface layer and a high-k dielectric layer disposed above the interface layer, and a gate electrode disposed above the gate dielectric, wherein the gate electrode is located around the first channel layer and the second channel layer, and wherein the gate electrode comprises: a work function layer disposed above the high-k dielectric layer, wherein the work function layer is located around the first channel layer and the second channel layer; and a cover disposed above the work function layer, wherein the cover comprises a metal nitride layer disposed above the work function layer and a silicon layer disposed above the metal nitride layer; wherein the gate dielectric and the work function layer fill the gap between the first channel layer and the second channel layer; wherein an outer region of the gate stack has a first oxygen content, an inner region of the gate stack has a second oxygen content, and a ratio of the first oxygen content to the second oxygen content is about 1 to about 1.25; and Wherein, a first thickness of the work function layer in the outer region of the gate stack is greater than a second thickness of the work function layer in the inner region of the gate stack.

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