High-efficiency computing device and method for manufacturing same

Abstract

The invention discloses a semiconductor device, a semiconductor structure and a method for forming the semiconductor device. The semiconductor structure comprises a first substrate and a second substrate. The first substrate has a plurality of first-type transistors formed by planar transistors or fin-type transistors, where a gate silicon oxide layer of each of the planar transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness. The second substrate is bonded to the first substrate and includes a plurality of second type transistors formed of wrap-around gate type transistors, where a gate silicon oxide layer of each of the wrap-around gate type transistors has a third thickness. The third thickness is less than the first thickness or the second thickness.

Description

Technical Field

[0001] The present invention relates to a structure of a computing device and a manufacturing method thereof, and in particular to a structure of a high-performance computing device and a manufacturing method thereof. Background Art

[0002] In advanced semiconductor manufacturing techniques, the continued reduction in device size and increasing complexity of circuit configurations have made the design and manufacture of integrated circuits (ICs) more challenging and costly. In the continued pursuit of better device performance, smaller footprints, and lower power consumption, advanced semiconductor manufacturing techniques that reduce line widths have been explored, including techniques that use gate-all-around (GAA) transistors. Gate-all-around transistors can be used in structures that differ significantly from their predecessors because channel current can be manipulated in a more efficient and controllable manner, thereby improving the electrical performance of devices that include gate-all-around transistors.

[0003] Although there have been some improvements in the technology used to manufacture semiconductor devices based on all-around gate transistors, such technology still cannot meet market demand. For example, the continuous attempts to reduce device size in advanced applications have made it difficult to integrate semiconductor devices. High-performance computing (HPC) devices (such as graphics processing unit (GPU) chips) require high-speed and low-power transistors to be formed on all-around gate chips. The core circuits of the all-around gate chip are mainly used for computing purposes, while the non-core circuits of the all-around gate chip (e.g., input / output circuits) are used to facilitate the operation of the core circuits. However, the non-core circuits of the all-around gate chip require thick gate dielectric materials to meet the large voltage drop requirements, and the limited inter nanosheet spacing between each semiconductor channel material nanosheet of the core circuit cannot accommodate thick gate dielectric materials.

[0004] Therefore, there is a need to solve the integration problem for manufacturing semiconductor devices based on all-around gate transistors. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor device includes: a first substrate including a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness; and a second substrate bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein a gate silicon oxide layer of each of the gate-all-around transistors has a third thickness. The third thickness is less than the first thickness or the second thickness.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a first substrate including a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein the first-type transistors operate at a first voltage, and wherein each of the plurality of first-type transistors has a first gate silicon oxide layer stacked with a first high-k dielectric layer, the first gate silicon oxide layer and the first high-k dielectric layer having a first combined thickness; and a second substrate bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein the second-type transistors operate at a second voltage less than the first voltage, and wherein each of the plurality of second-type transistors has a second gate silicon oxide layer stacked with a second high-k dielectric layer, the second gate silicon oxide layer and the second high-k dielectric layer having a second combined thickness. The first combined thickness is greater than the second combined thickness.

[0007] According to one aspect of the present disclosure, a method includes: forming a plurality of first die regions on a first semiconductor wafer, wherein each of the first die regions includes a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar transistors has a first thickness and a gate silicon oxide layer of each of the fin-type transistors has a second thickness; forming a first interconnect region adjacent to the first die region; forming a plurality of second die regions on a second semiconductor wafer, wherein each of the second die regions includes a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein a gate silicon oxide layer of each of the gate-all-around transistors has a third thickness; forming a second interconnect region adjacent to the second die region; and bonding the first semiconductor wafer to the second semiconductor wafer by electrically coupling each of the first die regions to a counterpart of the second die region. The third thickness is less than the first thickness or the second thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of discussion.

[0009] Figure 1A , 1B 1C is a perspective view of several types of transistors according to some embodiments of the present disclosure.

[0010] Figure 2 For some embodiments according to the present disclosure Figure 1C A schematic cross-sectional view of the transistor shown.

[0011] Figure 3Ais a schematic top view of a first semiconductor wafer according to some embodiments of the present disclosure.

[0012] Figure 3B is a schematic top view of a second semiconductor wafer according to some embodiments of the present disclosure.

[0013] Figure 4A , 4B 4C, 4D, 4E, 4F and 4G are examples of some embodiments according to the present disclosure. Figure 3A A schematic cross-sectional view of an intermediate stage of a method for forming a first semiconductor wafer is shown.

[0014] Figure 5 For some embodiments according to the present disclosure Figure 3A A schematic cross-sectional view of a first semiconductor wafer is shown.

[0015] Fig. 6A and 6B For some embodiments according to the present disclosure Figure 3B A schematic cross-sectional view of a second semiconductor wafer is shown.

[0016] Figure 7 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0017] Fig. 8A and 8B is a schematic cross-sectional view of an intermediate stage of a method of bonding a first semiconductor wafer to a second semiconductor wafer according to some embodiments of the present disclosure.

[0018] Fig. 9 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0019] Fig.10 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0020] Fig.11 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0021] Fig.12 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0022] Fig.13A , 13B , 13C and 13D are cross-sectional schematic diagrams of intermediate stages of a method of bonding a second semiconductor wafer to a first semiconductor wafer according to some embodiments of the present disclosure.

[0023] Fig.14is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0024] Fig.15 FIG. 1 is a schematic diagram showing transmission paths of power and signals of a semiconductor device according to some embodiments of the present disclosure.

[0025] Fig.16 FIG. 1 is a schematic diagram showing transmission paths of power and signals of a semiconductor device according to some embodiments of the present disclosure.

[0026] Fig.17 FIG. 1 is a schematic diagram showing transmission paths of power and signals of a semiconductor device according to some embodiments of the present disclosure.

[0027] Fig.18 FIG. 1 is a schematic diagram showing transmission paths of power and signals of a semiconductor device according to some embodiments of the present disclosure.

[0028] Fig.19 FIG. 1 is a schematic diagram showing transmission paths of power and signals of a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] This application claims priority to U.S. Provisional Patent Application No. 63 / 508,635, filed on June 16, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0030] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described in this disclosure to facilitate understanding of the present invention. Such examples are provided only to facilitate understanding and are not intended to limit this disclosure. For example, as described herein, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature so that the first and second features are not in direct contact. In addition, this disclosure may repeat reference numbers and / or letters in each example. The purpose of this repetition is to be simple and clear, and does not necessarily indicate the relationship between the various embodiments and / or configurations described.

[0031] In addition, for convenience of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature to another component or feature as shown in the figure. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may be oriented in other ways (e.g., rotated 90 degrees from the illustrated orientation), and the spatially relative descriptors used herein should be interpreted accordingly to include other orientations.

[0032] Although the numerical ranges and parameters describing the wide range of the present disclosure are approximate values, the numerical values ​​described in the specific examples are reported as accurately as possible. However, any numerical value essentially contains certain errors, which are necessarily caused by the deviations normally found in the individual test measurements. At the same time, as used herein, the terms "about", "approximately" or "substantially" may refer to a small percentage of a given value or range. Alternatively, the terms "about", "approximately" or "substantially" mean within the acceptable standard error of the indicated value when considered by a person of ordinary skill in the art. Unless otherwise expressly indicated, all numerical ranges, quantities, values ​​and percentages disclosed herein, such as the amount of material, duration, temperature, operating conditions, ratios of amounts, etc., should be understood to be adjusted by the terms "about", "approximately" or "substantially" in all cases. Accordingly, unless otherwise indicated, the numerical parameters described in the present disclosure and the attached patent application range are variable approximate values. At least, each numerical parameter should be understood according to the number of reported significant figures and by applying ordinary rounding techniques. Various ranges are expressed herein as from one endpoint to the other endpoint, or as between one endpoint and the other endpoint. Unless otherwise indicated, all ranges disclosed herein include each endpoint.

[0033] The present disclosure generally relates to semiconductor structures or semiconductor devices, and more particularly to structures or devices that combine different circuits manufactured using different transistor generations to improve device performance and reduce integration costs. The present disclosure discusses various embodiments, including two types of transistors, namely, gate-all-around (GAA) transistors and non-gate-all-around (nGAA) transistors. Gate-all-around transistors may include nanosheet transistors or nanowire transistors, and non-gate-all-around transistors may include planar transistors or fin transistors; however, the present disclosure is not limited thereto. Any variation of the above transistors may be classified as gate-all-around transistors or non-gate-all-around transistors. For example, non-gate-all-around transistors include planar field effect transistors, planar bipolar junction transistors, planar transistors with raised source / drain regions, vertical transistors, etc. Similarly, gate-all-around transistors include horizontal nanowire transistors, vertical nanowire transistors, etc.

[0034] The present disclosure proposes an effective method to take advantage of advanced technology nodes (such as wraparound gate transistors) to enhance computing power and reduce power consumption in core circuits used to drive computing-intensive applications (such as those involving artificial intelligence (AI), machine learning (ML), deep learning, big data, etc.). Wraparound gate transistors are potential candidates for use in core circuits due to their high speed, low power consumption, low operating voltage, and reduced device size. However, research shows that integrating core circuits and non-core circuits (including only wraparound gate transistors) on the same semiconductor wafer will face significant challenges in manufacturing. Integration is difficult due to different voltage requirements for core circuits and non-core circuits, where non-core circuits include peripheral circuits, input / output circuits, power supply circuits, memory circuits, etc., and are designed to operate at a voltage greater than that of the core circuit. Therefore, the gate dielectric layer in the wraparound gate transistor of the non-core circuit should be thicker than the gate dielectric layer in the wraparound gate transistor of the core circuit so that the wraparound gate transistor of the non-core circuit maintains a higher operating voltage. However, as will be described in detail below, thicker gate dielectric layers may not be compatible with the manufacturing specifications of existing all-around gate transistors. The narrow gaps between adjacent nanosheets or adjacent nanowires in all-around gate transistors do not leave enough space for forming thicker gate dielectric layers and other electrode gate layers. Therefore, all-around gate transistors are not easily modified to meet the higher voltage requirements of non-core circuits.

[0035] The present disclosure provides a semiconductor structure or semiconductor device, including a core circuit formed by wraparound gate transistors, which is manufactured by assigning different process nodes to the core circuit and the non-core circuit. For example, the core circuit is designed and manufactured at an advanced technology node (i.e., wraparound gate transistors), while the non-core circuit is designed and manufactured at an earlier or mature technology node. For example, the non-wrapped gate transistors are formed by planar or fin transistors. The wraparound gate transistors and the non-wrapped gate transistors are formed in respective semiconductor wafers. When the core circuit and the non-core circuit are designed on different semiconductor wafers, various advantages can be obtained. For example, conventional semiconductor intellectual property (IP) designated for the non-core circuit (which involves a manufacturing process compatible with mature technology nodes) can be used for HPC applications as long as the core circuit and its IP are separated from the non-core circuit and its IP and implemented on another semiconductor wafer. In this way, the design of new IP for integrating non-core circuits with core circuits on a single wafer can be omitted to save production costs, and resources can be directed to the design of pure computing engines (i.e., core circuits) on semiconductor wafers dedicated to HPC computing capabilities, wherein the core circuits involve compatible manufacturing processes with respect to advanced technology nodes. A semiconductor wafer having core circuits (which include wraparound gate transistors) is bonded to a semiconductor wafer having non-core circuits (which include non-wraparound gate transistors). Accordingly, a semiconductor structure or semiconductor device is obtained by cutting the bonded semiconductor wafers into individual dies and packaging them into semiconductor chips. Each of the semiconductor chips includes a first substrate formed by wraparound gate transistors in the core circuit and a second substrate formed by non-wraparound gate transistors in the non-core circuit, and the first substrate is bonded to the second substrate. Therefore, the core circuit can operate at full speed with minimal power consumption, and the non-core circuit can operate at a higher operating voltage without hindering integration with the core circuit. As a result, state-of-the-art processing components for high-speed, high-performance computing processors, such as graphics processing units (GPUs) or central processing units (CPUs) for artificial intelligence (AI) machine learning or deep learning, can be implemented in an efficient and economical manner.

[0036] Figure 1A , 1B1C are respective perspective views of transistors 110, 120, and 130 of different transistor types according to some embodiments. Transistor 110 may be a non-wraparound gate type transistor, such as a planar transistor. Transistor 120 may be another non-wraparound gate type transistor, such as a fin transistor. Transistor 130 may be a wraparound gate type transistor. Throughout this disclosure, transistors 110 and 120, as well as other transistors that are not wraparound gate type transistors, are classified as first type (second type) transistors, and transistor 130 and other transistors that are not wraparound gate type transistors are classified as second type (first type) transistors. Figure 1A The transistor 110 is represented by a metal oxide semiconductor (MOS) field effect transistor (FET). However, the present disclosure is not limited thereto. The transistor 110 may also be represented by a bipolar junction transistor or another non-wraparound gate transistor.

[0037] refer to Figure 1A , the transistor 110 includes a substrate 101, a gate structure 102, a source region 104, a drain region 106, a pair of gate spacers 108, and a gate dielectric layer 109. For the sake of clarity and simplicity, Figure 1A Some features of transistor 110 are omitted, such as isolation regions, lightly doped drain (LDD) regions, gate contacts, source contacts, drain contacts, contact etch stop layers, inter-layer dielectric (ILD) layers, etc.

[0038] The gate structure 102, the source region 104, and the drain region 106 may be electrically coupled to respective voltage sources via a gate contact, a source contact, and a drain contact (not shown separately), respectively, for turning on and off a channel current flowing in a channel region (not shown separately) directly below a gate dielectric layer 109 near an upper portion of the substrate 101 between the source region 104 and the drain region 106. In some embodiments, the gate dielectric layer 109 is formed of a dielectric material, such as silicon oxide or other suitable dielectric materials. The gate dielectric layer 109 is used to electrically isolate the gate structure 102 from the substrate 101 and the channel region, so that carriers can be attracted by an electric field generated by the gate structure 102, and the carriers can flow in the channel region. The gate structure 102 and the gate dielectric layer 109 are formed on a substrate 101 having a flat upper surface, and the channel region is formed in the substrate 101. Therefore, the transistor 110 is referred to as a planar transistor.

[0039] The material and thickness of the gate dielectric layer 109 play an important role in ensuring that the transistor 110 functions properly. The thickness of the gate dielectric layer 109 and its dielectric constant are carefully selected to optimize the balance between the electric field generated by the gate structure 102 and the integrity of the gate dielectric layer 109, so that the breakdown voltage of the gate dielectric layer 109 can be adjusted to an appropriate range. In some embodiments, the thickness of the gate dielectric layer 109 is further based on the operating voltage of the transistor 110, that is, the voltage applied to the gate structure 102, the source region 104 and / or the drain region 106. The gate dielectric layer 109 is associated with the non-wraparound gate type transistors 110, 120 in the substrate 101. In some embodiments, the gate dielectric layer 109 includes at least two layers: one layer can be a gate silicon oxide layer 105 (or a so-called junction layer) in direct contact with the surface of the substrate 101, and the other layer can be a high dielectric constant dielectric layer 107 stacked on the gate silicon oxide layer 105. The gate silicon oxide layer 105 is formed by a thermal growth process at a temperature greater than 1000° C., and the high-k dielectric layer 107 (such as HfO 2 or ZrO 2 ) is formed by a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc., depending on the required degree of precision.

[0040] In some embodiments, the thickness of the gate silicon oxide layer 105 is greater than about 1.8 nm. In some embodiments, the thickness of the high-k dielectric layer 107 is between about 8 nm and 20 nm.

[0041] refer to Figure 1B , transistor 120 includes substrate 101, gate structure 112, isolation region 103, source region 114, drain region 116, a pair of gate spacers 118, and gate dielectric layer 119. Source region 114 and drain region 116 are formed in fin structure 111. In some embodiments, fin structure 111 is etched at the location of source region 114 and drain region 116, and an epitaxial layer is formed on fin structure 111 or on substrate 101 on both sides of gate structure 112. For clarity and simplicity, Figure 1B Some features of transistor 120 are omitted, such as a lightly doped drain (LDD) region, a gate contact, a source contact, a drain contact, a contact etch stop layer, an interlayer dielectric (ILD) layer, etc.

[0042] The gate structure 112, the source region 114, and the drain region 116 may be electrically coupled to respective voltage sources via a gate contact, a source contact, and a drain contact (not shown separately), respectively, for turning on and off a channel current flowing in a channel region (not shown separately) of the fin structure 111 covered by a gate dielectric layer 119 and on the substrate 101 between the source region 114 and the drain region 116. In some embodiments, the gate dielectric layer 119 is formed of a dielectric material, such as silicon oxide or other suitable dielectric materials. The gate dielectric layer 119 is used to electrically isolate the gate structure 112 from the channel region, so that carriers can be attracted by the electric field generated by the gate structure 112, and the carriers can flow in the channel region. Since a fin-type fin structure 111 is used in the transistor 120, in which the channel region is surrounded by the gate structure 112 on both sides and the upper side of the fin structure 111, the transistor 120 is called a fin-type transistor. The current control and electric field distribution of transistor 120 are better than those of transistor 110 , and thus transistor 120 may provide improved performance and reduced power consumption compared to transistor 110 .

[0043] The material and thickness of the gate dielectric layer 119 play an important role in ensuring that the transistor 120 functions properly. The thickness of the gate dielectric layer 119 and its dielectric constant are carefully selected to optimize the balance between the electric field generated by the gate structure 112 and the integrity of the gate dielectric layer 119, so that the breakdown voltage of the gate dielectric layer 119 can be adjusted to an appropriate range. In some embodiments, the thickness of the gate dielectric layer 119 is also based on the operating voltage of the transistor 120, that is, the voltage applied to the gate structure 112, the source region 114 and / or the drain region 116. In some embodiments, the gate dielectric layer 119 includes at least two layers: one layer may be a gate silicon oxide layer 115 (or a so-called junction layer) in direct contact with the fin structure 111, and the other layer may be a high dielectric constant dielectric layer 117 stacked on the gate silicon oxide layer 115. The gate silicon oxide layer 115 is formed by a thermal growth process at a temperature greater than 1000° C., and the high dielectric constant dielectric layer 117 (such as HfO2 or ZrO2) is formed by a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc., depending on the required degree of precision.

[0044] In some embodiments, the thickness of gate silicon oxide layer 115 is greater than about 1.5 nm. In some embodiments, the thickness of gate silicon oxide layer 115 is less than the thickness of gate silicon oxide layer 105. In some embodiments, the thickness of high-k dielectric layer 117 is between about 3 nm and 15 nm.

[0045] refer to Figure 1C, the transistor 130 includes a substrate 101, a gate structure 122, an isolation region 103, a plurality of source regions 124, a plurality of drain regions 126, and a gate dielectric layer 129. The source regions 124 and the drain regions 126 are formed on both sides of the plurality of nanosheet structures 121. In some embodiments, the nanosheet structure 121 is etched at the locations of the source regions 124 and the drain regions 126, and an epitaxial layer is formed on both sides of the nanosheet structure 121. For the sake of clarity and simplicity, Figure 1C Some features of transistor 130 are omitted, such as a lightly doped drain (LDD) region, a gate contact, a source contact, a drain contact, a contact etch stop layer, an inter-layer dielectric (ILD) layer, etc.

[0046] The gate structure 122, the source region 124, and the drain region 126 may be electrically coupled to respective voltage sources via a gate contact, a source contact, and a drain contact (not shown separately), respectively, for turning on and off a channel current flowing in a channel region (not shown separately) of the nanosheet structure 121 between the source region 124 and the drain region 126 covered by a gate dielectric layer 129. In some embodiments, the gate dielectric layer 129 is formed of a dielectric material, such as silicon oxide or other suitable dielectric materials. The gate dielectric layer 129 is used to electrically isolate the gate structure 122 from the channel region, so that carriers can be attracted by the electric field generated by the gate structure 122, and the carriers can flow in the channel region. Since the nanosheet structure 121 is used in the transistor 130, wherein the channel region in the nanosheet structure 121 is surrounded by the gate structure 122 on four sides, the transistor 130 is called a gate-all-around (GAA) type transistor. Other types of all-around gate transistors, such as nanowire transistors, are also within the contemplated scope of all-around gate transistors. The current control and electric field distribution of transistor 130 are superior to those of transistors 110 and 120, and thus transistor 130 may provide improved performance and reduced power consumption compared to transistors 110 and 120.

[0047] In some embodiments, the non-wrap-around gate transistors 110 , 120 operate at a first voltage, and the wrap-around gate transistors operate at a second voltage that is less than the first voltage.

[0048] The material and thickness of the gate dielectric layer 129 play an important role in ensuring that the transistor 130 functions properly. The thickness of the gate dielectric layer 129 and its dielectric constant are carefully selected to optimize the balance between the electric field generated by the gate structure 122 and the integrity of the gate dielectric layer 129, so that the breakdown voltage of the gate dielectric layer 129 can be adjusted to an appropriate range. In some embodiments, the thickness of the gate dielectric layer 129 is also based on the operating voltage of the transistor 130, that is, the voltage applied to the gate structure 122. The gate dielectric layer 129 is associated with the wrap-around gate transistor 130 in the substrate 101. In some embodiments, the gate dielectric layer 129 includes at least two layers: one layer can be a gate silicon oxide layer 125 (or a so-called junction layer) in direct contact with the nanosheet, and the other layer can be a high dielectric constant dielectric layer 127 stacked on the gate silicon oxide layer 125. The gate silicon oxide layer 125 is formed by a thermal growth process at a temperature greater than 1000° C., and the high dielectric constant dielectric layer 127 (such as HfO2 or ZrO2) is formed by a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc., depending on the required degree of precision.

[0049] In some embodiments, the thickness of the gate silicon oxide layer 125 is less than about 1.0 nm. In some embodiments, the thickness of the high-k dielectric layer 127 is between about 3 nm and 10 nm. In some embodiments, the first combined thickness of the gate silicon oxide layer 125 and the high-k dielectric layer 127 is less than the second combined thickness of the gate silicon oxide layer 115 and the high-k dielectric layer 117 in the transistor 120 or the third combined thickness of the gate silicon oxide layer 105 and the high-k dielectric layer 107 in the transistor 110. In some embodiments, the first combined thickness is at least 20%, 40%, or 50% less than the second or third combined thickness.

[0050] Figure 2 According to some embodiments, Figure 1C FIG. 1 is a schematic cross-sectional view of the transistor 130 along the section line CC. Figure 2 In addition to the substrate 101, the gate structure 122, the source region 124, the drain region 126, and the gate dielectric layer 129, the transistor 130 further includes a bottom dielectric layer 202, a plurality of channel regions 212, and a plurality of internal spacers 214. In some embodiments, the gate dielectric layer 129 includes a junction layer 222 and a high-k dielectric layer 224. In some embodiments, the gate structure 122 includes one or more metal layers, for example, one or more diffusion barrier layers, one or more capping layers, one or more work function adjustment layers, and a filling layer. In addition, the source region 124 is formed to join the source region 124 for each channel region 212, and the drain region 126 is formed to join the drain region 126 for each channel region 212.

[0051] refer to Figure 1C and 2 In some embodiments, the gate structure 122 fills the space between adjacent channel regions 212. In some embodiments, the gate dielectric layer 129 surrounds the channel region 212 and is disposed between the gate structure 122 and the channel region 212. Based on the above, it is apparent that the size of the gate structure 122 and the gate dielectric layer 129 is constrained by the gap between adjacent channel regions 212. In addition, in order to maintain the desired channel current control, the gate structure 122 must be formed with sufficient thickness. Therefore, the thickness of the gate dielectric layer 129 is constrained. Since the thickness of the gate dielectric layer 129 is closely related to the breakdown voltage and operating voltage range of the transistor 130, the transistor 130 may not be suitable for relatively high voltage applications. Some peripheral circuits that are not core circuits are operated at a voltage greater than the core circuit voltage. Therefore, the thickness of the gate dielectric layer 129 may be limited to a level that is not suitable for non-core circuits, and thus a semiconductor device manufactured with an insufficiently thick gate dielectric layer 129 may face reliability issues despite having a wrap-around gate type transistor structure.

[0052] Some efforts have been made in the industry to fabricate gate-all-around transistors and non-gate-all-around transistors on the same semiconductor wafer to implement core circuits and non-core circuits of semiconductor devices. However, as described above, since the gate dielectric layer 129 specifications for core circuit and non-core circuit applications are significantly different from each other, it may be difficult for deposition equipment to deposit the gate dielectric layer 129 with substantially different core circuit and non-core circuit deposition requirements. Generally, the space between the channel regions of the gate-all-around transistors in the non-core circuit is allocated for the deposition of the gate dielectric layer and the gate structure. In a similar embodiment, in order to obtain different gate dielectric thicknesses in the gate-all-around structures of the core circuit and the non-core circuit on the same wafer, an additional step is performed before the gate dielectric deposition step, such as by etching or thinning adjacent nanosheet layers to selectively expand the space between the channel regions of the gate-all-around transistors in the non-core circuit. Such additional steps performed in the gate-all-around transistors in the non-core circuit increase manufacturing complexity and production costs, and reduce yield.

[0053] Therefore, the present disclosure proposes different viewpoints to solve the deposition problem. Since non-core circuits are not involved in the main task of high-speed, high-capacity computing operations, such non-core circuits can be manufactured on a substrate or wafer using a process that is less advanced than the core circuits, and then joined to core circuits manufactured on another independent substrate or wafer using a process that is more advanced than the non-core circuits, so as to form a semiconductor structure or semiconductor device that meets existing needs. Therefore, a semiconductor structure or device formed according to processes (or so-called process nodes) of different levels of advancement may include a core circuit with high-speed, low-power computing capabilities and a peripheral non-core circuit capable of sustained high operating voltage or current. Therefore, a high-speed computing processor can be obtained without sacrificing the reliability of the peripheral non-core circuits.

[0054] Figure 3A 3 is a schematic top view of a semiconductor wafer 300 according to some embodiments of the present disclosure, which may be a peripheral wafer having non-core circuits as described herein. The semiconductor wafer 300 includes a substrate. In some embodiments, the substrate includes a semiconductor material, such as bulk silicon. In some embodiments, the substrate includes other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, etc. In some embodiments, the substrate is a P-type semiconductor substrate (acceptor type). In some other embodiments, an N-type semiconductor substrate (donor type) is used. Alternatively, the substrate includes another elemental semiconductor, such as germanium; a compound semiconductor, including gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. In some embodiments, the substrate includes a portion forming a semiconductor-on-insulator (SOI) substrate. In other embodiments, the substrate may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer covering another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

[0055] In some embodiments, the semiconductor wafer 300 is divided into a plurality of device regions 302. The device regions 302 are separated and defined by a plurality of staggered scribe lines, which are also referred to as scribe line regions 304. The device regions 302 may be arranged in an array of substantially equal areas from a top view. The scribe line regions 304 may include parallel lines extending along the X direction and parallel lines extending along the Y direction perpendicular to the X direction, wherein the scribe line regions 304 serve as regions to divide the semiconductor wafer 300 into individual device regions 302.

[0056] In some embodiments, each of the device regions 302 includes a die region 310 and an interconnect region 320 adjacent to the die region 310 . Figure 3ATwo types of device regions 302 are shown, wherein the die region 310 (including the die regions 310A and 310B) and the interconnect region 320 (including the interconnect regions 320A and 320B) are configured in different ways. Figure 3A In the upper right sub-figure, the die area 310A and the interconnection machine area 320A are arranged side by side, that is, the die area 310A of the device area 302 and the interconnection machine area 320A of the same device area 302 share a side surface. Figure 3A In the lower right sub-figure, the four sides of the die region 310B are surrounded by the interconnect region 320B. In some embodiments, the four outer sides of the die region 310B contact the four inner sides of the interconnect region 320B. In some embodiments, the interconnect region 320 is a part of the interconnect structure of the device region 302.

[0057] In some embodiments, some semiconductor devices or components thereof are formed on or in the substrate of the die region 310 of each of the device regions 302. For example, some conductive features, semiconductor features, and dielectric features are formed or patterned on the substrate. Such components may form passive components such as resistors, capacitors, inductors, diodes, fuses, etc., or active components such as field effect transistors (FETs), bipolar junction transistors (BJTs), planar transistors, fin transistors, etc. In some embodiments, the die region 310 includes non-core circuits, such as peripheral circuits associated with non-wrap-around gate transistors, input / output circuits, analog circuits, power circuits, memory circuits, etc.

[0058] Figure 3B FIG. 3 is a top view of another semiconductor wafer 301 or a core wafer having a core circuit as referred to herein according to some embodiments. The semiconductor wafer 301 includes a substrate similar to the semiconductor wafer 300. The semiconductor wafer 301 is similar to the semiconductor wafer 300 in many aspects, and similar features are not described again.

[0059] In some embodiments, the semiconductor wafer 301 is divided into a plurality of device regions (die regions) 303 by scribe lines 305. In some embodiments, each of the device regions 303 includes a die region 330 and an interconnect region 340 adjacent to the die region 330. Figure 3B Two types of device regions 303 are shown, wherein the die region 330 (including the die regions 330A and 330B) and the interconnect region 340 (including the interconnect regions 340A and 340B) are configured in different ways. Figure 3B In the upper right sub-figure, the die area 330A and the interconnection machine area 340A are arranged side by side, that is, the die area 330A and the interconnection machine area 340A of the same device area 303 share a side surface. Figure 3BIn the lower right sub-figure, the four sides of the die region 330B are surrounded by the interconnect region 340B. In some embodiments, the four outer sides of the die region 330B contact the four inner sides of the interconnect region 340B. In some embodiments, the interconnect region 340 is a part of the interconnect structure of the device region 303.

[0060] In some embodiments, some semiconductor devices or components thereof are formed on or in the substrate of the die region 330 of each of the device regions 303. For example, some conductive features, semiconductor features, and dielectric features are formed or patterned on the substrate. Such components may form passive components such as resistors, capacitors, inductors, diodes, fuses, etc., or active components such as field effect transistors (FETs), wrap-around gate transistors, nanosheet transistors, nanowire transistors, etc. In some embodiments, the die region 330 includes core circuits associated with wrap-around gate transistors.

[0061] Figure 4A , 4B , 4C, 4D, 4E, 4F and 4G are cross-sectional schematic diagrams of intermediate stages of a method of forming a semiconductor wafer 300 or a peripheral wafer having non-core circuits as referred to herein according to some embodiments. Figures 4A to 4G The cross-section diagram is along Figure 1A It should be understood that the section line AA can be obtained at Figures 4A to 4G Additional steps are provided before, during, and after the steps shown, and some of the steps described below may be Figures 4A to 4G In other embodiments of the method shown, the steps are replaced or eliminated. For different embodiments of the present disclosure, the order of each step can be changed as needed.

[0062] refer to Figure 4A , providing or forming a blank semiconductor wafer 300 including a substrate layer 402. The substrate layer 402 includes a semiconductor substrate 401, whose material is the same as Figure 3A The material of the substrate of the semiconductor wafer 300 is similar. Subsequently, a plurality of isolation regions 306 and 308 are formed on the surface of the semiconductor substrate 401. The isolation regions 306 and 308 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. The isolation regions 306 and 308 are used to define and electrically separate the die region 310 and the interconnect region 320.

[0063] refer to Figure 4B , a well region 312 is formed in the grain region 310 near the surface of the semiconductor substrate 401. The well region 312 may be formed by an ion implantation operation. In some embodiments, the well region 312 may be doped with an N-type dopant, such as phosphorus, arsenic, etc., or a P-type dopant, such as boron, indium, etc.

[0064] The gate layer 404 is formed on the substrate layer 402. First, the gate dielectric layer 324 is deposited on the surface of the semiconductor substrate 401. Subsequently, the gate structure 322 is formed on the gate dielectric layer 324. The formation of the gate structure 322 includes performing a blanket deposition to form a dummy gate layer or a polysilicon gate layer on the gate dielectric layer 324, and performing a patterning operation to define the size of the gate structure 322 and the gate dielectric layer 324. In some embodiments, a pair of gate spacers 326 are formed on both sides of the gate structure 322. The gate dielectric layer 324 on the semiconductor substrate 401 is associated with the non-wraparound gate transistors 110 and 120 in the surrounding wafer. In some embodiments, the gate dielectric layer 324 includes at least two layers: one layer may be a gate silicon oxide layer 305 (or a so-called junction layer) directly in contact with the surface of the semiconductor substrate 401, and the other layer may be a high dielectric constant dielectric layer 307 stacked on the gate silicon oxide layer 305. The gate silicon oxide layer 305 is formed by a thermal growth process at a temperature greater than 1000° C., and the high-k dielectric layer 307 is formed by a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc., depending on the required accuracy.

[0065] refer to Figure 4C , a source region 314 and a drain region 314 (collectively referred to as source / drain regions 314) are formed in the semiconductor substrate 401 on both sides of the gate spacer 326. The gate spacer 326 may serve as a spacer between the gate structure 322 and the source region 314, or as a spacer between the gate structure 322 and the drain region 314. The source / drain region 314 may be formed by an ion implantation operation.

[0066] refer to Figure 4D , an interlayer dielectric (ILD) layer 332 is deposited on the substrate layer 402 and laterally surrounds the gate structure 322. Although not shown separately, a replacement gate process can be performed to remove the dummy gate layer and deposit a metallic gate electrode to replace the dummy gate layer. In addition, a plurality of contacts (including a source contact 334 and a drain contact 334) are formed in the interlayer dielectric layer 332 and are electrically coupled to the corresponding source / drain regions 314. In some embodiments, a gate contact 336 is formed on the gate structure 322 and electrically coupled thereto. Thus, the planar transistor 110 is formed on the semiconductor wafer 300.

[0067] refer to Figure 4E, a plurality of substrate vias (TSVs) 348 are formed in the interconnect region 320 and extend through the gate layer 404 and into the substrate layer 402. The substrate vias 348 are exposed at the surface of the gate layer 404. The substrate vias 348 may include a redistribution layer 406 (e.g. Figure 4F Substrate vias 348 may be used to electrically couple transistors 110 of semiconductor wafer 300 to and from external circuits outside the semiconductor structure or semiconductor device.

[0068] refer to Figure 4F , a redistribution layer (RDL) 406 is formed on the gate layer 404. The redistribution layer 406 can be regarded as a device region 302 (eg, Figure 3A 300). The redistribution layer 406 is configured to electrically interconnect components of the gate layer 404, or to electrically couple components of the gate layer 404 to a capping layer or external circuit of the semiconductor wafer 300. The redistribution layer 406 may include a plurality of metal line layers, wherein each of the metal line layers includes a plurality of conductive wires 344. The conductive wires 344 in each metal line layer extend in a horizontal direction and are interconnected via adjacent vertical conductive vias 346 or substrate vias 348 in individual conductive via layers. The conductive wires 344 and conductive vias 346 are formed of a conductive material such as copper, tungsten, aluminum, silver, titanium, tantalum, combinations thereof, and the like. The conductive wires 344 and conductive vias 346 may be electrically insulated by one or more intermetallic dielectric (IMD) layers 342. The intermetallic dielectric layer 342 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a polymeric material, and the like. The number and configuration of the metal line layers and the conductive via layers used for the conductive lines 344 and the conductive vias 346 can be configured as required to cope with different applications, and the present disclosure is not limited thereto.

[0069] refer to Figure 3A and 4F In some embodiments, the substrate layer 402 and the gate layer 404 include a plurality of device regions 302 on the first semiconductor wafer 300 (although Figure 4F Only one example device region 302 is shown, wherein each of the device regions 302 includes a die region 310 and one or more interconnect regions 320. In addition, in some embodiments, the redistribution layer 406 disposed on the plurality of device regions 302 together with the interconnect regions 320 form an interconnect structure for the die region 310 in each of the plurality of device regions 302. As described below, the interconnect structure is configured to transmit power or electrical signals between the non-wrap-around gate transistors 110, 120 in the peripheral wafer and the wrap-around gate transistor 130 in the core wafer.

[0070] refer to Figure 4G, the back side of substrate layer 402 is thinned to expose one end of substrate via 348. Thinning can be performed by chemical mechanical polishing (CMP) operation, mechanical grinding, or other suitable planarization operation. In some embodiments, the bottom of isolation regions 306 and 308 is exposed after the thinning operation.

[0071] Figure 5 According to some embodiments Figure 3A FIG. 3 is a schematic cross-sectional view of a semiconductor wafer 300 . Figure 5 The semiconductor wafer 300 is shown with Figure 4G The semiconductor wafer 300 shown is similar, and similar features are not described again. Figure 5 The semiconductor wafer 300 is shown with Figure 4G The semiconductor wafer 300 shown is different mainly in that (in some embodiments but not limited to the contents of the present disclosure) Figure 5 ) The substrate via 348 does not exist in the semiconductor wafer 300 or the surrounding wafers, such as Figure 5 shown.

[0072] It should be noted that Figure 4G and Figure 5 The semiconductor wafer 300 is shown for illustration purposes only. Other examples of non-wraparound gate transistors are also within the intended scope of the present disclosure. For example, the planar transistor 110 may be replaced with a fin transistor 120 or other non-wraparound gate transistors, but the present disclosure is not limited thereto.

[0073] Fig. 6A According to some other embodiments (such as Figure 3B ) is a cross-sectional schematic diagram of the semiconductor wafer 301 referred to in this article or the core wafer with core circuits. Fig. 6A The cross-section diagram is along Figure 1C The section line CC is obtained. Fig. 6A The semiconductor wafer 301 shown is similar to the first semiconductor wafer 300, and similar features are not described again. The semiconductor wafer 301 differs from the semiconductor wafer 300 mainly in that the semiconductor wafer 301 includes a plurality of wrap-around gate transistors 130 instead of planar transistors 110 or fin transistors 120. Fig. 6A As shown, semiconductor wafer 301 includes substrate layer 502 and gate layer 504 above substrate layer 502. The materials, configurations, and formation methods of substrate layer 502 and gate layer 504 are similar to those of substrate layer 402 and gate layer 404, respectively. Surround gate transistor 130 is formed in gate layer 504 and includes bottom dielectric layer 202, a plurality of channel regions 212, and a plurality of internal spacers 214. In some embodiments, as Figure 2As shown, the gate dielectric layer 129 includes a junction layer 222 and a high-k dielectric layer 224. In some embodiments, the gate structure 122 includes one or more metal layers, such as one or more diffusion barrier layers, one or more capping layers, one or more work function adjustment layers, and a filling layer. In addition, the source region 124 is a junction source region 124 formed for each channel region 212, and the drain region 126 is a junction drain region 126 formed for each channel region 212. Therefore, the wrap-around gate transistor 130 is formed on the semiconductor wafer 301.

[0074] Figure 6B For some embodiments according to the present disclosure Figure 3B FIG. 3 is a schematic cross-sectional view of a semiconductor wafer 301 . Figure 6B The semiconductor wafer 301 is shown with Fig. 6A The semiconductor wafer 301 shown is similar and similar features are not described again. Figure 6B The semiconductor wafer 301 is shown with Fig. 6A The semiconductor wafer 301 shown is different mainly in that Figure 6B The semiconductor wafer 301 is shown to further include a redistribution layer 506 or interconnect structure on the gate layer 504. The material, configuration and formation method of the redistribution layer 506 are similar to the material, configuration and formation method of the redistribution layer 406. The redistribution layer 506 is electrically connected to the surrounding gate transistor 130 via the source / drain contacts 334 or the gate contacts 336 deposited in the portion of the gate layer 504 on the surrounding gate transistor 130.

[0075] refer to Figure 3B and 6B In some embodiments, the substrate layer 502 and the gate layer 504 include a plurality of device regions 303 on the semiconductor wafer 301, wherein each of the device regions 303 includes a die region 330 and one or more interconnect regions 340. In addition, in some embodiments, a redistribution layer 506 deposited on the plurality of device regions 303 forms an interconnect structure for each die region 330 in the plurality of device regions 303. As described below, the interconnect structure is configured to transmit power or electrical signals between the non-surround gate transistors 110, 120 of the peripheral wafer and the surround gate transistor 130 of the core wafer.

[0076] Figure 77 is a schematic cross-sectional view of a semiconductor structure 700 according to some embodiments. It should be noted that the name of the semiconductor structure can be interchanged with the name of the semiconductor device herein. The semiconductor structure 700 is formed by bonding a semiconductor wafer 300 (or peripheral wafer) to a semiconductor wafer 301 (or core wafer). Each of the die regions 310 on the semiconductor wafer 300 is electrically coupled to a corresponding one of the die regions 330 on the semiconductor wafer 301. In some embodiments, before the bonding operation, each of the die regions 310 on the semiconductor wafer 300 is aligned in a vertical direction with a corresponding one of the die regions 330 on the semiconductor wafer 301. Similarly, each of the interconnect regions 320 on the semiconductor wafer 300 is aligned in a vertical direction with a corresponding one of the interconnect regions 340 on the semiconductor wafer 301.

[0077] The redistribution layer 406 of the semiconductor wafer 300 is bonded to the redistribution layer 506 of the semiconductor wafer 301. The bonding structure BS is formed by bonding the semiconductor wafer 300 and the semiconductor wafer 301 by the redistribution layer 406 and the redistribution layer 506. For example, the uppermost metal line layer of the redistribution layer 506 and the lowermost metal line layer of the redistribution layer 406 form the bonding structure BS of the semiconductor structure 700. As described below, the bonding structure BS is configured to supply power or transmit electrical signals to the surrounding gate type transistor 130 via the non-surrounding gate type transistors 110 and 120.

[0078] In some embodiments, bonding structure BS may be a hybrid bonding layer, wherein the exposed bonding pad 344A and the dielectric surface above redistribution layer 406 are bonded to the corresponding bonding pad 344B and the dielectric surface above redistribution layer 406. In some embodiments, semiconductor structure 700 is formed by front side bonding, wherein the front side of semiconductor wafer 300 faces the front side of semiconductor wafer 301.

[0079] In some embodiments, the semiconductor structure 700 in chip form is subsequently cut or separated into individual semiconductor structures. A cutting tool 710 may be used to perform the cutting operation. The cutting tool 710 may include a cutting laser, a cutting blade, etc.

[0080] Fig. 8A and 8B FIG. 3 is a cross-sectional view of an intermediate stage of a method for bonding a semiconductor wafer 300 to a semiconductor wafer 301 according to some embodiments of the present disclosure. Fig. 8A , a plurality of connectors 702 are formed above the redistribution layer 506 of the semiconductor wafer 301. The connectors 702 are configured to electrically connect the redistribution layer 506 to the redistribution layer 406 of the semiconductor wafer 300, such as Figure 8BAs shown. Connector 702 may include conductive materials such as conductive bumps, micro bumps, goal array bumps, controlled collapse chip connection (C4) bumps, etc. Connector 702 may include solder joints or soft metal materials. In some embodiments, the solder joints include materials such as tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), combinations thereof, or mixtures of other conductive materials. In one embodiment, the solder material is a lead-free material.

[0081] refer to Figure 8B , the semiconductor wafer 300 is bonded to the semiconductor wafer 301 via the connector 702. A flip-chip bonding operation may be performed, wherein the front side of the semiconductor wafer 300 is flipped and bonded to the semiconductor wafer 301. The bonding structure BS is formed by the redistribution layer 406, the connector 702, and the redistribution layer 506. For example, the under bump metal (UBM) 344A of the redistribution layer 406 is bonded to the under bump metal (UBM) 344B of the redistribution layer 506 via the connector 702. As described below, the bonding structure BS is configured to supply power or transmit electrical signals to the surrounding gate transistor 130 in the core wafer via the non-surrounding gate transistors 110, 120 in the peripheral wafer. In some embodiments, the semiconductor structure 800 is formed by front side bonding, wherein the front side of the semiconductor wafer 300 faces the front side of the semiconductor wafer 301.

[0082] Fig. 9 Schematic cross-sectional view of a semiconductor structure 900 according to some embodiments of the present disclosure. The semiconductor structure 900 is similar to the semiconductor structure 700, and similar features are not described repeatedly. The semiconductor structure 900 differs from the semiconductor structure 700 primarily in that the semiconductor structure 900 is formed by front-to-back bonding, wherein the front side of the semiconductor wafer 301 faces the back side of the semiconductor wafer 300. In some embodiments, the bonding structure BS may be a hybrid bonding layer, wherein the bonding pad 344B and the dielectric surface above the redistribution layer 506 are connected to the corresponding bonding pad and dielectric surface of the back side redistribution layer (not shown) on the back side of the semiconductor wafer 300. The back side redistribution layer of the semiconductor wafer 300 may be directly electrically coupled to the substrate via 348 of the semiconductor wafer 300.

[0083] Fig.101 is a schematic cross-sectional view of a semiconductor structure 1000 according to some embodiments of the present disclosure. The semiconductor structure 1000 is similar to the semiconductor structure 800, and similar features are not described again. The semiconductor structure 1000 differs from the semiconductor structure 800 primarily in that the semiconductor structure 1000 is formed by a front-to-back bonding method, wherein the front side of the semiconductor wafer 301 faces the back side of the semiconductor wafer 300. In some embodiments, the bonding is performed by forming the connector 702 on the under bump metal (UBM) 344B of the redistribution layer 506 and electrically connecting to the under bump metal (UBM) on the back side redistribution layer (not shown) disposed at the back side of the semiconductor wafer 300.

[0084] Fig.11 FIG. 1 is a schematic cross-sectional view of a semiconductor structure 1100 according to some embodiments of the present disclosure. Figure 8B The semiconductor structure 1100 is similar to the semiconductor structure 800 shown, and similar features are not described again. The semiconductor structure 1100 differs from the semiconductor structure 800 mainly in that the semiconductor wafer 300 further includes a substrate via 348 formed in the interconnect region 320 and electrically coupled to the redistribution layer 406. The different applications of the semiconductor structures 800 and 1100 of the present disclosure are as follows: Fig.15 and Fig.17 described.

[0085] Fig.12 FIG. 1 is a schematic cross-sectional view of a semiconductor structure 1200 according to some embodiments of the present disclosure. Fig.10 The semiconductor structure 1200 is similar to the semiconductor structure 1000, and similar features are not described again. The semiconductor structure 1200 differs from the semiconductor structure 1000 mainly in that the substrate via 348 of the semiconductor wafer 301 is omitted. The different applications of the semiconductor structures 1000 and 1200 of the present disclosure are as follows: Fig.16 and Fig.18 described.

[0086] Fig.13A , 13B 13C and 13D are cross-sectional views of intermediate stages of a method of bonding a semiconductor wafer 301 to a semiconductor wafer 300 to form a semiconductor structure 1300 according to some embodiments of the present disclosure. Fig.13A , a plurality of connectors 802 are formed above the redistribution layer 406 of the semiconductor wafer 300. The connectors 802 are configured to transmit electrical signals between the semiconductor wafer 300 and the semiconductor wafer 301, such as Fig. 13BAs shown. For example, connector 802 is connected to an under bump metal (UBM) of a backside redistribution layer (not shown) disposed at the back side of semiconductor wafer 301. Connector 802 may include conductive materials such as conductive bumps, micro bumps, goal array bumps, C4 bumps, etc. The material and configuration of connector 802 are similar to the material and configuration of connector 702. Semiconductor structure 1300 is formed by a front-to-back bonding method, wherein the front side of semiconductor wafer 300 faces the back side of semiconductor wafer 301.

[0087] refer to Fig. 13C , the back side of the semiconductor wafer 300 is thinned until the end of the substrate via 348 is exposed. The thinning operation can be performed using chemical mechanical polishing, mechanical grinding, or other suitable planarization methods. For example, the bottom end of the substrate via 348 in the semiconductor wafer 300 is exposed through the thinning operation. The exposed end of the substrate via 348 can be further connected to an external signal or power supply.

[0088] refer to Fig.13D , a plurality of connectors 804 are disposed at the exposed ends of substrate vias 348 in semiconductor wafer 300. Connectors 804 are configured to electrically connect semiconductor structure 1300 to an external circuit. Connectors 804 may include conductive materials such as conductive bumps, micro bumps, goal array bumps, C4 bumps, etc. The materials and configurations of connectors 804 are similar to those of connectors 702 or 802. In some embodiments, semiconductor structure 1300 is formed by front-to-back bonding, where the front side of semiconductor wafer 300 faces the back side of semiconductor wafer 301.

[0089] Fig.14 FIG. 14 is a schematic cross-sectional view of a semiconductor structure 1400 according to some embodiments of the present disclosure. The semiconductor structure 1400 is similar to the semiconductor structure 1300 shown in FIG. 13 , and similar features are not described again. The semiconductor structure 1400 differs from the semiconductor structure 1300 mainly in that Fig.14 The semiconductor wafer 300 and the semiconductor wafer 301 are bonded by a hybrid bonding structure.

[0090] In some embodiments, the bonding structure BS is formed by the redistribution layer 406 of the semiconductor wafer 300 and the backside redistribution layer (not shown) of the semiconductor wafer 301. For example, the hybrid bonding interface of the redistribution layer 406 of the semiconductor wafer 300 may contact the corresponding hybrid bonding interface of the backside redistribution layer (not shown) of the semiconductor wafer 301. The backside redistribution layer (not shown) of the semiconductor wafer 301 is at least electrically coupled to the substrate via 348 in the semiconductor wafer 301.

[0091] Fig.15FIG. 1 is a schematic diagram of a transmission path P1 of power and / or signals of a semiconductor structure 1500 according to some embodiments of the present disclosure. It should be noted that the name of the semiconductor structure can be interchanged with the name of the semiconductor device herein. The semiconductor structure 1500 can be electrically coupled to an external power source / ground or signal source / signal receiving point to communicate power or electrical signals.

[0092] The transmission path P1 is used to represent how power is electrically connected between a power source (outside the semiconductor structure 1500) and a ground terminal (outside the semiconductor structure 1500), or how an electrical signal is transmitted between a signal source (outside the semiconductor structure 1500) and a signal receiving point (outside the semiconductor structure 1500). In some embodiments, the non-core circuit in the peripheral substrate (i.e., the cut version of the aforementioned semiconductor wafer 300) is configured as an interface circuit between an external circuit (e.g., a power / ground network or a signal network) and a core circuit in the core substrate (i.e., the cut version of the aforementioned semiconductor wafer 301). Therefore, power or electrical signals from the external circuit can be transmitted to the core circuit in the core substrate via the non-core circuit in the peripheral substrate. Similarly, power or electrical signals output from the core circuit in the core substrate can be transmitted to the external circuit via the non-core circuit in the peripheral substrate.

[0093] refer to Fig.15 For example, in the chip-in direction, the transmission path P1 covers the path from the input terminal IP1 (such as the connector 804 in the interconnect region 340 of the semiconductor wafer 301) to the substrate via 348, the redistribution layer 506, the bonding structure BS, the redistribution layer 406, the non-surrounding gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the bonding structure BS and the redistribution layer 506 to reach the surrounding gate transistor 130 in the die region 330 of the semiconductor wafer 301. Fig.15 In the chip-in direction of the transmission path P1 shown, the signal or power passes through the bonding structure BS twice before reaching the core circuit (ie, the gate-all-around transistor 130 in the core wafer).

[0094] In the chip outward direction, the transmission path P1 covers the path from the wraparound gate transistor 130 in the die region 330 of the semiconductor wafer 300 to the redistribution layer 506, the bonding structure BS, the redistribution layer 406, the non-wrapping gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the bonding structure BS, the redistribution layer 506, and the substrate via 348 in the interconnect region 340 of the semiconductor wafer 301 to reach the output end OP1 (such as the connector 804 in the interconnect region 340 of the semiconductor wafer 301). Fig.15In the out-of-chip direction of the transmission path P1 shown, the signal or power passes through the bonding structure BS twice before reaching the output terminal OP1 from the core circuit.

[0095] The configuration of the semiconductor structure 1500 provides several advantages. The input terminal IP1 and the output terminal OP1 of the transmission path P1 are arranged on the same side of the semiconductor structure 1500 (i.e., the back side of the semiconductor wafer 301). There is no substrate via in the semiconductor wafer 300, thereby reducing production complexity and cost. The power / ground network or the signal network can be arranged on the same side of the semiconductor structure 1500, thereby simplifying the corresponding circuit design.

[0096] Fig.16 FIG. 1 is a schematic diagram of a power and / or signal transmission path P2 of a semiconductor device 1600 according to some embodiments of the present disclosure. Fig.16 In the chip-in direction, for example, the transmission path P2 covers the path from the input terminal IP2 (connector 804 in the interconnect region 340 of the semiconductor wafer 301) to the substrate via 348, redistribution layer 506, bonding structure BS in the interconnect region 340 of the semiconductor wafer 301, substrate via 348, redistribution layer 406 in the interconnect region 320 of the semiconductor wafer 300, non-surrounding gate type transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, redistribution layer 406, substrate via 348, bonding structure BS, redistribution layer 506 in the interconnect region 320 of the semiconductor wafer 300 and reaching the surrounding gate type transistor 130 in the die region 330 of the semiconductor wafer 301. Fig.16 In the chip-in direction of the transmission path P2 shown, the signal or power passes through the bonding structure BS twice before reaching the core circuit (ie, the gate-all-around transistor 130 in the core wafer).

[0097] In the chip outward direction, for example, the transmission path P2 covers the path from the wraparound gate transistor 130 in the die area 330 of the semiconductor wafer 301 to the redistribution layer 506, the bonding structure BS, the substrate via 348 in the interconnect area 320 of the semiconductor wafer 300, the redistribution layer 406, the non-wrapping gate transistor 110 or 120 in the die area 310 of the semiconductor wafer 300, the redistribution layer 406, the substrate via 348 in the interconnect area 320 of the semiconductor wafer 300, the bonding structure BS, the redistribution layer 506, and the substrate via 348 in the interconnect area 340 of the semiconductor wafer 301 to reach the output end OP2 (such as the connector 804 in the interconnect area 340 of the semiconductor wafer 301). Fig.16 In the out-of-chip direction of the transmission path P2 shown, the signal or power passes through the bonding structure BS twice before reaching the output terminal OP2 from the core circuit.

[0098] The configuration of the semiconductor device 1600 provides several advantages. The input end IP2 and the output end OP2 of the transmission path P2 are arranged on the same side of the semiconductor device 1600 (i.e., the back side of the semiconductor wafer 301). In addition, there is a substrate via 348 in the semiconductor wafer 300 to facilitate transmission in the front-to-back bonding scheme.

[0099] Fig.17 FIG. 1 is a schematic diagram of a power and / or signal transmission path P3 of a semiconductor device 1700 according to some embodiments. Fig.17 In the chip-in direction, for example, the transmission path P3 covers the path from the input terminal IP3 (such as the connector 804 in the interconnect region 320 of the semiconductor wafer 300), to the substrate via 348 in the interconnect region 320 of the semiconductor wafer 300, the redistribution layer 406, the non-surrounding gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the bonding structure BS, the redistribution layer 506, and reaches the surrounding gate transistor 130 in the die region 330 of the semiconductor wafer 301. Fig.17 In the chip-in direction of the transmission path P3 shown, the signal or power passes through the bonding structure BS only once before reaching the core circuit (ie, the gate-all-around transistor 130 in the core wafer).

[0100] In the chip-out direction, for example, the transmission path P3 covers the path from the wrap-around gate transistor 130 in the die region 330 of the semiconductor wafer 301 to the redistribution layer 506, the bonding structure BS, the redistribution layer 406, the non-wrapped gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the bonding structure BS (including the connector 702), the redistribution layer 506, and the substrate via 348 in the interconnection machine area 340 of the semiconductor wafer 301 to the output terminal OP3 (the connector 804 in the interconnection machine area 340 of the semiconductor wafer 301). The input terminal IP3 and the output terminal OP3 are arranged on opposite sides of the semiconductor device 1700. In the chip-out direction of the transmission path P3 shown, the signal or power passes through the bonding structure BS twice before reaching the output terminal OP3 from the core circuit.

[0101] The configuration of semiconductor device 1700 provides several advantages. The input terminal IP3 and the output terminal OP3 of transmission path P3 are arranged on opposite sides of semiconductor device 1700. Compared with existing semiconductor devices for high-speed operation (in which wrap-around gate type transistors and non-wrapped gate type transistors are integrated in the same wafer, or in which wrap-around gate type transistors are formed in the same wafer and provide different gate dielectric thicknesses for core circuits and non-core circuits), transmission path P3 allows greater design flexibility, increased line spacing, and larger input pad / output pad area / spacing.

[0102] Fig.18 FIG. 1 is a schematic diagram showing a transmission path P4 of power and / or signals of a semiconductor device 1800 according to some embodiments of the present disclosure. Fig.18 In the chip-in direction, the transmission path P4 covers the path from the input terminal IP4 (such as the connector 804 in the interconnect region 320 of the semiconductor wafer 300) to the redistribution layer 406, the non-surrounding gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the substrate via 348 in the interconnect region 320 of the semiconductor wafer 300, the bonding structure BS (including the connector 702), the redistribution layer 506 and the surrounding gate transistor 130 in the die region 330 of the semiconductor wafer 301. Fig.18 In the chip-in direction of the transmission path P4 shown, the signal or power passes through the bonding structure BS only once before reaching the core circuit (ie, the gate-all-around transistor 130 in the core wafer).

[0103] In the chip outward direction, the transmission path P4 covers the path from the wraparound gate transistor 130 in the die region 330 of the semiconductor wafer 301 to the redistribution layer 506, the bonding structure BS (including the connector 702), the substrate via 348 in the interconnect region 320 of the semiconductor wafer 300, the redistribution layer 406, the non-wrapping gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406 and reaches the output terminal OP4 (such as the connector 804 in the interconnect region 320 of the semiconductor wafer 300). Fig.18 In the out-of-chip direction of the transmission path P4 shown, the signal or power passes through the bonding structure BS only once before reaching the output terminal OP4 from the core circuit.

[0104] The configuration of semiconductor device 1800 provides several advantages. The input terminal IP4 and the output terminal OP4 of transmission path P4 are arranged on the same side of semiconductor device 1800 (i.e., the front side of semiconductor wafer 300). There is no substrate via in semiconductor wafer 301, thereby reducing production complexity and cost and obtaining more active area in the core circuit. Power / ground network or signal network can be arranged on the same side of semiconductor structure 1800, thereby simplifying the corresponding circuit design.

[0105] Fig.19 FIG. 1 is a schematic diagram showing a transmission path P5 of power and / or signals of a semiconductor device 1900 according to some embodiments of the present disclosure. Fig.19 , power or electrical signals flow along the transmission path P5 direction. For example, in the chip-in direction, the transmission path P5 covers the path from the input terminal IP5 (connector 804 in the interconnect region 320 of the semiconductor wafer 300) to the substrate via 348 in the interconnect region 320 of the semiconductor wafer 300, the redistribution layer 406, the non-wraparound gate transistor 110 or 120 in the die region 310 of the semiconductor wafer 300, the redistribution layer 406, the bonding structure BS (including the connector 802), the substrate via 348 in the interconnect region 340 of the semiconductor wafer 301, the redistribution layer 506 and the wraparound gate transistor 130 in the die region 330 of the semiconductor wafer 301. In the chip-in direction of the transmission path P5 shown, the signal or power passes through the bonding structure BS only once before reaching the core circuit (i.e., the wraparound gate transistor 130 in the core wafer).

[0106] In the chip outward direction, the transmission path P5 covers the path from the wraparound gate transistor 130 in the die area 330 of the semiconductor wafer 301 to the redistribution layer 506, the substrate via 348 in the interconnection machine area 340 of the semiconductor wafer 301, the bonding structure BS (including the connector 802), the redistribution layer 406, the non-wrapping gate transistor 110 or 120 in the die area 310 of the first semiconductor wafer 300, the redistribution layer 406, and the substrate via in the interconnection machine area 320 of the semiconductor wafer 300 to reach the output terminal OP5 (such as the connector 804 in the interconnection machine area 320 of the semiconductor wafer 300). Fig.19 In the out-of-chip direction of the transmission path P5 shown, the signal or power passes through the bonding structure BS only once before reaching the output terminal OP5 from the core circuit.

[0107] The configuration of semiconductor device 1900 provides several advantages. Input terminal IP5 and output terminal OP5 of transmission path P5 are arranged on the same side of semiconductor device 1900 (i.e., the back side of semiconductor wafer 300). Substrate vias 348 are present in semiconductor wafers 301 and 300 to facilitate signal / power transmission and incorporate front-to-back bonding structures. Power / ground networks or signal networks can be arranged on the same side of semiconductor structure 1900, thereby simplifying the corresponding circuit design.

[0108] The present disclosure discusses a semiconductor structure or a semiconductor device including a core circuit formed by wraparound gate transistors and a non-core circuit formed by non-wrapparound gate transistors. The wraparound gate transistors and the non-wrapparound gate transistors are formed in respective semiconductor wafers. The semiconductor wafer having the core circuit with the wraparound gate transistors is bonded to the semiconductor wafer having the non-core circuit with the non-wrapparound gate transistors. The wraparound gate transistors have a first gate dielectric layer including a first thickness, and the non-wrapparound gate transistors have a second gate dielectric layer including a second thickness greater than the first thickness. Among various types of non-wrapparound gate transistors, the gate dielectric thickness of the planar transistors is greater than the gate dielectric thickness of the fin transistors. After a dicing operation, the semiconductor structure or semiconductor device is formed by bonding a first substrate having the wraparound gate transistors in the core circuit to a second substrate having the non-wrapparound gate transistors in the non-core circuit. The core circuit can operate advanced transistors to perform high-speed tasks, and the non-core circuit can operate at a higher operating voltage without hindering integration with the core circuit. Therefore, the proposed semiconductor structure or semiconductor device may include the most advanced core circuit for use in the latest artificial intelligence or machine learning related applications.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments mentioned herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to the embodiments disclosed herein without departing from the spirit and scope of the present disclosure.

[0110] A brief explanation of the symbols used in the diagram

[0111] 122: Gate structure

[0112] 124: Source region

[0113] 126: Drain region

[0114] 202: bottom dielectric layer

[0115] 212: Channel Area

[0116] 214: Internal spacer

[0117] 222: junction layer

[0118] 224: High dielectric constant dielectric layer

[0119] 300, 301: Semiconductor wafer

[0120] 306,308: Quarantine Area

[0121] 310: Grain area

[0122] 312: Well region

[0123] 314: Source region / drain region

[0124] 320: Internet area

[0125] 322: Gate structure

[0126] 324: Gate dielectric layer

[0127] 326: Gate spacer

[0128] 330: Grain area

[0129] 332: Interlayer dielectric layer

[0130] 334:Contact

[0131] 336: Gate contact

[0132] 340: Internet area

[0133] 342: Intermetallic dielectric layer

[0134] 344: Wire

[0135] 344A, 344B: Bonding pads

[0136] 346: Conductive via

[0137] 348:Substrate access

[0138] 401:Semiconductor substrate

[0139] 402: substrate layer

[0140] 404: Gate layer

[0141] 406:Redistribution layer

[0142] 502: substrate layer

[0143] 504: Gate layer

[0144] 506: Heavy cloth layer

[0145] 700:Semiconductor Structure

[0146] 710: Cutting tools

Claims

1. A semiconductor structure comprising: a first substrate including a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness; and a second substrate bonded to the first substrate and comprising a plurality of second-type transistors formed of wrap-around gate transistors, wherein a gate silicon oxide layer of each of the wrap-around gate transistors has a third thickness; The third thickness is smaller than the first thickness or the second thickness.

2. The semiconductor structure of claim 1, wherein the third thickness is less than about 1 nm.

3. The semiconductor structure of claim 1, wherein the second thickness is substantially equal to or greater than about 1.5 nm.

4. The semiconductor structure of claim 1, wherein the first thickness is substantially equal to or greater than about 1.8 nm.

5. The semiconductor structure of claim 1, wherein the first-type transistors operate at a first voltage, and the second-type transistors operate at a second voltage less than the first voltage.

6. The semiconductor structure according to claim 1, further comprising: A bonding structure is disposed between the first substrate and the second substrate, wherein the first-type transistors and the second-type transistors are interconnected to allow a power signal or an electrical signal input from an input terminal to reach the second-type transistor by first passing through the bonding structure.

7. The semiconductor structure according to claim 6, wherein the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electric signal input from the input terminal to reach the second-type transistors by entering the first-type transistors before passing through the junction structure.

8. The semiconductor structure according to claim 7, wherein the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electric signal output from the second-type transistors to an output terminal to reach the output terminal by first passing through the junction structure.

9. The semiconductor structure of claim 6, further comprising a substrate via in at least one of the first substrate and the second substrate, electrically connected to the bonding structure.

10. The semiconductor structure of claim 6, wherein the bonding structure comprises one of a hybrid bonding layer, an under bump metallurgy, a conductive bump, or a micro bump.

11. The semiconductor structure of claim 1, wherein the second-type transistors form a processor for artificial intelligence machine learning or artificial intelligence deep learning applications.

12. The semiconductor structure according to claim 1, wherein the second substrate comprises at least one of an input / output circuit, an analog circuit, a power circuit, and a memory circuit.

13. A semiconductor device comprising: a first substrate comprising a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein the first-type transistors operate at a first voltage, and wherein each of the plurality of first-type transistors has a first gate silicon oxide layer stacked with a first high-k dielectric layer, the first gate silicon oxide layer and the first high-k dielectric layer having a first combined thickness; and a second substrate bonded to the first substrate and comprising a plurality of second-type transistors formed of gate-all-around transistors, wherein the second-type transistors operate at a second voltage less than the first voltage, and wherein each of the second-type transistors has a second gate silicon oxide layer stacked with a second high-k dielectric layer, the second gate silicon oxide layer and the second high-k dielectric layer having a second combined thickness; The first combined thickness is greater than the second combined thickness.

14. The semiconductor device according to claim 13, wherein the second voltage is provided to the second-type transistors via the first-type transistors and through a bonding structure between the first substrate and the second substrate.

15. The semiconductor device of claim 14, wherein the bonding structure comprises one of a hybrid bonding layer, an under bump metallurgy, a conductive bump, or a micro bump.

16. The semiconductor device of claim 13, wherein the second combined thickness is at least 50% less than the first combined thickness.

17. The semiconductor device of claim 13, wherein at least one of the first substrate and the second substrate comprises a substrate via electrically coupled to the other of the first substrate and the second substrate.

18. A method comprising: Forming a plurality of first die regions on a first semiconductor wafer, wherein each of the first die regions comprises a plurality of first-type transistors formed of planar transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness; forming a plurality of second die regions on a second semiconductor wafer, wherein each of the second die regions comprises a plurality of second-type transistors formed of wrap-around gate transistors, wherein a gate silicon oxide layer of each of the wrap-around gate transistors has a third thickness; and bonding the first semiconductor wafer to the second semiconductor wafer by electrically coupling each of the first die regions to a corresponding one of the second die regions; The third thickness is smaller than the first thickness or the second thickness.

19. The method according to claim 18, further comprising: A substrate via is formed in a first interconnect region of the first semiconductor wafer prior to bonding.

20. The method according to claim 18, before bonding the first semiconductor wafer to the second semiconductor wafer, further comprising: forming a portion of a bonding structure at a front side or a back side of the first semiconductor wafer; and A portion of the bonding structure is formed at a front side or a back side of the second semiconductor wafer.

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