Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals along a second direction; each source electrode bonding pad is located on the corresponding source electrode line, extends in the second direction and is located between the adjacent source electrode lines; the plurality of unit structures are arranged on the source electrode bonding pad along the first direction and the second direction and are connected with the source electrode bonding pad, and at least two unit structures which are mutually staggered in the first direction are positioned on the same source electrode bonding pad; the gate structures extend in the second direction and are connected with the unit structures located on the same source electrode bonding pad; the plurality of drain electrode structures are respectively located above the corresponding source electrode bonding pads, and each drain electrode structure is connected with the unit structure connected with the corresponding source electrode bonding pad; the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Semiconductor transistors (e.g., metal oxide semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, switches, and the like. Traditional MOS transistors use a planar structure. As the technology of semiconductor integrated circuits continues to develop over time, MOS transistors use a stacked structure to achieve miniaturization of transistors. In the design of the stacked structure, a number of source lines are usually formed on a substrate, and then a gate structure is formed on the source line. A number of channel structures are formed in the gate structure, and the channel structure is connected to the source line. A corresponding drain structure is formed on each channel structure, and a drain structure is connected to the source line through a channel structure, so that the driving capability of the semiconductor device is limited, which affects the electrical performance of the semiconductor device. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to improve the electrical performance of the semiconductor device.

[0004] In order to achieve the above object, the present invention provides a semiconductor device, comprising:

[0005] substrate;

[0006] A plurality of source lines are located on the substrate, extending along a first direction and arranged at intervals from each other along a second direction;

[0007] A plurality of source pads, each of the source pads is located on a corresponding source line and extends along the second direction and is located between adjacent source lines;

[0008] A plurality of unit structures are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two of the unit structures that are offset from each other in the first direction are located on the same source pad;

[0009] A gate structure extending along the second direction and connecting the unit structures located on the same source pad;

[0010] A plurality of drain structures are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

[0011] Optionally, both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction extend between adjacent source lines.

[0012] Optionally, the shape of the source pad includes rhombus or rectangle.

[0013] Optionally, a plurality of the source pads are arranged in an array, and two adjacent columns of the source pads are staggered along the second direction.

[0014] Optionally, the four unit structures are located on one source pad and are respectively located at four ends of the source pad.

[0015] Optionally, the gate structure includes a ring-shaped end.

[0016] Optionally, the gate structure includes a first portion and a second portion located on both sides of the unit structure along the first direction, and the first portion and the second portion are connected via the annular end.

[0017] Optionally, a gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between several of the gate structures.

[0018] The present invention also provides a method for preparing a semiconductor device, comprising:

[0019] providing a substrate;

[0020] Forming a plurality of source lines on the substrate, extending along a first direction and arranged at intervals from each other along a second direction;

[0021] forming a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines;

[0022] Forming a plurality of unit structures, which are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two of the unit structures which are offset from each other in the first direction are located on the same source pad;

[0023] forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad; and,

[0024] A plurality of drain structures are formed and are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

[0025] Optionally, the step of forming the unit structure includes:

[0026] forming a first sacrificial layer to at least cover the source pad;

[0027] Etching the first sacrificial layer to form a plurality of through holes, wherein the bottoms of the through holes expose the source pad;

[0028] forming a unit structure to fill the through hole;

[0029] The first sacrificial layer is removed by etching.

[0030] Optionally, the step of forming the gate structure includes:

[0031] forming a second sacrificial layer to at least cover the surface of the unit structure;

[0032] Etching and removing the second sacrificial layer on the top of the unit structure;

[0033] Forming a first isolation material layer to fill between adjacent unit structures, with the top of the first isolation material layer flush with the top of the unit structure;

[0034] Etching the first isolation material layer to form a plurality of first openings penetrating the first isolation material layer;

[0035] removing the second sacrificial layer to form a second opening in the area where the second sacrificial layer is located;

[0036] Forming a gate material layer to fill the first opening and the second opening;

[0037] The gate material layer is etched so that the top of the gate material layer is lower than the top of the unit structure, and the remaining gate material layer serves as the gate structure.

[0038] The semiconductor device and the preparation method thereof provided by the present invention include: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals from each other along a second direction; each source pad is located on a corresponding source line and extends along a second direction and is located between adjacent source lines; a plurality of unit structures are arranged along a first direction and a second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are offset from each other in the first direction are located on the same source pad; the gate structure extends along the second direction and is connected to the unit structures located on the same source pad; a plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present invention, a source pad is provided on the source line, the source pad extends along the second direction and is located between adjacent source lines, a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are offset from each other in the first direction are located on the same source pad, the gate structure is connected to the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, so that each drain structure is connected to the corresponding source pad through a plurality of unit structures, thereby increasing the driving current of the semiconductor device and thus improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A top view of a semiconductor device provided according to an embodiment of the present invention.

[0040] Figure 2 and Figure 3 A schematic cross-sectional view of a semiconductor device provided according to an embodiment of the present invention.

[0041] Figure 4 to Figure 45 A schematic diagram of corresponding steps of a method for preparing a semiconductor device provided in one embodiment of the present invention.

[0042] Wherein, the accompanying drawings are marked as follows:

[0043] 10-substrate; 20-source line; 20a-source pad; 31-second isolation material layer; 32-first isolation material layer; 33-third isolation material layer; 34-fourth isolation material layer; 41-isolation oxide layer; 42-protective layer; 43-gate dielectric layer; 50-etching stop layer; 61-first sacrificial layer; 62-through hole; 63-unit structure; 64-second sacrificial layer; 70-barrier layer; 71-first opening; 72-second opening; 80-gate material layer; 82-gate structure; 90-drain structure; 100-side wall. DETAILED DESCRIPTION

[0044] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0045] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] Figure 1 A top view of a semiconductor device provided in this embodiment, Figure 2 and Figure 3 A cross-sectional schematic diagram of a semiconductor device provided in this embodiment, Figure 2 for Figure 1 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Figure 3 for Figure 1 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Figure 1 In order to show the source line and gate structure, some structures are omitted and the drain structure is set transparent. Figure 1 to Figure 3 The present embodiment provides a semiconductor device, including: a substrate 10, a plurality of source lines 20, a plurality of source pads 20a, a plurality of unit structures 63, a gate structure 82 and a plurality of drain structures 90, wherein the substrate 10 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto. In the present embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connector is formed in the dielectric layer, and the electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0047] A plurality of source lines 20 are located on the substrate 10 (specifically, located on the dielectric layer), and the plurality of source lines 20 extend along the first direction D1 and are arranged at intervals from each other along the second direction D2, and a second isolation material layer 31 is filled between adjacent source lines 20. In this embodiment, the source line 20 may include a first source barrier layer, a source metal layer, a second source barrier layer, and a source semiconductor layer (not shown separately in the figure) stacked sequentially from bottom to top, wherein the materials of the first source barrier layer and the second source barrier layer may include TiN, the material of the source metal layer may include W, and the material of the source semiconductor layer may include polysilicon; the material of the second isolation material layer 31 may include one of a low-k dielectric material, an oxide, a nitride, an oxynitride, and oxycarbon silicon nitride, but is not limited to the above materials.

[0048] Each source pad 20a is located on the corresponding source line 20 and extends along the second direction D2 and is located between adjacent source lines 20. In this embodiment, the shape of the source pad 20a includes a rhombus or a rectangle ( Figure 1 The source pad in is blocked by the gate structure 82 and the drain structure 90, Figure 1 The source pad and the drain structure 90 have the same shape (both are diamond-shaped), but are not limited to this; both ends of the source pad 20a along the first direction D1 are located on the source line 20, and both ends of the source pad 20a along the second direction D2 are extended between adjacent source lines 20. A number of source pads 20a are arranged in an array (specifically, a staggered array distribution), and two adjacent columns of source pads 20a are staggered along the second direction D2. In this embodiment, the source pad 20a is used for conductive connection, and the material of the source pad 20a may include polysilicon, but is not limited to this material. In this embodiment, an isolation oxide layer 41 is filled between a number of source pads 20a, and the isolation oxide layer 41 is flush with the top of the source pad 20a.

[0049] Several unit structures 63 are arranged along the first direction D1 and the second direction D2 on the source pad 20a and connected to the source pad 20a, and at least two unit structures 63 that are offset from each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a (two ends along the first direction D1 and two ends along the second direction D2, that is, at the four angles of the rhombus). Several unit structures 63 are also arranged in an array (specifically, a staggered array distribution), and two adjacent columns of unit structures 63 are staggered along the second direction D2. In this embodiment, the material of the unit structure 63 may include polysilicon (with doped ions), and may also include one or more combinations of metal silicide materials, ferroelectric materials, high-k dielectric materials, and indium gallium zinc oxide (IGZO), but is not limited to the above materials.

[0050] The gate structure 82 extends along the second direction D2 and connects the unit structure 63 located on the same source pad 20a. In this embodiment, the gate structure 82 includes a ring-shaped end portion 82a ( Figure 1 The gate structure 82 includes a first portion 82b and a second portion 82c located on both sides of the unit structure 63 along the first direction D1 (the left side of the unit structure 63 in the figure may be the first portion 82b, and the right side of the unit structure 63 may be the second portion 82c), and the first portion 82b and the second portion 82c are connected by a ring-shaped end 82a. In this embodiment, the gate structure 82 may be a metal stack, such as TiN, W, but is not limited to the above materials.

[0051] Further, a gate dielectric layer 43 and a barrier layer 70 are provided between the gate structure 82 and the unit structure 63, the gate dielectric layer 43 and the barrier layer 70 are sequentially arranged along the sidewalls of the unit structure 63, and a portion of the gate structure 82 is located on the gate dielectric layer 43 and the barrier layer 70. Furthermore, an etch stop layer 50 is also included, the etch stop layer 50 covers the isolation oxide layer 41 and a portion of the source pad 20a, the gate dielectric layer 43 and the barrier layer 70 are located on the etch stop layer 50, and a portion of the gate structure 82 is located on the etch stop layer 50. In this embodiment, the material of the gate dielectric layer 43 may include at least one of silicon oxide, silicon nitride and silicon oxynitride, the barrier layer 70 may include titanium nitride, and the material of the etch stop layer 50 may include silicon carbide, but is not limited to the above materials.

[0052] Furthermore, it also includes a first isolation material layer 32 and a third isolation material layer 33, the first isolation material layer 32 is filled between adjacent gate structures 82; the top of the gate structure 82 is lower than the top of the cell structure 63, the second isolation material layer 33 is located on the gate structure 82, and the tops of the cell structure 63, the first isolation material layer 32 and the second isolation material layer 33 are flush. In this embodiment, the material of the first isolation material layer 32 and the third isolation material layer 33 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides and oxycarbon silicon nitride, but is not limited to the above materials.

[0053] Several drain structures 90 are respectively located above the corresponding source pads 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a. In this embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four unit structures 63. In this embodiment, the drain structure 90 includes a drain barrier layer and a drain metal layer (not shown in the figure) stacked in sequence from bottom to top, wherein the material of the drain barrier layer may include TiN, and the material of the drain metal layer may include W, but is not limited to the above materials.

[0054] Furthermore, it also includes a side wall 100 and a fourth isolation material layer 34, the side wall 100 covers the side of the drain structure 90; the fourth isolation material layer 34 is filled between adjacent drain structures 90; the materials of the side wall 100 and the fourth isolation material layer 34 are different, the material of the side wall 100 may include silicon nitride, and the material of the fourth isolation material layer 34 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides and oxycarbon silicon nitride, but is not limited to the above materials.

[0055] In the present embodiment, a source pad 20a is provided on the source line 20, the source pad 20a extends along the second direction D2 and is located between adjacent source lines 20, a plurality of unit structures 63 are arranged along the first direction D1 and the second direction D2 and are located on the source pad 20a and are connected to the source pad 20a, and at least two unit structures 63 that are offset from each other in the first direction D1 are located on the same source pad 20a, the gate structure 82 is connected to the unit structures 63 located on the same source pad 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a, so that each drain structure 90 is connected to the corresponding source pad 20a through a plurality of unit structures 63, thereby improving the driving current of the semiconductor device and thus improving the electrical performance of the semiconductor device.

[0056] This embodiment further provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, comprising:

[0057] Step S1: providing a substrate;

[0058] Step S2: forming a plurality of source lines on the substrate, extending along a first direction and arranged at intervals from each other along a second direction;

[0059] Step S3: forming a plurality of source pads, each of which is located on a corresponding source line and extends along the second direction and is located between adjacent source lines;

[0060] Step S4: forming a plurality of unit structures, which are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two unit structures which are offset from each other in the first direction are located on the same source pad;

[0061] Step S5: forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad;

[0062] Step S6: forming a plurality of drain structures respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad.

[0063] Figure 4 to Figure 45 The following is a schematic diagram of the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 4 to Figure 45The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0064] Please refer to Figures 4 to 6 , Figure 5 for Figure 4 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Figure 6 for Figure 4 Schematic cross-sectional view along section line B1B2 in FIG. Execute step S1: provide a substrate 10, and the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon substrate on an insulating layer, but is not limited thereto. In this embodiment, a dielectric layer (not shown in the figure) is also formed on the substrate 10, and an electrical connector is formed in the dielectric layer, and the electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0065] Please refer to Figures 4 to 6 , perform step S2: form a plurality of source lines 20 on the substrate 10, wherein the plurality of source lines 20 extend along the first direction D1 and are arranged spaced apart from each other along the second direction D2, and a second isolation material layer 31 is filled between adjacent source lines 20, and the materials of the source lines 20 and the second isolation material layer 31 are as described above.

[0066] Please refer to Figures 4 to 6 , step S3 is performed: forming a plurality of source pads 20a, each of which is located on the corresponding source line 20 and extends along the second direction D2 between adjacent source lines 20, both ends of the source pad 20a along the first direction D1 are located on the source line 20, and both ends of the source pad 20a along the second direction D2 are extended between adjacent source lines 20. The plurality of source pads 20a are arranged in an array (specifically, in a staggered array), and two adjacent columns of source pads 20a are staggered along the second direction D2, and the material of the source pads 20a is as described above.

[0067] Executing step S4: the step of forming a unit structure comprises:

[0068] Please refer to Figure 7 to Figure 9 , Figure 8 for Figure 7 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig. 9 for Figure 7 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Figure 7The first sacrificial layer 61 is set transparent, and some process layers are omitted. An isolation oxide layer 41 is formed to fill between a number of source pads 20a, and the isolation oxide layer 41 is flush with the top of the source pad 20a; an etch stop layer 50 is formed to cover the isolation oxide layer 41 and the source pad 20a; a first sacrificial layer 61 is formed to at least cover the source pad 20a, and specifically, due to the presence of the etch stop layer 50, the first sacrificial layer 61 covers the etch stop layer 50; the material of the first sacrificial layer 61 may include silicon nitride, and the materials of the isolation oxide layer 41 and the etch stop layer 50 are as described above.

[0069] Please refer to Figure 10 to Figure 12 , Fig.11 for Fig.10 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.12 for Fig.10 The first sacrificial layer 61 and the etch stop layer 50 are etched to form a plurality of through holes 62, the bottoms of the through holes 62 expose the source pad 20a (exposing at least a portion of the top surface of the source pad 20a).

[0070] Please refer to Figure 13 to Figure 15 , Fig.14 for Fig.13 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.15 for Fig.13 A cross-sectional schematic diagram along the section line B1B2 in FIG. A unit structure 63 is formed to fill the through hole 62, and a plurality of unit structures 63 are arranged along the first direction D1 and the second direction D2 on the source pad 20a and connected to the source pad 20a, and at least two unit structures 63 that are offset from each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a. A plurality of unit structures 63 are also arranged in an array (specifically, an interlaced array distribution), and two adjacent columns of unit structures 63 are interlaced along the second direction D2; the material of the unit structure 63 is as described above.

[0071] For further information, please refer to Figure 16 to Figure 18 , Fig.17 for Fig.16 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.18 for Fig.16 The unit structure 63 is etched so that the top of the unit structure 63 is lower than the top of the first sacrificial layer 61, and then a protective layer 42 is formed to cover the top of the unit structure 63 so that the protective layer 42 is flush with the top of the first sacrificial layer 61. The material of the protective layer 42 may include silicon oxide.

[0072] For further information, please refer to Figure 19 to Figure 21 , Fig. 20 for Fig.19 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.21 for Fig.19 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Fig.19 The first sacrificial layer 61 is removed by etching, and the sidewalls of the unit structure 63 and the surface of the etching stop layer 50 are exposed.

[0073] Executing step S5: the step of forming a gate structure includes:

[0074] Please refer to Figure 22 to Figure 24 , Fig.23 for Fig. 22 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.24 for Fig. 22 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Fig. 22 The second sacrificial layer 62 is provided with transparency, and some process layers are omitted. The second sacrificial layer 62 is formed by a self-alignment process to at least cover the surface of the unit structure 63. Before forming the second sacrificial layer 62, a gate dielectric layer 43 and a barrier layer 70 are sequentially formed to cover the surface of the unit structure 63, and the gate dielectric layer 43, the barrier layer 70 and the second sacrificial layer 62 extend to cover the surface of the etch stop layer 50 exposed by the adjacent unit structure 63; the materials of the gate dielectric layer 43 and the barrier layer 70 are as described above, and the material of the second sacrificial layer 62 may include silicon nitride.

[0075] Please refer to Figure 25 to Figure 27 , Fig.26 for Fig.25 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig. 27 for Fig.25 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Fig. 22 Part of the gate dielectric layer 43 , the barrier layer 70 and the second sacrificial layer 62 are etched to expose the etch stop layer 50 and the protection layer 42 , and after etching, the remaining gate dielectric layer 43 , the barrier layer 70 and the second sacrificial layer 62 are arranged along the sidewalls of the unit structure 63 .

[0076] Please refer to Figure 28 to Figure 30 , Fig.29 for Fig.28 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.30 for Fig.28 A first isolation material layer 32 is formed to fill between adjacent unit structures 63. Due to the presence of the protection layer 42, the top of the first isolation material layer 32 is flush with the top of the protection layer 42. The material of the first isolation material layer 32 is as described above.

[0077] Please refer to Figure 31 to Figure 33 , Fig.32 for Fig.31 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.33 for Fig.31 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Fig.31 The first isolation material layer 32 is etched to form a plurality of first openings 71 penetrating the first isolation material layer 32 . The first openings 71 are located on both sides of the second sacrificial layer 62 .

[0078] Please refer to Figure 34 to Figure 36 , Fig.35 for Fig.34 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.36 for Fig.34 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Fig.31 The second sacrificial layer 62 is removed to form a second opening 72 in the area where the second sacrificial layer 62 is located, and the first opening 71 and the second opening 72 are connected.

[0079] Please refer to Figure 37 to Figure 39 , Fig.38 for Fig.37 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.39 for Fig.37 A gate material layer 80 is formed to fill the first opening 71 and the second opening 72 , and the gate material layer 80 is flush with the top of the first isolation material layer 32 .

[0080] Please refer to Figure 40 to Figure 42 , Fig.41 for Fig.40 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.42 for Fig.40 Schematic cross-sectional view along the section line B1B2 in FIG. The gate material layer is etched so that the top of the gate material layer is lower than the top of the unit structure 63, and the remaining gate material layer is used as the gate structure 82. The gate structure 82 extends along the second direction D2 and connects the unit structure 63 located on the same source pad 20a; the material of the gate structure 82 is as described above. Then, a third isolation material layer 33 is formed to cover the gate structure 82, the first isolation oxide layer 32 and the protection layer 42, and the material of the third isolation material layer 33 is as described above.

[0081] Please refer to Figure 43 to Figure 45 , Fig.44 for Fig.43 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Fig.45 for Fig.43A cross-sectional diagram along the section line B1B2 is shown in FIG. Part of the third isolation material layer 33, part of the first isolation oxide layer 32 and the protection layer 42 are removed by etching to expose the top of the unit structure 63. After etching, the third isolation material layer 33, the first isolation oxide layer 32 and the top of the unit structure 63 are flush.

[0082] Please refer to Figure 1 to Figure 3 , execute step S6: form a plurality of drain structures 90 respectively located above the corresponding source pads 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a. In the present embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four unit structures 63, and the material of the drain structure 90 is as described above.

[0083] Furthermore, it also includes forming a sidewall spacer 100 to cover the side of the drain structure 90 , and forming a fourth isolation material layer 34 to fill between adjacent drain structures 90 ; the materials of the sidewall spacer 100 and the fourth isolation material layer 34 are as described above.

[0084] In summary, the semiconductor device and the preparation method thereof provided by the present invention include: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals from each other along a second direction; each source pad is located on a corresponding source line and extends along a second direction and is located between adjacent source lines; a plurality of unit structures are arranged along a first direction and a second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are staggered from each other in the first direction are located on the same source pad; the gate structure extends along the second direction and is connected to the unit structures located on the same source pad; a plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present invention, a source pad is provided on the source line, the source pad extends along the second direction and is located between adjacent source lines, a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are offset from each other in the first direction are located on the same source pad, the gate structure is connected to the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, so that each drain structure is connected to the corresponding source pad through a plurality of unit structures, thereby increasing the driving current of the semiconductor device and thus improving the electrical performance of the semiconductor device.

[0085] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of source lines are located on the substrate, extending along a first direction and arranged at intervals from each other along a second direction; A plurality of source pads, each of the source pads is located on a corresponding source line and extends along the second direction and is located between adjacent source lines; A plurality of unit structures are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two of the unit structures that are offset from each other in the first direction are located on the same source pad; A gate structure extending along the second direction and connecting the unit structures located on the same source pad; A plurality of drain structures are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

2. The semiconductor device according to claim 1, wherein Both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction are extended and located between adjacent source lines.

3. The semiconductor device according to claim 2, wherein: The source pad has a rhombus or a rectangle shape.

4. The semiconductor device according to claim 1, wherein A plurality of the source pads are arranged in an array, and the source pads in two adjacent rows are staggered along the second direction.

5. The semiconductor device according to claim 2, wherein: The four unit structures are located on one source pad and are respectively located at four ends of the source pad.

6. The semiconductor device according to claim 1, wherein: The gate structure includes a ring-shaped end.

7. The semiconductor device according to claim 6, wherein: The gate structure includes a first portion and a second portion located at two sides of the unit structure along the first direction, and the first portion and the second portion are connected through the annular end.

8. The semiconductor device according to claim 1, wherein A gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between a plurality of the gate structures.

9. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Forming a plurality of source lines on the substrate, extending along a first direction and arranged at intervals from each other along a second direction; forming a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines; Forming a plurality of unit structures, which are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two of the unit structures which are offset from each other in the first direction are located on the same source pad; forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad; and, A plurality of drain structures are formed and are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The steps of forming the unit structure include: forming a first sacrificial layer to at least cover the source pad; Etching the first sacrificial layer to form a plurality of through holes, wherein the bottoms of the through holes expose the source pad; forming a unit structure to fill the through hole; The first sacrificial layer is removed by etching.

11. The method for preparing a semiconductor device according to claim 9, wherein: The steps of forming the gate structure include: forming a second sacrificial layer to at least cover the surface of the unit structure; Etching and removing the second sacrificial layer on the top of the unit structure; Forming a first isolation material layer to fill between adjacent unit structures, with the top of the first isolation material layer flush with the top of the unit structure; Etching the first isolation material layer to form a plurality of first openings penetrating the first isolation material layer; removing the second sacrificial layer to form a second opening in the area where the second sacrificial layer is located; Forming a gate material layer to fill the first opening and the second opening; The gate material layer is etched so that the top of the gate material layer is lower than the top of the unit structure, and the remaining gate material layer serves as the gate structure.

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