Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the manufacturing method of the semiconductor device comprises the steps: forming sacrificial layers and conductive layers which are sequentially and alternately arranged on a substrate in the thickness direction of the substrate, enabling the sacrificial layers and the conductive layers which are sequentially and alternately arranged to form a stacked structure, and enabling the lattice mismatch degree of the sacrificial layers and the conductive layers to be smaller than or equal to 0.5%; forming a groove extending along a direction perpendicular to the substrate in the stack structure through patterned etching, the groove exposing a side wall of the conductive layer and a side wall of the sacrificial layer; selectively etching the side wall of the exposed sacrificial layer, removing the sacrificial layer to form a cavity, reserving the conductive layer, and exposing at least part of the side surface of the conductive layer by the cavity; filling the cavity and the groove with an insulating layer; removing part of the insulating layer to form a channel which exposes at least part of the side surface of the conductive layer; and sequentially forming a gate insulating layer and a gate electrode on the side surface of the exposed conductive layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of devices contained in a single chip are increasing accordingly. In order to obtain higher storage capacity, lower leakage, and higher integration, new structures and simple process semiconductor device designs have become a demand. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0005] Along the thickness direction of the substrate, forming sacrificial layers and conductive layers alternately arranged in sequence on the substrate, the sacrificial layers and conductive layers alternately arranged in sequence form a stacked structure, and the lattice mismatch between the sacrificial layers and the conductive layers is less than or equal to 0.5%;

[0006] By patterned etching, a groove extending in a direction perpendicular to the substrate is formed in the stacked structure, wherein the groove exposes a side wall of the conductive layer and a side wall of the sacrificial layer;

[0007] Selectively etching the exposed sidewalls of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, wherein the cavity exposes at least a portion of the side surfaces of the conductive layer;

[0008] Filling the cavity and the groove with an insulating layer;

[0009] removing a portion of the insulating layer to form a channel, wherein the channel exposes at least a portion of a side surface of the conductive layer;

[0010] A gate insulating layer and a gate electrode surrounding the conductive layer are sequentially formed on the exposed side surface of the conductive layer.

[0011] In an exemplary embodiment, the material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

[0012] In an exemplary embodiment, the sacrificial layer is made of gallium arsenide, and the conductive layer is made of aluminum gallium arsenide.

[0013] In an exemplary embodiment, the sum of the thickness of the sacrificial layer and the thickness of the adjacent conductive layer is greater than or equal to 20 nanometers and less than or equal to 100 nanometers.

[0014] In an exemplary embodiment, the stacked structure includes n sacrificial layers and n conductive layers, where n is a natural number greater than or equal to 2, the film layer close to the substrate side in the stacked structure is a sacrificial layer, and the film layer away from the substrate side in the stacked structure is a conductive layer.

[0015] In an exemplary embodiment, after selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer and form the cavity, the method further comprises:

[0016] forming an epitaxial layer on the exposed side of the conductive layer;

[0017] Alternatively, after removing part of the insulating layer to form the channel, the method further comprises:

[0018] An epitaxial layer is formed on the exposed side of the conductive layer.

[0019] In an exemplary embodiment, the thickness of the epitaxial layer is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometers.

[0020] In an exemplary embodiment, the thickness of the epitaxial layer is greater than 5 nanometers.

[0021] In an exemplary embodiment, the material of the epitaxial layer is silicon.

[0022] In an exemplary embodiment, after sequentially forming a gate insulating layer and a gate electrode surrounding the conductive layer on the exposed side of the conductive layer, the method further includes:

[0023] Removing one end of each of the conductive layers by patterned etching to form a plurality of strip-shaped grooves;

[0024] A bit line is formed in each of the strip-shaped grooves through a deposition process, and each of the bit lines is connected to a corresponding conductive layer.

[0025] In an exemplary embodiment, after forming a bit line in each of the strip-shaped grooves through a deposition process, the method further includes:

[0026] Removing the insulating layer corresponding to the end of the conductive layer away from the bit line by patterned etching to expose the end of the conductive layer;

[0027] By means of a deposition process, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on the one end of the conductive layer, so that the one end of the conductive layer forms a first capacitor electrode.

[0028] The present disclosure also provides a semiconductor device manufactured by any of the above-mentioned methods for manufacturing a semiconductor device, wherein the semiconductor device at least comprises a plurality of transistors located on a substrate and arranged in sequence along a thickness direction of the substrate;

[0029] The transistor includes a channel, a gate electrode surrounding the sidewall of the channel, a gate insulating layer arranged between the channel and the gate electrode, a first electrode and a second electrode; the first electrode is connected to the second electrode through the channel, and the first electrode, the channel and the second electrode are an integrated structure and include the same conductive material.

[0030] In an exemplary embodiment, a buffer layer is further included, and the buffer layer is disposed on a side of the substrate facing the transistor.

[0031] In an exemplary embodiment, the same conductive material is gallium arsenide or aluminum gallium arsenide.

[0032] In an exemplary embodiment, an epitaxial layer is further included, and the epitaxial layer is at least disposed between the channel and the gate insulating layer.

[0033] An embodiment of the present disclosure also provides an electronic device, comprising the aforementioned semiconductor device.

[0034] The manufacturing method of the semiconductor device in the embodiment of the present disclosure increases or eliminates the critical thickness of the stacked structure due to lattice mismatch by making the lattice mismatch between the sacrificial layer and the conductive layer less than or equal to 0.5%. The sacrificial layer and the conductive layer can be stacked in multiple layers by epitaxy, thereby increasing the number of stacked layers in the stacked structure, improving the integration of the semiconductor device, and ensuring the lattice quality of the sacrificial layer and the conductive layer, thereby avoiding the lattice mismatch between the sacrificial layer and the conductive layer due to the large number of stacked layers in the stacked structure, affecting the lattice quality of the sacrificial layer and the conductive layer, and reducing the performance of the conductor device.

[0035] The manufacturing method of the semiconductor device in the embodiment of the present application is to use the sacrificial layer made of aluminum gallium arsenide (Al x Ga 1-x As), and the conductive layer is made of gallium arsenide (GaAs), which greatly reduces the lattice mismatch between the sacrificial layer and the conductive layer. The lattice mismatch of this order of magnitude can be ignored during the epitaxial growth of the sacrificial layer and the conductive layer, so that the sacrificial layer and the conductive layer can be superimposed in infinite layers.

[0036] In the method for manufacturing a semiconductor device in an embodiment of the present application, the etching selectivity ratio of the sacrificial layer to the conductive layer changes with the content of aluminum (Al) in the sacrificial layer. The etching selectivity ratio of the sacrificial layer to the conductive layer can be controlled by controlling the content of aluminum (Al) in the sacrificial layer. Thus, in a subsequent etching process, a hydrogen fluoride (HF) solution can be used as an etching solution to selectively etch and remove the sacrificial layer while retaining the conductive layer.

[0037] The manufacturing method of the semiconductor device of the embodiment of the present application adopts gallium arsenide (GaAs) as the conductive layer, so that the conductive layer has the characteristics of low static power consumption and high driving current. The biggest problem of gallium arsenide materials compared with Si materials is that the interface state density is too high. This problem has been confirmed in the field of high-speed and high-frequency devices. The interface state density of gallium arsenide (GaAs) materials can be reduced to 10^11eV through some processes. -1 cm -2 , ensuring the performance of the device.

[0038] The manufacturing method of the semiconductor device of the embodiment of the present application adopts silicon as the substrate and gallium arsenide (GaAs) as the conductive layer, and can reduce the threading dislocation density of the conductive layer and the sacrificial layer by epitaxy of the buffer layer. For example, the threading dislocation density of the heteroepitaxial gallium arsenide (GaAs) material on silicon (001) can be reduced to 10^6cm -2 Magnitude.

[0039] The manufacturing method of the semiconductor device in the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer to improve the electron mobility of the conductive layer, so that the semiconductor device has a higher on-state current (I on ).

[0040] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) as a conductive layer to improve the conductivity of the conductive layer, so that the channel formed by the conductive layer has a higher channel conductance, thereby reducing the energy consumption of the semiconductor device.

[0041] The manufacturing method of the semiconductor device in the embodiment of the present application can improve the operating frequency of the semiconductor device by integrating part of the peripheral circuit using a gallium arsenide (GaAs) layer, for example, improving the operating frequency of the semiconductor device as a sensitive amplifier.

[0042] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0043] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0045] Figure 1 A schematic diagram of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment;

[0046] Figure 2 for Figure 1 A cross-sectional view along the a-a' direction;

[0047] Figure 3 A schematic diagram of a semiconductor device after a stacked structure is formed in a manufacturing process provided by an exemplary embodiment;

[0048] Figure 4a A schematic diagram of a semiconductor device after a groove is formed in a manufacturing process provided by an exemplary embodiment;

[0049] Figure 4b for Figure 4a A cross-sectional view along the a-a' direction;

[0050] Figure 5 A schematic diagram of a semiconductor device after a cavity is formed in a manufacturing process provided by an exemplary embodiment;

[0051] Figure 6a A schematic diagram of a semiconductor device after a first insulating layer and a second insulating layer are formed in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0052] Figure 6b for Figure 6a A cross-sectional view along the a-a' direction;

[0053] Figure 7a A schematic diagram of a semiconductor device after a gate insulating layer and a gate electrode are formed in a manufacturing process of an exemplary embodiment;

[0054] Figure 7b for Figure 7a A cross-sectional view along the a-a' direction;

[0055] Figure 8a A schematic diagram of a semiconductor device after a first bit line and a second bit line are formed in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0056] Figure 8b for Figure 8a A cross-sectional view along the a-a' direction;

[0057] Figure 9a A schematic diagram of a semiconductor device along a direction parallel to a substrate provided for yet another exemplary embodiment;

[0058] Figure 9b for Figure 9a A cross-sectional view along the a-a' direction;

[0059] Fig.10 A schematic diagram of a semiconductor device manufacturing process after forming an epitaxial layer according to an exemplary embodiment Figure 1 ;

[0060] Fig.11 A schematic diagram of a semiconductor device manufacturing process after forming an epitaxial layer according to an exemplary embodiment Figure 2 . DETAILED DESCRIPTION

[0061] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0062] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0063] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0064] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0065] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0066] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0067] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0068] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0069] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0070] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0071] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0072] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0073] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0074] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0075] Along the thickness direction of the substrate, forming sacrificial layers and conductive layers alternately arranged in sequence on the substrate, the sacrificial layers and conductive layers alternately arranged in sequence form a stacked structure, and the lattice mismatch between the sacrificial layers and the conductive layers is less than or equal to 0.5%;

[0076] By patterned etching, a groove extending in a direction perpendicular to the substrate is formed in the stacked structure, wherein the groove exposes a side wall of the conductive layer and a side wall of the sacrificial layer;

[0077] Selectively etching the exposed sidewalls of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, wherein the cavity exposes at least a portion of the side surfaces of the conductive layer;

[0078] Filling the cavity and the groove with an insulating layer;

[0079] removing a portion of the insulating layer to form a channel, wherein the channel exposes at least a portion of a side surface of the conductive layer;

[0080] A gate insulating layer and a gate electrode are sequentially formed on the exposed side of the conductive layer.

[0081] The semiconductor device disclosed in the present invention is described below by way of some exemplary embodiments.

[0082] Figure 1 A schematic diagram of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment; Figure 2 for Figure 1 In an exemplary embodiment, as shown in FIG. Figure 1 and Figure 2 As shown, the semiconductor device may include: a transistor, a capacitor, a bit line extending in a direction parallel to the substrate, and a word line extending in a direction perpendicular to the substrate. In one embodiment, the semiconductor device containing only transistors and capacitors forms a 1T1C structure; the transistors are connected to the bit lines and the capacitors respectively.

[0083] In an exemplary embodiment, the transistor includes a channel 73, a first electrode 74, a second electrode 75, a gate electrode 71, and a gate insulating layer 72. The first electrode 74 and the second electrode 75 are respectively located on opposite sides of the channel 73 in the first direction D1. A first end of the first electrode 74 is connected to the channel 73, and a second end of the first electrode 74 is connected to a bit line. A first end of the second electrode 75 is connected to the channel 73, and a second end of the second electrode 75 is connected to a capacitor. The gate insulating layer 72 is disposed between the gate electrode 71 and the channel 73, and the gate electrode 71 surrounds the sidewall of the channel 73 via the gate insulating layer 72.

[0084] In an exemplary embodiment, the capacitor includes a first capacitor electrode 91, a second capacitor electrode 92 and a capacitor dielectric layer 93, wherein the capacitor dielectric layer 93 is located between the second capacitor electrode 92 and the first capacitor electrode 91. The first capacitor electrode 91 is connected to the second end of the second electrode 75.

[0085] In an exemplary embodiment, the first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91 are an integrated structure and include the same conductive material, that is, the first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91 are different regions of the conductive layer arranged in sequence along the first direction D1.

[0086] In practical applications, the integrated structure can be understood as a conductive line or line shape, a portion of which is surrounded by a gate insulating layer and a gate electrode, and one end of the remaining portion is connected to the bit line as a first electrode, and the other end is used as a second electrode and a first capacitor electrode.

[0087] In an exemplary embodiment, a buffer layer is further included, and the buffer layer is disposed on a side of the substrate facing the transistor.

[0088] In an exemplary embodiment, the same conductive material is gallium arsenide or aluminum gallium arsenide.

[0089] In an exemplary embodiment, an epitaxial layer is further included, and the epitaxial layer is at least disposed between the channel and the gate insulating layer.

[0090] The technical solution of this embodiment is further explained below through the manufacturing process of the memory of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0091] In an exemplary embodiment, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0092] Step 101: forming a stacking structure.

[0093] The stacking structure is formed by forming a buffer layer 2 on a substrate 1; then, forming a sacrificial layer 31 and a conductive layer 32 alternately arranged in sequence on the buffer layer 2, and the sacrificial layer 31 and the conductive layer 32 alternately arranged in sequence form a stacking structure 3, such as Figure 3 shown.

[0094] In an exemplary embodiment, the lattice mismatch between the sacrificial layer 31 and the conductive layer 32 is less than or equal to 0.5%.

[0095] In the embodiment of the present application, the lattice mismatch between the sacrificial layer 31 and the conductive layer 32 is made less than or equal to 0.5%, thereby increasing the critical thickness of the stacked structure due to the lattice mismatch. The sacrificial layer 31 and the conductive layer 32 can be stacked in multiple layers by epitaxy, thereby increasing the number of periods of the stacked structure and improving the integration of the semiconductor device. The crystal quality of the sacrificial layer 31 and the conductive layer 32 in the stacked structure is ensured to avoid a decrease in the performance of the conductor device.

[0096] In an exemplary embodiment, the material of the sacrificial layer 31 may be aluminum gallium arsenide (AlGaAs), and the material of the conductive layer 32 may be gallium arsenide (GaAs).

[0097] In the embodiment of the present application, the material of the sacrificial layer 31 is aluminum gallium arsenide (AlGaAs), and the material of the conductive layer 32 is gallium arsenide (GaAs), so that the lattice mismatch between the sacrificial layer 31 and the conductive layer 32 is 0.14%. This order of magnitude of lattice mismatch can be ignored during the epitaxial growth process of the sacrificial layer 31 and the conductive layer 32, so that the sacrificial layer 31 and the conductive layer 32 can be superimposed in infinite layers.

[0098] In the embodiment of the present application, the etching selectivity ratio of the sacrificial layer 31 to the conductive layer 32 changes with the content of aluminum (Al) in the sacrificial layer 31. The etching selectivity ratio of the sacrificial layer 31 to the conductive layer 32 can be controlled by controlling the content of aluminum (Al) in the sacrificial layer 31. Thus, in the subsequent etching process, a hydrogen fluoride (HF) solution can be used as an etching solution to selectively etch and remove the sacrificial layer 31 while retaining the conductive layer 32.

[0099] The manufacturing method of the semiconductor device in the embodiment of the present application adopts gallium arsenide (GaAs) as the conductive layer, so that the conductive layer has the characteristics of low static power consumption and high driving current.

[0100] The manufacturing method of the semiconductor device of the embodiment of the present application adopts silicon as the substrate and gallium arsenide (GaAs) as the conductive layer, and can reduce the threading dislocation density of the conductive layer and the sacrificial layer by epitaxy of the buffer layer. For example, the threading dislocation density of the heteroepitaxial gallium arsenide (GaAs) material on silicon (001) can be reduced to 10^6cm -2 Magnitude.

[0101] The manufacturing method of the semiconductor device in the embodiment of the present application uses gallium arsenide (GaAs) as the conductive layer to improve the electron mobility of the conductive layer, so that the semiconductor device has a higher on-state current (I on ).

[0102] The manufacturing method of the semiconductor device of the embodiment of the present application uses gallium arsenide (GaAs) as a conductive layer to improve the conductivity of the conductive layer, so that the channel formed by the conductive layer has a higher channel conductance, thereby reducing the energy consumption of the semiconductor device.

[0103] The manufacturing method of the semiconductor device in the embodiment of the present application can improve the operating frequency of the semiconductor device by integrating part of the peripheral circuit using a gallium arsenide (GaAs) layer, for example, improving the operating frequency of the semiconductor device as a sensitive amplifier.

[0104] In an exemplary embodiment, the stacked structure 3 may include n sacrificial layers 31 and n conductive layers 32, and the n sacrificial layers 31 and n conductive layers 32 are alternately arranged in sequence along the thickness direction of the substrate 1. Wherein n is a natural number greater than or equal to 2, for example, n may be a natural number such as 2, 3, 4, 5, 6, etc. The film layer close to the substrate 1 side in the stacked structure 3 may be the sacrificial layer 31, and the film layer far from the substrate 1 side in the stacked structure 3 may be the conductive layer 32.

[0105] In an exemplary embodiment, the sum of the thickness of the sacrificial layer 31 and the thickness of the adjacent conductive layer 32 is greater than or equal to 20 nanometers and less than or equal to 100 nanometers, that is, the sum of the thickness of one sacrificial layer 31 and one adjacent conductive layer 32 is greater than or equal to 20 nanometers and less than or equal to 100 nanometers. For example, the thickness of the sacrificial layer 31 may be greater than or equal to 30 nm and less than or equal to 60 nm, and the thickness of the conductive layer 32 may be greater than or equal to 10 nm and less than or equal to 30 nm.

[0106] The manufacturing method of the semiconductor device in the embodiment of the present application prevents the thickness of adjacent sacrificial layers and conductive layers from being too thin or too thick by making the sum of the thickness of adjacent sacrificial layers and conductive layers greater than or equal to 20 nanometers and less than or equal to 100 nanometers, thereby facilitating subsequent processes.

[0107] In some embodiments, the stacked structure may include n+1 sacrificial layers and n conductive layers; or, the stacked structure may include n sacrificial layers and n+1 conductive layers, which will not be described in detail in the embodiments of the present disclosure.

[0108] In an exemplary embodiment, the buffer layer 2 may be formed by a high-low temperature combined growth method, a superlattice dislocation filter layer method, or a pattern substrate assisted method.

[0109] In an exemplary embodiment, the sacrificial layer 31 and the conductive layer 32 may be formed by epitaxy.

[0110] In an exemplary embodiment, the substrate 1 may be a semiconductor substrate, such as a silicon substrate, or may be any other substrate that can meet the requirements for epitaxial growth of the stacked structure.

[0111] Step 102: forming a groove.

[0112] In an exemplary embodiment, the stacked structure 3 includes two sacrificial layers 31 and two conductive layers 32 as an example to illustrate the subsequent preparation process of the semiconductor device. Among them, the film layer on the side close to the substrate 1 in the stacked structure 3 is the sacrificial layer 31, and the film layer on the side away from the substrate 1 in the stacked structure 3 can be the conductive layer 32.

[0113] In an exemplary embodiment, forming the groove includes: on the basis of the substrate 1 formed with the aforementioned pattern, two grooves 5 are formed in the stacked structure 3 by patterned etching, such as a dry etching process, so that the conductive layer 32 in the stacked structure 3 includes a main body 321 and a plurality of branches 322 cross-connected with the main body 321.

[0114] In an exemplary embodiment, in a direction parallel to the substrate 1, the main body 321 of the conductive layer 32 is in the shape of an elongated strip and extends along the second direction D2; the multiple branches 322 of the conductive layer 32 are in the shape of an elongated strip and extend along the first direction D1, and the multiple branches 322 are arranged at intervals along the second direction D2 and are all vertically connected to the main body 321.

[0115] In an exemplary embodiment, in a direction parallel to the substrate 1, the shapes of the two grooves 5 are both rectangular, the two grooves 5 extend along the first direction D1, and are arranged at intervals along the second direction D2. In a direction perpendicular to the substrate 1, the grooves 5 extend along the direction perpendicular to the substrate 1, and the grooves 5 extend from the surface of the stacked structure 3 away from the substrate 1, sequentially penetrate the conductive layer 32 and the sacrificial layer 31 in the stacked structure 3, and extend to the surface of the buffer layer 2. The bottom of the groove 5 is the surface of the buffer layer 2 corresponding to the groove 5, and the sidewalls of the groove 5 expose part of the sidewalls of the conductive layer 32 and part of the sidewalls of the sacrificial layer 31 of the stacked structure 3.

[0116] Subsequently, through patterned etching, grooves are formed on opposite sides of the stacked structure 3 in the first direction D1, and a support layer 4 is formed in the groove. In a direction parallel to the substrate 1, the support layer 4 extends along the second direction D2, and the support layer 4 is located on opposite sides of the groove 5 in the first direction D1, and is connected to a side surface of the groove 5 in the first direction D1, that is, the side surface of the support layer 4 can serve as a side surface of the groove 5 in the first direction D1; the conductive layer 32 in the stacked structure 3 is connected to the support layer 4 at opposite ends in the first direction D1, and the support layer 4 is used to support the conductive layer 32 in subsequent processes to prevent the conductive layer 32 from collapsing; Figure 4a and Figure 4b As shown, the first direction D1 and the second direction D2 are both parallel to the plane where the substrate 1 is located, and the first direction D1 and the second direction D2 intersect, and for example, the first direction D1 and the second direction D2 are perpendicular.

[0117] In an exemplary embodiment, the material of the support layer 4 may be silicon nitride.

[0118] Step 103: forming a cavity.

[0119] In an exemplary embodiment, forming the cavity includes: on the basis of the substrate 1 formed with the aforementioned pattern, using an etching solution, selectively etching the sidewalls of each sacrificial layer 31 exposed by the groove 5, etching away the sacrificial layer 31, and retaining the conductive layer 32, so that the area where each sacrificial layer 31 is removed forms a cavity 33 extending in a direction parallel to the substrate 1, and each cavity 33 exposes the upper side and the lower side of the conductive layer 32, such as Figure 5 The upper side is the surface of the conductive layer 32 away from the substrate 1 , and the lower side is the surface of the conductive layer 32 close to the substrate 1 .

[0120] In one exemplary embodiment, the etching solution may include a hydrogen fluoride (HF) solution.

[0121] Step 104: forming a first insulating layer and a second insulating layer.

[0122] In an exemplary embodiment, forming the first insulating layer and the second insulating layer includes: on the basis of the substrate 1 formed with the aforementioned pattern, depositing insulating films in the cavities and grooves 5 of each layer, so that the insulating films filling the cavities of each layer form the first insulating layer 61, and the insulating films filling the grooves 5 form the second insulating layer 62; then, through a grinding process, the surface of the second insulating layer 62 away from the substrate 1 is flattened, such as Figure 6a and Figure 6b shown.

[0123] In an exemplary embodiment, the material of the insulating film may include silicon oxide (SiOx), so that the materials of the first insulating layer 61 and the second insulating layer 62 both include silicon oxide (SiOx).

[0124] In an exemplary embodiment, the insulating thin film may be deposited by chemical vapor deposition or atomic layer deposition.

[0125] Step 105 , forming a gate insulating layer and a gate electrode.

[0126] In an exemplary embodiment, forming a gate insulating layer and a gate electrode comprises: on the basis of the substrate 1 formed with the aforementioned pattern, forming a channel exposing the side walls of the multiple branches 322 of each layer of the conductive layer 32 in each layer of the first insulating layer 61 and the second insulating layer 62 through patterned etching, the channel surrounds the side walls of the multiple branches 322 of each layer of the conductive layer 32 to form a ring structure extending along the first direction D1, and the channel exposes the side walls of the multiple branches 322 of the conductive layer 32 corresponding to it; then, forming a gate insulating layer 72 and a gate electrode 71 in the channel in sequence, the gate insulating layer 72 surrounds the side walls of the multiple branches 322 of each layer of the conductive layer 32, the gate electrode 71 surrounds the side walls of the multiple branches 322 of each layer through the gate insulating layer 72, the gate electrode 71 is insulated from the side walls of the multiple branches 322 of each layer by the gate insulating layer 72, and the multiple branches 322 of the conductive layer 32 and the region corresponding to the gate electrode 71 form a channel 73; then, filling the gap of the channel with an insulating material, such as Figure 7a and Figure 7b shown.

[0127] In an exemplary embodiment, the gate electrodes 71 corresponding to each of the conductive layers 32 may be connected together to form a word line extending in a direction perpendicular to the substrate 1 .

[0128] In an exemplary embodiment, the gate insulating layer 72 and the gate electrode 71 may be formed by an atomic layer deposition method.

[0129] Step 106: forming a first bit line and a second bit line.

[0130] The first bit line and the second bit line are formed by: on the basis of the substrate 1 formed with the aforementioned pattern, removing a part of the area located in the main body of the conductive layer 32 by patterned etching to form a strip groove; then, forming the first bit line 81 and the second bit line 82 in each strip groove by an atomic layer deposition process, and forming a third insulating layer 63 between the first bit line 81 and the second bit line 82; forming a first electrode 74 in an area where multiple branches of each layer of the conductive layer 32 are located between the first bit line 81 and the gate electrode 71; the first bit line 81 is connected to the first electrode 74 of the conductive layer 32 located on the side away from the substrate 1 in the stacked structure, and the second bit line 82 is connected to the first electrode 74 of the conductive layer 32 located on the side close to the substrate 1 in the stacked structure, and the third insulating layer 63 separates the first bit line 81 from the second bit line 82, as shown in FIG. Figure 8a and Figure 8b shown.

[0131] In an exemplary embodiment, in a direction parallel to the substrate 1 , the first bit line 81 is in a long strip shape and extends along the second direction D2 . The first bit line 81 is arranged in the same layer as the conductive layer 32 on the side away from the substrate 1 in the stacked structure and is connected to the first electrode 74 of the conductive layer 32 .

[0132] In an exemplary embodiment, in a direction parallel to the substrate 1 , the third insulating layer 63 is in a strip shape and extends along the second direction D2 . The third insulating layer 63 is located between the first bit line 81 and the second bit line 82 . The third insulating layer 63 and the first bit line 81 are disposed in the same layer.

[0133] In an exemplary embodiment, in a direction parallel to the substrate 1, the second bit line 82 is in a strip shape and extends along the second direction D2, and the second bit line 82 is located on the side of the third insulating layer 63 away from the first bit line 81. In a direction perpendicular to the substrate 1, the second bit line 82 includes a main body portion extending in a direction perpendicular to the substrate 1 and a connecting portion extending in a direction parallel to the substrate 1, wherein a first end of the connecting portion is disposed in the same layer as the conductive layer 32 located on the side close to the substrate 1 in the stacked structure and is connected to the first electrode 74 of the conductive layer 32, and a second end of the connecting portion extends in a direction opposite to the first direction D1 and is connected to the first end of the main body portion; and a second end of the main body portion extends in a direction perpendicular to the substrate, is disposed in the same layer as the third insulating layer 63 and the first bit line 81, and is separated from the first bit line 81 by the third insulating layer 63.

[0134] Step 107, forming a capacitor.

[0135] The formation of the capacitor includes: on the basis of the substrate 1 formed with the aforementioned pattern, removing the first insulating layer and the second insulating layer corresponding to the ends of the multiple branches of each conductive layer 32 away from the first bit line 81 and the second bit line 82 by patterned etching, and exposing the ends of the multiple branches away from the first bit line 81 and the second bit line 82; then, sequentially forming a capacitor dielectric layer 93 and a second capacitor electrode 92 on the exposed multiple branches, the exposed multiple branches forming the first capacitor electrode 91, and the multiple branches located in the region between the gate electrode 71 and the first capacitor electrode 91 forming the second electrode 75, such as Figure 1 and Figure 2 The first electrode 74, the channel 73, the second electrode 75 and the gate electrode 71 form a transistor; the first capacitor electrode 91 and the second capacitor electrode 92 form a capacitor.

[0136] In an exemplary embodiment, the second capacitor electrode 92 surrounds the sidewall of the first capacitor electrode 91 via the capacitor dielectric layer 93 to form a ring structure extending in a direction parallel to the substrate.

[0137] In an exemplary embodiment, different regions of the plurality of branches of each conductive layer 32 form the first electrode 74 , the channel 73 , the second electrode 75 and the first capacitor electrode 91 .

[0138] In the embodiment of the present disclosure, the first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91 are formed by the same conductive layer 32 material, so that the first electrode 74, the channel 73, the second electrode 75 and the first capacitor electrode 91 form an integrated structure, which simplifies the production process, reduces the production cost, and is easy to manufacture.

[0139] In some embodiments, the present disclosure provides a method for manufacturing a semiconductor device. Figure 1 The difference between the manufacturing method of the semiconductor device shown is that in step 101, the material of the sacrificial layer 31 can be gallium arsenide (GaAs), and the material of the conductive layer 32 can be aluminum gallium arsenide (AlGaAs). In step 102, the sacrificial layer 31 can be selectively etched away by an etching solution, and the conductive layer 32 is retained. The etching solution includes a mixture of citric acid and hydrogen peroxide.

[0140] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device of the present disclosure is Figure 1 and Figure 2 The difference between the semiconductor devices shown is that Figure 9a and 9b As shown, the semiconductor device in the embodiment of the present disclosure further includes an epitaxial layer 11 , which is disposed at least on the sidewall of the channel 73 and between the channel 73 and the gate insulating layer 72 .

[0141] In an exemplary embodiment, the epitaxial layer 11 is disposed on the sidewalls of the integrated structure forming the first electrode 74 , the channel 73 , the second electrode 75 and the first capacitor electrode 91 , and the epitaxial layer 11 overlaps with the orthographic projection of the integrated structure on the substrate.

[0142] In an exemplary embodiment, the epitaxial layer 11 surrounds the sidewalls of the trench 73 to form a ring-shaped structure extending in a direction parallel to the substrate.

[0143] In an exemplary embodiment, the material of the epitaxial layer 11 may include silicon.

[0144] In an exemplary embodiment, the thickness of the epitaxial layer 11 is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometers.

[0145] In an exemplary embodiment, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is Figure 1 The difference between the manufacturing method of the semiconductor device shown is that, after step 103 and before step 104, the manufacturing method of the semiconductor device of the embodiment of the present disclosure further includes: forming an epitaxial layer.

[0146] The formation of the epitaxial layer includes: on the basis of the substrate 1 formed with the aforementioned pattern, on the multiple branches of the conductive layer exposed by the cavity and the groove, a silicon film is deposited by an atomic layer deposition process, so that the silicon film forms an epitaxial layer 11, and the epitaxial layer 11 covers part of the side walls of the multiple branches, such as Fig.10 shown.

[0147] In an exemplary embodiment, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is Figure 1 The manufacturing method of the semiconductor device shown is different in that, in step 105 , a gate insulating layer and a gate electrode are formed.

[0148] The gate insulating layer and the gate electrode are formed by: on the basis of the substrate formed with the aforementioned pattern, a channel is formed in each first insulating layer 61 and second insulating layer 62 through patterned etching to expose the side walls of the multiple branches 322 of each conductive layer 32, the channel surrounds the side walls of the multiple branches 322 of each conductive layer 32 to form a ring structure extending along the first direction D1, and the channel exposes the side walls of the multiple branches 322 of the conductive layer 32 corresponding to the channel; then, on the exposed side walls of the multiple branches 322, a silicon film is deposited through an epitaxial process to make the silicon film An epitaxial layer 11 is formed; subsequently, a gate insulating layer 72 and a gate electrode 71 are sequentially formed in the channel, the gate insulating layer 72 surrounds the side walls of the multiple branches 322 of each layer of the conductive layer 32 through the epitaxial layer 11, the gate electrode 71 surrounds the side walls of the multiple branches 322 of each layer through the gate insulating layer 72 and the epitaxial layer 11, the gate electrode 71 is insulated from the side walls of the multiple branches 322 of each layer by the gate insulating layer 72, and the multiple branches 322 of the conductive layer 32 and the region corresponding to the gate electrode 71 form a channel 73; subsequently, an insulating material is used to fill the gap in the channel, such as Fig.11 shown.

[0149] In the semiconductor device of the disclosed embodiment, the epitaxial layer 11 is disposed on the sidewall of the channel 73 and overlaps with the orthographic projection of the channel 73 on the substrate. The epitaxial layer 11 does not overlap with the orthographic projections of the first electrode 74 , the second electrode 75 and the first capacitor electrode 91 on the substrate.

[0150] The semiconductor device of the embodiment of the present disclosure can optimize the interface of the conductive layer 32 through the epitaxial layer, improve the disadvantage that the conductive layer 32 material has no stable oxide, reduce the interface state of the conductive layer 32, increase the carrier mobility of the conductive layer 32, reduce the off current, and thus improve the electrical properties of the semiconductor device.

[0151] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device of the present disclosure is Figure 9a and 9bThe difference between the semiconductor devices shown is that the thickness of the epitaxial layer of the semiconductor device in the embodiment of the present disclosure is greater than or equal to 3 nanometers, the epitaxial layer of the semiconductor device in the embodiment of the present disclosure can be used as a channel, and the conductive layer can be used as a supporting layer, thereby improving the compatibility of the semiconductor device.

[0152] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0153] Along the thickness direction of the substrate, forming sacrificial layers and conductive layers alternately arranged in sequence on the substrate, the sacrificial layers and conductive layers alternately arranged in sequence form a stacked structure, and the lattice mismatch between the sacrificial layers and the conductive layers is less than or equal to 0.5%;

[0154] By patterned etching, a groove extending in a direction perpendicular to the substrate is formed in the stacked structure, wherein the groove exposes a side wall of the conductive layer and a side wall of the sacrificial layer;

[0155] Selectively etching the exposed sidewalls of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, wherein the cavity exposes at least a portion of the side surfaces of the conductive layer;

[0156] Filling the cavity and the groove with an insulating layer;

[0157] removing a portion of the insulating layer to form a channel, wherein the channel exposes at least a portion of a side surface of the conductive layer;

[0158] A gate insulating layer and a gate electrode are sequentially formed on the exposed side of the conductive layer.

[0159] In an exemplary embodiment, the material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

[0160] In an exemplary embodiment, the sacrificial layer is made of gallium arsenide, and the conductive layer is made of aluminum gallium arsenide.

[0161] In an exemplary embodiment, the stacked structure includes n sacrificial layers and n conductive layers, where n is a natural number greater than or equal to 2, the film layer close to the substrate side in the stacked structure is a sacrificial layer, and the film layer away from the substrate side in the stacked structure is a conductive layer.

[0162] In an exemplary embodiment, after selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer and form the cavity, the method further comprises:

[0163] forming an epitaxial layer on the exposed side of the conductive layer;

[0164] Alternatively, after removing part of the insulating layer to form the channel, the method further comprises:

[0165] An epitaxial layer is formed on the exposed side of the conductive layer.

[0166] In an exemplary embodiment, the thickness of the epitaxial layer is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometers.

[0167] In an exemplary embodiment, the thickness of the epitaxial layer is greater than 5 nanometers.

[0168] In an exemplary embodiment, the material of the epitaxial layer is silicon.

[0169] In an exemplary embodiment, after sequentially forming a gate insulating layer and a gate electrode on the exposed side of the conductive layer, the method further includes:

[0170] Removing one end of each of the conductive layers by patterned etching to form a strip-shaped groove;

[0171] A bit line is formed in the strip-shaped groove through a deposition process, and the bit line is connected to a corresponding conductive layer.

[0172] In an exemplary embodiment, after forming the bit line in the strip-shaped groove by a deposition process, the method further includes:

[0173] Removing the insulating layer corresponding to the end of the conductive layer away from the bit line by patterned etching to expose the end of the conductive layer;

[0174] By means of a deposition process, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on the one end of the conductive layer, so that the one end of the conductive layer forms a first capacitor electrode.

[0175] The present disclosure also provides an electronic device, including a semiconductor device manufactured by the method for manufacturing a semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0176] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Along the thickness direction of the substrate, forming sacrificial layers and conductive layers alternately arranged in sequence on the substrate, the sacrificial layers and conductive layers alternately arranged in sequence form a stacked structure, and the lattice mismatch between the sacrificial layers and the conductive layers is less than or equal to 0.5%; By patterned etching, a groove extending in a direction perpendicular to the substrate is formed in the stacked structure, wherein the groove exposes a side wall of the conductive layer and a side wall of the sacrificial layer; Selectively etching the exposed sidewalls of the sacrificial layer to remove the sacrificial layer, forming a cavity, and retaining the conductive layer, wherein the cavity exposes at least a portion of the side surfaces of the conductive layer; Filling the cavity and the groove with an insulating layer; removing a portion of the insulating layer to form a channel, wherein the channel exposes at least a portion of a side surface of the conductive layer; A gate insulating layer and a gate electrode surrounding the conductive layer are sequentially formed on the exposed side surface of the conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the sacrificial layer is aluminum gallium arsenide, and the material of the conductive layer is gallium arsenide.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the sacrificial layer is gallium arsenide, and the material of the conductive layer is aluminum gallium arsenide.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The sum of the thickness of the sacrificial layer and the thickness of the adjacent conductive layer is greater than or equal to 20 nanometers and less than or equal to 100 nanometers.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The stacked structure includes n sacrificial layers and n conductive layers, where n is a natural number greater than or equal to 2. The film layer close to the substrate in the stacked structure is a sacrificial layer, and the film layer far from the substrate in the stacked structure is a conductive layer.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: After selectively etching the exposed sidewall of the sacrificial layer to remove the sacrificial layer and form a cavity, the method further comprises: forming an epitaxial layer on the exposed side of the conductive layer; Alternatively, after removing part of the insulating layer to form the channel, the method further comprises: An epitaxial layer is formed on the exposed side of the conductive layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The thickness of the epitaxial layer is less than or equal to 5 nanometers and greater than or equal to 0.1 nanometers.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The thickness of the epitaxial layer is greater than 5 nanometers.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: The material of the epitaxial layer is silicon.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: After sequentially forming a gate insulating layer and a gate electrode surrounding the conductive layer on the exposed side of the conductive layer, the method further comprises: Removing one end of each of the conductive layers by patterned etching to form a plurality of strip-shaped grooves; A bit line is formed in each of the strip-shaped grooves through a deposition process, and each of the bit lines is connected to a corresponding conductive layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: After forming a bit line in each of the strip-shaped grooves through a deposition process, the method further comprises: Removing the insulating layer corresponding to the end of the conductive layer away from the bit line by patterned etching to expose the end of the conductive layer; By means of a deposition process, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on the one end of the conductive layer, so that the one end of the conductive layer forms a first capacitor electrode.

12. A semiconductor device, characterized in that: A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the semiconductor device comprises at least a plurality of transistors located on a substrate and arranged in sequence along a thickness direction of the substrate; The transistor includes a channel, a gate electrode surrounding the sidewall of the channel, a gate insulating layer arranged between the channel and the gate electrode, a first electrode and a second electrode; the first electrode is connected to the second electrode through the channel, and the first electrode, the channel and the second electrode are an integrated structure and include the same conductive material.

13. The semiconductor device according to claim 12, characterized in that It also includes a buffer layer, which is arranged on a side of the substrate facing the transistor.

14. The semiconductor device according to claim 12, wherein: The same conductive material is gallium arsenide or aluminum gallium arsenide.

15. The semiconductor device according to claim 12, characterized in that The invention also includes an epitaxial layer, wherein the epitaxial layer is at least arranged between the channel and the gate insulating layer.

16. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 12 to 15.

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