Device structure of semiconductor device, manufacturing method and electronic device

Abstract

The application discloses a preparation method of a semiconductor device and electronic equipment, and the method comprises the following steps: alternately stacking a plurality of insulating layers and metal layers on a substrate to form a laminated structure; forming a plurality of transistors arranged in a multilayer array in the laminated structure, wherein the transistors comprise a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite sidewalls of the via; the channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a semiconductor device structure, fabrication method, and electronic device. Background Technology

[0002] 3D (3D) memory is an emerging form of memory. It is a semiconductor memory device that uses stacking technology to accumulate layers. Compared with planar memory, 3D memory increases storage density, thereby reducing the production cost per GB (gigabyte). Summary of the Invention

[0003] This application provides a semiconductor device structure, fabrication method, and electronic device that can achieve 3D stacking and effectively improve drive current. The technical solution is as follows:

[0004] On one hand, a method for fabricating a semiconductor device is provided, the method comprising:

[0005] Multiple insulating and metal layers are alternately stacked on a substrate to form a stacked structure;

[0006] Multiple transistors are formed in a multilayer array within the stacked structure. Each transistor includes a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer. The first isolation layer and the second isolation layer are located on two opposite sidewalls of the via. The channel layer covers the sidewalls of the first isolation layer and the second isolation layer, forming a first channel, a second channel, a third channel, and a fourth channel. The gate dielectric layer covers the channel layer. The metal gate layer covers the gate dielectric layer.

[0007] In some embodiments, after forming the stacked structure, the method further includes:

[0008] A capacitor is fabricated on one side of the transistor in the stacked structure to form a semiconductor device, and the capacitor is connected to the transistor.

[0009] In some embodiments, forming a transistor within the stacked structure includes:

[0010] A protective layer is deposited on the surface of the stacked structure; the protective layer material is removed from a designated area of ​​the surface, the designated area being related to the transistor location;

[0011] The stacked structure is etched to form multiple through holes;

[0012] The stacked structure is oxidized so that the metal layer exposed on the inner wall of the through hole is oxidized to form the first isolation layer and the second isolation layer;

[0013] Deposit channel material on the first isolation layer and the second isolation layer to form the first channel, the second channel, the third channel and the fourth channel;

[0014] A gate dielectric material is deposited on the first channel, the second channel, the third channel, and the fourth channel to form a gate dielectric layer;

[0015] The via is etched to expose the insulating layer of the via, and a metal gate material is deposited on the gate dielectric layer to form a metal gate layer.

[0016] In some embodiments, etching the stacked structure to form the plurality of vias includes:

[0017] The stacked structure is etched in a direction perpendicular to the substrate to obtain multiple through holes;

[0018] The stacked structure is wet-etched to narrow the exposed metal layers in the plurality of vias.

[0019] In some embodiments, after oxidizing the stacked structure to oxidize the metal layer exposed on the inner wall of the via, and before depositing the channel material on the first and second isolation layers, the method further includes:

[0020] The oxide metal layer inside the via is etched to expose the metal layer on the sidewalls of the via, excluding the first and second isolation layers.

[0021] In some embodiments, after depositing a metallic gate material on the gate dielectric layer, the method further includes:

[0022] A groove structure is formed in the laminated structure; an insulating material is filled in the through holes and the grooves.

[0023] In some embodiments, the channel layer is made of a metal oxide semiconductor material.

[0024] On the other hand, a semiconductor device is provided, the semiconductor device comprising:

[0025] Substrate and stacked structure;

[0026] The stacked structure is located on the substrate; the stacked structure includes:

[0027] The array comprises multiple layers of memory cells stacked in a direction perpendicular to the substrate and multiple bit lines extending in a first direction parallel to the substrate. Each layer of the memory cell array includes multiple memory cells arranged in an array, and each bit line is connected to at least one column of memory cells arranged in the first direction. Each memory cell includes a transistor.

[0028] The transistor includes: a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite sidewalls of the via, and the channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively, forming a first channel, a second channel, a third channel, and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

[0029] In some embodiments, the storage unit further includes: a capacitor;

[0030] The capacitor is connected to the end of the transistor in the memory cell that is furthest from the bit line.

[0031] In some embodiments, the gate connections of the transistors form a word line along a row of memory cells arranged perpendicular to the substrate.

[0032] In some embodiments, two columns of memory cells arranged along the first direction and adjacent to each other along a second direction parallel to the substrate share a bit line, wherein the first direction intersects the second direction.

[0033] On the other hand, a transistor is provided, the transistor comprising:

[0034] Via, first isolation layer, second isolation layer, channel layer, gate dielectric layer, and metal gate layer;

[0035] The first isolation layer and the second isolation layer are located on two opposite sidewalls of the via. The channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively, forming a first channel, a second channel, a third channel and a fourth channel. The gate dielectric layer covers the channel layer. The metal gate layer covers the gate dielectric layer.

[0036] In some embodiments, the channel layer is made of a metal oxide semiconductor material.

[0037] On one hand, an electronic device is provided, the electronic device including a storage device, the storage device including a semiconductor device prepared according to the semiconductor device preparation method described above.

[0038] In some embodiments, the electronic device includes a smartphone, computer, tablet computer, artificial intelligence device, wearable device, or smart mobile terminal.

[0039] The beneficial effects of the technical solutions provided in this application include at least the following:

[0040] It is possible to fabricate a semiconductor device with multiple channels and a stacked arrangement, namely a 3D memory, which can increase the driving current of the memory. Moreover, the three-dimensional stacked design increases the storage density of the 3D memory and reduces the manufacturing cost per GB. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a semiconductor device and a transistor provided in an exemplary embodiment of this application;

[0043] Figure 2 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0045] Figure 4 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application;

[0046] Figure 5 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0047] Figure 6 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0048] Figure 7 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0049] Figure 8 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0050] Figure 9 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0051] Figure 10 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0052] Figure 11 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0053] Figure 12 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0054] Figure 13 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0055] Figure 14 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0056] Figure 15 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application;

[0057] Figure 16 This is a schematic diagram of the relevant steps in the preparation process provided by an exemplary embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0059] This application provides a semiconductor device, with reference to... Figure 1 , Figure 1 Figure (A) illustrates the structure of a semiconductor device, which includes a substrate 100 and a stacked structure 101 located on the substrate 100. The stacked structure 101 includes: multiple layers of memory cell arrays stacked perpendicular to the substrate, and multiple bit lines 102 extending along a first direction parallel to the substrate and the upper surface of the substrate 100. Each memory cell array includes multiple memory cells 103 arranged in an array. Each bit line 102 is connected to at least one column of memory cells 103 arranged along the first direction. Each memory cell 103 includes a transistor 104. Figure 1 Taking the enlarged top view of the memory cell 103 in part (A) as an example, referring to Figure (B), the transistor 104 in the memory cell 103 includes:

[0060] The via 105 includes a first isolation layer 106, a second isolation layer 107, a channel layer 108, a gate dielectric layer 109, and a metal gate layer 110. The first isolation layer 106 and the second isolation layer 107 are located on two opposite sidewalls of the via 105. The channel layer 108 covers the sidewalls of the first isolation layer 106 and the second isolation layer 107, forming a first channel 111, a second channel 112, a third channel 113, and a fourth channel 114. The gate dielectric layer 109 covers the channel layer 108. The metal gate layer 110 covers the gate dielectric layer 109.

[0061] In the process of constructing transistor 104, since the sidewalls of via 105 other than the first isolation layer 106 and the second isolation layer 107 are embedded inside the stacked structure 101, this part cannot be observed in the enlarged top view (B). Only the sidewalls where the first isolation layer 106 and the second isolation layer 107 are located in via 105 can be observed.

[0062] The storage unit also includes: capacitor 115;

[0063] Capacitor 115 is connected to the end of transistor 104 in memory cell 103 away from bit line 102.

[0064] In a row of memory cells 103 arranged perpendicular to the substrate 100, the gates of transistors 104 are connected to form a word line, and the metal gate layer 110 serves as the word line, that is, the switch of transistors 104, connecting transistors 104 in the same string; the bit line 102 serves as the data signal write line, connecting transistors 104 in the same string.

[0065] Two columns of memory cells 103 arranged along a first direction and adjacent along a second direction parallel to the substrate 100 share a bit line, wherein the first direction intersects the second direction.

[0066] In transistor 104, the channel layer 108 is made of metal-oxide-semiconductor material. The metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of transistor 104 is relatively small (less than or equal to 10⁻¹⁵ A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), IZOx, etc., as long as the leakage current of transistor 104 meets the requirements. The specific adjustments can be made according to the actual situation.

[0067] In this application embodiment, a method for fabricating a semiconductor device is provided. Optionally, this method for fabricating a semiconductor device is mainly applied in the fabrication process of a 3D memory.

[0068] Based on the above introduction to semiconductor devices, Figure 2 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application, such as... Figure 2 As shown, the method includes the following steps.

[0069] Step 201: Alternately stack multiple insulating layers and metal layers on the substrate to form a stacked structure.

[0070] The bottommost insulating layer is in contact with the substrate. By stacking these layers on the substrate to fabricate transistors, device area can be reduced and device density increased, making 3D memory possible.

[0071] Reference Figure 3 , Figure 3 Figure (A1) shows a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305, and a third metal layer 306 sequentially stacked on a substrate 300. Optionally, the first direction is the bit line direction. Figure 3 Figure (A2) shows a two-dimensional cross-sectional view of the stacked structure as observed along the first direction.

[0072] It should be noted that the above Figure 3 This is merely a schematic diagram of a multi-layer stack; in some embodiments, the specific number of stacked layers is determined based on the device design.

[0073] Step 202: Multiple transistors arranged in a multilayer array are formed within the stacked structure. The transistors include vias, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer. The first isolation layer and the second isolation layer are located on two opposite sidewalls of the via. The channel layers cover the sidewalls of the first isolation layer and the second isolation layer respectively, forming a first channel, a second channel, a third channel, and a fourth channel. The gate dielectric layer covers the channel layer. The metal gate layer covers the gate dielectric layer.

[0074] In some embodiments, the layers in the transistor are in a surrounding relationship, wherein the first isolation layer and the second isolation layer are identical in structure and material. Since each isolation layer has two sidewalls, the entire transistor has four sidewalls. That is, when a channel layer is formed on the sidewalls, four channels can be obtained. Furthermore, the subsequent gate dielectric layer and the metal gate layer are also sequentially covered and formed outside the channel layer where the four channels are located.

[0075] Reference Figure 1 , Figure 1Section (B) shows the structure of the transistor as observed in the vertical direction.

[0076] The method provided in this application embodiment can fabricate a semiconductor device with multiple channels and stacked arrangement, namely a 3D memory. It can increase the driving current of the memory, and the three-dimensional stacked design can increase the storage density of the 3D memory and reduce the manufacturing cost per GB.

[0077] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of this application, the method comprising:

[0078] Step 401: Multiple insulating layers and metal layers are alternately stacked on the substrate to form a stacked structure.

[0079] The aforementioned alternating stacking refers to first stacking an insulating layer on the substrate, then stacking a metal layer, with the metal layer and insulating layer being stacked alternately, so that a metal layer is stacked between every two insulating layers, and the topmost layer of this stacked structure is a metal layer.

[0080] In some embodiments, based on oxidation properties, the metal layer can be selected from easily oxidized metals such as Ti (titanium), Mo (molybdenum), and Ta (tantalum).

[0081] Reference Figure 3 , Figure 3 Figure (A1) shows a three-dimensional structure of a substrate in which a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305, and a third metal layer 306 are sequentially stacked. Optionally, the first direction is the bit line direction. Figure 3 (A2) shows a two-dimensional planar view of the (A1) structure observed along the first direction.

[0082] Step 402: Deposit a protective layer material on the surface of the stacked structure.

[0083] In some embodiments, the protective layer can be made of Nitride (titanium nitride). The protective layer material can also be other substances that do not react with the metal stack; the present application does not limit the selection of the protective layer material.

[0084] In some embodiments, a protective layer material is applied to the surface of the stacked structure using ALD (Atomic Layer Deposition) or chemical vapor deposition techniques.

[0085] Reference Figure 5 , Figure 5 (A1) shows a three-dimensional structural diagram of a stacked structure with a protective layer material 500 deposited. Figure 5 (A2) shows a two-dimensional planar view of the (A1) structure observed along the first direction.

[0086] Step 403: Remove the protective layer material from the surface of a specified area, which is related to the location of the transistor.

[0087] The designated area is used to fabricate transistors. The area is elongated, with the width of the elongation matching the width of the transistor and the length matching the width of the stacked structure.

[0088] In some embodiments, based on photolithography, the protective layer material on the surface of a designated area is removed according to the required transistor dimensions. The number of designated areas is determined based on fabrication requirements, and this embodiment does not limit this number.

[0089] Reference Figure 6 , Figure 6 (A1) shows a three-dimensional structural diagram of the laminated structure with the surface protective layer material removed from the specified area 600. Figure 6 (A2) shows a two-dimensional planar view of the (A1) structure observed along the first direction.

[0090] Step 404: Etch the stacked structure in a direction perpendicular to the substrate to obtain multiple vias.

[0091] Among them, based on the dry etching process, a stacked structure is etched in a designated area to obtain through holes, and the width of the multiple through holes is consistent from top to bottom.

[0092] In some embodiments, the size of the via in the direction perpendicular to the substrate matches the size of the transistor.

[0093] Reference Figure 7 , Figure 7 (A1) shows a three-dimensional schematic diagram of a stacked structure with the same width of through-hole 700, where 300 is the substrate. Optionally, the vertical direction is the word line direction. Figure 7 (A2) shows a two-dimensional top view of the structure (A1) observed along the vertical direction. In the process of constructing the transistor, since the sidewalls of the via 700 other than the first isolation layer and the second isolation layer are embedded inside the stacked structure, this part cannot be observed in the top view (A2). Only the sidewalls where the first isolation layer and the second isolation layer are located in the via can be observed.

[0094] Step 405: Perform wet etching on the stacked structure to narrow the exposed metal layers in the multiple vias.

[0095] Among them, based on the isotropic nature of wet etching, the width of the lateral etching of the metal layer can be close to the depth of the longitudinal etching, thereby making the metal layer in the stacked structure uniformly narrower.

[0096] Understandably, after the etching operation is performed, the via structure used to form the transistor can be observed in the vertical direction.

[0097] Reference Figure 8 , Figure 8 (A1) shows a three-dimensional structure diagram after etching the stacked structure in the vertical direction. Figure 8 (A2) shows a two-dimensional top view of the structure (A1) observed along the vertical direction. In the process of building the transistor, since the sidewalls of the via, except for the first and second isolation layers, are embedded inside the stacked structure, this part cannot be observed in the top view (A2). Only the sidewalls where the first and second isolation layers are located in the via can be observed.

[0098] As can be seen from the top view, the width of the metal layer 801 in the through hole is smaller than the width of the insulating layer 802.

[0099] Step 406: Oxidize the stacked structure to oxidize the metal layer exposed on the inner wall of the through hole to form a first isolation layer and a second isolation layer.

[0100] In this process, the vias are exposed outside the protective layer. Therefore, through oxidation, the metal layer of the vias can be made to form a metal oxide, thereby forming the first isolation layer and the second isolation layer. The metal oxide is an insulator, which can isolate the channel layer material subsequently deposited on both sides to form a multi-channel semiconductor device.

[0101] Among them, the anodic oxidation process, which utilizes electrochemical principles, can achieve this oxidation treatment and generate metal oxides.

[0102] In some embodiments, the metal in the metal layer can be selected from Ti (titanium), Mo (molybdenum), or Ta (tantalum), and correspondingly, the oxide produced after oxidation can be TiO2. x (titanium oxide), MoO x (Molybdenum oxide), TaO x (Tantalum oxide), these metal oxides act as insulators and serve as supports.

[0103] Reference Figure 9 , Figure 9 (A1) shows a three-dimensional structural diagram of the stacked structure of metal oxide layer 900 obtained after oxidizing the metal layer. Figure 9(A2) shows a two-dimensional top view of the structure (A1) observed along the vertical direction. In the process of building the transistor, since the sidewalls of the via, except for the first and second isolation layers, are embedded inside the stacked structure, this part cannot be observed in the top view (A2). Only the sidewalls where the first and second isolation layers are located in the via can be observed.

[0104] In addition, after the oxidation step and before depositing the channel material, an etching process is performed to etch the oxidized metal layer inside the via, so that the sidewalls of the via, except for the first and second isolation layers, are exposed to the metal layer. One side of the exposed metal layer is used to connect the bit line, and the other side is used to connect the capacitor, so that the metal layer can make good contact with the bit line and the capacitor.

[0105] Step 407: Deposit channel material on the first and second isolation layers to form the first channel, the second channel, the third channel, and the fourth channel.

[0106] In some embodiments, the channel material is generally selected from metal oxide semiconductor materials with high electrical stability to maintain the electrical performance of the device during the stacking process. The first channel, the second channel, the third channel and the fourth channel are composed of IGZO (Indium Gallium Zinc Oxide).

[0107] In some embodiments, channel material is deposited on the surface of the via using ALD (Atomic Layer Deposition) or chemical vapor deposition techniques.

[0108] Reference Figure 10 , Figure 10 (A1) shows a three-dimensional structural diagram of the stacked structure of the deposition channel material 1000. Figure 10 (A2) shows a two-dimensional top view of (A1) viewed along the vertical direction. Figure 10 (A3) is Figure 10 The enlarged view of part 1001 in (A2) shows the first channel 1002, the second channel 1003, the third channel 1004, the fourth channel 1005, the first isolation layer 1006, and the second isolation layer 1007. The material used for all four channels is channel material 1000. During the transistor construction process, since the sidewalls of the vias other than the first and second isolation layers are embedded inside the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3). Only the sidewalls where the first and second isolation layers are located in the vias can be observed.

[0109] Step 408: Deposit gate dielectric material on the first channel, second channel, third channel and fourth channel to form a gate dielectric layer.

[0110] The gate dielectric material is a high-K material, which is used as the dielectric between the first channel, second channel, third channel and fourth channel of the transistor and the connected gate.

[0111] In some embodiments, channel material is deposited on the surface of the via using ALD (Atomic Layer Deposition) or chemical vapor deposition techniques.

[0112] Reference Figure 11 , Figure 11 (A1) shows a three-dimensional structural diagram of the stacked structure of the deposited gate dielectric material 1100. Figure 11 (A2) shows a two-dimensional top view of the structure in (A1) as observed along the vertical direction. Figure 11 (A3) is Figure 11 The enlarged view of part 1101 in (A2) shows the gate dielectric material 1100 covering the channel layer to form the gate dielectric layer. In the process of building the transistor, since the sidewalls of the via except for the first isolation layer and the second isolation layer are embedded inside the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3). Only the sidewalls where the first isolation layer and the second isolation layer are located in the via can be observed.

[0113] Step 409: Etch through-holes to expose the insulating layer of the through-holes, and deposit metal gate material on the gate dielectric layer to form a metal gate layer.

[0114] In some embodiments, the protrusions on the inner sidewalls of the via are etched to expose the insulating layer. Because wet etching narrows the metal layer, and the first and second isolation layers formed by oxidation are narrower than the insulating layer, there will be protrusions at the location of the insulating layer within the via. After the channel material and gate dielectric material are deposited, channel material and gate dielectric material will also be deposited on the protruding portions of the insulating layer. Etching these protrusions to expose the insulating layer removes the channel material deposited on the protrusions. The exposed insulating layer separates the channel material within the via. This etching operation removes parasitic MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) in the vertical direction.

[0115] Reference Figure 12 , Figure 12 (A1) shows a three-dimensional structural diagram of the stacked structure after etching the protruding insulating layer. Figure 12(A2) shows a two-dimensional top view of (A1) observed along the vertical direction, where 1100 is still the gate dielectric material. Figure 12 (A3) is Figure 12 The enlarged view of part 1200 in (A2) shows a three-dimensional structure of the via after etching the protruding insulating layer. In the process of building the transistor, since the sidewalls of the via, except for the first and second isolation layers, are embedded inside the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3). Only the sidewalls where the first and second isolation layers are located in the via can be observed.

[0116] In this process, a metal gate material is further deposited on the outer layer of the original gate dielectric material to form a metal gate layer. The gate connections formed by this metal gate layer within the same via form word lines. Optionally, the deposition of the metal gate material is achieved using an ALD process.

[0117] Reference Figure 13 , Figure 13 (A1) shows a three-dimensional structural diagram of the stacked structure after the deposition of the metal grid material. Figure 13 (A2) shows a two-dimensional top view of (A1) viewed along the vertical direction. Figure 13 (A3) is Figure 13 The enlarged view of part 1300 in (A2) shows the metal gate material 1301 covering the gate dielectric layer to form a metal gate layer. In the process of building the transistor, since the sidewalls of the via except for the first isolation layer and the second isolation layer are embedded inside the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3). Only the sidewalls where the first isolation layer and the second isolation layer are located in the via can be observed.

[0118] Step 410: Form a trench structure in the stacked structure after the metal grid layer has been deposited.

[0119] In some embodiments, the stacked structure between two transistors arranged in a horizontal direction is etched, the stacked structure between the two transistors including the stacked structure between the two transistors in a first region and a second region, to obtain a trench structure.

[0120] The trench is used to fill oxide, which insulates adjacent transistors.

[0121] Reference Figure 14 , Figure 14 (A1) shows a three-dimensional structure diagram after etching the stacked structure, where 1400 is the formed trench structure. Figure 14(A2) shows a two-dimensional top view of the structure (A1) observed along the vertical direction. In the process of building the transistor, since the sidewalls of the via, except for the first and second isolation layers, are embedded inside the stacked structure, this part cannot be observed in the top view (A2). Only the sidewalls where the first and second isolation layers are located in the via can be observed.

[0122] Step 411: Fill the through holes and trenches with a separating material.

[0123] The insulating material used for filling has insulating properties and is used to support the through-hole structure of the transistor.

[0124] Reference Figure 15 , Figure 15 Figure (A) shows a three-dimensional structural diagram of the laminated structure after it has been filled with insulating material 1500 and ground smooth. As can be seen from the figure, the unetched portion of the laminated structure still contains a protective layer 500. Figure 15 (B) shows a two-dimensional top view of the structure in (A) along the vertical direction. In the process of building the transistor, since the sidewalls of the via, except for the first and second isolation layers, are embedded inside the stacked structure, this part cannot be observed in the top view (B). Only the sidewalls of the first and second isolation layers in the via can be observed.

[0125] Step 412: Remove the remaining protective layer from the surface of the laminated structure.

[0126] In some embodiments, the residual protective layer material on the surface of the stacked structure is etched using a dry etching process.

[0127] The protective layer is used to protect the parts of the stacked structure that do not need to be etched, preventing them from being damaged during the etching process. In addition, the protective layer can also protect the metal layer underneath, preventing it from being oxidized during the oxidation process.

[0128] Reference Figure 16 , Figure 16 A three-dimensional structural diagram of the stacked structure after the protective layer is removed is shown. As can be seen from the diagram, after the protective layer is removed, the uppermost third metal layer 306 is exposed.

[0129] Step 413: A capacitor is fabricated on one side of the transistor in the stacked structure to form a semiconductor device, which is connected to the transistor.

[0130] In some embodiments, after any of the above etching or filling steps, a smoothing operation can be performed by CMP (Chemical Mechanical Polishing) to ensure the smoothness of the stacked structure, thereby ensuring the hermeticity of the device.

[0131] Reference Figure 1 , Figure 1 (A) shows a three-dimensional structural diagram of a semiconductor device. The illustration shows the fabrication of four transistor strings at once. Therefore, it can be seen that capacitors 115 are added on both sides, that is, capacitors are added on one side of each transistor. In some embodiments, the method of adding capacitors is matched to the fabrication requirements.

[0132] The method provided in this application embodiment can fabricate a semiconductor device that maintains electrical stability, namely a 3D memory. Based on the method of simultaneously fabricating multiple transistors, a multi-channel memory is obtained, which can increase the amount of drive current. Furthermore, IGZO has amorphous characteristics, and its selection as a channel material ensures stable processing and allows for the stacking of more layers while maintaining stable electrical properties. Moreover, the three-dimensional stacking design increases the storage density of the 3D memory and reduces the manufacturing cost per GB.

[0133] On the other hand, an electronic device is provided, which includes a logic device, and the logic device includes a semiconductor device as described in the above embodiments. This logic device can be applied to logic units and memories, etc.

[0134] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or smart mobile terminal.

[0135] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0136] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0137] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: Multiple insulating and metal layers are alternately stacked on a substrate to form a stacked structure; Multiple transistors are formed in a multilayer array within the stacked structure. Each transistor includes a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer. The first isolation layer and the second isolation layer are located on opposite sidewalls of the via. The channel layer covers the sidewalls of the first isolation layer and the second isolation layer, forming a first channel, a second channel, a third channel, and a fourth channel. The first isolation layer, the second isolation layer, and the channel layer all extend along a second direction parallel to the substrate. The gate dielectric layer covers the channel layer. The metal gate layer covers the gate dielectric layer.

2. The method according to claim 1, characterized in that, After forming the stacked structure, the method further includes: A capacitor is fabricated on one side of the transistor in the stacked structure to form a semiconductor device, and the capacitor is connected to the transistor.

3. The method according to claim 1, characterized in that, The formation of transistors within the stacked structure includes: A protective layer is deposited on the surface of the stacked structure; the protective layer material is removed from a designated area of ​​the surface, the designated area being related to the transistor location; The stacked structure is etched to form multiple through holes; The stacked structure is oxidized so that the metal layer exposed on the inner wall of the through hole is oxidized to form the first isolation layer and the second isolation layer; Deposit channel material on the first isolation layer and the second isolation layer to form the first channel, the second channel, the third channel and the fourth channel; A gate dielectric material is deposited on the first channel, the second channel, the third channel, and the fourth channel to form a gate dielectric layer; The via is etched to expose the insulating layer of the via, and a metal gate material is deposited on the gate dielectric layer to form a metal gate layer.

4. The method according to claim 3, characterized in that, The etching of the stacked structure to form multiple vias includes: The stacked structure is etched in a direction perpendicular to the substrate to obtain multiple through holes; The stacked structure is wet-etched to narrow the exposed metal layers in the plurality of vias.

5. The method according to claim 3, characterized in that, The step of oxidizing the stacked structure to oxidize the metal layer exposed on the inner wall of the through-hole, and before depositing the channel material on the first and second isolation layers, further includes: The oxide metal layer inside the via is etched to expose the metal layer on the sidewalls of the via, excluding the first and second isolation layers.

6. The method according to claim 3, characterized in that, After depositing the metallic gate material on the gate dielectric layer, the method further includes: A trench structure is formed in the laminated structure; an insulating material is filled in the through holes and the trench structure.

7. The method according to claim 1, characterized in that, The channel layer is made of metal oxide semiconductor material.

8. A semiconductor device, characterized in that, include: Substrate and stacked structure; The stacked structure is located on the substrate; The stacked structure includes: The array comprises multiple layers of memory cells stacked in a direction perpendicular to the substrate and multiple bit lines extending in a first direction parallel to the substrate. Each layer of the memory cell array includes multiple memory cells arranged in an array, and each bit line is connected to at least one column of memory cells arranged in the first direction. Each memory cell includes a transistor. The transistor includes: a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite sidewalls of the via, and the channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively, forming a first channel, a second channel, a third channel, and a fourth channel; the first isolation layer, the second isolation layer, and the channel layer all extend along a second direction parallel to the substrate; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

9. The semiconductor device according to claim 8, characterized in that, The storage unit also includes: a capacitor; The capacitor is connected to the end of the transistor in the memory cell that is furthest from the bit line.

10. The semiconductor device according to claim 8, characterized in that, Along a row of memory cells arranged perpendicular to the substrate, the gate connections of the transistors form a word line.

11. The semiconductor device according to claim 8, characterized in that, Two columns of memory cells arranged along the first direction and adjacent to each other along a second direction parallel to the substrate share a bit line, wherein the first direction intersects the second direction.

12. A transistor, characterized in that, include: Via, first isolation layer, second isolation layer, channel layer, gate dielectric layer, and metal gate layer; The first isolation layer and the second isolation layer are located on two opposite sidewalls of the via. The channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively, forming a first channel, a second channel, a third channel and a fourth channel. When the transistor is applied to a semiconductor device, the first isolation layer, the second isolation layer and the channel layer all extend along a second direction parallel to the substrate of the semiconductor device. The gate dielectric layer covers the channel layer. The metal gate layer covers the gate dielectric layer.

13. The transistor according to claim 12, characterized in that, The channel layer is made of metal oxide semiconductor material.

14. An electronic device, characterized in that, The electronic device includes a storage device, which includes a semiconductor device prepared according to the method for preparing a semiconductor device as described in any one of claims 1 to 7.

15. The electronic device according to claim 14, characterized in that, The electronic devices include smartphones, computers, tablets, artificial intelligence devices, wearable devices, or smart mobile terminals.

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