A 2F-1T-1C unit circuit, memory computing circuit and chip

Abstract

This invention relates to the field of in-memory computing, specifically a 2F-1T-1C cell circuit, an in-memory computing circuit, and a chip. The cell circuit includes N-type FeFET transistors F1 and F2, an NMOS transistor M0, and a capacitor C0. The source of M0 and the drains of F1 and F2 are connected to one end of C0 and serve as node X; the other end of C0 is grounded. The gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL. The gates of F1 and F2 are connected to word lines WLA and WLB, respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2, respectively. It can support the storage and multiplication of signed numbers and supports XOR operations on unsigned numbers. When applied to an in-memory computing circuit, it can further realize multiply-accumulate operations between signed numbers and complex content addressing. This invention solves the problem of insufficient efficiency of existing FeFET-based NVMs in BNN tasks.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing, and in particular to a 2F-1T-1C unit circuit and an in-memory computing circuit and chip using the unit circuit. Background Technology

[0002] With the rapid development of artificial intelligence and big data technologies, the scale of data continues to grow, placing higher demands on the storage density, computing efficiency, and power consumption control of hardware systems. The traditional von Neumann architecture faces the "memory wall" bottleneck, requiring frequent data transfer between memory and the arithmetic unit, introducing significant latency and leading to a substantial increase in static power consumption, making it difficult to meet current needs. Based on this, Computing-In-Memory (CIM) has emerged, effectively solving the data transfer problem by embedding computing units within memory. Against this backdrop, novel nonvolatile memory (NVM), due to its high-density storage and in-situ computing potential, has become an important direction for breaking through the limitations of traditional architectures.

[0003] Currently, resistive random access memory (RRAM) and spin-transfer torque-based magnetic random access memory (STT-MRAM) have gained widespread attention in the field of in-memory computing. Ferroelectric field-effect transistors (FeFETs), with their unique advantages, demonstrate even greater application potential in in-memory computing scenarios: First, FeFETs evolved from the traditional metal-oxide-semiconductor field-effect transistor (MOSFET) structure, possessing excellent CMOS process compatibility. Second, as a voltage-controlled device, FeFETs feature fast switching speed, high on / off ratio, and low leakage current, effectively reducing energy consumption and signal interference during in-memory computing. Furthermore, FeFETs can achieve multi-level cell (MLC) storage in CMOS processes, further increasing storage density.

[0004] FeFETs can achieve non-volatile control of the transistor threshold voltage (Vth) by adjusting the polarization intensity of the HfO2 ferroelectric layer with different gate programming voltages: a positive polarization voltage decreases the Vth of the FeFET, while a negative polarization voltage increases it. In binary neural networks (BNNs), convolution operations involve multiplying and accumulating +1 and -1. However, existing FeFET-based NVMs typically only perform multiplication and multiplying-accumulation operations between signed inputs and unsigned weights, making it difficult to perform multiplication between signed numbers. Therefore, they cannot be efficiently applied to data processing tasks involving networks with higher precision than BNNs (such as convolutional neural networks, CNNs). Summary of the Invention

[0005] To address the inefficiency of existing FeFET-based NVMs in high-precision network tasks, this invention provides a 2F-1T-1C unit circuit, as well as a memory computing circuit and chip using this unit circuit.

[0006] The technical solution provided by this invention is as follows:

[0007] A 2F-1T-1C cell circuit is disclosed for storing signed numbers and performing multiplication operations between signed numbers. The circuit includes N-type FeFET transistors F1 and F2, an NMOS transistor M0, and a capacitor C0. The circuit connections are as follows: the source of M0 and the drains of F1 and F2 are connected to one end of C0, denoted as node X; the other end of C0 is grounded. The gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL. The gates of F1 and F2 are connected to word lines WLA and WLB, respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2, respectively.

[0008] In the multiplication operation, the pre-stored 2-bit signed weight W is represented by the threshold states of F1 and F2; and a set of complementary voltage signals V are input through SL1 and SL2. SL1 and V SL2 The signed input IN represents a multi-bit input. Then the node voltage V of node X... X The difference between the input and the reference voltage Vref is used to characterize the product P between the signed input and the signed weight. The encoding logic of IN is: using 1 / 2VDD as Vref, V... SL1 V SL2 The difference between Vref and Vref is β • ΔV0, where one of them is greater than Vref and the other is less than Vref; where ΔV0 represents the preset gradient voltage. β Indicates the multiplier. β ∈N + Then, V SL1 >V SL2The symbol for IN is "+", V SL1 <V SL2 The symbol for IN is "-"; β That is, the value of IN; V SL1 =V SL2 =Vref indicates that IN is "0". The encoding logic of P is: V X >Vref indicates that P is a positive number; V X <Vref indicates that P is negative; |V X -Vref| is a multiple of a gradient voltage ΔV0. α This represents the value of P. α ∈N + .

[0009] As a further improvement of this invention, the encoding logic of W in the multiplication operation is as follows:

[0010] When F1 is a low threshold state (LVT) and F2 is a high threshold state (HVT), W is represented as "+1".

[0011] When F1 is a high threshold state and F2 is a low threshold state, W is represented as "-1".

[0012] When F1 is a high threshold state and F2 is a high threshold state, W is represented as "0".

[0013] As a further improvement of the present invention, the operation logic of the 2F-1T-1C unit circuit performing the multiplication operation between the signed input and the signed weight is as follows:

[0014] (i) By controlling the voltage states of WLA, WLB, SL1 and SL2, the corresponding threshold states are written to F1 and F2 to complete the pre-storage of W.

[0015] (ii) Set SAE to high level VDD, precharge C0 through AWL so that the initial voltage of X is 1 / 2VDD, and set SAE to low level after precharging.

[0016] (iii) Preset the voltage values ​​of SL1 and SL2 according to the preset encoding logic to complete the IN input.

[0017] (iv) Obtain the node voltage of node X and decode it into the corresponding product P.

[0018] As a further improvement of the present invention, in the data storage function, the operation logic for writing signed numbers by the 2F-1T-1C unit circuit is as follows:

[0019] First set WLA to write level (V) W), set WLB to low level; set SL1 and SL2 to low level; to set F1 to the low threshold state. Then set SL1 and SL2 to the write level (V W ), and then set F2 to the high threshold state to complete the writing of the data "+1".

[0020] First, set WLA to low level, WLB to the write level, and SL1 and SL2 to low level; to set F2 to the low threshold state. Then set SL1 and SL2 to the write level (V W ), and then set F1 to the high threshold state to complete the writing of the data "-1".

[0021] Connect WLA and WLB to low level, and connect SL1 and SL2 to the write level (V W ), and then set both F1 and F2 to the high threshold state to complete the writing of the data "0".

[0022] As a further improvement of the present invention, the operation logic for the 2F-1T-1C cell circuit to implement signed number reading is as follows:

[0023] (I) Set SAE to high level, pre-charge C0 through AWL so that the initial voltage of X is V1, and then set SAE to low level after the pre-charge is completed.

[0024] (II) Set SL1 and SL2 to low level.

[0025] (III) First, set WLA to the read level Vr (0 <LVT <Vr <HVT), and set WLB to low level; obtain the first level state X1 of X; then set WLA to low level and WLB to Vr; obtain the second level state X2 of X; then the read logic of the stored data is:

[0026] If X1 is low level, it means the stored data is "+1", if X1 is high level and X2 is low level, it means the stored data is "-1"; if X1 is high level and X2 is high level, it means the stored data is "0".

[0027] As a further improvement of the present invention, the operation logic for the 2F-1T-1C cell circuit to perform the exclusive-NOR operation between single-bit unsigned numbers is as follows:

[0028] S1: Characterize one of the operands IN1 of the exclusive-NOR operation through the threshold states of F1 and F2, and perform pre-writing:

[0029] Among them, when F1 is in the low threshold state and F2 is in the high threshold state, it characterizes IN1 as "1"; when F1 is in the high threshold state and F2 is in the low threshold state, it characterizes IN1 as "0".

[0030] S2: Set SAE to high level, precharge C0 through AWL so that the initial voltage of X is V1, and set SAE to low level after precharging.

[0031] S3: Input the other operand IN2 of the XOR operation, characterized by the level states of SL1 and SL2:

[0032] When SL1 is high and SL2 is low, IN2 is "1"; when SL1 is low and SL2 is high, IN2 is "0".

[0033] S4: Read the XOR operation result based on the level state of node X:

[0034] Wherein, if X is high, it means that the result of the XOR operation is 1; if X is low, it means that the result of the XOR operation is 0.

[0035] The present invention also includes a memory computing circuit, which includes a memory computing array, a column driving circuit, a row driving circuit, and an output circuit.

[0036] The in-memory array is composed of the 2F-1T-1C cell circuits described above, arranged as an array of in-memory cells. Each in-memory cell also includes a CMOS switch, with one end connected to node X and the other end connected to the computation bit line ML. In the in-memory array, the in-memory cells in the same column share WLA, WLB, SAE, AWL, and ML; the in-memory cells in the same row share SL1 and SL2.

[0037] The column driver circuit sets WLA, WLB, SAE, and AWL to specified voltage levels. WLA and WLB include write, low, and read voltage levels; SAE includes high and low voltage levels; and AWL includes VDD and 1 / 2VDD. The row driver circuit sets SL1 and SL2 to specified voltage values. The voltage range of SL1 and SL2 is 0-VDD, where VDD+V must be maintained. LVT ≤V r To avoid calculation errors caused by threshold loss, V LVT This represents the threshold voltage of the FeFET in a low threshold state.

[0038] The output circuit includes a sensitive amplifier and an analog-to-digital converter connected to each ML in the memory array. The sensitive amplifier is used to quantize the level state of the ML to realize the reading of stored data and logic operation results; the analog-to-digital converter is used to quantize the bit line voltage value of the ML to realize the reading of arithmetic operation results.

[0039] As a further improvement of the present invention, the memory-based circuit utilizes each memory-based unit to perform a multiplication operation between a multi-bit signed input and a two-bit signed weight.

[0040] Furthermore, the memory-based circuit utilizes multiple memory units in the same column but different rows to perform multiplication and accumulation operations between each multi-bit signed input IN1~INn and each two-bit signed weight W1~Wn; its operation logic includes:

[0041] S01: In a number of cycles, W1~Wn are pre-stored in the storage units of the specified rows in sequence.

[0042] In this case, the same two-bit signed weights are written synchronously within the same period.

[0043] S02: Pre-charge 1 / 2VDD of the corresponding column's ML; then input each multi-bit signed input IN1~INn through SL1 and SL2 of each row.

[0044] S03: Charge sharing of calculation results is achieved through CMOS switches between each memory unit and ML, so that the multiply-accumulate operation result is reflected on the bit line voltage of ML; the bit line voltage value of ML is quantized to obtain the multiply-accumulate operation result.

[0045] Furthermore, the results of operations on different columns are directly added or shifted and added according to their weights to support multiplication or multi-accumulation operations between multi-bit signed inputs and signed weights greater than 2 bits.

[0046] As a further improvement of the present invention, the memory computing circuit supports TCAM addressing operations, including:

[0047] SL1 and SL2 are used as addressing lines to achieve addressing data input.

[0048] During the addressing operation, the X of the corresponding memory cell is first precharged to a high level via the AWL signal, and then the addressing data is input; the addressing result is reflected in the level state of the ML of the corresponding column.

[0049] By controlling the switching state of the CMOS switches connected to the ML for each memory cell, the memory cells that do not participate in addressing are shielded.

[0050] The present invention also includes a chip which is packaged from the memory computing circuit as described above.

[0051] The present invention has the following beneficial effects:

[0052] This invention provides a novel FeFET memory circuit with a 2F-1T-1C architecture, which can store three states within a single unit circuit using only four basic electronic components, thus supporting the storage of signed numbers. Compared to the three-valued storage logic of traditional CMOS memory circuits, the circuit of this invention has a smaller unit area overhead, thereby improving storage density to a certain extent.

[0053] This invention also provides an arithmetic operation strategy for signed multiplication based on a novel 2F-1T-1C structure. This strategy uses the two input lines SL1 and SL2 to generate multiple input mappings, increasing the number of input bits in signed multiplication and improving computational efficiency to some extent. Furthermore, this unit can also support XOR operations between unsigned numbers; its performance is more comprehensive, and its application prospects are broad.

[0054] Applying the 2F-1T-1C structure to a memory array yields a novel in-memory computing circuit. This invention provides a controllable discharge channel for each in-memory computing unit via CMOS switches, enabling charge-based storage of calculation results. Compared to current-based in-memory computation, this method produces more accurate results. Furthermore, the circuit utilizes the closed-loop logic of the CMOS switches to determine whether a unit participates in the overall computation, allowing for computation using only local circuitry, thus offering considerable flexibility.

[0055] In practical applications, the storage data retrieval and XNOR logic operation of the circuit of this invention are directly read through SA, requiring no additional hardware overhead and simplifying the complexity of the peripheral circuit. Furthermore, because this invention can directly implement signed number multiplication operations on a simplified circuit architecture, its computational efficiency is relatively higher, and the calculation results are more concise. Attached Figure Description

[0056] Figure 1 This is a circuit diagram of the 2F-1T-1C unit circuit provided in Embodiment 1 of the present invention.

[0057] Figure 2 This is a schematic diagram of the 2F-1T-1C unit circuit in Embodiment 1 of the present invention to implement the data "+1" read and write operation.

[0058] Figure 3 This is a schematic diagram of the 2F-1T-1C unit circuit in Embodiment 1 of the present invention for implementing the read and write operation of data "-1".

[0059] Figure 4 This is a schematic diagram of the 2F-1T-1C unit circuit in Embodiment 1 of the present invention for implementing the read and write operation of data "0".

[0060] Figure 5This is a circuit diagram of the 2F-1T-1C unit circuit in Embodiment 1 of the present invention for implementing signed multiplication operations.

[0061] Figure 6 This is a schematic diagram of the memory computing circuit provided in Embodiment 2 of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0064] Example 1

[0065] This embodiment provides a 2F-1T-1C cell circuit, which can serve as a basic unit for FeFET-based memory devices. Based on this 2F-1T-1C cell circuit, signed number storage and multiplication operations between signed numbers can be implemented. Furthermore, the 2F-1T-1C cell circuit can also perform XNOR operations between unsigned numbers.

[0066] Specifically, such as Figure 1 As shown, the 2F-1T-1C unit circuit provided in this embodiment includes two N-type FeFET transistors F1 and F2, one NMOS transistor M0, and one capacitor C0. The circuit connection is as follows: the source of M0 and the drains of F1 and F2 are connected to one end of C0, and the connection point is denoted as node X; the other end of C0 is grounded. The gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL. The gates of F1 and F2 are connected to word lines WLA and WLB, respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2, respectively.

[0067] In the storage function of this unit circuit, the data written in the unit circuit can be jointly characterized by the threshold states of two N-type FeFET transistors; M0 constitutes a precharge channel to adjust the voltage of node X, and works with capacitor C0 to realize data writing and reading. Specifically, for the N-type FeFET transistor, applying voltages of different amplitudes for the same duration to its gate can change the magnitude of the FeFET threshold voltage, which reflects the storage state of the FeFET and serves as a marker of stored data. When a write voltage V is applied to the FeFET gate... w (V) w When the gate is set to a low level (VDD) and the drain is set to a low level (0V), the FeFET is written with a low threshold voltage (LVT). Conversely, when the gate is set to a low level, the drain is set to the write voltage VDD. w The source is set to the write voltage V. w When the gate and source voltages are the same, the FeFET will be written with a high threshold voltage (HVT). If the gate and source voltages are the same, the write state will not change.

[0068] I. Data Storage

[0069] This embodiment details the implementation of signed number storage by the 2F-1T-1C unit circuit, following the order of data writing and data reading operations:

[0070] In the data storage function of the 2F-1T-1C unit circuit, the operation logic for writing signed numbers can be divided into three cases: writing data "+1", "-1" and "0".

[0071] like Figure 2 As shown, when writing "+1", WLA can be set to the write level V first. W WLB is set low; and SL1 and SL2 are both set low. At this time, F1 is set to the low threshold state. Next, SL1 and SL2 are set to the write level V. W At this point, F1, which was previously written to the LVT, will be turned on, and the voltage at its source will be transferred to point X. After a specified period of time, F2, which has a gate voltage of 0, will be reversed and programmed to be a high threshold voltage (HVT), that is, F2 will be set to a high threshold state, thereby completing the writing of the data "+1".

[0072] Accordingly, such as Figure 3 As shown, the process of writing "-1" is similar to writing "+1," only the execution objects F1 and F2 in the process of writing "+1" need to be swapped. Specifically, the process of writing "-1" in this embodiment is as follows: first, set WLA to low level, WLB to write level, and SL1 and SL2 to low level; then set F2 to low threshold state. Next, set SL1 and SL2 to write level V.W , and then set F1 to the high threshold state to complete the writing of the data "-1".

[0073] Finally, different from the need for two stages to set F1 and F2 to different threshold states when writing "+1" and "-1", during the process of writing "0", only one stage is required to directly set both F1 and F2 to the high threshold state. Specifically, as Figure 4 shown, connect WLA and WLB to low level, and connect SL1 and SL2 to the writing level V W , and then set both F1 and F2 to the high threshold state to complete the writing of the data "0".

[0074] In the 2F-1T-1C cell circuit of this embodiment, the stored data is characterized by the threshold states of F1 and F2. Therefore, in the data reading stage, it is possible to identify the threshold states of the two by whether the X node in the high level state can discharge through each FeFET, and complete the data reading.

[0075] Specifically, as Figures 2-4 shown, the operation logic for the 2F-1T-1C cell circuit to implement signed number reading is:

[0076] (Ⅰ) Set SAE to high level, and pre-charge C0 through AWL so that the initial voltage of X is V1, V1 < V W , and after the pre-charge is completed, set SAE to low level. This step is to set the level state of the X node high at the initial node to create conditions for the candidate to discharge through the FeFET in the low threshold state.

[0077] (Ⅱ) Set SL1 and SL2 to low level. This step pre-sets SL1 and SL2 to low level, and lays the foundation for subsequent detection of whether the X node can discharge through each FeFET.

[0078] (Ⅲ) First, set WLA to the reading level Vr (0 < LVT < Vr < HVT), and set WLB to low level; obtain the first level state X1 of X; then set WLA to low level, and set WLB to Vr; obtain the second level state X2 of X; then the reading logic of the stored data is:

[0079] If X1 is low level, it means the stored data is "+1", if X1 is high level and X2 is low level, it means the stored data is "-1"; if X1 is high level and X2 is high level, it means the stored data is "0".

[0080] In summary, during the data reading operation of the 2F-1T-1C unit circuit in this embodiment, if the stored data is "+1", it indicates that F1 is in a low threshold state. This means that node X can discharge through F1 during the first test; that is, if X1 is low, the stored data is "+1". If the stored data is not "+1", it indicates that F1 is in a high threshold state. In this case, node X cannot discharge through F1 during the first test. In the second test, if the original stored data is "-1", it indicates that F2 is in a low threshold state. In this case, node X can discharge through F2 during the second test; that is, if X1 is high and X2 is low, the stored data is "+1". Conversely, if the original stored data is "0", it indicates that F2 is also in a high threshold state. In this case, node X cannot discharge through F2 during the second test; that is, if X1 is high and X2 is high, the stored data is "0".

[0081] II. Arithmetic Operations

[0082] Building upon the aforementioned data reading function, this embodiment further implements a special signed multiplication operation based on the circuit structure and principle of the 2F-1T-1C unit circuit. Specifically, in the multiplication operation, the 2F-1T-1C unit circuit supports characterizing the pre-stored 2-bit signed weight W through the threshold states of F1 and F2; and through a set of complementary voltage signals V input via SL1 and SL2. SL1 and V SL2 The signed input IN represents a multi-bit input. Then the node voltage V of node X... X The difference between the input and the reference voltage Vref is used to characterize the product P between the signed input and the signed weight.

[0083] In detail, when the 2F-1T-1C unit circuit in this embodiment performs a multiplication operation, the encoding logic of the signed weight W (2 bits) is shown in the table below:

[0084] Table 1: Truth Table of Signed Weighted W Encoding

[0085]

[0086] That is: when F1 is a low threshold state and F2 is a high threshold state, W is represented as "+1"; when F1 is a high threshold state and F2 is a low threshold state, W is represented as "-1"; when F1 is a high threshold state and F2 is a high threshold state, W is represented as "0".

[0087] Accordingly, the encoding logic for multi-bit signed input IN (≥2 bits) is shown in the table below:

[0088] Table 2: Truth Table for Signed Input IN Encoding

[0089]

[0090] Referring to the table above, in this embodiment, 1 / 2VDD (i.e., 450mV) is used as the reference voltage Vref. SL1 V SL2 The difference between Vref and Vref is β • ΔV0, where one of them is greater than Vref and the other is less than Vref. Here, ΔV0 represents the preset gradient voltage. β Indicates the multiplier. β ∈N + Then, V SL1 >V SL2 The symbol for IN is "+", V SL1 <V SL2 The symbol for IN is "-"; β That is, the value of IN; V SL1 =V SL2 =Vref indicates that IN is "0".

[0091] It should be noted that Table 2 primarily uses a 3-bit (-3 to +3) IN number as an example for signal encoding, where the gradient voltage ΔV0 is set to 50mV. In other embodiments, ΔV0 can be further reduced, thereby utilizing V SL1 and V SL2 Encode the signed input with higher bits.

[0092] Finally, based on the above weights and inputs, the encoding logic of the product operation result in the 2F-1T-1C unit circuit of this embodiment is as follows: If V X >Vref indicates that P is a positive number; V X <Vref indicates that P is negative; |V X -Vref| is a multiple of a gradient voltage ΔV0. α This represents the value of P. α ∈N + .

[0093] Specifically, in the operation of 3-bit IN and 2-bit W, the encoding logic of the product is shown in the table below:

[0094] Table 3: Logical Truth Table for Signed Multiplication

[0095]

[0096] In the table above, X represents any state or voltage value. When either the weight or the input is 0, the product result is always 0.

[0097] In practical applications, such as Figure 5As shown, the operation logic of the 2F-1T-1C unit circuit in this embodiment for performing multiplication between signed inputs and signed weights is as follows:

[0098] (i) The pre-storage of W is completed by writing the corresponding threshold states to F1 and F2 through controlling the voltage states of WLA, WLB, SL1 and SL2. Specifically, the pre-storage of the signed weights is implemented using the data writing operation described above.

[0099] (ii) Set SAE to high level and precharge C0 through AWL so that the initial voltage of X is 1 / 2VDD. After the precharge is completed, set SAE to low level.

[0100] (iii) Preset the voltage values ​​of SL1 and SL2 according to the preset encoding logic to complete the IN input;

[0101] (iv) Obtain the node voltage of node X and decode it into the corresponding product P.

[0102] For example, taking "0×(+1)" as an example, the input is 0, the weight is +1, then V SL1 and V SL2 Both are 450mV. F1 is in LVT mode, and F2 is in HVT mode. Before performing the calculation, M0 is turned on, and the capacitor is pre-charged to 450mV through AWL. The input voltage Vr is WLA and WLB. At this time, since F1 is LVT conducting and F2 is HVT non-conducting, the source voltage of F1 is transferred to the capacitor through F1. The voltage at node X is still 450mV, indicating that the calculation result is "0". This is consistent with the calculation logic of "0×(+1)=0".

[0103] Continuing with the example of "(-1)×0", with an input of -1 and a weight of 0, then V SL1 and V SL2 The voltages are 400mV and 500mV respectively. F1 and F2 are both HVT. Before calculation, M0 is turned on, and the capacitor is pre-charged to 450mV through AWL. The input voltages Vr are WLA and WLB. At this time, since F1 and F2 are both HVT and not conducting, their source voltages cannot be transferred to the capacitor. The node voltage of X remains at 450mV, indicating that the calculation result is 0. This is consistent with the calculation logic of "(-1)×0=0".

[0104] Next, taking "(-1)×(-1)" as an example, the input is -1 and the weight is -1, then V SL1 and V SL2The voltages are 400mV and 500mV respectively. F1 is in HVT mode and F2 is in LVT mode. Before performing the calculation, M0 is turned on and the capacitor is precharged to 450mV through AWL. The input voltages Vr are WLA and WLB. At this time, since F1 is in HVT mode and not conducting, and F2 is in LVT mode and conducting, the source voltage of F2 is transferred to the capacitor through F2. The node voltage of X is 500mV, which means that the calculation result is 1. This is consistent with the calculation logic of "(-1)×(-1)=1".

[0105] In summary, when the 2F-1T-1C unit circuit of this embodiment performs a multiplication operation between two signed numbers, one weight is stored in the unit, and the other input is input through SL1 and SL2. The calculation result is finally reflected in the voltage value of the upper plate of the capacitor, i.e., node X.

[0106] III. Logical Operations

[0107] The 2F-1T-1C unit circuit in this embodiment can also be used to perform XOR operations between single-bit unsigned numbers. Similar to multiplication, an unsigned number IN1 can be pre-stored in the unit and characterized by the threshold states of F1 and F2, while another unsigned data IN2 can be input through SL1 and SL2. The final operation result is reflected in the node voltage of node X.

[0108] It should be noted that, unlike the signed multiplication operation mentioned earlier, which focuses on the magnitude of the values, the XOR operation in this embodiment is a logical operation that only concerns the binary states of the input and the result. Therefore, the signal logic of the two operations differs. Specifically, the XOR operation logic of the 2F-1T-1C unit circuit in this embodiment is as follows:

[0109] S1: Characterize one of the operands IN1 of the XOR operation using the threshold states F1 and F2, and pre-write it:

[0110] Specifically, when F1 is a low threshold state and F2 is a high threshold state, IN1 is represented as "1"; when F1 is a high threshold state and F2 is a low threshold state, IN1 is represented as "0".

[0111] S2: Set SAE to high level, precharge C0 through AWL so that the initial voltage of X is V1, and set SAE to low level after precharging.

[0112] S3: Input the other operand IN2 of the XOR operation, characterized by the level states of SL1 and SL2:

[0113] When SL1 is high and SL2 is low, IN2 is "1"; when SL1 is low and SL2 is high, IN2 is "0".

[0114] S4: Read the XOR operation result based on the level state of node X:

[0115] Wherein, if X is high, it means that the result of the XOR operation is 1; if X is low, it means that the result of the XOR operation is 0.

[0116] Based on this, analyzing the circuit principle reveals the following: If IN1=0 and IN2=0, then F1 is cut off and F2 is turned on. A high-level signal is transmitted from F2 to point X, and an XNOR operation is performed. The voltage at X is read as "1" through SA, so the XNOR result is 1. If IN1=0 and IN2=1, then F1 is cut off and F2 is turned on, and a low-level signal is transmitted from F2 to point X. The XNOR operation is performed, and the voltage at X is read as "0" through SA, so the XNOR result is 0. If IN1=1 and IN2=0, then F1 is turned on and F2 is cut off, and a low-level signal is transmitted from F1 to point X. The XNOR operation is performed, and the voltage at X is read as "0" through SA, so the XNOR result is 0. If IN1=1 and IN2=1, then F1 is turned on and F2 is cut off, and a high-level signal is transmitted from F1 to point X. The XNOR operation is performed, and the voltage at X is read as "1" through SA, so the XNOR result is 1.

[0117] Example 2

[0118] Based on the scheme in Embodiment 1, this embodiment further provides a memory computing circuit, such as... Figure 6 As shown, it includes a memory computing array, column driver circuits, row driver circuits, and output circuits. The circuit also includes other peripheral circuits for implementing data storage and logical operations. These peripheral circuits are common to various FeFET-based memory computing circuits and will not be described in detail in this embodiment. Only the core parts for implementing arithmetic operations in this invention will be described in detail.

[0119] Specifically, the in-memory array is composed of 2F-1T-1C cell circuits arranged as in-memory cells, as shown in Embodiment 1. Furthermore, each in-memory cell includes a CMOS switch, with one end connected to node X and the other end connected to the computation bit line ML. In the in-memory array, in-memory cells in the same column share WLA, WLB, SAE, AWL, and ML; and in-memory cells in the same row share SL1 and SL2. Therefore, in-memory cells in different rows within the same column can selectively connect node X to ML using their respective CMOS switches to achieve charge sharing.

[0120] The column driver circuit is used to set WLA, WLB, SAE, and AWL to specified voltage levels. In practical applications, WLA and WLB can be set to write levels (V). WThe reading states are: SL1 (0V) and SL2 (Vr); SAE includes a high-level state (VDD) and a low-level state (0V); AWL includes VDD and 1 / 2VDD. The row drive circuit is used to set SL1 and SL2 to specified voltage values, and the voltage range of SL1 and SL2 is 0-VDD.

[0121] The output circuit includes a sensitive amplifier and an analog-to-digital converter connected to each ML in the memory array. The sensitive amplifier is used to quantize the level state of the ML to realize the reading of stored data and logic operation results; the analog-to-digital converter is used to quantize the bit line voltage value of the ML to realize the reading of arithmetic operation results.

[0122] In practical applications, the memory-based computing circuit of this embodiment can utilize each memory-based computing unit to perform multiplication operations between multi-bit signed inputs and two-bit signed weights, as described above. Specifically, the memory-based computing circuit of this embodiment can also utilize multiple memory-based computing units in the same column but different rows to perform multiplication-accumulation operations between each multi-bit signed input IN1~INn and each two-bit signed weight W1~Wn; its operation logic includes:

[0123] S01: In a number of cycles, W1~Wn are pre-stored in the storage units of the specified rows in sequence.

[0124] In this case, the same two-bit signed weights are written synchronously within the same period; while signed weights with different values ​​need to be written sequentially within different periods.

[0125] S02: Pre-charge 1 / 2VDD of the corresponding column's ML; then input each multi-bit signed input IN1~INn through SL1 and SL2 of each row.

[0126] S03: Charge sharing of calculation results is achieved through CMOS switches between each memory unit and ML, so that the multiply-accumulate operation result is reflected on the bit line voltage of ML; the bit line voltage value of ML is quantized to obtain the multiply-accumulate operation result.

[0127] Specifically, in this embodiment, considering that the above-mentioned multiply-accumulate operation process is essentially to complete the signed multiplication operation in each memory unit, and then "superimpose" the X node voltage corresponding to the product result onto the calculation bit line ML in sequence through charge sharing, so that the voltage of the calculation bit line becomes the average value of all capacitor voltages, the sum of the results of each signed multiplication operation, i.e., the MAC operation result, can be obtained by quantizing the bit line voltage value of the calculation bit line ML. Therefore, the operation process of the multiply-accumulate operation will not be described in detail in this embodiment.

[0128] Furthermore, in the practical application of the memory-based computing circuit in this embodiment, the operation results of different columns can be directly added or shifted and added according to their weights to support the multiplication or multi-accumulation operation between multi-bit signed inputs and signed weights greater than 2 bits.

[0129] For example, suppose we need to calculate the product between a 3-bit signed input IN and a 3-bit signed weight W. This can be accomplished using two different columns of a storage array. The operational logic is as follows: First, the 3-bit signed weight W is divided into a 2-bit signed weight W1, consisting of the sign bit and the high-value bits, and a 2-bit signed weight W2, consisting of the sign bit and the low-value bits. Then, in the storage units of the two columns, the multiplication operations IN×W1 and IN×W2 are performed synchronously and sequentially according to the aforementioned operational logic. Next, the multiplication results are output through the ML of their respective columns and quantized by an analog-to-digital converter. Finally, the calculation results on the two ML columns are shifted and added according to the weights of the value bits in W1 and W2, thus obtaining the product between the 3-bit signed input IN and the 3-bit signed weight W.

[0130] Similarly, the multiplication and accumulation operations between multiple multi-bit (>2) signed inputs IN1~INn and multiple multi-bit (>2) signed weights W1~Wn can also be completed using multiple storage units in different rows and columns. The operation process includes decomposing each multi-bit signed weight into multiple 2-bit signed weights and distributing them to storage units in different columns for execution, as well as shifting and adding the quantized results of the multiplication and accumulation operations on ML in different columns.

[0131] Furthermore, considering that each memory cell in the storage array has the logical operation function of performing XOR operation, the memory array provided in this embodiment can also use this logical operation function to realize TCAM addressing operation in the memory array. Specifically, the key points of the memory circuit supporting TCAM addressing operation include: (1) using SL1 and SL2 as addressing lines to realize addressing data input. (2) During the addressing operation, the X of the corresponding memory cell is precharged to a high level through the AWL signal, and then the addressing data is input; the addressing result is reflected in the level state of the ML of the corresponding column. (3) By controlling the switching state of the CMOS switches connected to the ML of each memory cell, the memory cells that do not participate in the addressing are shielded. This shielding function enables the memory circuit of this embodiment to support non-contiguous multi-cell addressing, as well as multi-cell addressing across rows or columns.

[0132] Specifically, before the search, a high-level signal can be applied to the SAE, and the capacitor can be pre-charged through the AWL. The CMOS switch of the cell to be addressed is closed and connected to the addressing line ML. The CMOS switch of the cell not to be addressed is not closed, reducing the addressing range and improving the efficiency of a single search.

[0133] The writing of pre-stored data in the addressing operation is similar to the aforementioned XOR operation, but its operational logic differs from that of the multiplication operation. During the addressing operation, WLA and WLB are input to Vr. If searching for "1", search lines SL1 and SL2 are input with a high level (1) and a low level (0) respectively. If the search result matches, the capacitor does not discharge, ML remains high, and the result is read as "1" by the sensitive amplifier. Conversely, if the capacitor discharges, the sensitive amplifier reads a result of 0, indicating a mismatch.

[0134] If searching for "0", search lines SL1 and SL2 are input with a low level (0) and a high level (1) respectively. If the search result matches, the capacitor does not discharge, ML remains at a high level, and the result is read as "1" by the sensitive amplifier. Conversely, if the capacitor discharges, the sensitive amplifier reads "0", indicating that the result does not match.

[0135] In practical applications, in order to directly apply the above solution, this embodiment also provides a chip, which is packaged from the memory computing circuit as described above.

[0136] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A 2F-1T-1C unit circuit, characterized in that, It is used to implement the storage of signed numbers and the multiplication operation between signed numbers; it includes N-type FeFET transistors F1 and F2, NMOS transistor M0 and capacitor C0; the source of M0 is connected to the drain of F1 and F2 and one end of C0, and is denoted as node X; the other end of C0 is grounded; the gate of M0 is connected to the precharge enable line SAE, and the drain of M0 is connected to the precharge voltage line AWL; the gates of F1 and F2 are connected to word lines WLA and WLB respectively, and the sources of F1 and F2 are connected to input signal lines SL1 and SL2 respectively; In the multiplication operation, the pre-stored 2-bit signed weight W is represented by the threshold states of F1 and F2; and a set of complementary voltage signals V are input through SL1 and SL2. SL1 and V SL2 The signed input IN represents a multi-bit input; the encoding logic of IN is: using 1 / 2VDD as Vref, V... SL1 V SL2 The difference between Vref and Vref is β • ΔV0, where one is greater than Vref and the other is less than Vref; where ΔV0 represents the preset gradient voltage. β Indicates the multiplier. β ∈N + Then, V SL1 >V SL2 The symbol for IN is "+", V SL1 <V SL2 The symbol for IN is "-"; β That is, the value of IN; V SL1 =V SL2 =Vref indicates that IN is "0"; Then the node voltage V of node X X The difference between the reference voltage Vref and the input voltage is used to characterize the product P between IN and W; the encoding logic of P is: V X >Vref indicates that P is a positive number; V X <Vref indicates that P is negative; |V X -Vref| is a multiple of a gradient voltage ΔV0. α This represents the value of P. α ∈N + .

2. The 2F-1T-1C unit circuit according to claim 1, characterized in that: In multiplication, the encoding logic of W is as follows: When F1 is a low threshold state and F2 is a high threshold state, W is represented as "+1"; When F1 is a high threshold state and F2 is a low threshold state, W is represented as "-1"; When F1 is a high threshold state and F2 is a high threshold state, W is represented as "0".

3. The 2F-1T-1C unit circuit according to claim 1, characterized in that: Its operation logic for performing multiplication between signed inputs and signed weights is as follows: (i) By controlling the voltage states of WLA, WLB, SL1 and SL2, the corresponding threshold states are written to F1 and F2 to complete the pre-storage of W; (ii) Set SAE to high level VDD, precharge C0 through AWL so that the initial voltage of X is 1 / 2VDD, and set SAE to low level after precharging. (iii) Preset the voltage values ​​of SL1 and SL2 according to the preset encoding logic to complete the IN input; (iv) Obtain the node voltage of node X and decode it into the corresponding product P.

4. The 2F-1T-1C unit circuit according to claim 3, characterized in that: In the data storage function, the operation logic for writing signed numbers is as follows: First set WLA to write level V W WLB is set to low level; SL1 and SL2 are set to low level; F1 is set to low threshold state; then SL1 and SL2 are set to write level, and then F2 is set to high threshold state to complete the writing of data "+1"; First, set WLA to low level and WLB to write level; set SL1 and SL2 to low level; then set F2 to low threshold state; then set SL1 and SL2 to write level, and then set F1 to high threshold state to complete the writing of data "-1"; Connect WLA and WLB to low level, connect SL1 and SL2 to write level, and then set F1 and F2 to high threshold state to complete the writing of data "0".

5. The 2F-1T-1C unit circuit according to claim 1, characterized in that, The logic for implementing signed number reading is as follows: (I) Set SAE to high level and precharge C0 through AWL so that the initial voltage of X is V1. After the precharge is completed, set SAE to low level. (II) Set SL1 and SL2 to low level; (III) First, set WLA to the read level Vr and WLB to low level; obtain the first level state X1 of X; then set WLA to low level and WLB to Vr; obtain the second level state X2 of X; If X1 is low, it means the stored data is "+1"; if X1 is high and X2 is low, it means the stored data is "-1"; if X1 is high and X2 is high, it means the stored data is "0".

6. The 2F-1T-1C unit circuit according to claim 1, characterized in that: It is also used to perform XOR operations between single-bit unsigned numbers, with the following operation logic: S1: Characterize one of the operands IN1 of the XOR operation using the threshold states F1 and F2, and pre-write it: When F1 is a low threshold state and F2 is a high threshold state, IN1 is represented as "1"; when F1 is a high threshold state and F2 is a low threshold state, IN1 is represented as "0". S2: Set SAE to high level, precharge C0 through AWL so that the initial voltage of X is V1, and set SAE to low level after precharging is complete; S3: Input the other operand IN2 of the XOR operation, characterized by the level states of SL1 and SL2: When SL1 is high and SL2 is low, IN2 is "1"; when SL1 is low and SL2 is high, IN2 is "0". S4: Read the XOR operation result based on the level state of node X: Wherein, if X is high, it means that the result of the XOR operation is 1; if X is low, it means that the result of the XOR operation is 0.

7. A memory computing circuit, characterized in that: It includes: The in-memory array is formed by arranging the 2F-1T-1C unit circuit as described in any one of claims 1-6 as an array of in-memory units; each in-memory unit further includes a CMOS switch, one end of which is connected to node X and the other end is connected to the computing bit line ML; in the in-memory array, each in-memory unit in the same column shares WLA, WLB, SAE, AWL and ML; each in-memory unit in the same row shares SL1 and SL2; The column driver circuit is used to set WLA, WLB, SAE, and AWL to specified level states, wherein WLA and WLB include write level state, low level state, and read level state; SAE includes high level state and low level state; and AWL includes VDD and 1 / 2VDD. A row drive circuit, which is used to set SL1 and SL2 to a specified voltage value; The output circuit includes a sensitive amplifier and an analog-to-digital converter connected to each ML in the memory array. The sensitive amplifier is used to quantize the level state of the ML to realize the reading of stored data and logical operation results. The analog-to-digital converter is used to quantize the bit line voltage value of the ML to realize the reading of arithmetic operation results.

8. The memory computing circuit according to claim 7, characterized in that: Each storage unit performs a multiplication operation between a multi-bit signed input and a two-bit signed weight. And / or, using multiple storage units in the same column but different rows, perform multiplication and accumulation operations between each multi-bit signed input IN1~INn and each two-bit signed weight W1~Wn; its operation logic includes: S01: In a number of cycles, W1~Wn are pre-stored in the storage units of the specified row in sequence; Among them, the same two-bit signed weights are written synchronously within the same period; S02: Pre-fill 1 / 2VDD of the corresponding column's ML; then input each multi-bit signed input IN1~INn through SL1 and SL2 of each row. S03: Charge sharing of calculation results is achieved through CMOS switches between each memory unit and ML, so that the multiply-accumulate operation result is reflected in the bit line voltage of ML; the bit line voltage value of ML is quantized to obtain the multiply-accumulate operation result; And / or, the results of operations on different columns are shifted and added according to their weights to support multiplication or multi-accumulation operations between multi-bit signed inputs and signed weights greater than 2 bits.

9. The memory computing circuit according to claim 7, characterized in that: It supports TCAM addressing operations, including: SL1 and SL2 are used as addressing lines to achieve addressing data input; During the addressing operation, the X of the corresponding memory cell is first precharged to a high level via the AWL signal, and then the addressing data is input; the addressing result is reflected in the level state of the ML of the corresponding column; By controlling the switching state of the CMOS switches connected to the ML for each memory cell, the memory cells that do not participate in addressing are shielded.

10. A chip, characterized in that: It is packaged from the memory computing circuit as described in any one of claims 7-9.

Images