GaN half-bridge circuit and GaN bootstrap power supply voltage generator circuit

Abstract

The invention discloses a GaN half-bridge circuit and a GaN bootstrap supply voltage generator circuit. The circuit includes a bootstrap supply voltage generator configured to supply a first supply voltage, and includes a switching node. The circuit further comprises a bootstrap transistor, a bootstrap transistor driving circuit and a bootstrap capacitor connected with the switch node and the bootstrap transistor. The bootstrap capacitor is configured to supply a first power supply voltage when a voltage at the switching node is equal to a second switching node voltage, and the bootstrap transistor is configured to electrically connect the bootstrap capacitor with a power supply node at the second power supply voltage when the voltage at the switching node is equal to the first switching node voltage, and the bootstrap power supply voltage generator does not comprise an independent diode which is connected in parallel with the drain electrode and the source electrode of the bootstrap transistor.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of April 7, 2020, application number 202010267078.5, and invention name “GaN half-bridge circuit and GaN bootstrap power supply voltage generator circuit”.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims priority to U.S. Patent Application No. 16 / 375,729, filed on April 4, 2019, entitled “BOOTSTRAP POWER SUPPLY CIRCUIT,” which was granted and published on March 24, 2020 as U.S. Patent No. 10,601,302. Technical Field

[0005] The present invention relates generally to power conversion circuits, and more particularly to power conversion circuits utilizing one or more GaN-based semiconductor devices. Background Art

[0006] Electronic devices such as computers, servers, and televisions, among others, employ one or more power conversion circuits to convert one form of electrical energy to another form of electrical energy. Some power conversion circuits convert a high DC voltage to a lower DC voltage using a circuit topology known as a half-bridge converter. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new half-bridge converter circuits and components may be needed to meet the needs of new electronic devices. SUMMARY OF THE INVENTION

[0008] One inventive aspect is a GaN half-bridge circuit, the GaN half-bridge circuit including a GaN bootstrap supply voltage generator configured to supply a first supply voltage, the bootstrap supply voltage generator including a switch node, wherein the voltage at the switch node varies between the first switch node voltage and a second switch node voltage, a bootstrap transistor including a gate, a bootstrap transistor drive circuit configured to control the voltage at the gate of the bootstrap transistor, and a bootstrap capacitor connected to the switch node and the bootstrap transistor, wherein the bootstrap capacitor is configured to supply the first supply voltage when the voltage at the switch node is equal to the second switch node voltage, and wherein the bootstrap transistor is configured to electrically connect the bootstrap capacitor to the supply node at the second supply voltage when the switch node is equal to the first switch node voltage, wherein the bootstrap supply voltage generator does not include a separate diode in parallel with the drain and source of the bootstrap transistor.

[0009] Another inventive aspect is a GaN bootstrap supply voltage generator configured to supply a first supply voltage, the bootstrap supply voltage generator comprising a switch node, wherein a voltage at the switch node varies between a first switch node voltage and a second switch node voltage, a bootstrap transistor including a gate, a bootstrap transistor drive circuit configured to control a voltage at a gate of the bootstrap transistor, and a bootstrap capacitor connected to the switch node and the bootstrap transistor, wherein the bootstrap capacitor is configured to supply the first supply voltage when the voltage at the switch node is equal to the second switch node voltage, wherein the bootstrap transistor is configured to electrically connect the bootstrap capacitor to a substantially fixed voltage supply at a second supply voltage when the voltage at the switch node is equal to the first switch node voltage, wherein the bootstrap transistor drive circuit The circuit is configured to conditionally cause the bootstrap transistor to conduct current from a basic fixed voltage power supply to the bootstrap capacitor when a voltage at a connection between the bootstrap capacitor and the bootstrap transistor is less than the voltage of the basic fixed voltage power supply by causing a voltage at a gate terminal of the bootstrap transistor to be greater than the voltage of the basic fixed voltage power supply by an amount greater than a threshold voltage of the bootstrap transistor, and wherein the bootstrap transistor drive circuit is configured to conditionally conduct current from the basic fixed voltage power supply to the bootstrap capacitor when a voltage at a connection between the bootstrap capacitor and the bootstrap transistor is less than the voltage at the basic fixed voltage power supply by an amount greater than a threshold voltage of the bootstrap transistor by causing a voltage at a gate terminal of the bootstrap transistor to be substantially equal to a voltage of a fixed power supply.

[0010] Another inventive aspect is a GaN bootstrap supply voltage generator configured to supply a first supply voltage, the bootstrap supply voltage generator including a switch node, wherein the voltage at the switch node varies between the first switch node voltage and a second switch node voltage, including a bootstrap transistor at a gate, a bootstrap transistor drive circuit configured to control the voltage at the gate of the bootstrap transistor, and a bootstrap capacitor connected to the switch node and the bootstrap transistor, wherein the bootstrap capacitor is configured to supply the first supply voltage when the voltage at the switch node is equal to the second switch node voltage, and wherein the bootstrap transistor is configured to electrically connect the bootstrap capacitor to the supply node at the second supply voltage when the voltage at the switch node is equal to the first switch node voltage, wherein the bootstrap transistor drive circuit is configured to conditionally cause the voltage at the gate of the bootstrap transistor to be greater than a voltage of a fixed power supply by an amount greater than a threshold voltage of the bootstrap transistor, and wherein the bootstrap transistor drive circuit is configured to conditionally cause the voltage at the gate of the bootstrap transistor to be substantially equal to the voltage of the fixed power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a simplified schematic diagram of a half-bridge power conversion circuit according to an embodiment of the present invention;

[0012] Figure 2 yes Figure 1 A simplified schematic diagram of the circuitry within the low-side control circuit shown;

[0013] Figure 3 yes Figure 1 A schematic diagram of a first level-shift transistor shown;

[0014] Figure 4 yes Figure 1 A schematic diagram of a level shift driver circuit is shown;

[0015] Figure 5 yes Figure 1 The schematic diagram of the blanking pulse generator circuit shown;

[0016] Figure 6 yes Figure 5 An example of the waveform within the blanking pulse generator is shown;

[0017] Figure 7 yes Figure 1 Schematic diagram of a bootstrap transistor driving circuit shown;

[0018] Figure 8 yes Figure 1 A block diagram of a low-side transistor driver circuit is shown;

[0019] Fig. 9 yes Figure 1 The schematic diagram of the starting circuit shown;

[0020] Fig.10 is a series of diode-connected GaN-based enhancement mode transistors that can be used as Fig. 9 The diode clamp in the schematic diagram;

[0021] Fig.11 yes Figure 1 The schematic diagram of the UVLO circuit shown;

[0022] Fig.12 yes Figure 1 Schematic diagram of the bootstrap capacitor charging circuit shown;

[0023] Fig.13 is with Fig.12 A schematic diagram of an alternative bootstrap capacitor charging circuit compared to the circuit shown;

[0024] Fig.14 yes Figure 1 A schematic diagram of the high-side logic and control circuit shown;

[0025] Fig.15 yes Fig.14A schematic diagram of a first level shift receiver circuit is shown;

[0026] Fig.16 yes Fig.14 A schematic diagram of a second level shift receiver circuit shown;

[0027] Fig.17 yes Fig.14 The schematic diagram of the pull-up trigger circuit shown;

[0028] Fig.18 yes Fig.14 Schematic diagram of the high-side UVLO circuit shown;

[0029] Fig.19 yes Fig.14 A schematic diagram of a high-side transistor driver circuit is shown;

[0030] Fig. 20 yes Fig.14 A schematic diagram of a high-side reference voltage generating circuit is shown;

[0031] Fig.21 is a simplified schematic diagram of a half-bridge power conversion circuit according to another embodiment of the present invention;

[0032] Fig. 22 yes Fig.21 A simplified schematic diagram of the circuitry within the low-side control circuit shown;

[0033] Fig.23 yes Fig. 22 A schematic diagram of a first level-shift transistor shown;

[0034] Fig.24 yes Fig. 22 A schematic diagram of the inverter / buffer circuit shown;

[0035] Fig.25 yes Fig. 22 The schematic diagram of the on-pulse generator circuit shown;

[0036] Fig.26 yes Fig. 22 A schematic diagram of a shutdown pulse generator circuit is shown;

[0037] Fig. 27 yes Fig. 22 The schematic diagram of the blanking pulse generator circuit shown;

[0038] Fig.28 yes Fig. 22 A schematic diagram of a low-side transistor driving circuit is shown;

[0039] Fig.29 yes Fig.21A simplified schematic diagram of the circuitry within the high-side control circuit shown;

[0040] Fig.30 yes Fig.29 Schematic diagram of a level shift 1 receiver circuit shown;

[0041] Fig.31 yes Fig.29 Schematic diagram of a level shift 2 receiver circuit shown;

[0042] Fig.32 yes Fig.29 Schematic diagram of the high-side UVLO circuit shown;

[0043] Fig.33 yes Fig.29 A schematic diagram of a high-side transistor driver circuit is shown;

[0044] Fig.34 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention;

[0045] Fig.35 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention;

[0046] Fig.36 is a diagrammatic representation of a portion of an electronic package according to an embodiment of the present invention;

[0047] Fig.37 yes Fig.36 Illustration of an electronic package;

[0048] Fig.38 is a schematic diagram of an alternative embodiment of a bootstrap capacitor charging circuit;

[0049] Fig.39 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0050] Fig.40 It is shown Fig.39 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0051] Fig.41 is a schematic diagram of an implementation scheme of a VH generator circuit;

[0052] Fig.42 Yes Description Fig.41 A timing diagram showing the timing relationship between various signals of the VH generator circuit;

[0053] Fig.43 is the schematic diagram of the HGATE generator circuit;

[0054] Fig.44 It is shown Fig.43 A timing diagram showing the timing relationship between various signals of the HGATE generator circuit;

[0055] Fig.45 is the schematic diagram of the LGATE generator circuit;

[0056] Fig.46 It is shown Fig.45 A timing diagram showing the timing relationship between various signals of the LGATE generator circuit;

[0057] Fig.47 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0058] Fig.48 It is shown Fig.47 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0059] Fig.49 is the schematic diagram of the HGATE generator circuit;

[0060] Fig.50 It is shown Fig.49 A timing diagram showing the timing relationship between various signals of the HGATE generator circuit;

[0061] Fig.51 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0062] Fig.52 It is shown Fig.51 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0063] Fig.53 is a schematic diagram of the VH generator circuit;

[0064] Fig.54 Yes Description Fig.53 A timing diagram showing the timing relationship between various signals of the VH generator circuit;

[0065] Fig.55 is the schematic diagram of the HGATE generator circuit;

[0066] Fig.56 It is shown Fig.55 A timing diagram showing the timing relationship between various signals of the HGATE generator circuit;

[0067] Fig.57 is the schematic diagram of the LGATE generator circuit;

[0068] Fig.58 It is shown Fig.57A timing diagram showing the timing relationship between various signals of the LGATE generator circuit;

[0069] Fig.59 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0070] Fig.60 It is shown Fig.59 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0071] Fig.61 is the schematic diagram of the HGATE generator circuit;

[0072] Fig.62 It is shown Fig.61 A timing diagram showing the timing relationship between various signals of the HGATE generator circuit;

[0073] Fig.63 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0074] Fig.64 It is shown Fig.64 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0075] Fig.65 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0076] Fig.66 It is shown Fig.65 A timing diagram showing the timing relationship between various signals of a bootstrap transistor driving circuit;

[0077] Fig.67 is a schematic diagram of an implementation scheme of a bootstrap transistor drive circuit;

[0078] Fig.68 It is shown Fig.67 A timing diagram showing the timing relationship between various signals of the bootstrap transistor drive circuit. DETAILED DESCRIPTION OF THE INVENTION

[0080] Certain embodiments of the present invention relate to half-bridge power conversion circuits that employ one or more gallium nitride (GaN) devices. Although the present invention can be used in a wide variety of half-bridge circuits, some embodiments of the present invention are particularly suitable for half-bridge circuits designed to operate at high frequency and / or high efficiency using integrated driver circuits, integrated level shifting circuits, integrated bootstrap capacitor charging circuits, integrated startup circuits, and / or hybrid solutions using GaN devices and silicon devices, as described in more detail below.

[0081] Half-bridge circuit #1

[0082] Reference now Figure 1 In some embodiments, the circuit 100 may include a pair of complementary power transistors (also referred to herein as switches) controlled by one or more control circuits configured to regulate power delivered to a load. In some embodiments, the high-side power transistor is disposed on the high-side device together with portions of the control circuit, and the low-side power transistor is disposed on the low-side device together with portions of the control circuit, as described in more detail below.

[0083] Figure 1 The integrated half-bridge power conversion circuit 100 shown includes: a low-side GaN device 103, a high-side GaN device 105, a load 107, a bootstrap capacitor 110 and other circuit elements, as shown and discussed in more detail below. Some embodiments may also have an external controller ( Figure 1 1 ), the external controller provides one or more inputs to the circuit 100 to adjust the operation of the circuit. The circuit 100 is for illustrative purposes only, and other variations and configurations are within the scope of the present disclosure.

[0084] In one embodiment, the low-side GaN device 103 can have a GaN-based low-side circuit 104 including a low-side power transistor 115 having a low-side control gate 117. The low-side circuit 104 can further include an integrated low-side transistor driver 120, the output 123 of the integrated low-side transistor driver 120 connected to the low-side transistor control gate 117. In another embodiment, the high-side GaN device 105 can have a GaN-based high-side circuit 106 including a high-side power transistor 125 having a high-side control gate 127. The high-side circuit 106 can further include an integrated high-side transistor driver 130, the output 133 of the integrated high-side transistor driver 130 connected to the high-side transistor control gate 127.

[0085] A voltage source 135 (also referred to as a mains voltage) may be connected to a drain 137 of the high-side transistor 125, and the high-side transistor may be used to control the power input to the power conversion circuit 100. The high-side transistor 125 may further have a source 140 coupled to a drain 143 of the low-side transistor 115, thereby forming a switch node 145. The low-side transistor 115 may have a source 147 connected to ground. In one embodiment, the low-side transistor 115 and the high-side transistor 125 may be GaN-based enhancement mode field effect transistors. In other embodiments, the low-side transistor 115 and the high-side transistor 125 may be any other type of device, including but not limited to a GaN-based depletion mode transistor, a GaN-based depletion mode transistor connected in series with a silicon-based enhancement mode field effect transistor, a silicon carbide-based transistor, or a silicon-based transistor, the gate of the depletion mode transistor being connected to the source of the silicon-based enhancement mode transistor.

[0086] In some embodiments, the high-side device 105 and the low-side device 103 may be made of GaN-based materials. In one embodiment, the GaN-based material may include a GaN layer on a silicon layer. In a further embodiment, the GaN-based material may include, but is not limited to, a GaN layer on a layer of silicon carbide, sapphire, or aluminum nitride. In one embodiment, the GaN-based layer may include, but is not limited to, a composite stack of other III-nitrides (e.g., aluminum nitride and indium nitride) and III-nitride alloys (e.g., AlGaN and InGaN). In a further embodiment, the GaN-based low-voltage side circuit 104 and the GaN-based high-voltage side circuit 106 may be arranged on a monolithic GaN-based device. In other embodiments, the GaN-based low-side circuit 104 may be arranged on a first GaN-based device, and the GaN-based high-side circuit 106 may be arranged on a second GaN-based device. In some further embodiments, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may be arranged on more than two GaN-based devices. In one embodiment, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may include any number of active or passive circuit elements arranged in any configuration.

[0087] Low-side devices

[0088] The low-side device 103 may include many circuits for the control and operation of the low-side device and the high-side device 105. In some embodiments, the low-side device 103 may include a logic, control and level shifting circuit (low-side control circuit controller) 150, which controls the switching of the low-side transistor 115 and the high-side transistor 125 and other functions, as discussed in more detail below. The low-side device 103 may also include a startup circuit 155, a bootstrap capacitor charging circuit 157 and a shielding capacitor 160, which are also discussed in more detail below.

[0089] Reference now Figure 2 , functionally illustrating the circuits within the low side control circuit 150. Each circuit within the low side control circuit 150 will be discussed below, and in some cases in detail. Figure 3-14 In one embodiment, the main function of the low-side control circuit 150 may be to receive one or more input signals, such as PWM signals, from a controller and control the operation of the low-side transistor 115 and the high-side transistor 125 .

[0090] In one embodiment, first and second level shift transistors 203, 205, respectively, may be used to communicate with high-side logic and control circuitry 153 (see Figure 1 ). In some embodiments, the first level-shift transistor 203 may be a high voltage enhancement mode GaN transistor. In further embodiments, the first level-shift transistor 203 may be similar to the low-side transistor 115 (see Figure 1 ) and the high-side transistor 125, except that its size can be much smaller (for example, the gate width of the minimum channel length of the first level-shift transistor can be tens of microns).

[0091] In other embodiments, the first level-shift transistor 203 may experience both high voltage and high current simultaneously (i.e., the device may operate in a high power portion of the device safe operating area) as long as the high-side transistor 125 (see ) is turned on. Such conditions may result in relatively high power consumption, and therefore some embodiments may involve design and device reliability considerations in the design of the first level-shift transistor 203, as discussed in more detail below. In further embodiments, a first level-shift resistor 207 may be added in series with the source 210 of the first level-shift transistor 203 to limit the gate 213 to the voltage of the source 210, thereby limiting the maximum current through the first level-shift transistor. Other methods may be used to limit the current through the first level-shift transistor 203 and are within the scope of the present disclosure. The drain 215 of the first level-shift transistor 203 may be coupled to the high-side logic and control circuit 153 (see Figure 1 ), as discussed in more detail below.

[0092] In one embodiment, the first level-shift transistor 203 may include a portion of an inverter circuit having a first input and a first output and configured to receive a first input logic signal at a first input terminal and in response, provide a first inverted output logic signal at a first output terminal, as discussed in more detail below. In other embodiments, the first input and first inverted output logic signals may be referenced to different potentials. In some embodiments, the first level-shift resistor 207 may be capable of operating with a first inverted output logic signal referenced to a voltage 13 volts higher than the reference voltage of the first input logic signal. In other embodiments, it may be capable of operating with a first inverted output logic signal referenced to a voltage 20 volts higher than the reference voltage of the first input logic signal, and in other embodiments, it may be higher between 80-400 volts.

[0093] In other embodiments, the first level shift resistor 207 can be replaced by any form of current sink. For example, in one embodiment, the source 210 of the first level shift transistor 203 can be connected to a depletion mode device with a gate to source short. In another embodiment, a depletion mode device can be made by replacing the enhancement mode gate stack with a high voltage field plate metal stacked on top of the field dielectric layer. The thickness of the field dielectric and the work function of the metal can be used to determine the pinch-off voltage of the stack.

[0094] In other embodiments, the first level shift resistor 207 may be replaced by a current sink. The current sink may use a reference current (Iref) which may be provided by the startup circuit 155 (in Figure 1 Both the depletion mode transistor and current sink implementations can result in significant device area reduction compared to the resistor implementation (ie, because a relatively small depletion mode transistor is sufficient and the startup circuit 155 already provides Iref).

[0095] The second level-shift transistor 205 can be designed similarly to the first level-shift transistor 203 (e.g., in terms of voltage capability, current handling capability, thermal resistance, etc.). Similar to the first level-shift transistor 203, the second level-shift transistor 205 can also be constructed with active current sinks or resistors. In one embodiment, the main difference from the second level-shift transistor 205 can be in its operation. In some embodiments, the main purpose of the second level-shift transistor 205 can be to prevent false triggering of the high-side transistor 125 when the low-side transistor 115 is turned off (see Figure 1 ).

[0096] In one embodiment, for example, false triggering may occur in boost operation when the low-side transistor 115 is turned off causing load current to flow through the high-side transistor 125 while the transistor is operating in the third quadrant with its gate shorted to its source (i.e., in synchronous rectification mode). Since the switch node is at a voltage close to ground when the low-side transistor 115 is turned on and then transitions to the rail voltage 135 in a relatively short period of time, this condition may introduce a dv / dt condition at the switch node (Vsw) 145. The resulting parasitic C*dv / dt current (i.e., C=Coss of the first level-shift transistor 203 plus any other capacitance to ground) may cause the first level-shift node 305 (see Figure 3 ) is pulled low, which will then turn on the high-side transistor 125. In some embodiments, this condition may be undesirable because there may be no dead time control and shoot-through may occur due to both the high-side transistor 125 and the low-side transistor 115 being in a conductive state at the same time.

[0097] Figure 3 1 shows an embodiment showing how the first level-shift transistor 203 can be electrically coupled to the high-side device 105. The first level-shift transistor 203 located on the low-side device 103 is shown together with a pull-up resistor 303 that can be located on the high-side device 105 (see FIG. Figure 1 ). In some embodiments, the first level-shift transistor 203 can be used as a pull-down transistor in a resistor pull-up inverter.

[0098] In a further embodiment, when the level shift driver circuit 217 (see Figure 2 ) provides a high gate signal (L1_DR) to the first level shift transistor 203, the first level shift node 305 is pulled low, which is inverted by the high side logic and control circuit 153 (see Figure 1 ). The inverted signal appears as a high state signal, which turns on the high-side transistor 137 (see Figure 1 ), and then pulls the voltage at the switch node (Vsw) 145 to close to the mains voltage 135.

[0099] In contrast, when the level shift driver circuit 217 (see Figure 2 ) supplies a low gate signal to the first level shift transistor 203, the first level shift node 305 is pulled to a high logic state, which is inverted by the high side logic and control circuit 153 (see Figure 1). The inverted signal appears as a low logic state signal that turns off the high-side transistor 125. This approach can result in a non-inverted gate signal to the high-side transistor 125. In further embodiments, the first level-shift transistor 203 can be designed to be large enough to pull down on the first level-shift node 305, but not so large that its drain-to-source and drain-to-substrate (i.e., semiconductor substrate) capacitances cause false triggering of the high-side logic and control circuit 153.

[0100] In some embodiments, the pull-up resistor 303 may alternatively be an enhancement mode transistor, a depletion mode transistor, or a reference current source element. In further embodiments, the pull-up resistor 303 may be coupled between the drain and positive terminal of a floating power supply (e.g., a bootstrap capacitor discussed in more detail below) referenced to a voltage rail different from ground. In still other embodiments, a first capacitor (see FIG. 1 ) may be present between the first output terminal (LS_NODE) ​​305 and the switch node (Vsw) 145. Figure 1 ), and there may be a second capacitor between the first output terminal and ground, wherein the first capacitor is larger than the second capacitor. The first capacitor may be designed so that in response to a high dv / dt signal at the switch node (Vsw) 145 (see Figure 1 ), allowing most of the C*dv / dt current to be conducted through the first capacitor, ensuring that the voltage at the first output terminal 305 tracks the voltage at the switch node (Vsw). In some embodiments, the shielding capacitor 160 (see Figure 1 ) can be designed to function as the first capacitor as described above. In another embodiment, shielding capacitor 160 (see Figure 1 ) can be used to connect the first output terminal 305 and the switch node (Vsw) 145 in the half-bridge power conversion circuit 100 (see Figure 1 ) generates capacitance between them. In other embodiments, shielding capacitor 160 (see Figure 1 ) can also be used to minimize the capacitance between the first output terminal 305 and the substrate (i.e., the semiconductor substrate). More specifically, in some embodiments, a shielding capacitor 160 can be created by adding a conductive shielding layer to the device and coupling the layer to the switch node (Vsw) 145. This structure can effectively create two capacitors. One capacitor is coupled between the output terminal 305 and the switch node (Vsw) 145, and the other capacitor is coupled between the switch node and the substrate. Therefore, the capacitance between the output terminal 305 and the substrate is actually eliminated. In other embodiments, the shielding capacitor 160 (see Figure 1 ) may be constructed on the low-side chip 103 .

[0101] Logic, control and level shifting circuits 150 (see Figure 2) may have other functions and circuits, such as, but not limited to, a level shift driver circuit 217, a low-side transistor drive circuit 120, a blanking pulse generator 223, a bootstrap transistor drive circuit 225 and an undervoltage lockout output (input) circuit 227, as described in more detail below in separate figures.

[0102] Reference now Figure 4 , showing the level shift driver circuit 217 in more detail. In one embodiment, the level shift driver circuit 217 can include a first inverter 405 and a second inverter 410 in a sequential chain. In other embodiments, since the level shift driver circuit 217 can drive a first level shift transistor 203 with a small gate width, a buffer stage may not be required.

[0103] In one embodiment, the level shift driver circuit 217 is driven directly by a pulse width modulated high side signal (PWM_HS) from a controller (not shown). In some embodiments, the (PWM_HS) signal can be supplied by an external control circuit. In one embodiment, the external control circuit can be an external controller that is in the same package as the high side device 105, the low side device 103, both devices, or separate packages. In other embodiments, the level shift driver circuit 217 can also include logic that controls when the level shift driver circuit communicates with the first level shift transistor 203 (see Figure 3 In one embodiment, an optional low side under voltage lockout output signal (LS_UVLO) may be generated by an under voltage lockout output circuit within the level shift driver circuit 217. The low side under voltage lockout output circuit may be used to shut down the level shift driver circuit 217 if (Vcc) or (Vdd) of the low side (Vdd_LS) is below a certain reference voltage or a fraction of a reference voltage.

[0104] In another embodiment, the level shift driver circuit 217 can generate a shoot-through protection signal for the low-side transistor (STP_LS) that is used to prevent shoot-through caused by overlapping gate signals on the low-side transistor 115 and the high-side transistor 125. The function of the (STP_LS) signal can be to ensure that when the gate signal to the high-side transistor 125 is low, the low-side driver circuit 120 (see Figure 2 ) communicates only with the gate terminal of the low-side transistor 115. In other embodiments, the output of the first inverter 405 can be used to generate a shoot-through protection signal (STP_LS) for the low-side transistor 115.

[0105] In further embodiments, logic for UVLO and shoot-through protection can be implemented by adding a multi-input NAND gate to the first inverter 405, where the inputs to the NAND gate are the (PWM_HS), (LS_UVLO), and (STP_HS) signals. In yet other embodiments, the first inverter 405 can only respond to the (PWM_HS) signal if both the (STP_HS) and (LS_UVLO) signals are high. In other embodiments, the STP_HS signal can be generated from the low-side gate driver block 120, as explained in more detail in a separate figure.

[0106] Reference now Figure 5 , the blanking pulse generator 223 can be used to generate a pulse signal corresponding to the turn-off transient of the low-side transistor 115. Then, the pulse signal can turn on the second level-shift transistor 205 for the duration of the pulse, thereby triggering the high-side device 105 (see Figure 1 ) on the control circuit to prevent the first level shift node 305 voltage from being erroneously pulled down.

[0107] Figure 5 A schematic diagram of an embodiment of a blanking pulse generator 223 is shown. In some embodiments, the gate signal (LS_GATE) of the low-side transistor 115 is fed as an input to the blanking pulse generator 223. The (LS_GATE) signal is inverted by the first stage inverter 505, and then it is sent through the RC pulse generator 510 to generate a positive pulse. In some embodiments, because the pulse corresponds to the falling edge of the (LS_GATE) signal, an inverted signal may be required. The capacitor 515 in the RC pulse generator 510 circuit can be used as a high-pass filter, allowing the dv / dt at its input to appear across the resistor 520. Once the dv / dt disappears at the input of the RC pulse generator 510, the capacitor 515 can be slowly charged through the resistor 520, causing the voltage waveform across the resistor to decay slowly. Then the pulse can be sent through the second inverter 525, the third inverter 530 and the buffer 535 to generate a square wave pulse for the blanking pulse (B_PULSE) signal. The duration of the pulse may be determined by the values ​​of capacitor 515 and resistor 520 in RC pulse generator 510. In some embodiments, capacitor 515 may be constructed using an enhancement mode GaN transistor with a drain to source short.

[0108] Reference now Figure 6, an example waveform 600 within the blanking pulse generator 223 is shown for one embodiment. Trace 605 shows the falling edge of the low side gate pulse (LS_GATE). Trace 610 shows the rising edge of the output of the first stage inverter 505. Trace 615 shows the output of the RC pulse generator 510, and trace 620 shows the resulting blanking pulse (B_PULSE) signal, which is the output of the blanking pulse generator 223.

[0109] Reference now Figure 7 , the bootstrap transistor drive circuit 225 is shown in more detail. The bootstrap transistor drive circuit 225 includes an inverter 730, a first buffer 735, and a second buffer 745. The bootstrap transistor drive circuit 225 can receive a (BOOTFET_DR_IN) signal from the low-side driver circuit 120. The (BOOTFET_DR_IN) signal can be inverted relative to the LS_GATE signal. The bootstrap transistor drive circuit 225 can be configured to provide a charge to the bootstrap charging circuit 157 (see Figure 1 ) provides the gate drive signal that is called as (BOOTFET_DR), as discussed in more detail below.When low-side transistor 115 is turned on, (BOOTFET_DR) gate drive signal can be timed to turn on the bootstrap transistor.And, because bootstrap transistor driver circuit 225 is driven by (Vcc), the output of this circuit can have the voltage from 0 volts of low state to (Vcc)+6 volts of high state.In one embodiment, the bootstrap transistor is turned on after the low-side transistor 115 is turned on, and the bootstrap transistor is turned off before the low-side transistor is turned off.

[0110] In some embodiments, the turn-on transient of the (BOOTFET_DR) signal can be delayed by introducing a series delay resistor 705 to the input of the second buffer 745, which can be the gate of the transistor in the final buffer stage. In other embodiments, the turn-on transient of the low-side transistor 115 (see Figure 1 ). In one embodiment, one or more capacitors may be used in the bootstrap transistor drive circuit 225 and support a voltage on the order of, for example, about 20 volts (Vcc), depending on the end user's requirements and the design of the circuit. In some embodiments, one or more capacitors may be made with a field dielectric to a GaN capacitor instead of an enhancement mode transistor with a drain to source short.

[0111] Reference now Figure 8, a block diagram of the low-side transistor driver circuit 120 is shown. The low-side transistor driver circuit 120 may have a first inverter 805, a buffer 810, a second inverter 815, a second buffer 820, and a third buffer 825. The third buffer 825 may provide a (LS_GATE) signal to the low-side transistor 115 (see Figure 5 1). In some embodiments, two inverter / buffer stages may be used because the input to the gate of low-side transistor 115 (see Figure 1 ) may be synchronized with (Vin). Thus, (Vin) being in a high state may correspond to (Vgate) of the low-side transistor 115 being in a high state, and vice versa.

[0112] In further embodiments, certain portions of the low-side driver circuit 120 may have asymmetric hysteresis. Some embodiments may include asymmetric hysteresis using a resistor divider 840 and a transistor pull-down 850.

[0113] Further embodiments may have multiple input NAND gates for the (STP_LS) signal (shoot-through protection on the low-side transistor 115). In one embodiment, the low-side driver circuit 120 may receive the shoot-through protection signal (STP_LS) from the level-shift driver circuit 217. The purpose of the (STP_LS) signal may be similar to the (STP_HS) signal described previously. The (STP_LS) signal may ensure that the low-side transistor driver circuit 120 does not engage the gate 117 of the low-side transistor 115 when the output of the level-shift driver circuit 217 is in a high state (see Figure 1 In other embodiments, the output of the first inverter stage 805 can be used as a (STP_HS) signal for the level shift driver circuit 217 and a (BOOTFET_DR_IN) signal for the bootstrap transistor driver circuit 225.

[0114] In some embodiments, the low-side transistor driver circuit 120 can be configured to operate in a manner similar to that of the UVLO circuit 227 (see Figure 2 ) receives the (LS_UVLO) signal using multiple input NAND gates. Further embodiments may employ a turn-off delay resistor that may be connected in series with the gate of the final pull-down transistor in the final buffer stage 825. This delay resistor may be used in some embodiments to ensure that the bootstrap transistor is turned off before the low-side transistor 115 is turned off.

[0115] Reference now Fig. 9, showing the startup circuit 155 in more detail. The startup circuit 155 can be designed to have multiple functions, as discussed in more detail below. First, the startup circuit 155 can be used to provide an internal voltage (START_Vcc in this case) and provide sufficient current to support the circuit driven by (Vcc). This voltage can be maintained to support the circuit until (Vcc) is externally charged to the required voltage from the mains voltage 135 (V+). The startup circuit 155 can also provide a reference voltage (Vref) that can be independent of the startup voltage and a reference current sink (Iref).

[0116] In one embodiment, the depletion mode transistor 905 can act as the main current source in the circuit. In other embodiments, the depletion mode transistor 905 can be formed by a metal layer disposed above the passivation layer. In some embodiments, the depletion mode transistor 905 can use a high voltage field plate (typically inherent to any high voltage GaN technology) as a gate metal. In other embodiments, a field dielectric can be used as a gate insulator. The resulting gated transistor can be a depletion mode device with a high channel pinch-off voltage (Vpinch) (i.e., the pinch-off voltage is proportional to the field dielectric thickness). The depletion mode transistor 905 can be designed to block a relatively high voltage between its drain (connected to V+) and its source. Such a connection can be referred to as a source follower connection. The depletion mode transistor 905 can have a gate 906 coupled to ground, a source 907 coupled to a first node 911, and a drain 909 coupled to a voltage source 135.

[0117] In a further embodiment, the series connection of the enhancement mode low voltage transistor 910 of the same diode connection can be connected in series with the depletion mode transistor 905. The series connection of the enhancement mode low voltage transistor 910 of the same diode connection can be connected in series between the first node 911 and the second node 912. One or more intermediate nodes 913 can be arranged between each of the series connection of the enhancement mode low voltage transistor 910 of the same diode connection. The width-to-length ratio of the transistor can set the current drawn from (V+) and the voltage across each diode. In order to remove the threshold voltage and process variation sensitivity, the series connection of the enhancement mode low voltage transistor 910 of the same diode connection can be designed as a device with a large channel length. In some embodiments, the series connection of the enhancement mode low voltage transistor 910 of the same diode connection can be replaced by one or more high value resistors.

[0118] In a further embodiment, at the bottom of the series connection of the same diode-connected enhancement mode low voltage transistor 910, a current mirror 915 can be composed of two enhancement mode low voltage transistors and used to generate a reference current sink (Iref). The first current mirror transistor 920 can be diode-connected, and the second current mirror transistor 925 can have a gate connected to the gate of the first current mirror transistor. The sources of the first current mirror transistor 920 and the second current mirror transistor 925 can be coupled and grounded respectively. The drain terminal of the first current mirror transistor 920 can be coupled to the second junction 912, and the source terminal of the second current mirror transistor 925 can be used as a current sink terminal. The stack of the current mirror 915 and the series connection of the same diode-connected enhancement mode low voltage transistor 910 can form a so-called "source follower load" depletion mode transistor 905.

[0119] In other embodiments, when the gate 906 of the depletion mode transistor 905 is grounded, the source 907 of the depletion mode transistor can present a voltage close to (Vpinch) when current is supplied to the "source follower load". At the same time, the voltage drop across the diode-connected transistor 920 in the current mirror 915 can be close to the threshold voltage (Vth) of the transistor. This condition means that the voltage drop across each of the series of identical diode-connected enhancement mode low voltage transistors 910 can be equal to (Vpinch-Vth) / n, where "n" is the number of diode-connected enhancement mode transistors between the current mirror 915 and the depletion mode transistor 905.

[0120] For example, if the gate of the start-up transistor 930 is connected from the bottom to the third same diode-connected enhancement mode low voltage transistor, the gate voltage of the start-up transistor can be 3*(Vpinch-Vth) / n+Vth. Therefore, the start-up voltage can be 3*(Vpinch-Vth) / n+Vth-Vth=3*(Vpinch-Vth) / n. As a more specific example, in one embodiment, (Vpinch)=40 volts, (Vth)=2 volts, where n=6 and (Vstartup)=19 volts.

[0121] In other embodiments, the startup circuit 155 can generate a reference voltage signal (Vref). In one embodiment, the circuit that generates (Vref) can be similar to the startup voltage generation circuit discussed above. The reference voltage transistor 955 can be connected between two transistors in series of the same diode-connected enhancement mode low voltage transistor 910. In one embodiment, (Vref) = (Vpinch-Vth) / n.

[0122] In additional embodiments, a disable pull-down transistor 935 may be connected between the gate and source of the enable transistor 930. When the disable signal is high, the enable transistor 930 will be disabled. A pull-down resistor 940 may be connected to the gate of the disable transistor 935 to prevent erroneous turn-on of the disable transistor. In other embodiments, a diode clamp 945 may be connected between the gate and source terminals of the enable transistor 930 to ensure that the gate-to-source voltage capability of the enable transistor is not violated during circuit operation (i.e., configured as a gate overvoltage protection device). In some embodiments, the diode clamp 945 may be made of a series connection of a diode-connected GaN-based enhancement mode transistor 1050, such as Fig.10 shown.

[0123] Reference now Fig.11 , which shows the UVLO circuit 227 in more detail. In some embodiments, the UVLO circuit 227 can have a differential comparator 1105, a lower level shifter 1110, and an inverter 1115. In other embodiments, the UVLO circuit 227 can use the (Vref) and (Iref) generated by the startup circuit 155 in the differential comparator / lower level shifter circuit (see Fig. 9 ) to generate a signal (LS_UVLO) which is fed into the level shift driver circuit 217 (see Figure 2 ) and low-side transistor driver circuit 120. In some embodiments, UVLO circuit 227 can also be designed to have asymmetric hysteresis. In other embodiments, the output of UVLO circuit 227 can be independent of the threshold voltage. This can be achieved by selecting a differential comparator with a higher gain. In one embodiment, the gain can be increased by increasing the value of the current source and pull-up resistor in the differential comparator. In some embodiments, the limit of the current and resistor can be set by (Vref).

[0124] In other embodiments, the voltages (VA) and (VB) 1120 and 1125 can be proportional to (Vcc) or (Vdd_LS) and (Vref) as dictated by the resistor divider ratio on each input, respectively. When (VA) 1120>(VB) 1125, the output of the inverting terminal becomes a low state. In a particular embodiment, since the current source creates a source follower configuration, the low state = (Vth). Similarly, when (VA) 1120<(VB) 1125, the output enters a high state (Vref). In some embodiments, a lower level shifter 1110 may be required because the low voltage needs to be shifted down by a threshold voltage to ensure that the low input to the next stage is below (Vth). The down-shifted output can be inverted by a simple resistor pull-up inverter 1115. The output of inverter 1115 is the (LS_UVLO) signal.

[0125] Reference now Fig.12 , showing the bootstrap capacitor charging circuit 157 in more detail. In one embodiment, the bootstrap diode and transistor circuit 157 may include a parallel connection of a high voltage diode connected enhancement mode transistor 1205 and a high voltage bootstrap transistor 1210. In further embodiments, the high voltage diode connected enhancement mode transistor 1205 and the high voltage bootstrap transistor 1210 may be designed to share the same drain finger. In some embodiments, the (BOOTFET_DR) signal may be obtained from the bootstrap transistor drive circuit 225 (see Figure 2 As described above, the high voltage bootstrap transistor 1210 can be connected to the low side transistor 115 (see Figure 1 ) are turned on at the same time.

[0126] Reference now Fig.13 , an alternative bootstrap diode and transistor circuit 1300 may be used to replace the above Fig.12 The bootstrap diode and transistor circuit discussed in 157. Fig.13 In the embodiment shown, a depletion mode device 1305 cascaded by an enhancement mode low voltage GaN device 1310 may be connected as shown in schematic 1300. In another embodiment, the gate of the depletion mode device 1305 may be grounded to reduce the voltage stress on the cascaded enhancement mode device 1310, depending on the pinch-off voltage of the depletion mode device.

[0127] High-side devices

[0128] Reference now Fig.14 , details an embodiment of the high-side logic and control circuit 153. In one embodiment, the high-side driver 130 receives inputs from the first level-shifted receiver 1410 and the high-side UVLO circuit 1415 and sends a (HS_GATE) signal to the high-side transistor 125 (see Figure 1 ). In yet other embodiments, the pull-up trigger circuit 1425 is configured to receive the (LSHIFT_1) signal and control the pull-up transistor 1435. In some embodiments, the second level shift receiver circuit 1420 is configured to control the blanking transistor 1440. The pull-up transistor 1435 and the blanking transistor 1440 can be connected in parallel with the pull-up resistor 1430. Each circuit within the high-side logic and control circuit 153 is discussed below, and in some cases in Figure 16-20 is shown in more detail in .

[0129] Reference now Fig.15, showing the first level shift receiver 1410 in more detail. In some embodiments, the first level shift receiver 1410 can convert the (L_SHIFT1) signal into a (LS_HSG) signal, which can be driven by the high-side transistor driver 130 (see Fig.14 ) to drive the high-side transistor 125 (see Figure 1 ). In further embodiments, the first level shift receiver 1410 may have three enhancement mode transistors 1505, 1510, 1515 employed in a multi-level down-shifter and a plurality of diode-connected transistors 1520 used as diode clamps, as discussed in more detail below.

[0130] In one embodiment, the first level shift receiver 1410 can shift the (L_SHIFT1) signal down by 3*Vth (e.g., each enhancement mode transistor 1505, 1510, 1515 can have a gate-to-source voltage close to Vth). In some embodiments, the last source follower transistor (e.g., in this case, transistor 1515) can have a three diode-connected transistor clamp 1520 between its gate and source. In other embodiments, this arrangement can be used because its source voltage can only be as high as (Vdd_HS) (i.e., because its drain is connected to Vdd_HS), while its gate voltage can be as high as V(L_SHIFT1)–2*Vth. Therefore, in some embodiments, the maximum gate-to-source voltage on the last source follower transistor 1515 can be greater than the maximum rated gate-to-source voltage of the device technology. The output of the final source follower transistor 1515 is the high-side transistor driver 130 (see Figure 1 ) is an input of the clamp 1520 (i.e., the output is the LS_HSG signal). In other embodiments, fewer or more than three source follower transistors may be used. In still other embodiments, fewer or more than three diode-connected transistors may be used in the clamp 1520.

[0131] Reference now Fig.16 , showing the second level shift receiver 1420 in more detail. In one embodiment, the second level shift receiver 1420 can have a lower level shift circuit 1605 and an inverter circuit 1610. In some embodiments, the second level shift receiver 1420 can be constructed in a similar manner to the first level shift receiver 1410 (see Fig.15 ), except that the second level shift receiver may have only one lower level shift circuit (e.g., enhancement mode transistor 1615) and a follow-up on inverter circuit 1610. In one embodiment, the lower level shift circuit 1605 may be from the second level shift transistor 205 (see Figure 2) receives the (L_SHIFT2) signal. In one embodiment, the inverter circuit 1610 can be driven by the (Vboot) signal, and the gate voltage of the pull-up transistor of the inverter can be used as the (BLANK_FET) signal to drive the blanking transistor 1440 (see Fig.14 ). In some embodiments, the voltage can go from 0 volts in the low state to (Vboot+0.5*(Vboot-Vth)) in the high state. Similar to the first level shift receiver 1410, the second level shift receiver 1420 can have a diode connected transistor clamp 1620 across the gate to source of the source follower transistor 1615. In other embodiments, the clamp 1620 can include less than or more than three diode connected transistors.

[0132] Reference now Fig.17 , showing the pull-up trigger circuit 1425 in more detail. In one embodiment, the pull-up trigger circuit 1425 can have a first inverter 1705, a second inverter 1710, an RC pulse generator 1715, and a gate-to-source clamp 1720. In some embodiments, the pull-up trigger circuit 1425 can receive the (L_SHIFT1) signal as an input, and in response, generate a pulse immediately when the (L_SHIFT1) voltage transitions to near the input threshold of the first inverter 1705. The generated pulse can be used as a (PULLUP_FET) signal to drive the pull-up transistor 1435 (see Fig.14 ). The second inverter 1710 may be driven by (Vboot) instead of (Vdd_HS) because the gate voltage of the pull-up transistor 1435 may need to be greater than the (L_SHIFT1) signal voltage.

[0133] Reference now Fig.18 , showing the high-side UVLO circuit 1415 in more detail. In one embodiment, the high-side UVLO circuit 1415 can have a lower level shifter 1805, a resistive pull-up inverter 1810 with asymmetric hysteresis, and a gate-to-source clamp 1815. In a further embodiment, when the voltage of the bootstrap capacitor 110 is below a certain threshold, the (HS_UVLO) signal generated by the high-side UVLO circuit 1415 can be turned off by the high-side driver circuit 130 (see Fig.14) to prevent circuit failure. In some embodiments, the voltage (Vboot) of the bootstrap capacitor 110 (i.e., the floating supply voltage) is measured, and in response, a logic signal is generated and combined with the output signal (LS_HSG) from the first level shift receiver 1410, and then used as an input to the high-side gate drive circuit 130. More specifically, in this embodiment, for example, when (Vboot) decreases to less than 4×Vth above the voltage of the switch node (Vsw) 145, the UVLO circuit is designed to engage. In other embodiments, different threshold levels may be used.

[0134] In another embodiment, the high-side UVLO circuit 1415 can shift down (Vboot) in the lower level shifter 1805 and transmit the signal to the inverter 1810 with asymmetric hysteresis. The output of the inverter 1810 with asymmetric hysteresis can generate a (HS_UVLO) signal, which is logically combined with the output from the first level shift receiver 1410 to turn off the high-side transistor 125 (see Figure 1 ). In some embodiments, hysteresis can be used to reduce the high-side transistor 125 (see Figure 1 )'s number of self-triggered turn-on and turn-off events, which may be detrimental to the overall performance of the half-bridge circuit 100.

[0135] Reference now Fig.19 , showing the high-side transistor driver 130 in more detail. The high-side transistor driver 130 may have a first inverter stage 1905 followed by a high-side driver stage 1910. The first inverter stage 1905 may be coupled to a level shifter 1 receiver 1410 (see Fig.15 ) receives the down-shifted (LS_HSG) signal and inverts it. The down-shifted signal can then be sent through the high-side driver stage 1910. The high-side driver stage 1910 can generate a (HS_GATE) signal to drive the high-side transistor 125 (see Figure 1 In other embodiments, the first inverter stage 1905 may include a two-input NOR gate that can ensure that the high-side transistor 125 (see Figure 1 ) is turned off.

[0136] Reference now Fig. 20 , a reference voltage generation circuit 2000 may be used to generate a high side reference voltage from a power rail. Such a circuit may be placed on the high side GaN device 105 to generate an internal power supply for the reference switch node voltage 145. In some embodiments, the circuit 2000 may be similar to Fig. 9145 . One difference in circuit 2000 may be the addition of a source follower capacitor 2010 connected between the first node 2011 and the second node 2012. In some embodiments, the source follower capacitor 2010 may be required to ensure that a well-regulated voltage is formed between the first node 2011 and the second node 2012 that does not fluctuate with the dv / dt present at the switching node (Vsw) 145. In other embodiments, a reference voltage capacitor 2015 may be connected between the source of the reference voltage transistor 2055 and the second node 2012. In some embodiments, the drain of the reference voltage transistor 2055 may be connected to the (Vboot) node. In some embodiments, the reference voltage capacitor 2015 may be required to ensure that (Vref) is well regulated and does not respond to high dv / dt conditions at the switching node (Vsw) 145 (see Figure 1 ). In yet other embodiments, another difference in circuit 2000 may be that second node 2012 may be coupled to a constantly changing voltage, such as switch node (Vsw) 145 (see Figure 1 ), rather than through the current sink circuit 915 (see Fig. 9 In yet another embodiment, (Vref) may be used as (Vdd_HS) in the half-bridge circuit 100.

[0137] Another difference in circuit 2000 may be the addition of a high voltage diode connected transistor 2025 coupled between the series connection of the depletion mode transistor 2005 and the identical diode connected enhancement mode low voltage transistor 2020 (i.e., the gate of the transistor is coupled to the source of the transistor). More specifically, the high voltage diode connected transistor 2025 may have a source coupled to the source of the depletion mode transistor 2005, a drain coupled to the first node 2011, and a gate coupled to its source. The high voltage diode connected transistor 2025 may be used to ensure that the source follower capacitor 2010 does not discharge when the voltage on the top plate of the source follower capacitor rises above (V+). In further embodiments, the source follower capacitor 2010 may be relatively small and may be integrated on a semiconductor substrate or within an electronic package. Fig. 20 Also shown in FIG. 1 is a bootstrap capacitor 110 , which may be added externally in the half-bridge circuit.

[0138] In some embodiments, shield capacitor 160 (see Figure 1 ) can be shifted from the first level shift node 305 (see Figure 3) and a second level shift node (not shown) are connected to the switch node 145 to help reduce false triggering as described above. In some embodiments, the larger the value of the shielding capacitor 160, the more immune the circuit will be to false triggering effects due to parasitic capacitance to ground. However, during the off period of the high-side transistor 125, the shielding capacitor 160 can be connected to the first level shift node 305 by the pull-up resistor 303 (see Figure 3 ) discharge. This can significantly slow down the turn-off process of the high-side transistor 125. In some embodiments, this consideration can be used to set an upper limit on the value of the shielding capacitor 160. In other embodiments, the first level shift node 305 (see Figure 3 ) overvoltage condition on the first level shift node 305 (see Figure 3 ), with the gate and source connected to the switch node (Vsw) 145 (see Figure 1 In further embodiments, a second shielding capacitor and a second clamping circuit may be placed between the second level shifting node and the switch node (Vsw) 145 (see Figure 1 ).

[0139] Half-bridge circuit #1 operation

[0140] The following sequence of operations of the half-bridge circuit 100 is provided as an example only, and other sequences may be used without departing from the present invention. Figure 1 , Figure 2 and Fig.14 .

[0141] In one embodiment, when the (PWM_LS) signal from the controller is high, the low side logic, control and level shifting circuit 150 sends a high signal to the low side transistor driver 120. The low side transistor driver 120 then transmits the (LS_GATE) signal to the low side transistor 115 to turn it on. This sets the switch node voltage (Vsw) 145 to near 0 volts. When the low side transistor 115 is turned on, it provides a path for the bootstrap capacitor 110 to be charged through the bootstrap charging circuit 157, which can be connected between (Vcc) and (Vboot). The charging path has a high voltage bootstrap diode 1205 (see Fig.12 ) and the parallel combination of transistor 1210. (BOOTFET_DR) signal to bootstrap transistor 1210 (see Fig.12 ) provides a drive signal that provides a low resistance path for charging the bootstrap transistor 110.

[0142] Bootstrap diode 1205 (see Fig.12 ) can be used to ensure that there is a path for charging the bootstrap capacitor 110 during startup when there is no gate drive signal (LS_GATE) for the low-side transistor 115. During this period of time, the (PWM_HS) signal should be low. If the (PWM_HS) signal is accidentally turned on (i.e., in a high state) during this period of time, the (STP_HS) signal generated from the low-side transistor driver 120 will prevent the high-side transistor 125 from turning on. If the (PWM_LS) signal is turned on while the (PWM_HS) signal is turned on, the (STP_LS) signal generated from the level shift driver circuit 217 will prevent the low-side transistor 115 from turning on. Moreover, in some embodiments, when (Vcc) or (Vdd_LS) is lower than a preset threshold voltage level, the (LS_UVLO) signal can prevent the low-side transistor 115 and the high-side transistor 125 from turning on.

[0143] In further embodiments, when the (PWM_LS) signal is low, the low-side gate signal (LS_GATE) to the low-side transistor 115 is also low. During the dead time between the (PWM_LS) signal low state to the (PWM_HS) high state transition, depending on the direction of power flow, the inductive load will force the high-side transistor 125 or the low-side transistor 115 to turn on in synchronous rectifier mode. If the high-side transistor 125 is turned on during the dead time (e.g., during boost mode operation), the voltage of the switch node (Vsw) 145 can rise to close to (V+) 135 (mains voltage).

[0144] In some embodiments, due to capacitive coupling to ground, the dv / dt conditions on the switch node 145 (Vsw) may tend to shift the first level shift node (LSHIFT_1) 305 (see Figure 3 ) to a low state relative to the switching node (Vsw) 145. This may turn on the high side gate drive circuit 130, causing unintended triggering of the high side transistor 125. In one embodiment, this may result in no dead time, which may cause a shoot-through condition to compromise the half-bridge circuit 100. In a further embodiment, to prevent this from occurring, the blanking pulse generator 223 may sense the turn-off transient of the low side transistor 115 and send a pulse to turn on the second level shift transistor 205. This may pull the (L_SHIFT2) signal voltage to a low state and then communicate with the second level shift receiver 1420 to generate a blanking pulse signal (B_PULSE) to drive the blanking transistor 1440. The blanking transistor 1440 may then act as a pull-up to prevent the first level shift node (LSHIFT_1) 305 (see Figure 3) enters a low state relative to the switch node (Vsw) 145.

[0145] In another embodiment, after the dead time, when the (PWM_HS) signal goes high, the level shift driver circuit 217 can send a high signal to the gate of the first level shift transistor 203 (via the L1_DR signal from the level shift driver circuit 217). The high signal will raise the first level shift node (LSHIFT_1) 305 (see FIG. 1 ) relative to the switch node (Vsw) 145. Figure 3 ) is pulled low, which will generate a high signal at the input of the high-side transistor 125, thereby turning on the high-side transistor 125. The switch node voltage (Vsw) 145 will remain close to (V+) 135. In one embodiment, during this time, the bootstrap capacitor 110 can be discharged through the first level-shift transistor 203 (which is in a conductive state during this time).

[0146] If the high-side transistor 125 remains on for a relatively long time (i.e., a large duty cycle), the voltage of the bootstrap capacitor 110 will drop to a low enough voltage that will prevent the high-side transistor 125 from turning off when the (PWM_HS) signal goes low. In some embodiments, this may occur because the maximum voltage that the (L_SHIFT1) signal can reach is (Vboot), which may be too low to turn off the high-side transistor 125. In some embodiments, this situation can be prevented by the high-side UVLO circuit 1415, which forces the high-side transistor 125 to turn off by sending a high input to the high-side gate drive circuit 130 when (Vboot) is below a certain level.

[0147] In yet other embodiments, when the (PWM_HS) signal goes low, the first level-shift transistor 203 will also be turned off (via the L1_DR signal from the level-shift driver circuit 217). This will turn the first level-shift node (LSHIFT_1) 305 (see Figure 3 ) to a high state. However, in some embodiments, this process may be relatively slow because of the high value pull-up resistor 303 (see Figure 3 ) (used to reduce power consumption in some embodiments) requires a first level shift node (L_SHIFT1) 305 (see Figure 3 ) are charged, including the output capacitance (Coss) of the first level shift transistor 213 and the shielding capacitor 160. This will increase the turn-off delay of the high-side transistor 125. In order to reduce the turn-off delay of the high-side transistor 125, the pull-up trigger circuit 1425 can be used to sense the first level shift node (L_SHIFT1) 305 (see Figure 3) is higher than (Vth). This condition can generate a (PULLUP_FET) signal applied to the pull-up transistor 1435, which acts in parallel with the pull-up resistor 1430 and can significantly accelerate the first level shift node (L_SHIFT1) 305 (see Figure 3 ) pull-up voltage speeds up the shutdown process.

[0148] Half-bridge circuit #2

[0149] Reference now Fig.21 , discloses a second embodiment of a half-bridge circuit 2100. The half-bridge circuit 2100 may have Figure 1 The same block diagram of circuit 100 is shown, however, the level-shift transistors in circuit 2100 can be operated with pulsed inputs rather than continuous signals, as described in more detail below. In some embodiments, the pulsed inputs can result in lower power dissipation, reduced stress on the level-shift transistors, and reduced switching time, as discussed in more detail below.

[0150] Continue to refer Fig.21 , one embodiment includes an integrated half-bridge power conversion circuit 2100, which employs a low-side GaN device 2103, a high-side GaN device 2105, a load 2107, a bootstrap capacitor 2110, and other circuit elements, as discussed in more detail below. Some embodiments may also have an external controller ( Fig.21 2100 ), the external controller provides one or more inputs to the circuit 2100 to adjust the operation of the circuit. The circuit 2100 is for illustrative purposes only, and other variations and configurations are within the scope of the present disclosure.

[0151] like Fig.21 As further shown, in one embodiment, the integrated half-bridge power conversion circuit 2100 may include a low-side circuit disposed on a low-side GaN device 2103 including a low-side transistor 2115 having a low-side control gate 2117. The low-side circuit may further include an integrated low-side transistor driver 2120 having an output 2123 connected to the low-side transistor control gate 2117. In another embodiment, the high-side circuit may be disposed on a high-side GaN device 2105 including a high-side transistor 2125 having a high-side control gate 2127. The high-side circuit may further include an integrated high-side transistor driver 2130 having an output 2133 connected to the high-side transistor control gate 2127.

[0152] The high-side transistor 2125 can be used to control the power input to the power conversion circuit 2100 and has a voltage source (V+) 2135 (sometimes referred to as a mains voltage) connected to the drain 2137 of the high-side transistor. The high-side transistor 2125 can further have a source 2140 coupled to the drain 2143 of the low-side transistor 2115, thereby forming a switch node (Vsw) 2145. The low-side transistor 2115 can have a grounded source 2147. In one embodiment, the low-side transistor 2115 and the high-side transistor 2125 can be enhancement mode field effect transistors. In other embodiments, the low-side transistor 2115 and the high-side transistor 2125 can be any other type of device, including but not limited to a GaN-based depletion mode transistor, a GaN-based depletion mode transistor connected in series with a silicon-based enhancement mode field effect transistor, a silicon carbide-based transistor, or a silicon-based transistor, the gate of the depletion mode transistor being connected to the source of the silicon-based enhancement mode transistor.

[0153] In some embodiments, the high-side device 2105 and the low-side device 2103 can be made of GaN-based materials. In one embodiment, the GaN-based material can include a GaN layer on a silicon layer. In further embodiments, the GaN-based material can include, but is not limited to, a GaN layer on a layer of silicon carbide, sapphire, or aluminum nitride. In one embodiment, the GaN-based layer can include, but is not limited to, a composite stack of other III-nitrides (such as aluminum nitride and indium nitride) and III-nitride alloys (such as AlGaN and InGaN).

[0154] Low-side devices

[0155] The low-side device 2103 may have many circuits for the control and operation of the low-side device and the high-side device 2105. In some embodiments, the low-side device 2103 may include a low-side logic, control and level shifting circuit (low-side control circuit 2150) that controls the switching of the low-side transistor 2115 and the high-side transistor 2125 and other functions, as discussed in more detail below. The low-side device 2103 may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157, and a shielding capacitor 2160, which are also discussed in more detail below.

[0156] Reference now Fig. 22 , functionally illustrates the circuits within the low side control circuit 2150. Each circuit within the low side control circuit 2150 will be discussed below, and in some cases, in Figure 23-28In one embodiment, the main function of the low-side control circuit 2150 may be to receive one or more input signals, such as PWM signals, from a controller and control the operation of the low-side transistor 2115 and the high-side transistor 2125 .

[0157] The first level-shift transistor 2203 may be an "on" pulsed level-shift transistor, while the second level-shift transistor 2215 may be an "off" pulsed level-shift transistor. In one embodiment, a pulse width modulated high-side (PWM_HS) signal from a controller (not shown) may be processed by an inverter / buffer 2250 and sent to an on-pulse generator 2260 and an off-pulse generator 2270. The on-pulse generator 2260 may generate a pulse corresponding to a low-to-high-state transition of the (PWM_HS) signal, thereby turning on the first level-shift transistor 2203 for the duration of the pulse. The off-pulse generator 2270 may similarly generate a pulse corresponding to a high-to-low-state transition of the (PWM_HS) signal, thereby turning on the second level-shift transistor 2205 for the duration of the off-pulse.

[0158] The first and second level-shift transistors 2203, 2205, respectively, can be used as pull-down transistors in a resistor pull-up inverter circuit. More specifically, turning on can mean that the corresponding level-shift node voltage is pulled down relative to the switch node (Vsw) 2145 voltage, and turning off can cause the corresponding level-shift node to present a (Vboot) voltage. Since the first and second level-shift transistors 2203, 2215, respectively, are "on" only for the duration of the pulse, the power dissipation and stress level on these two devices can be less than Figure 1 A half-bridge circuit 100 is shown.

[0159] A first resistor 2207 and a second resistor 2208 may be added in series with the source of the first level-shift transistor 2203 and the second level-shift transistor 2215, respectively, to limit the gate-to-source voltage and thus the maximum current through the transistors. The first and second resistors 2207, 2208 may be less than Figure 1 The source follower resistors in the half-bridge circuit 100 shown may help make the pull-down action of the first and second level-shift transistors 2203 , 2215 faster, thereby reducing the propagation delay to the high-side transistor 2125 .

[0160] In further embodiments, the first resistor 2207 and the second resistor 2208 may each be replaced by any form of current sink. One embodiment may connect the sources of the first and second level shift transistors 2203, 2205, respectively, to a depletion mode device with a gate to source short. One embodiment of a depletion mode transistor formed with high voltage GaN technology may be to replace the enhancement mode gate stack with one of the high voltage field plate metals superimposed on the field dielectric layer. The thickness of the field dielectric and the work function of the metal may control the pinch-off voltage of the stack.

[0161] In further embodiments, the first resistor 2207 and the second resistor 2208 may be replaced by current sinks, respectively. In one embodiment, the start-up circuit 2155 (see Fig.21 ) generates a reference current (Iref). Both the depletion mode transistor implementation and the current sink implementation can result in significant die area reduction compared to the resistor option (ie, because a small depletion mode transistor is sufficient and Iref is already available).

[0162] The bootstrap transistor drive circuit 2225 can be similar to the above Figure 2 The bootstrap transistor driving circuit 225 shown in FIG. The bootstrap transistor driving circuit 2225 can receive input from the low-side driving circuit 2220 (see FIG. Fig. 22 ) and charges the bootstrap capacitor 2157 (see Fig.21 ) provides a gate drive signal referred to as (BOOTFET_DR), as discussed in more detail above.

[0163] Reference now Fig.23 , showing a first level-shift transistor 2203 and a pull-up resistor 2303 that may be located in the high-side device 2105. In some embodiments, the first level-shift transistor 2203 may be used as a pull-down transistor in a resistor pull-up inverter, similar to Figure 3 As described above, the pull-up resistor 2303 can be set in the high-side device 2105 (see Fig.21 ). The second level-shift transistor 2215 may have a similar configuration. In some embodiments, a first capacitor may exist between the first output terminal (LS_NODE) ​​2305 and the switch node (Vsw) 2145 (see Fig.21 ), and there may be a second capacitance between the first output terminal 2305 and ground, wherein the first capacitance is greater than the second capacitance. The first capacitance may be designed so that in response to a high dv / dt signal at the switch node (Vsw) 2145 (see Fig.21), allowing most of the C*dv / dt current to be conducted through the first capacitor, ensuring that the voltage at the first output terminal 2305 tracks the voltage at the switch node (Vsw). As described above, the shielding capacitor 2160 (see Fig.21 ) can be configured to function as a first capacitor. In another embodiment, shielding capacitor 2160 (see Fig.21 ) can be used for the first output terminal 2305 and the switch node (Vsw) 2145 in the half-bridge power conversion circuit 2100 (see Fig.21 ) between the first output terminal 2305 and the substrate of the semiconductor device. The shielding capacitor 2160 can also be used to minimize the capacitance between the first output terminal 2305 and the substrate of the semiconductor device. In another embodiment, the shielding capacitor 2160 can be constructed on the low-side GaN device 2103.

[0164] Reference now Fig.24 , the inverter / buffer circuit 2250 is shown in more detail. In one embodiment, the inverter / buffer circuit 2250 can have a first inverter stage 2405 and a first buffer stage 2410. In a further embodiment, the inverter / buffer circuit 2250 can be driven directly by a (PWM_HS) signal from a controller (not shown). The output of the first inverter stage 2405 can be a pass pulse generator 2260 (see Fig. 22 )'s input signal (PULSE_ON), ​​and the output of the first buffer stage 2410 can be the input signal (PULSE_OFF) of the shut-off pulse generator 2270.

[0165] In some embodiments, the UVLO circuit 2227 (see Fig. 22 ) is sent to a NAND gate disposed in the first inverter stage 2405 to generate an optional (LS_UVLO) signal. This circuit can be used to shut down the level shifting operation when (Vcc) or (Vdd_LS) is below a certain reference voltage (or a portion of a reference voltage). In another embodiment, the inverter / buffer circuit 2250 can also be a low-side transistor 2115 (see Fig.21 ) generates a shoot-through protection signal (STP_LS1) that can be applied to the low-side transistor gate drive circuit 2120. When the (PWM_HS) signal is high, this can turn off the low-side transistor gate drive circuit 2120 (see Fig.21 ) to prevent pass-through.

[0166] Reference now Fig.25, showing the conduction pulse generator 2260 in more detail. In one embodiment, the conduction pulse generator 2260 can have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520, a third inverter stage 2525, and a third buffer stage 2530. In a further embodiment, the conduction pulse generator 2260 can have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520, a third inverter stage 2525, and a third buffer stage 2530. Fig. 22 ) input (PULSE_ON signal can be first inverted and then transformed into a turn-on pulse by the RC pulse generator 2515 and the square wave generator. The result of this operation is the gate drive signal (LI_DR), which is sent to the first level shift transistor 2203 (see Fig. 22 ).

[0167] In further embodiments, the turn-on pulse generator 2260 may include one or more logic functions, such as, for example, a binary or combinational function. In one embodiment, the turn-on pulse generator 2260 may have a multi-input NOR gate for the (STP_HS) signal. The (STP_HS) signal may have the same polarity as the (LS_GATE) signal. Thus, if the (STP_HS) signal is high (corresponding to the LS_GATE signal being high), then a turn-on pulse may not be generated because Fig.25 The first inverter circuit 2505 in is pulled low, which will disable the pulse generator 2515.

[0168] In further embodiments, the RC pulse generator 2515 may include a clamping diode (not shown). The clamping diode may be added to ensure that the RC pulse generator 2515 operates at a very small duty cycle for the (PWM_LS) signal. In some embodiments, the conduction pulse generator 2260 may be configured to receive input pulses in the range of 2 nanoseconds to 20 microseconds and send pulses of substantially constant duration within this range. In one embodiment, if the voltage across the clamping diode becomes greater than (Vth), the clamping diode may turn on and short out the resistor in the RC pulse generator 2515 (providing very little capacitor discharge time). This may significantly increase the maximum operating duty cycle of the pulse generator circuit 2260 (relative to the PWM_HS signal).

[0169] Reference now Fig.26 , showing the shutdown pulse generator 2270 in more detail. In one embodiment, the shutdown pulse generator 2270 can have an RC pulse generator 2603, a first inverter stage 2605, a second inverter stage 2610, and a first buffer stage 2615. In a further embodiment, the shutdown pulse generator 2270 can receive a signal from the inverter / buffer circuit 2250 (see Fig. 22) input signal (PULSE_OFF), which can then be transmitted to the RC pulse generator 2603.

[0170] In other embodiments, the pulse from the RC pulse generator 2603 is sent through the first inverter stage 2605, the second inverter stage 2610, and the buffer stage 2615. The pulse can then be sent as the (L2_DR) signal to the second level shift transistor 2215 (see Fig. 22 ). A clamping diode may also be included in the turn-off pulse generator 2270. In some embodiments, the operating principle may be similar to that described above with respect to the turn-on pulse generator 2260 (see Fig.25 ) This working principle can ensure that the shutdown pulse generator 2270 works when the conduction time of the high-side transistor 2125 is very short (see Fig.21 ) (i.e., the circuit will operate at a relatively small duty cycle). In some embodiments, the off pulse generator 2270 can be configured to receive an input pulse in the range of 2 nanoseconds to 20 microseconds and send a pulse of substantially constant duration within the range. In further embodiments, the off level shift pulse can be shortened by the on input pulse so that the off time on the high side transistor 2125 is less than 50 nanoseconds.

[0171] In some embodiments, the RC pulse generator 2603 may include a capacitor connected to a resistor divider network. The output from the resistor may be a signal (INV) that is sent to the inverter 2275 (see Fig. 22 ), the inverter 2275 generates a shoot-through protection signal (STP_LS2) that is sent to the low-side driver circuit 2220. In further embodiments, the off pulse generator 2270 can include one or more logic functions, such as, for example, binary or combinational functions. In one embodiment, similar to the (STP_LS1) signal, the (STP_LS2) signal is sent to a NAND logic circuit within the low-side driver circuit 2220. In some embodiments, these signals can be used to ensure that the low-side transistor 2115 (see Fig.21 ) is not turned on (i.e., because the high-side transistor 2125 is turned off during the off pulse). In some embodiments, this method can be used to compensate for the turn-off propagation delay (i.e., the PULSE_OFF signal can enable shoot-through protection), thereby ensuring that the low-side transistor 2115 is turned on only after the gate of the high-side transistor 2125 is completely turned off.

[0172] In a further embodiment, a second level shift transistor 2215 may be used to level shift the blanking pulse to the high side device 2105. To achieve this, a blanking pulse may be sent to the NOR input of the first inverter stage 2605. Due to the high dv / dt condition at the switch node Vsw 2145 (see Fig. 20 ), therefore, the blanking pulse can be used to suppress false triggering. In some embodiments, the blanking pulse may not be used to filter dv / dt induced or other undesirable level-shifted output pulses.

[0173] Reference now Fig. 27 , the blanking pulse generator 2223 is shown in more detail. In one embodiment, the blanking pulse generator 2223 can be a Figure 1 A simpler design is used in the half-bridge circuit 100 shown because the square wave pulse generator is already part of the turn-off pulse generator 2270. In one embodiment, the (LS_GATE) signal is fed as an input from the low-side gate driver circuit 2220 to the blanking pulse generator 2223 (see Fig. 22 ). This signal can be inverted and then sent through the RC pulse generator to produce a positive pulse. In some embodiments, an inverted signal can be used because the pulse needs to correspond to the falling edge of the (LS_GATE) signal. Its output can be used as the blanking pulse input (B_PULSE) of the shutdown pulse generator 2270.

[0174] Reference now Fig.28 , showing the low-side transistor driver circuit 2220 in more detail. In one embodiment, the low-side transistor driver circuit 2220 can have a first inverter stage 2805, a first buffer stage 2810, a second inverter stage 2815, a second buffer stage 2820, and a third buffer stage 2825. In some embodiments, two inverter / buffer stages can be used because the input of the gate of the low-side transistor 2115 is synchronized with the (PWM_LS) signal. Therefore, in some embodiments, a (PWM_LS) high state can correspond to a (LS_GATE) high state, and vice versa.

[0175] In further embodiments, the low-side transistor driver circuit 2220 may also include an asymmetric hysteresis using a resistor divider with a transistor pull-down similar to the scheme described in 120 (see Figure 8 In one embodiment, the low-side transistor driver circuit 2220 includes multiple input NAND gates for (STP_LS1) and (STP_LS2) (shoot-through prevention on the low-side transistor 2115) signals. The (STP_LS1) and (STP_LS2) signals can ensure that when the high-side transistor 2125 is turned on, the low-side transistor driver circuit 2220 (see Fig. 22 ) is not connected to the low-side transistor 2115 (see Fig.21 ) communication. This technique can be used to avoid the possibility of shoot-through. Other embodiments may include a NAND gate for the (LS_UVLO) signal (similar to the above in Fig.28 ). One embodiment may include a turn-off delay resistor in series with the gate of the final pull-down transistor. This may be used to ensure that the bootstrap transistor is turned off before the low-side transistor 2115 is turned off.

[0176] In a further embodiment, the low-side device 2103 (see Fig.21 ) may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157, a shielding capacitor 2160 and a UVLO circuit 2227, which may be similar to the startup circuit 155, the bootstrap capacitor charging circuit 157, the shielding capacitor 160 and the UVLO circuit 227, respectively, as described above.

[0177] High-side devices

[0178] Reference now Fig.29 , shows in more detail the high-side logic and control circuit 2153 and how it interacts with the high-side transistor driver 2130. In some embodiments, the high-side logic and control circuit 2153 can be used in the same manner as above. Fig.15 In further embodiments, the high-side logic and control circuit 2153 may operate in a different manner, as discussed in more detail below.

[0179] In one embodiment, the level shift 1 receiver circuit 2910 receives the first level shift transistor 2203 (see Fig. 22 ) receives the (L_SHIFT1) signal, the first level shift transistor 2203 receives a turn-on pulse upon the transition from a low state to a high state of the (PWM_HS) signal, as described above. In response, the level shift 1 receiver circuit 2910 drives the gate of the pull-up transistor 2960 (e.g., a low voltage enhancement mode GaN transistor in some embodiments). In other embodiments, the pull-up transistor 2960 can then pull up the voltage of the state storage capacitor 2955 to a value close to (Vdd_HS) relative to the voltage of the switch node (Vsw) 2145. The voltage on the state storage capacitor 2955 can then be transferred to the high side transistor driver 2130 and to the gate of the high side transistor gate 2127 (see Fig.21) to turn on the high-side transistor 2125. In some embodiments, the state storage capacitor 2955 can be a latch storage logic circuit that is configured to change state in response to a first pulse input signal and change state in response to a second pulse input signal. In other embodiments, the state storage capacitor 2955 can be replaced by any type of latch circuit, such as but not limited to an RS flip-flop.

[0180] In further embodiments, during this time, the level shift 2 receiver circuit 2920 can maintain the pull-down transistor 2965 (e.g., a low voltage enhancement mode GaN transistor in some embodiments) in an off state. This can cut off any discharge path for the state storage capacitor 2955. Thus, in some embodiments, the state storage capacitor 2955 can have a relatively small charging time constant and a relatively large discharging time constant.

[0181] Similarly, the level shift 2 receiver 2920 can receive the second level shift transistor 2215 (see Fig. 22 ) receives the (L_SHIFT2) signal, the second level shift transistor 2215 receives the off pulse when the (PWM_HS) signal transitions from a high state to a low state, as discussed above. In response, the level shift 2 receiver circuit 2920 drives the gate of the pull-down transistor 2965 (e.g., a low voltage enhancement mode GaN transistor in some embodiments). In further embodiments, the pull-down transistor 2965 can then pull down (i.e., discharge) the voltage of the state storage capacitor 2955 to a value close to the switch node (Vsw) 2145, which can result in the high side transistor 2125 being turned off by the high side transistor driver 2130.

[0182] Continue to refer Fig.29 , a first shielding capacitor 2970 and a second shielding capacitor 2975 may be connected from the (L_SHIFT1) and (L_SHIFT2) nodes, respectively, to help prevent the switching node (Vsw) 2145 (see Fig.21 ) during high dv / dt conditions at ). In a further embodiment, the (L_SHIFT1) and (L_SHIFT2) nodes are connected to the switch node (Vsw) 2145 (see Fig.21 ) can also be clamped between the switch node (Vsw) 2145 (see Fig.21 ) and the potential difference between the (L_SHIFT1) and (L_SHIFT2) nodes will not exceed (Vth). This can be used to provide a voltage for the high-side transistor 2125 (see Fig.21 ) produces relatively fast turn-on and turn-off.

[0183] Reference now Fig.30, the level shift 1 receiver 2910 is shown in more detail. In one embodiment, the level shift 1 receiver 2910 may include a lower level shifter 3005, a first inverter 3010, a second inverter 3015, a first buffer 3020, a third inverter 3025, a second buffer 3030, and a third buffer 3135. In some embodiments, the level shift 1 receiver 2910 shifts (modulates) the (L_SHIFT1) signal down by a voltage of 3×Vth (e.g., using three enhancement mode transistors, each of which may have a gate to source voltage close to Vth). In other embodiments, fewer or more lower shift transistors may be used.

[0184] In further embodiments, the final source follower transistor can have a three diode connected transistor clamp across its gate to its source. In some embodiments, this configuration can be used because its source voltage can only be as high as (Vdd_HS) (i.e., since its drain is connected to Vdd_HS), while its gate voltage can be as high as V(L_SHIFT1)–2*Vth. Therefore, in some embodiments, the maximum gate-to-source voltage on the final source follower transistor can be greater than the maximum rated gate-to-source voltage in this technology.

[0185] In further embodiments, the first inverter 3010 may also have a NOR gate for the high side undervoltage lockout output using the (UV_LS1) signal generated by the high side UVLO circuit 2915. In one embodiment, the output of the level shift 1 receiver 2910 (see Fig.29 ) may be a (PU_FET) signal which is transmitted to the pull-up transistor 2960 (see Fig.29 ) gate. The voltage of this signal can vary from 0 volts in the low state to (Vdd_HS)+(Vdd_HS-Vth) in the high state. This voltage can maintain the on state for the duration of the on pulse.

[0186] Reference now Fig.31 , showing the level shift 2 receiver 2920 in more detail. In one embodiment, the level shift 2 receiver 2920 can be similar to the level shift 1 receiver 2910 discussed above. In other embodiments, the level shift 2 receiver 2920 can include a blanking pulse generator 3105, a lower level shifter 3110, a first inverter 3115, a second inverter 3120, a first buffer 3125, a third inverter 3130, a second buffer 3135, and a third buffer 3140. In one embodiment, the blanking pulse generator 3105 can be used in addition to the 3*Vth lower level shifter 3110 and multiple inverter / buffer stages.

[0187] In other embodiments, different configurations may be used. In some embodiments, when high level transistor 2125 (see Fig.21 ) turns off and blanks transistor 2940 (see Fig.29 ) drive to obtain better dv / dt immunity, this particular configuration may be useful when the level shift 2 receiver 2920 is doubled. In some embodiments, the blanking pulse generator 3105 may be used with Fig.17 1520 is the same as the level shift 2 receiver 1520 shown in FIG. In one embodiment, the level shift 2 receiver 2920 (see Fig.29 ) can receive the (L_SHIFT2) and (UV_LS2) signals and, in response, send a (PD_FET) signal to pull down transistor 2965. In further embodiments, the first inverter 3115 can have a bias for the high side UVLO circuit 2915 (see Fig.29 )'s (UV_LS2) signal's two input NAND gate.

[0188] Reference now Fig.32 , showing the high side UVLO circuit 2915 in more detail. In one embodiment, the high side UVLO circuit 2915 can include a lower level shifter 3205 and a resistor pull-up inverter stage 3210. In some embodiments, the high side UVLO circuit 2915 can be configured to shut down the high side transistor 2125 (see FIG. 21B ) when the voltage of the bootstrap capacitor 2110 drops below a certain threshold. Fig.21 ) to prevent circuit failure. In one example embodiment, the high-side UVLO circuit 2915 is designed to engage when (Vboot) decreases to a value less than 4*Vth below the voltage of the switch node (Vsw) 2145. In another embodiment, the output of the lower level shifter 3205 can be the (UV_LS2) signal sent to the second level shift receiver 2920, and the output of the resistive pull-up inverter stage 3210 can be the (UV_LS1) signal sent to the first level shift receiver 2910.

[0189] As discussed below, in some embodiments, the high-side UVLO circuit 2915 can be used with the above respectively Fig.14 and Fig.18 1415 for the half-bridge circuit 100 discussed in . In one embodiment, the (Vboot) signal can be shifted down by 3*Vth and passed to the resistor pull-up inverter stage 3210. In a further embodiment, due to the level shift 2 receiver circuit 2920 (see Fig.29 ) based on the high-side transistor 2125 (see Fig.21) controls the shutdown process, applying the 3*Vth down-shifted output directly to the NAND gate at the input of the level shift 2 receiver circuit 2920 will engage the undervoltage lockout output.

[0190] However, in some embodiments, since the bootstrap voltage may be too low, this may also keep the pull-up transistor 2960 (see Fig.29 ) is turned on. In some embodiments, this may cause a conflict. When the level shift 2 receiver circuit 2920 (see Fig.29 ) attempts to keep the high-side transistor 2125 (see Fig.21 ) is off, the level shift 1 receiver circuit 2910 may attempt to turn on the high side transistor. To avoid this, some embodiments may switch the high side UVLO circuit 2915 (see Fig.29 ) and sends it to the NOR input on the level shift 1 receiver circuit 2910. This ensures that the level shift 1 receiver circuit 2910 does not interfere with the shutdown process caused by UVLO.

[0191] Reference now Fig.33 , showing the high side transistor driver 2130 in more detail. In one embodiment, the high side transistor driver 2130 may include a first inverter 3305, a first buffer 3310, a second inverter 3315, a second buffer 3320, and a third buffer 3325. In some embodiments, the high side transistor driver 2130 may be a first inverter 3305, a first buffer 3310, a second inverter 3315, a second buffer 3320, and a third buffer 3325. Figure 1 A more basic design of the high-side transistor driver 130 is used in the half-bridge circuit 100 shown. In one embodiment, the high-side transistor driver 2130 is fed from the state storage capacitor 2955 (see Fig.29 ) receives the (S_CAP) signal and transmits the corresponding drive (HS_GATE) signal to the high-side transistor 2125 (see Fig.21 ). More specifically, when the (S_CAP) signal is in a high state, the (HS_GATE) signal is in a high state, and vice versa.

[0192] Half-bridge Circuit #2 Operation

[0193] The following operation sequence of the half-bridge circuit 2100 (see Fig.21 ) are merely examples, and other sequences may be used without departing from the present invention. Fig.21 , Fig. 22 and Fig.29 .

[0194] In one embodiment, when the (PWM_LS) signal is in a high state, the low-side logic, control and level shift circuit 2150 can send a high signal to the low-side transistor driver 2120, which then transmits the signal to the low-side transistor 2115 to turn it on. This can set the voltage of the switch node (Vsw) 2145 to nearly 0 volts. In a further embodiment, when the low-side transistor 2115 is turned on, it can provide a path for charging the bootstrap capacitor 2110. The charging path can have a parallel combination of a high-voltage bootstrap diode and a transistor.

[0195] In some embodiments, the bootstrap transistor driver circuit 2225 can provide a drive signal (BOOTFET_DR) to the bootstrap transistor, which provides a low resistance path for charging the bootstrap capacitor 2110. In one embodiment, the bootstrap diode can ensure that there is a path for charging the bootstrap capacitor 2110 during startup when there is no low-side gate drive signal (LS_GATE). During this period of time, the (PWM_HS) signal should be in a low state. If the (PWM_HS) signal is turned on unintentionally during this time, the (STP_HS) signal generated from the low-side driver circuit 2220 can prevent the high-side transistor 2125 from turning on. If the (PWM_LS) signal is turned on while the (PWM_HS) signal is turned on, the (STP_LS1) and (STP_LS2) signals generated by the inverter / buffer 2250 and the inverter 2275, respectively, will prevent the low-side transistor 2115 from turning on. Additionally, in some embodiments, when (Vcc) or (Vdd_LS) is below a predetermined voltage level, the (LS_UVLO) signal can prevent the low-side gate 2117 and the high-side gate 2127 from turning on.

[0196] Conversely, in some embodiments, when the (PWM_LS) signal is in a low state, the (LS_GATE) signal to the low-side transistor 2115 may also be in a low state. In some embodiments, during the dead time between the (PWM_LS) low signal and the (PWM_HS) high signal transition, depending on the direction of power flow, the inductive load may force the high-side transistor 2125 or the low-side transistor 2115 to conduct in synchronous rectifier mode. If the high-side transistor 2125 is turned on during the dead time (e.g., in boost mode), the voltage of the switch node (Vsw) 2145 may rise to close to (V+) 2135 (i.e., the mains voltage). The dv / dt condition on the switch node (Vsw) 2145 may tend to pull the (L_SHIFT1) node to a low state relative to the switch node (i.e., due to capacitive coupling to ground), which may turn on the high-side transistor driver 2130, thereby causing the high-side transistor 2125 to conduct unexpectedly. This situation may offset the dead time, resulting in a direct pass.

[0197] In some embodiments, this condition can be prevented by using the blanking pulse generator 2223 to sense the turn-off transient of the low-side transistor 2115 and send a pulse to turn on the second level-shift transistor 2205. This can pull the (L_SHIFT2) signal to a low state, which can then communicate with the level-shift 2 receiver circuit 2920 to generate a blanking pulse to drive the blanking transistor 2940. In one embodiment, the blanking transistor 2940 can act as a pull-up to prevent the (L_SHIFT1) signal from going to a low state relative to the switch node (Vsw) 2145.

[0198] In a further embodiment, after the dead time of the (PWM_HS) signal transitioning from a low state to a high state, the on-pulse generator 2260 may generate an on-pulse. This may pull the (L_SHIFT1) node voltage down for a short period of time. In another embodiment, the signal may be inverted by the level shift 1 receiver circuit 2910, and a short high signal may be sent to the pull-up transistor 2960, which charges the state storage capacitor 2955 to a high state. This may result in a corresponding high signal at the input of the high-side transistor driver 2130, which may turn on the high-side transistor 2125. The voltage of the switch node (Vsw) 2145 may remain close to (V+) 2135 (i.e., the mains voltage). Since there is no discharge path, the voltage of the state storage capacitor 2955 may remain in a high state during this time.

[0199] In yet other embodiments, during the on pulse, the bootstrap capacitor 2110 may be discharged through the first level-shift transistor 2203. However, since the time period is relatively short, the bootstrap capacitor 2110 may not be as effective as when the first level-shift transistor 2203 is on for the entire duration of the (PWM_HS) signal (e.g., Figure 1 More specifically, in some embodiments, this may result in a switching frequency at which the UVLO engages that is greater than Figure 1 The switching frequency in the half-bridge circuit 100 is a relatively low value.

[0200] In some embodiments, when the (PWM_HS) signal transitions from a high state to a low state, the shutdown pulse generator 2270 can generate a shutdown pulse. This can pull the (L_SHIFT2) node voltage down for a short period of time. The signal can be inverted by the level shift 2 receiver circuit 2920, and a short high state signal can be sent to pull down the transistor 2965, which will discharge the state storage capacitor 2955 to a low level. This will result in a low signal at the input of the high-side transistor driver 2130, which will turn off the high-side transistor 2125. In further embodiments, the voltage of the state storage capacitor 2955 can remain in a low state during this time because it has no discharge path.

[0201] In one embodiment, since the turn-off process in circuit 2100 does not involve charging the level-shift node capacitor through a high-value pull-up resistor, the turn-off time can be shorter than Figure 1 The turn-off time in the half-bridge circuit 100 is relatively short. In further embodiments, the turn-on and turn-off processes of the high-side transistor 2125 can be controlled by the conduction of substantially similar level-shift transistors 2203, 2205, so the turn-on and turn-off propagation delays can be substantially similar. This can result in no need for Figure 1 Implementation of a pull-up trigger circuit and / or a pull-up transistor used in the half-bridge circuit 100.

[0202] ESD Circuit

[0203] Reference now Fig.34 In some embodiments, one or more pins (i.e., connections from semiconductor devices within an electronic package to external terminals on the electronic package) may employ an electrostatic discharge (ESD) clamp circuit to protect the circuit. The following embodiments illustrate ESD clamp circuits that may be used on one or more pins in one or more embodiments disclosed herein, as well as other embodiments where ESD protection may be desired. In further embodiments, the ESD clamp circuits disclosed herein may be used on GaN-based devices.

[0204] One embodiment of an electrostatic discharge (ESD) clamp circuit 3400 is shown. The ESD clamp circuit 3400 can have a configuration that employs one or more source follower stages 3405 made of enhancement mode transistors. Each source follower stage 3405 can have a gate 3406 connected to a source 3407 of an adjacent source follower stage. Fig.34 In the embodiment shown, four source follower stages 3405 are employed, but in other embodiments, fewer or more may be used. Resistor 3410 is coupled to source 3407 of source follower stage 3405 .

[0205] The ESD transistor 3415 is coupled to one or more source follower stages 3405 and can be configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse, as described below. A resistor 3410 is disposed between the source 3420 of the ESD transistor 3415 and each source 3407 of the source follower stage 3405. The drain 3408 of the source follower stage 3405 is connected to the drain 3425 of the ESD transistor 3415. The source 3407 of the last source follower stage is coupled to the gate 3430 of the ESD transistor 3415.

[0206] In one embodiment, the turn-on voltage of the ESD clamp circuit 3400 can be set by the total number of source follower stages 3405. However, because the last source follower stage is a transistor with a drain 3408 to source 3407 voltage and a gate 3406 to source voltage, the current flowing through the final resistor 3410 is relatively large and may result in a large gate 3430 to source 3420 voltage across the ESD transistor 3415. This may result in a relatively large capacity for ESD current and, in some embodiments, improved leakage performance compared to other ESD circuit configurations.

[0207] In other embodiments, the ESD clamp circuit 3400 can have multiple degrees of freedom with respect to transistor size and resistor values. In some embodiments, the ESD clamp circuit 3400 can be smaller than other ESD circuit configurations. In other embodiments, the performance of the ESD clamp circuit 3400 can be improved by gradually increasing the size of the source follower stage 3405 as the source follower stage 3405 gets closer to the ESD transistor 3415. In other embodiments, the resistor 3410 can be replaced by a depletion mode transistor, a reference current sink, or a reference current source.

[0208] Reference now Fig.35 Shows something like Fig.34 , but the ESD clamp circuit 3500 can have resistors in different configurations, as discussed in more detail below. The ESD clamp circuit 3500 can have a configuration that employs one or more source follower stages 3505 made of one or more enhancement mode transistors. Each source follower stage 3505 can have a gate 3506 connected to a source 3507 of an adjacent source follower stage. Fig.35In the embodiment shown, four source follower stages 3505 are used, but in other embodiments, fewer or more can be used. Resistors 3510 are coupled between sources 3507 of adjacent source follower stages 3505. ESD transistors 3515 are coupled to the source follower stages 3505, wherein the resistors 3510 are disposed between the sources 3520 of the ESD transistors 3515 and the sources 3507 of the source follower stages 3505. The drains 3508 of the source follower stages 3505 can be coupled together and coupled to the drain 3525 of the ESD transistors 3515.

[0209] Electronic Packaging

[0210] Reference now Fig.36 and Fig.37 In some embodiments, one or more semiconductor devices may be provided in one or more electronic packages. Countless packaging configurations and types of electronic packages are available and are within the scope of the present disclosure. Fig.36 One embodiment of a so-called quad no-lead electronic package having two semiconductor devices therein is shown.

[0211] Electronic package 3600 may have a package base 3610 having one or more die pads 3615 surrounded by one or more terminals 3620. In some embodiments, package base 3610 may include a lead frame, while in other embodiments it may include an organic printed circuit board, a ceramic circuit, or other materials.

[0212] exist Fig.36 In the embodiment shown, the first device 3620 is mounted to the first die pad 3615 and the second device 3625 is mounted to the second die pad 3627. In another embodiment, one or more of the first device 3620 and the second device 3625 can be mounted on an insulator (not shown) respectively, which is mounted to the package base 3610. In one embodiment, the insulator can be a ceramic or other non-conductive material. The first and second devices 3620, 3625 are electrically coupled to the terminal 3640 by wire bonding 3630 or any other type of electrical interconnection (for example, a flip chip bump or column that can be used in a flip chip application). The wire bonding 3630 can extend between the device bonding pads 3635 to the terminal 3640, and in some cases, to the die pads 3615, 3627, and in other cases, to the device bonding pads 3635 on the adjacent device.

[0213] Reference now Fig.37, an isometric view of an electronic package 3600 is shown. Terminals 3640 and die attach pads 3615 and 3627 may be arranged on an outer surface and configured to be attached to a printed circuit board or other device. In other embodiments, terminals 3640 and die attach pads 3615 and 3627 may be accessible only within the interior of electronic package 3600, and other connections may be provided on the exterior of the electronic package. More specifically, some embodiments may have internal electrical wiring, and there may not be a one-to-one correlation between internal and external connections.

[0214] In further embodiments, the corresponding first device 3620 and the second device 3625 (see Fig.36 ) and the top surface of the package base 3610 can be encapsulated by a non-conductive material such as a molding compound. A variety of other electronic packages can be used, such as but not limited to SOIC, DIPS, MCM, etc. In addition, in some embodiments, each device can be in a separate electronic package, while other embodiments can have two or more electronic devices in a single package. Other embodiments can have one or more passive devices in one or more electronic packages.

[0215] Alternative bootstrap voltage generation

[0216] Fig.38 3800 is a schematic diagram of an alternative embodiment of a bootstrap capacitor charging circuit 3800. The bootstrap capacitor charging circuit 3800 has similar or identical features to the other bootstrap capacitor charging circuits discussed herein. The bootstrap capacitor charging circuit 3800 includes a transistor 3800 and does not include a parallel connected diode, such as Fig.12 157 of the bootstrap capacitor charging circuit 157 shown in FIG. 15 . In at least some embodiments, transistor 1205 does not have a parasitic diode between its source and drain, such as a parasitic body diode in a conventional transistor formed in a silicon substrate. In some embodiments, the (BOOTFET_DR) signal can be generated by one of the bootstrap transistor drive circuits discussed below. The bootstrap transistor 3800 can be connected to Figure 1 The low side transistors 115 are shown turned on substantially simultaneously. In various embodiments, the bootstrap transistor 3800 can be an enhancement mode (emode) device or a depletion mode (dmode) device.

[0217] Fig.39is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 3900 connected to a bootstrap transistor 3970 and indirectly connected to a bootstrap capacitor 3980. The bootstrap transistor 3970 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 3980 can be similar or identical to other bootstrap capacitors discussed herein.

[0218] The bootstrap transistor drive circuit 3900 includes logic circuits 3910, 3914 and 3916, a VH generator circuit 3920, an HGATE generator circuit 3930, an LGATE generator circuit 3940, an H switch 3950, an optional parallel resistor 3955, an optional pull-up resistor 3957, an optional diode 3959 and an L switch 3960.

[0219] Logic circuit 3910 receives control signals at nodes SIGNAL_A and LS_GATE. The control signals at nodes SIGNAL_A and LS_GATE can be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous version and an inverted version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_A can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_A is opposite to the polarity of the control signal at the node LS_GATE, such as Fig.40 , and will be discussed in further detail below.

[0220] Logic circuit 3910 receives control signals at nodes SIGNAL_A and LS_GATE and generates a first signal at node I.

[0221] VH generator circuit 3920 receives the signal at node I and the signal at node LGATE generated by LGATE generator circuit 3940, as described below. VH generator circuit 3920 generates a signal at node H based on control signals at nodes SIGNAL_A and LS_GATE.

[0222] Logic circuit 3914 receives the control signal at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVDD.

[0223] HGATE generator circuit 3930 receives a signal at node I and a signal at node IBVDD and generates a signal at node HGATE based on the received signals.

[0224] Logic circuit 3916 receives the control signals at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVCCB.

[0225] LGATE generator circuit 3940 receives a signal at node I and a signal at node IBVCCB and generates a signal at node LGATE based on the received signals.

[0226] The H switch 3950 and the L switch 3960 cooperatively generate a signal at the node BOOTFET_DR based on the voltage at the signal node H and the power supply node VCC, and additionally based on the signals at the nodes HGATE and LGATE.

[0227] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 3970. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 3970 conducts when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 3970 is not conductive while the voltage at the node VSW is high or transitions between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0228] In some embodiments, the bootstrap transistor driver circuit 3900 includes an optional resistive element 3955 connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0229] In some embodiments, the bootstrap transistor driver circuit 3900 includes an optional resistive element 3957, which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0230] In some embodiments, the bootstrap transistor driver circuit 3900 includes an optional diode 3959 connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode 3959 includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the diode 3959.

[0231] Fig.40 39 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 3900.

[0232] refer to Fig.39 and 40 , as shown, the control signal at node LS_GATE is a delayed and inverted version of the control signal at node SIGNAL_A, where the delay Fig.40 Indicated by D in the middle.

[0233] Logic circuit 3910 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logic inversion OR (INV OR) function.

[0234] VH generator circuit 3920 receives the signal at node I and the signal at node LGATE generated by LGATE generator circuit 3940, as described below. Based on the control signals at nodes I and LGATE, VH generator circuit 3920 generates a signal at node H, where the signal at node H is an inverted and level-shifted version of the signals at nodes I and LGATE, as shown in FIG. Fig.40 An example of an implementation of the VH generator circuit 3920 is provided below with reference to Fig.41 and Fig.42 Have a discussion.

[0235] Logic circuit 3914 receives the control signals at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVDD.

[0236] HGATE generator circuit 3930 receives the signal at node I and the signal at node IBVDD, and generates a signal at node HGATE based on the received signals. Fig.40 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at nodes I and IBVDD. Fig.43 and Fig.44 Examples of implementations of HGATE generator circuit 3930 are discussed.

[0237] Logic circuit 3916 receives the control signals at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVCCB.

[0238] LGATE generator circuit 3940 receives the signal at node I and the signal at node IBVCCB and generates a signal at node LGATE based on the received signals, wherein the signal at node LGATE is a level-shifted version of the signal at node I, such as Fig.40 As shown below. Fig.45 and Fig.46 Examples of implementations of LGATE generator circuit 3930 are discussed.

[0239] H switch 3950 and L switch 3960 cooperate to generate a signal on node BOOTFET_DR based on the voltage at signal node H and power node VCC, and also based on the signals at nodes HGATE and LGATE. The signals at nodes HGATE and LGATE are non-overlapping high time signals, so H switch 3950 and L switch 3960 are never conductive at the same time. Fig.40 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node H. When the signal at the node HGATE is high, the voltage at the power supply node H is VCC+VDD.

[0240] Due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the H switch 3950 is conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at the node VSW is low. Fig.40 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 3970 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 3970, the bootstrap transistor BOOTFET 3970 is conductive, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0241] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the L switch 3960 can be conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high or transitions between high and low or between low and high. Fig.40 As shown, when the voltage at node VSW is high, bootstrap transistor BOOTFET 3970 is non-conductive and the voltage at node Vboot is equal to or substantially equal to the voltage at power supply node VCC plus the voltage swing of node VSW.

[0242] Fig.41 is a schematic diagram of a VH generator circuit 4100, which can be used as Fig.39 VH generator circuit 3920.

[0243] Fig.42 is a timing diagram showing the timing relationship between various signals of the VH generator circuit 4100.

[0244] refer to Fig.41 and 42 As shown in the figure, the VH generator circuit 4100 receives the signal at the node I through the inverter 4110, and inverts the signal at the node I to generate a signal at the node N. In addition, the VH generator circuit 4100 receives the signal at the node LGATE through the transistor 4120. Fig.42 As shown in , when the voltage at the node N is the ground voltage and the voltage at the node LGATE is high, the transistor 4120 charges the capacitor 4130 and makes the voltage at the output OUT equal to or substantially equal to the voltage at the power supply VCC. In addition, in response to the voltage at the node N increasing to the voltage of the power supply VDD and the voltage at the node LGATE being low, the voltage increase of the voltage at the node N is capacitively coupled to the output node OUT, so that when the voltage at the node N is high, the voltage at the output OUT is equal to or substantially equal to the voltage at the power supply VCC plus the voltage of the power supply VDD.

[0245] Fig.43 Can be used as Fig.39 Schematic diagram of HGATE generator circuit 4300 of HGATE generator circuit 3930. HGATE generator circuit 4300 includes switches 4310 and 4320, switch 4330, capacitor 4340, resistor 4350, and switch 4360.

[0246] Fig.44 is a timing diagram showing the timing relationship between various signals of the HGATE generator circuit 4300.

[0247] refer to Fig.43 As shown, the HGATE generator circuit 4300 receives signals at nodes I, IBVDD, and BOOTFET_DR, and generates a signal at output OUT based on the received signals, wherein the signal at output OUT is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.44 as shown in .

[0248] The signal at node I is received at each of switches 4310 and 4320. When the signal at node I is high, switch 4310 is conductive, which causes the voltage at node N2 to be low. In addition, when the signal at node I is high, switch 4320 is conductive, which causes the voltage at N1 to be low. In addition, when the signal at node IBVDD is high, switch 4360 charges capacitor 4340 so that the voltage at output OUT becomes equal to or substantially equal to the voltage of power supply VDD.

[0249] When the signal at node I is low, switches 4310 and 4320 cannot conduct. Therefore, node N2 is charged to or toward the voltage on power supply VDD through resistor 4350, causing switch 4330 to become conductive and charge node N1 to the voltage at node BOOTFET_DR. The voltage increase from 0 to the voltage on node BOOTFET_DR is capacitively coupled to output node OUT, so in response to the signal at node I going low, the voltage at output OUT is equal to or substantially equal to the voltage at node BOOTFET_DR (VCC+VDD) plus the voltage of power supply VDD, as shown in FIG. Fig.44 shown.

[0250] Fig.45 Can be used as Fig.39 Schematic diagram of LGATE generator circuit 4500 of LGATE generator circuit 3940. LGATE generator circuit 4500 includes capacitor 4510 and switch 4520.

[0251] Fig.46 is a timing diagram showing the timing relationship between various signals of LGATE generator circuit 4500.

[0252] refer to Fig.45 As shown, the LGATE generator circuit 4500 receives signals at nodes I and IBVCCB and generates a signal at output OUT based on the received signals, wherein the signal at output OUT is a level-shifted version of the signal at node I, as shown in FIG. Fig.46 shown.

[0253] When the signal at node I is low and the signal at node IBVCCB is high, switch 4520 charges output node OUT to or toward the voltage of power supply VCC. When the signal at node IBVCCB is low and as node I transitions to a high level, the voltage increase from 0 to the voltage of power supply VDD is capacitively coupled to output node OUT, and thus, in response to the signal at node I becoming high, the voltage at output OUT is equal to or substantially equal to the voltage at power supply VCC plus the voltage of power supply VDD.

[0254] Fig.47 47 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 4700 connected to a bootstrap transistor BOOTFET 4770 and indirectly connected to a bootstrap capacitor 4780. The bootstrap transistor 4770 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 4780 can be similar or identical to other bootstrap capacitors discussed herein.

[0255] The bootstrap transistor driving circuit 4700 includes logic circuits 4710 , 4714 and 4716 , an inverter 4720 , an HGATE generator circuit 4730 , an LGATE generator circuit 4740 , an H switch 4750 and an L switch 4760 .

[0256] Logic circuit 4710 receives control signals at nodes SIGNAL_B and LS_GATE. The control signals at nodes SIGNAL_B and LS_GATE can be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and non-inverting version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_B can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_B is the same as the polarity of the control signal at the node LS_GATE, such as Fig.48 As shown, it will be discussed in further detail below.

[0257] Logic circuit 4710 receives control signals at nodes SIGNAL_B and LS_GATE and generates a signal at node I.

[0258] Inverter 4720 receives the signal at node I and produces an inverted and level-shifted version of the received signal at node H.

[0259] The logic circuit 4714 receives the control signals at the nodes SIGNAL_A and LS_GATE and generates a second signal at the node IBVDD.

[0260] The HGATE generator circuit 4730 receives a signal at the node I and a signal at the node IBVDD, and generates a signal at the node HGATE based on the received signals.

[0261] Logic circuit 4716 receives control signals at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVCCB.

[0262] LGATE generator circuit 4740 receives a signal at node I and a signal at node IBVCCB and generates a signal at node LGATE based on the received signals.

[0263] The H switch 4750 and the L switch 4760 cooperatively generate a signal on the node BOOTFET_DR based on the voltage at the signal node H and the power supply node VCC, and additionally based on the signals at the nodes HGATE and LGATE.

[0264] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 4770. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 4770 conducts when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 4770 is not conducting while the voltage at the node VSW is high or transitioning between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0265] In some embodiments, the bootstrap transistor drive circuit 4700 includes an optional resistive element connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0266] In some embodiments, the bootstrap transistor driver circuit 4700 includes an optional resistive element, which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0267] In some embodiments, the bootstrap transistor driver circuit 4700 includes an optional diode connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the optional diode.

[0268] Fig.48is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 4700.

[0269] refer to Fig.47 and 48 , as shown, the control signal at node LS_GATE is a delayed and non-inverted version of the control signal at node SIGNAL_B, where the delay Fig.48 Indicated by D in the middle.

[0270] Logic circuit 4710 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logical INV OR function.

[0271] Inverter 4720 receives the signal at node I and generates a signal at node H, where the signal at node H is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.48 shown.

[0272] The logic circuit 4714 receives the control signals at the nodes SIGNAL_A and LS_GATE and generates a second signal at the node IBVDD.

[0273] HGATE generator circuit 4730 receives the signal at node I and the signal at node IBVDD, and generates a signal at node HGATE based on the received signals. Fig.48 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at nodes I and IBVDD. Figures 49 to 50 An example of an implementation of the HGATE generator circuit 4730 is discussed.

[0274] Logic circuit 4716 receives control signals at nodes SIGNAL_A and LS_GATE and generates a second signal at node IBVCCB.

[0275] LGATE generator circuit 4740 receives the signal at node I and the signal at node IBVCCB, and generates a signal at node LGATE based on the received signals, wherein the signal at node LGATE is a level-shifted version of the signal at node I, such as Fig.48 As shown above. Figure 45 to Figure 46 Examples of implementations of LGATE generator circuit 4730 are discussed.

[0276] H switch 4750 and L switch 4760 cooperate to generate a signal on node BOOTFET_DR based on the voltage at signal node H and power node VCC, and also based on the signals at nodes HGATE and LGATE. The signals at nodes HGATE and LGATE are non-overlapping high time signals, so H switch 4750 and L switch 4760 are never conductive at the same time. Fig.48 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node H, which is VCC+VDD when the signal at the node HGATE is high.

[0277] Due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the H switch 4750 is conductive and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at the node VSW is low. Fig.48 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 4770 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 4770. The bootstrap transistor BOOTFET 4770 is conductive, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0278] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the L switch 4760 can be conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high or transitions between high and low or between low and high. Fig.48 As shown, when the voltage at the node VSW is high, the bootstrap transistor BOOTFET 4770 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0279] Fig.49 Can be used as Fig.47 Schematic diagram of HGATE generator circuit 4900 of HGATE generator circuit 4730. HGATE generator circuit 4900 includes inverter 4910, pass switch 4920, parallel resistor 4930, pull-down switches 4940 and 4950, pull-up switch 4960, capacitor 4970, and resistor 4980.

[0280] Fig.50 is a timing diagram showing the timing relationship between various signals of the HGATE generator circuit 4900.

[0281] refer to Fig.49 , HGATE generator circuit 4900 receives signals at nodes I, IBVDD and H, and generates a signal at output HGATE based on the received signals, wherein the signal at output HGATE is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.50 as shown in .

[0282] The signal at node I is received at inverter 4910 and at each of switches 4940 and 4950. In addition, the signal at node H is received at pass switch 4920, and the signal at node IBVDD is received at the gate of pull-up switch 4960.

[0283] When the signal at node I is high, the signal at node H is low, and the signal at node IBVDD is high, the pass switch 4920 cannot conduct, switches 4940 and 4950 can conduct, and the pull-up switch 4960 can conduct. Fig.50 As shown, the voltages at the node N1 and the output HGATE are low, and the voltage at the node N2 is substantially equal to the voltage at the power supply VDD.

[0284] In addition, when the signal at node I is low, the signal at node H is high, the signal at node IBVDD is low, the switch 4920 can conduct, the switches 4940 and 4950 cannot conduct, and the pull-up switch 4960 cannot conduct. Therefore, the voltage at node N1 is equal to the voltage at node H (VCC+VDD), the voltage at node N2 is substantially equal to the voltage at node H (VCC+VDD) plus the voltage at the power supply VDD, that is, VCC+2VDD, and the voltage at the output node HGATE is also equal to or substantially equal to VCC+2VDD, as shown in FIG. Fig.50 as shown in .

[0285] Fig.51 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 5100 connected to a bootstrap transistor 5170 and indirectly connected to a bootstrap capacitor 5180. The bootstrap transistor 5170 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 5180 can be similar or identical to other bootstrap capacitors discussed herein.

[0286] The bootstrap transistor driving circuit 5100 includes a logic circuit 5110, a VH generator circuit 5120, an HGATE generator circuit 5130, an LGATE generator circuit 5140, an H switch 5150, an optional parallel resistor 5155, an optional pull-up resistor 5157, an optional diode 5159 and an L switch 5160.

[0287] The logic circuit 5110 receives control signals at the nodes SIGNAL_A and LS_GATE. The control signals at the nodes SIGNAL_A and LS_GATE may be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and inverted version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_A can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_A is opposite to the polarity of the control signal at the node LS_GATE, such as Fig.52 As shown, it will be discussed in further detail below.

[0288] The logic circuit 5110 receives the control signals at the nodes SIGNAL_A and LS_GATE and generates a first signal at the node I.

[0289] The VH generator circuit 5120 receives a signal at node I, and based on the received signal, the VH generator circuit 5120 generates a signal at node H.

[0290] The HGATE generator circuit 5130 receives a signal at node I and generates a signal at node HGATE based on the received signal.

[0291] LGATE generator circuit 5140 receives the signal at node I and generates a signal at node LGATE based on the received signal.

[0292] The H switch 5150 and the L switch 5160 cooperatively generate a signal at the node BOOTFET_DR based on the voltage at the signal node H and the power supply node VCC, and additionally based on the signals at the nodes HGATE and LGATE.

[0293] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 5170. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 5170 is conductive when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 5170 is not conductive while the voltage at the node VSW is high or transitions between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0294] In some embodiments, the bootstrap transistor driver circuit 5100 includes an optional resistive element 5155 connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0295] In some embodiments, the bootstrap transistor driver circuit 5100 includes an optional resistive element 5157 , which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0296] In some embodiments, the bootstrap transistor driver circuit 5100 includes an optional diode 5159 connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode 5159 includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the diode 5159.

[0297] Fig.52 51 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 5100.

[0298] refer to Fig.51 and 52 , the control signal at node LS_GATE is a delayed and inverted version of the control signal at node SIGNAL_A, where the delay Fig.52 Indicated by D in the middle.

[0299] Logic circuit 5110 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logic INV OR function.

[0300] The VH generator circuit 5120 receives the signal at node I and generates a signal at node H, wherein the signal at node H is an inverted and level-shifted version of the signal at node I, such as Fig.52 As shown in the following. Fig.53 and Fig.54 Examples of implementations of the VH generator circuit 5120 are discussed.

[0301] HGATE generator circuit 5130 receives the signal at node I and generates a signal at node HGATE based on the received signal. Fig.52 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at nodes I and IBVDD. Fig.55 and Fig.56 An example of an implementation of the HGATE generator circuit 5130 is discussed.

[0302] The LGATE generator circuit 5140 receives the signal at the node I and generates a signal at the node LGATE based on the received signal, wherein the signal at the node LGATE is a level-shifted version of the signal at the node I, such as Fig.52 As shown below. Fig.45 and Fig.46 Examples of implementations of LGATE generator circuit 5130 are discussed.

[0303] H switch 5150 and L switch 5160 cooperate to generate a signal at node BOOTFET_DR based on the voltage at signal node H and power node VCC, and also based on the signals at nodes HGATE and LGATE. The signals at nodes HGATE and LGATE are non-overlapping high time signals, so H switch 5150 and L switch 5160 are never conductive at the same time. Fig.52 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is at a high level, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node H, and when the signal at the node HGATE is high, the voltage is VCC+VDD.

[0304] Due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the H switch 5150 is conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at the node VSW is low. Fig.52As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 5170 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 5170, the bootstrap transistor BOOTFET 5170 is conductive, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0305] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE and the voltage swing at the switch node VSW, the L switch 5160 is conductive and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high or transitions between high and low or between low and high. Fig.52 As shown, when the voltage at the node VSW is high, the bootstrap transistor BOOTFET 5170 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0306] Fig.53 is a schematic diagram of a VH generator circuit 5300, which can be used as Fig.51 VH generator circuit 5120.

[0307] Fig.54 is a timing diagram showing the timing relationship between various signals of the VH generator circuit 5300.

[0308] refer to Fig.53 and 54 , the VH generator circuit 5300 receives the signal at node I at the inverter 5310 and the buffer 5340. The inverter 5310 inverts the signal at node I to generate a signal at node N, and the buffer 5340 level-shifts the signal at node I to generate a signal at node G. Fig.54 As shown, although the voltage at the node N is the ground voltage and the voltage at the node G is high, the transistor 5320 charges the capacitor 5330 and makes the voltage at the output OUT equal to or substantially equal to the voltage at the power supply VCC. In addition, in response to the voltage at the node N increasing to the voltage of the power supply VDD and the voltage at the node G being low, the voltage increase of the voltage at the node N is capacitively coupled to the output node OUT, so that when the voltage at the node N is high, the voltage at the output OUT is equal to or substantially equal to the voltage at the power supply VCC plus the voltage of the power supply VDD.

[0309] Fig.55 Can be used as Fig.51Schematic diagram of HGATE generator circuit 5500 of HGATE generator circuit 5130. HGATE generator circuit 5500 includes switches 5510 and 5520, switch 5530, capacitor 5540, resistor 5550, and dmode switch 5560.

[0310] Fig.56 is a timing diagram showing the timing relationship between various signals of the HGATE generator circuit 5500.

[0311] refer to Fig.55 As shown, the HGATE generator circuit 5500 receives a signal at node I and generates a signal at output OUT based on the received signal, wherein the signal at output OUT is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.56 shown.

[0312] The signal at node I is received at each of switches 5510, 5520, and 5560. When the signal at node I is high, switch 5510 can conduct, which causes the voltage at node N2 to be low. Additionally, when the signal at node I is high, switch 5520 can conduct, which causes the voltage at N1 to be low. Furthermore, when the signal at node I is high, dmode switch 5560 can also conduct, which causes the voltage at output out to be equal to or substantially equal to the voltage of power supply VDD.

[0313] When the signal at node I is low, switches 5510, 5520, and 5560 cannot conduct. Therefore, node N2 is charged to or toward the voltage at power supply VDD through resistor 5550, enabling switch 5530 to conduct and charge node N1 to the voltage at node BOOTFET_DR. The voltage increase from 0 to the voltage at node BOOTFET_DR is capacitively coupled to output node OUT, so in response to the signal at node I going low, the voltage at output OUT is equal to or substantially equal to the voltage at node BOOTFET_DR (VCC+VDD) plus the voltage of power supply VDD, as shown in FIG. Fig.56 shown.

[0314] Fig.57 is a schematic diagram of the LGATE generator circuit 5700, which can be used as Fig.51 LGATE generator circuit 5140. LGATE generator circuit 5700 includes a capacitor 5710, a dmode switch 5720, an inverter 5730 and a buffer 5740.

[0315] Fig.58 is a timing diagram showing the timing relationship between various signals of LGATE generator circuit 5700.

[0316] refer to Fig.57 As shown in the figure, the LGATE generator circuit 5700 receives a signal at a node I and generates a signal at an output OUT based on the received signal, wherein the signal at the output OUT is a level-shifted version of the signal at the node I, as shown in FIG. Fig.58 as shown in .

[0317] When the signal at node I is low, the signal at node G is high (VCC), and the dmode switch 5720 charges the output node OUT to or toward the voltage at the power supply VCC. In addition, when the signal at node I is low, the signal at node C is high (VDD). When the signal at node I is high, the signal at node G is low, and as the voltage at node C transitions to a high level, the voltage increase at node C from 0 to the voltage on the power supply VDD is capacitively coupled to the output node OUT, and therefore, in response to the signal at node I becoming high, the voltage at the output OUT will be equal to or substantially equal to the voltage at the power supply VCC plus the voltage of the power supply VDD.

[0318] Fig.59 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 5900 connected to a bootstrap transistor 5970 and indirectly connected to a bootstrap capacitor 5980. The bootstrap transistor 5970 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 5980 can be similar or identical to other bootstrap capacitors discussed herein.

[0319] The bootstrap transistor driving circuit 5900 includes a logic circuit 5910 , an inverter 5920 , an HGATE generator circuit 5930 , an LGATE generator circuit 5940 , an H switch 5950 , and an L switch 5960 .

[0320] Logic circuit 5910 receives control signals at nodes SIGNAL_B and LS_GATE. The control signals at nodes SIGNAL_B and LS_GATE can be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and non-inverting version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_B can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_B is the same as the polarity of the control signal at the node LS_GATE, such as Fig.60 As shown, it will be discussed in further detail below.

[0321] Logic circuit 5910 receives control signals at nodes SIGNAL_B and LS_GATE and generates a signal at node I.

[0322] Inverter 5920 receives the signal at node I and generates an inverted and level-shifted version of the received signal at node H.

[0323] HGATE generator circuit 5930 receives the signal at node I and generates a signal at node HGATE based on the received signal.

[0324] LGATE generator circuit 5940 receives the signal at node I and generates a signal at node LGATE based on the received signal.

[0325] The H switch 5950 and the L switch 5960 cooperatively generate a signal at the node BOOTFET_DR based on the voltage at the signal node H and the power supply node VCC, and additionally based on the signals at the nodes HGATE and LGATE.

[0326] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 5970. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 5970 can conduct when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 5970 cannot conduct when the voltage at the node VSW is high or transitions between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0327] In some embodiments, the bootstrap transistor drive circuit 5900 includes an optional resistive element connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0328] In some embodiments, the bootstrap transistor driver circuit 5900 includes an optional resistive element, which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0329] In some embodiments, the bootstrap transistor driver circuit 5900 includes an optional diode connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the optional diode.

[0330] Fig.60 59 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 5900.

[0331] refer to Fig.59 and Fig.60 , the control signal at node LS_GATE is a delayed and non-inverted version of the control signal at node SIGNAL_B, where the delay Fig.60 Indicated by D in the middle.

[0332] Logic circuit 5910 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logical INV OR function.

[0333] Inverter 5920 receives the signal at node I and generates a signal at node H, where the signal at node H is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.60 shown.

[0334] HGATE generator circuit 5930 receives the signal at node I and generates a signal at node HGATE based on the received signal. Fig.60 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at node I. Fig.61 and Fig.62 An example of an implementation of the HGATE generator circuit 5930 is discussed.

[0335] LGATE generator circuit 5940 receives the signal at node I and generates a signal at node LGATE based on the received signal, wherein the signal at node LGATE is a level-shifted version of the signal at node I, such as Fig.60 As shown in the above reference Fig.45 and Fig.46 Examples of implementations of LGATE generator circuit 5930 are discussed.

[0336] H switch 5950 and L switch 5960 cooperate to generate a signal on node BOOTFET_DR based on the voltage at signal node H and power node VCC, and also based on the signals at nodes HGATE and LGATE. The signals at nodes HGATE and LGATE are non-overlapping high time signals, so H switch 5950 and L switch 5960 are never conductive at the same time. Fig.60 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node H, which is VCC+VDD when the signal at the node HGATE is high.

[0337] Due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the H switch 5950 is conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at the node VSW is low. Fig.60 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 5970 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 5970, the bootstrap transistor BOOTFET 5970 can conduct electricity, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0338] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE, and the voltage swing at the switch node VSW, the L switch 5960 can be conductive, and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high or transitions between high and low or between low and high. Fig.60 As shown, when the voltage at the node VSW is high, the bootstrap transistor BOOTFET 5970 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0339] Fig.61 Can be used as Fig.59 Schematic diagram of HGATE generator circuit 6100 of HGATE generator circuit 5930. HGATE generator circuit 6100 includes inverter 6110, pass switch 6120, parallel resistor 6130, pull-down switches 6140 and 6150, pull-up dmode switch 6160, capacitor 6170, and resistor 6180.

[0340] Fig.62 is a timing diagram showing the timing relationship between various signals of the HGATE generator circuit 6100.

[0341] refer to Fig.61 , the HGATE generator circuit 6100 receives the signals at nodes I and H and generates a signal at the output HGATE based on the received signals, wherein the signal at the output HGATE is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.62 shown.

[0342] The signal at the node I is received at the inverter 6110, each of the switches 6140 and 6150, and the pull-up dmode switch 6160. In addition, the signal at the node H is received at the pass switch 6120.

[0343] When the signal at node I is high and the signal at node H is low, the pass switch 6120 cannot conduct, switches 6140 and 6150 can conduct, and the pull-up dmode switch 6160 can conduct. Fig.62 As shown, the voltage at the node N1 and the output HGATE is low, and the voltage at the node N2 is substantially equal to the voltage at the power supply VDD.

[0344] In addition, when the signal at node I is low and the signal at node H is high, the switch 6120 can conduct, the switches 6140 and 6150 cannot conduct, and the pull-up dmode switch 6160 cannot conduct. Therefore, the voltage at node N1 is equal to the voltage at node H (VCC+VDD), the voltage at node N2 is substantially equal to the voltage at node H (VCC+VDD) plus the voltage at the power supply VDD, that is, VCC+2VDD, and the voltage at the output node HGATE is also equal to or substantially equal to VCC+2VDD, as shown in FIG. Fig.62 as shown in .

[0345] Fig.63 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 6300 connected to a bootstrap transistor 6370 and indirectly connected to a bootstrap capacitor 6380. The bootstrap transistor 6370 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 6380 can be similar or identical to other bootstrap capacitors discussed herein.

[0346] The bootstrap transistor drive circuit 6300 includes a logic circuit 6310 , a VH generator circuit 6320 , an inverter 6330 , a buffer 6340 , an H dmode switch 6350 , an optional shunt resistor 6355 , an optional pull-up resistor 6357 , an optional diode 6359 , and an L dmode switch 6360 .

[0347] The logic circuit 6310 receives control signals at the nodes SIGNAL_A and LS_GATE. The control signals at the nodes SIGNAL_A and LS_GATE may be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and inverted version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_A can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_A is opposite to the polarity of the control signal at the node LS_GATE, such as Fig.64 As shown, it will be discussed in further detail below.

[0348] The logic circuit 6310 receives the control signals at nodes SIGNAL_A and LS_GATE and generates a first signal at node I.

[0349] The VH generator circuit 6320 receives a signal at node I, and based on the received signal, the VH generator circuit 6320 generates a signal at node H.

[0350] Inverter 6330 receives the signal at node I and produces an inverted and level-shifted version of the signal at node I as the signal at node HGATE.

[0351] Buffer 6340 receives the signal at node I, receives the signal at node I, and produces a level-shifted version of the signal at node I as the signal at node LGATE.

[0352] H dmode switch 6350 and L dmode switch 6360 cooperate to generate a signal on node BOOTFET_DR based on the voltage at signal node H and power supply node VCC, and additionally based on signals at nodes HGATE and LGATE.

[0353] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 6370. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 6370 is conductive when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 6370 is not conductive while the voltage at the node VSW is high or transitioning between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0354] In some embodiments, the bootstrap transistor drive circuit 6300 includes an optional resistive element 6355 connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0355] In some embodiments, the bootstrap transistor driver circuit 6300 includes an optional resistive element 6357 , which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0356] In some embodiments, the bootstrap transistor driver circuit 6300 includes an optional diode 6359 connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode 6359 includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the diode 6359.

[0357] Fig.64 63 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 6300.

[0358] refer to Fig.63 and 64 , as shown, the control signal at node LS_GATE is a delayed and inverted version of the control signal at node SIGNAL_A, where the delay Fig.64 Indicated by D in the middle.

[0359] Logic circuit 6310 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logic INV OR function.

[0360] The VH generator circuit 6320 receives the signal at node I and generates a signal at node H, where the signal at node H is an inverted and level-shifted version of the signal at node I, such as Fig.64 As shown in the above reference Figure 53 to Figure 54 Examples of implementations of the VH generator circuit 6320 are discussed.

[0361] Inverter 6330 receives the signal at node I and generates a signal at node HGATE based on the received signal. Fig.64 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at node I.

[0362] Buffer 6340 receives the signal at node I and generates a signal at node LGATE based on the received signal, wherein the signal at node LGATE is a level-shifted version of the signal at node I, such as Fig.64 shown.

[0363] The H dmode switch 6350 and the L dmode switch 6360 cooperate to generate a signal on the node BOOTFET_DR based on the voltage at the signal node H and the power node VCC, and also based on the signals at the nodes HGATE and LGATE. The signals at the nodes HGATE and LGATE are non-overlapping high time signals, so the H dmode switch 6350 and the L dmode switch 6360 can never be conductive at the same time. Fig.64 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node H, which is VCC+VDD when the signal at the node HGATE is high.

[0364] Due to the timing coordination between the control signals at nodes SIGNAL_A and LS_GATE and the voltage swing at the switch node VSW, the Hdmode switch 6350 is conductive and the voltage at node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at node VSW is low. Fig.64 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 6370 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 6370, the bootstrap transistor BOOTFET 6370 is conductive, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0365] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE and the voltage swing at the switch node VSW, the L dmode switch 6360 is conductive and the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high, or transitions between high and low or between low and high. Fig.64 As shown, when the voltage at the node VSW is high, the bootstrap transistor BOOTFET 6370 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0366] Fig.65 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 6500 connected to a bootstrap transistor 6570 and indirectly connected to a bootstrap capacitor 6580. The bootstrap transistor 6570 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 6580 can be similar or identical to other bootstrap capacitors discussed herein.

[0367] The bootstrap transistor driving circuit 6500 includes a logic circuit 6510 , an inverter 6520 , an inverter 6530 , a buffer 6540 , an H dmode switch 6550 , and an L dmode switch 6560 .

[0368] Logic circuit 6510 receives control signals at nodes SIGNAL_B and LS_GATE. The control signals at nodes SIGNAL_B and LS_GATE can be, for example, Figure 8 The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and non-inverting version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_B can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_B is the same as the polarity of the control signal at the node LS_GATE, such as Fig.66 As shown, and discussed in further detail below.

[0369] Logic circuit 6510 receives control signals at nodes SIGNAL_B and LS_GATE and generates a signal at node I.

[0370] Inverter 6520 receives the signal at node I and produces an inverted and level-shifted version of the received signal at node H.

[0371] Inverter 6530 receives the signal at node I and produces an inverted and level-shifted version of the signal at node I as the signal at node HGATE.

[0372] Buffer 6540 receives the signal at node I, receives the signal at node I, and produces a level-shifted version of the signal at node I as the signal at node LGATE.

[0373] H dmode switch 6550 and L dmode switch 6560 cooperate to generate a signal at node BOOTFET_DR based on the voltage at signal node H and power supply node VCC, and additionally based on the signals at nodes HGATE and LGATE.

[0374] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 6570. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 6570 is conductive when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 6570 is not conductive while the voltage at the node VSW is high or transitioning between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0375] In some embodiments, the bootstrap transistor drive circuit 6500 includes an optional resistive element 6555 connected between the node BOOTFET_DR and the node H, which can be a resistor.

[0376] In some embodiments, the bootstrap transistor driver circuit 6500 includes an optional resistive element 6557, which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0377] In some embodiments, the bootstrap transistor driver circuit 6500 includes an optional diode 6559 connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode 6559 includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the diode 6559.

[0378] Fig.66 65 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 6500.

[0379] refer to Fig.65 and 66 , as shown, the control signal at node LS_GATE is a delayed and non-inverted version of the control signal at node SIGNAL_B, where the delay Fig.66 Indicated by D in the middle.

[0380] Logic circuit 6510 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logical INV OR function.

[0381] Inverter 6520 receives the signal at node I and generates a signal at node H, where the signal at node H is an inverted and level-shifted version of the signal at node I, as shown in FIG. Fig.66 shown.

[0382] Inverter 6530 receives the signal at node I and generates a signal at node HGATE based on the received signal. Fig.66 As shown, the signal generated at node HGATE is an inverted and level-shifted version of the signal at node I.

[0383] Buffer 6540 receives the signal at node I and generates a signal at node LGATE based on the received signal, wherein the signal at node LGATE is a level-shifted version of the signal at node I, such as Fig.66 as shown in .

[0384] The H dmode switch 6550 and the L dmode switch 6560 cooperate to generate a signal on the node BOOTFET_DR based on the voltage at the signal node H and the power supply node VCC, and also based on the signals at the nodes HGATE and LGATE. The signals at the nodes HGATE and LGATE are non-overlapping high time signals, so the H dmode switch 6550 and the L dmode switch 6560 can never be conductive at the same time. Fig.66 As shown, when the signal at the node LGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node VCC. In addition, when the signal at the node HGATE is high, the signal at the node BOOTFET_DR is equal to or substantially equal to the voltage at the power supply node HGATE. When the signal at the node HGATE is high, the voltage is VCC+VDD.

[0385] Due to the timing coordination between the control signals at nodes SIGNAL_A and LS_GATE, and the voltage swing at switch node VSW, H dmode switch 6550 is conductive and the voltage at node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at node VSW is low. Fig.66 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor BOOTFET 6570 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor BOOTFET 6570, the bootstrap transistor BOOTFET 6570 can conduct electricity, and the voltage of the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0386] Furthermore, due to the timing coordination between the control signals at the SIGNAL_A and LS_GATE nodes and the voltage swing at the switch node VSW, the L dmode switch 6560 is conductive and the voltage at the BOOTFET_DR node is equal to or substantially equal to VCC while the voltage at the VSW node is high or transitions between high and low or between low and high. Fig.66 As shown, when the voltage at the node VSW is high, the bootstrap transistor BOOTFET 6570 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0387] Fig.67 67 is a schematic diagram of an embodiment of a bootstrap transistor driver circuit 6700 connected to a bootstrap transistor 6770 and indirectly connected to a bootstrap capacitor 6780. The bootstrap transistor 6770 can be similar or identical to other bootstrap transistors described herein, and the bootstrap capacitor 6780 can be similar or identical to other bootstrap capacitors discussed herein.

[0388] The bootstrap transistor driving circuit 6700 includes a logic circuit 6710 and a buffer 6720 .

[0389] Logic circuit 6710 receives control signals at nodes SIGNAL_B and LS_GATE. The control signals at nodes SIGNAL_B and LS_GATE can be, for example, Figure 8The control signal at the node LS_GATE is generated at the low-side transistor driver circuit 120 shown. As described above, the control signal at the node LS_GATE is used to control the conductive state of the low-side power transistor 115. The control signal at the node LS_GATE can be, for example, a previous and non-inverting version of the control signal at the node LS_GATE. For example, the control signal at the node SIGNAL_B can be generated by the last one in a group of inverters and / or buffers connected in series, and the control signal at the node LS_GATE can be generated by the previous inverter or buffer in the group, wherein the polarity of the control signal at the node SIGNAL_B is the same as the polarity of the control signal at the node LS_GATE, such as Fig.68 As shown, it will be discussed in further detail below.

[0390] Logic circuit 6710 receives control signals at nodes SIGNAL_B and LS_GATE and generates a signal at node I.

[0391] Buffer 6720 receives the signal at node I and produces a level-shifted version of the received signal at node BOOTFET_DR.

[0392] The signal at the node BOOTFET_DR controls the conductive state of the bootstrap transistor BOOTFET 6770. The control signals at the nodes SIGNAL_A and LS_GATE are timed so that the bootstrap transistor BOOTFET 6770 is conductive when the voltage at the node VSW is low, so that when the voltage at the node VSW is low, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC. The control signals at the nodes SIGNAL_A and LS_GATE are also timed so that the bootstrap transistor BOOTFET 6770 is not conductive while the voltage at the node VSW is high or transitions between high and low or between low and high. Therefore, when the voltage at the node VSW is high, the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0393] In some embodiments, the bootstrap transistor driver circuit 6700 includes an optional resistive element, which can be a resistor, connected between the output of the buffer 6720 and the node BOOTFET_DR.

[0394] In some embodiments, the bootstrap transistor driver circuit 6700 includes an optional resistive element, which can be a resistor, connected between the node BOOTFET_DR and the power supply node VCC.

[0395] In some embodiments, the bootstrap transistor driver circuit 6700 includes an optional diode connected between the node BOOTFET_DR and the node Vboot, wherein the anode of the diode is connected to the node BOOTFET_DR and the cathode of the diode is connected to the node Vboot. In some embodiments, the diode includes a plurality of diodes connected in series. For example, 2, 3, 4, 5 or more diodes can be connected in series as the diode.

[0396] Fig.68 is a timing diagram showing the timing relationship between various signals of the bootstrap transistor driving circuit 6700.

[0397] refer to Fig.67 and 68 , as shown, the control signal at node LS_GATE is a delayed and non-inverted version of the control signal at node SIGNAL_B, where the delay Fig.68 Indicated by D in the middle.

[0398] Logic circuit 6710 receives control signals at nodes SIGNAL_A and LS_GATE, and generates a first signal at node I according to its logical INV OR function.

[0399] Buffer 6720 receives the signal at node I and generates a signal at node BOOTFET_DR, wherein the signal at node BOOTFET_DR is a level-shifted version of the signal at node I, such as Fig.68 shown.

[0400] Due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE and the voltage swing at the switch node VSW, the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC+VDD, while the voltage at the node VSW is low. Fig.68 As shown, when the voltage at the node VSW is low, the voltage at the gate terminal of the bootstrap transistor 6770 is greater than the voltage of the power supply VCC by an amount greater than the threshold voltage of the bootstrap transistor 6770, the bootstrap transistor 6770 can conduct electricity, and the voltage of the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC.

[0401] In addition, due to the timing coordination between the control signals at the nodes SIGNAL_A and LS_GATE and the voltage swing at the switch node VSW, the voltage at the node BOOTFET_DR is equal to or substantially equal to VCC, while the voltage at the node VSW is high or transitions between high and low or between low and high. Fig.68As shown, when the voltage at the node VSW is high, the bootstrap transistor 6770 cannot conduct, and the voltage at the node Vboot is equal to or substantially equal to the voltage at the power supply node VCC plus the voltage swing of the node VSW.

[0402] Certain circuits, such as basic logic circuits, are shown here using schematic symbols, and no transistor-level description is given. These circuits can be implemented using techniques known to those skilled in the art. For example, those described in U.S. Patent Application No. 16 / 375,394, entitled “GaN LOGIC CIRCUITS,” filed on April 4, 2019, can be used. Alternatively, other circuits can be used.

[0403] Although various embodiments of the present invention have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the present invention.Accordingly, the present invention is not to be limited except in accordance with the appended claims and their equivalents.

[0404] Although the present invention is disclosed by the specific embodiments described above, those embodiments are not intended to limit the present invention. Based on the above disclosed methods and technical aspects, those skilled in the art can make changes and modifications to the presented embodiments without departing from the spirit and scope of the present invention.

Claims

1. Half-bridge circuit, including: A bootstrap power supply voltage generator is configured to provide a first power supply voltage, the bootstrap power supply voltage generator comprising: a switch node, wherein a voltage at the switch node varies between a first switch node voltage and a second switch node voltage; a bootstrap transistor including a gate; a bootstrap capacitor connected to the switch node and the bootstrap transistor, wherein the bootstrap capacitor is configured to supply the first power supply voltage while the voltage at the switch node is equal to the second switch node voltage; and A bootstrap transistor drive circuit, comprising one or more depletion mode switches, wherein the one or more depletion mode switches are configured to control the voltage at the gate of the bootstrap transistor, wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are configured to conditionally enable the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor when the voltage at the connection between the bootstrap capacitor and the bootstrap transistor is less than the voltage of the voltage supply, and wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are also configured to conditionally enable the bootstrap transistor to be non-conductive when the voltage at the connection between the bootstrap capacitor and the bootstrap transistor is greater than the voltage of the voltage supply.

2. The half-bridge circuit of claim 1 , wherein the bootstrap transistor drive circuit is configured to conditionally cause the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor by causing the voltage at the gate of the bootstrap transistor to have a conduction drive voltage, wherein the one or more depletion mode switches are configured to generate the conduction drive voltage.

3. The half-bridge circuit of claim 1 , wherein the bootstrap transistor drive circuit is configured to conditionally cause the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor by causing a voltage at the gate of the bootstrap transistor to have a conduction drive voltage, wherein the one or more depletion mode switches are configured to pass the conduction drive voltage from a conduction drive voltage generator circuit to the gate of the bootstrap transistor.

4. The half-bridge circuit of claim 1 , wherein the bootstrap transistor drive circuit is configured to conditionally render the bootstrap transistor non-conductive between the voltage supply and the bootstrap capacitor by causing a voltage at the gate of the bootstrap transistor to have a non-conductive drive voltage, wherein the one or more depletion mode switches are configured to pass the non-conductive drive voltage from the non-conductive drive voltage supply to the gate of the bootstrap transistor.

5. The half-bridge circuit of claim 1 , wherein the bootstrap transistor driving circuit is configured to turn off the bootstrap transistor in response to an electronic event, wherein the electronic event causes the voltage at the switch node to change from the first node voltage to the second node voltage. 6 . The half-bridge circuit of claim 1 , further comprising a first source of the first power transistor connected to a first drain of the second power transistor at the switch node. 7 . The half-bridge circuit of claim 6 , wherein each of the first power transistor and the second power transistor is formed of gallium nitride.

8. The half-bridge circuit of claim 1, wherein the one or more depletion mode switches are formed of gallium nitride.

9. A bootstrap supply voltage generator circuit, configured to supply a first supply voltage, the bootstrap supply voltage generator circuit comprising: a switch node, wherein a voltage at the switch node varies between a first switch node voltage and a second switch node voltage; a bootstrap transistor including a gate; a bootstrap capacitor connected to the switch node and the bootstrap transistor, wherein the bootstrap capacitor is configured to supply the first supply voltage while the voltage at the switch node is equal to the second switch node voltage; as well as A bootstrap transistor drive circuit, comprising one or more depletion mode switches, wherein the one or more depletion mode switches are configured to control the voltage at the gate of the bootstrap transistor, wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are configured to conditionally enable the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor when the voltage at the connection between the bootstrap capacitor and the bootstrap transistor is less than the voltage of the voltage supply, and wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are also configured to conditionally enable the bootstrap transistor to be non-conductive when the voltage at the connection between the bootstrap capacitor and the bootstrap transistor is greater than the voltage of the voltage supply.

10. The bootstrap supply voltage generator circuit of claim 9, wherein the bootstrap transistor drive circuit is configured to conditionally cause the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor by causing the voltage at the gate of the bootstrap transistor to have a conduction drive voltage, wherein the one or more depletion mode switches are configured to generate the conduction drive voltage.

11. The bootstrap supply voltage generator circuit of claim 9 , wherein the bootstrap transistor drive circuit is configured to conditionally cause the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor by causing a voltage at the gate of the bootstrap transistor to have a conduction drive voltage, wherein the one or more depletion mode switches are configured to pass the conduction drive voltage from the conduction drive voltage generator circuit to the gate of the bootstrap transistor.

12. The bootstrap supply voltage generator circuit of claim 9 , wherein the bootstrap transistor drive circuit is configured to conditionally render the bootstrap transistor non-conductive between the voltage supply and the bootstrap capacitor by causing a voltage at the gate of the bootstrap transistor to have a non-conductive drive voltage, wherein the one or more depletion mode switches are configured to pass the non-conductive drive voltage from a non-conductive drive voltage supply to the gate of the bootstrap transistor.

13. The bootstrap supply voltage generator circuit of claim 9, wherein the bootstrap transistor drive circuit is configured to turn off the bootstrap transistor in response to a signal, wherein the signal causes the voltage at the switch node to change from the first switch node voltage to the second switch node voltage.

14. The bootstrapped supply voltage generator circuit of claim 9, further comprising a first source of the first power transistor connected to a first drain of the second power transistor at the switch node.

15. The bootstrapped supply voltage generator circuit of claim 14, wherein each of the first power transistor and the second power transistor comprises gallium nitride.

16. The bootstrapped supply voltage generator circuit of claim 9, wherein the one or more depletion mode switches comprise gallium nitride.

17. A bootstrap power generator circuit comprising: Single GaN substrate; a power transistor comprising a power gate, a power drain and a power source, wherein a voltage at the power drain varies between a first power drain node voltage and a second power drain node voltage according to a power control signal at the power gate; a bootstrap transistor including a bootstrap gate; a bootstrap capacitor connected to the power drain, wherein the bootstrap transistor is configured to charge the bootstrap capacitor when the voltage at the power drain is equal to the first power drain node voltage, and wherein the bootstrap capacitor is configured to power a circuit having another source connected to the power drain when the voltage at the power drain is equal to the second power drain node voltage; as well as a bootstrap transistor drive circuit comprising one or more depletion mode switches configured to generate a bootstrap control signal at the bootstrap gate, wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are configured to conditionally cause the bootstrap transistor to conduct current from the voltage supply to the bootstrap capacitor when a voltage at a connection between the bootstrap capacitor and the bootstrap transistor is less than a voltage of a voltage supply, and wherein the one or more depletion mode switches of the bootstrap transistor drive circuit are further configured to conditionally cause the bootstrap transistor to be non-conductive when a voltage at a connection between the bootstrap capacitor and the bootstrap transistor is greater than the voltage of the voltage supply, The bootstrap transistor driving circuit, the bootstrap transistor and the power transistor are each integrated on the GaN substrate.

18. The bootstrap power supply generator circuit of claim 17, further comprising a power transistor drive circuit configured to generate the power control signal based on a drive signal, wherein the bootstrap transistor drive circuit is configured to control the bootstrap control signal in response to the drive signal.

19. The bootstrap power generator circuit of claim 17, wherein the bootstrap transistor driving circuit is configured to render the bootstrap transistor non-conductive in response to a signal generation when the power transistor is in a non-conductive state.

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