Bootstrap circuit for switching converter

Abstract

The invention provides a bootstrap circuit for a switching converter. The bootstrap circuit comprises an enable signal generating circuit, a first transistor, a bootstrap capacitor, a voltage feedback circuit, an error amplifier and a charge pump. Through the bootstrap circuit provided by the invention, when the switching converter is in a high resistance state, most of circuit modules needing to consume quiescent current in a bst-sw voltage domain are closed, the voltage difference in the bst-sw voltage domain does not need to be monitored, the quiescent current consumption in the bst-sw voltage domain is ensured to be minimum, and only leakage consumption of each logic circuit exists. Meanwhile, through the charge pump, when the switching converter is in a high-resistance state, the node voltage is utilized to charge and complement energy for the bootstrap voltage, so that after the switching converter exits from the high-resistance state, the switching converter has a quick response capability to open a high-side switching tube to output power. The problem that the quiescent current of a chip is too large in the prior art is solved, the power consumption of the switching converter is reduced on the premise of ensuring reliable operation, and the efficiency of the switching converter is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of switching converters, and in particular to a bootstrap circuit for a switching converter. Background Art

[0002] In order to pursue high efficiency and low power consumption in a switching converter, the quiescent current of the switching converter needs to be designed. The smaller the quiescent current, the higher the conversion efficiency of the switching converter during light load or no-load standby. The common idea of ​​reducing the quiescent current is to turn off various circuit modules in the switching converter as much as possible in the high-impedance state (hereinafter referred to as the HZ state) where both the high-side switch tube and the low-side switch tube of the switching converter are turned off and not working.

[0003] The bst-sw voltage domain is a floating power rail that changes with the node voltage VSW, and is used to control the high-side switch tube. Normally, the voltage difference within the bst-sw voltage domain is usually controlled and regulated by the loop negative feedback. It should be noted that when the voltage difference is too low, the high-side switch tube will not be able to turn on normally. Due to the existence of the negative feedback loop, it is necessary to continuously consume current to transmit the voltage difference information within the bst-sw voltage domain. In order to resist the noise generated when the switch node SW switches up and down, a larger quiescent current is required to support the operation of the negative feedback loop. And this part of the quiescent current usually needs to be directly provided by the power supply terminal VIN of the switching converter, which is difficult to meet the low quiescent current requirements of the switching converter. Therefore, in the HZ state of the switching converter, it is usually hoped to turn off this part of the quiescent current.

[0004] However, when the switching converter is in the HZ state, once the load changes, we expect the switching converter to respond quickly and turn on the high-side switch tube to output power immediately. Otherwise, the output voltage will drop significantly, causing system failure. Therefore, even in the HZ state, the voltage of the bst-sw voltage domain must always be guaranteed to be sufficient. However, if the quiescent current used to maintain the negative feedback loop is completely turned off, the system cannot detect whether the voltage of the bst-sw voltage domain is sufficient. Summary of the invention

[0005] The present invention aims to at least solve the technical problem in the prior art that the static current of the switching converter is too large in the HZ state.

[0006] To this end, the present invention provides a bootstrap circuit for a switching converter, wherein the switching converter includes a high-side switch tube and a low-side switch tube, and the voltage at a common node of the high-side switch tube and the low-side switch tube is a node voltage. The bootstrap circuit includes an enable signal generating circuit, a first transistor, a bootstrap capacitor, a voltage feedback circuit, an error amplifier, and a charge pump.

[0007] Wherein, the enable signal generating circuit is used to generate an enable signal, and when both the high-side switch tube and the low-side switch tube are turned off, the enable signal is invalid, otherwise the enable signal is valid. The first transistor has a first end, a second end and a control end, the first end of the first transistor is coupled to the input end of the switch converter to receive the input voltage, and the control end of the first transistor receives the error signal; the bootstrap capacitor has a first end and a second end, the first end of the bootstrap capacitor is coupled to the common node of the high-side switch tube and the low-side switch tube, and the second end of the bootstrap capacitor is coupled to the second end of the first transistor through a diode, wherein the voltage at the second end of the bootstrap capacitor is the bootstrap voltage. The voltage feedback circuit receives the enable signal, and when the enable signal is invalid, the voltage feedback circuit does not work; when the enable signal is valid, the voltage feedback circuit samples the voltage difference between the bootstrap voltage and the node voltage, and generates a sampling signal representing the voltage difference according to the voltage difference. The error amplifier receives the sampling signal and the reference signal, and the error amplifier compares the sampling signal and the reference signal and amplifies the error between the two to generate an error signal, wherein the reference signal represents the preset voltage difference between the bootstrap voltage and the node voltage. The charge pump has a first end, a second end and a third end, the first end of the charge pump is coupled to the first end of the bootstrap capacitor to receive a node voltage, the second end of the charge pump receives a clock signal, and the third end of the charge pump is coupled to the second end of the bootstrap capacitor, wherein when the enable signal is invalid, the charge pump raises the node voltage by a preset voltage difference according to the clock signal to generate a bootstrap voltage at its third end.

[0008] Furthermore, the voltage domain between the bootstrap voltage and the node voltage can be defined as a first voltage domain, namely the bst-sw voltage domain, the bootstrap voltage is the high potential in the first voltage domain, and the node voltage is the low potential in the first voltage domain.

[0009] It can be understood that the above-mentioned bootstrap circuit is mainly used to generate a high potential in the first voltage domain, that is, a bootstrap voltage. Therefore, in some bootstrap circuits, the bootstrap capacitor can be omitted, or the bootstrap capacitor can be placed outside the chip.

[0010] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0011] When the switching converter is in the HZ state, most of the circuit modules in the bst-sw voltage domain that need to consume static current are turned off, and there is no need to monitor the voltage difference in the bst-sw voltage domain, ensuring that the static current consumption in the bst-sw voltage domain is minimal, and only the leakage consumption of each logic circuit exists. At the same time, the present disclosure introduces a charge pump, so that when the switching converter is in the HZ state, the node voltage is used to charge and replenish the bootstrap voltage, and when the switching converter exits the HZ state, it still has a fast response capability to turn on the high-side switch tube output power. The problem of excessive static current of the chip in the prior art is solved, and the power consumption of the switching converter is reduced while ensuring reliable operation, and the efficiency of the switching converter is improved.

[0012] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0014] Figure 1 is a module diagram of a bootstrap circuit for a switching converter according to an embodiment of the present invention;

[0015] Figure 2 is a module diagram of a bootstrap circuit for a switching converter according to yet another embodiment of the present invention;

[0016] Figure 3 is a circuit schematic diagram of a bootstrap circuit for a switching converter according to an embodiment of the present invention;

[0017] Figure 4 is a waveform diagram of a clock signal in a bootstrap circuit for a switching converter according to an embodiment of the present invention;

[0018] Figure 5 The diagram is a circuit schematic diagram of a charge pump in a bootstrap circuit for a switching converter according to an embodiment of the present invention.

[0019] in, Figures 1 to 5 The corresponding relationship between the reference numerals and the component names is as follows:

[0020] 1. Bootstrap circuit; 11. Enable signal generating circuit; 12. Voltage feedback circuit; 13. Charge pump; 14. Undervoltage detection circuit; 15. Oscillator; 40. Driver. DETAILED DESCRIPTION

[0021] References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this article, which neither exclude nor require the presence of undescribed features. Unless otherwise explicitly stated, the features recorded in the dependent claims can be freely combined with each other. The elements defined by "one" or "one" (i.e., singular form) throughout the document do not exclude the possibility of multiple elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify the direct electrical connection between circuit elements, while the term "coupling" is used to specify the electrical connection between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used here includes any and all combinations of one or more related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). In addition, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to a voltage or current that may not be completely constant in a high or low state.

[0022] Refer to the following Figures 1 to 5 In the following embodiments, the topology of the switching converter is shown as a high-side switch HS, a low-side switch LS, an inductor L and a capacitor C. OUT The buck BUCK topology structure is formed by connecting. Among them, the main switch tube HS and the freewheeling switch tube LS are shown as N-type metal semiconductor field effect transistors (NMOS). It can be understood that this is not a limitation on the types of the main switch tube HS and the freewheeling switch tube LS, which may also include any suitable controllable semiconductor switch devices such as PMOS, DMOS, JFET, IGBT, etc. Similarly, the switching converter may not be limited to the BUCK topology, but may also be other suitable switch topologies.

[0023] The switching converter includes a first voltage domain and a second voltage domain. Usually, the first voltage domain is a high voltage domain, and the second voltage domain is a low voltage domain. When driving the high-side switch tube HS, it is necessary to convert the control signal in the low voltage domain (for example, the high-side switch control signal HS_on for controlling the high-side switch tube HS and the low-side switch control signal LS_on for controlling the low-side switch tube LS) to the high voltage domain. The voltage on the common node of the high-side switch tube HS and the low-side switch tube LS is shown as a node voltage VSW, and the bootstrap circuit 1 is used to generate a bootstrap voltage VBST; wherein, the bst-sw voltage domain between the node voltage VSW and the bootstrap voltage VBST is the first voltage domain, the bootstrap voltage VBST is a high potential in the first voltage domain, and the node voltage VSW is a low potential in the first voltage domain.

[0024] like Figure 1 As shown, the first embodiment of the present invention proposes a bootstrap circuit 1 for a switching converter. The bootstrap circuit 1 includes an enable signal generating circuit 11, a first transistor M1, a bootstrap capacitor CBST, a voltage feedback circuit 12, an error amplifier EA and a charge pump 13.

[0025] Among them, the enable signal generating circuit 11 is used to generate an enable signal EN, which is a logic high-low level signal in the high voltage domain, and has a valid state (e.g., a logic high level) and an invalid state (e.g., a logic low level). When both the high-side switch tube HS and the low-side switch tube LS are turned off, that is, the switching converter enters the HZ state, the enable signal EN is invalid. When the switching converter does not enter the HZ state, the enable signal EN is valid.

[0026] The first transistor M1 has a first end, a second end and a control end. The first end of the first transistor M1 is coupled to the input end of the switching converter to receive the input voltage, and the control end of the first transistor M1 receives the error signal VG. The bootstrap capacitor CBST has a first end and a second end. The first end of the bootstrap capacitor CBST is coupled to the common node of the high-side switch tube HS and the low-side switch tube LS. The second end of the bootstrap capacitor CBST is coupled to the second end of the first transistor M1 through a diode D, wherein the voltage at the second end of the bootstrap capacitor CBST is the bootstrap voltage VBST. The voltage feedback circuit 12 receives an enable signal EN. When the enable signal EN is invalid, the voltage feedback circuit 12 does not work; when the enable signal EN is valid, the voltage feedback circuit 12 samples the voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW, and generates a sampling signal IFB representing the voltage difference Vd according to the voltage difference Vd.

[0027] The error amplifier EA receives the sampling signal IFB and the reference signal Iref, compares the sampling signal IFB with the reference signal Iref and amplifies the error between the two to generate an error signal VG, wherein the reference signal Iref represents a preset voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW. The preset voltage difference Vd is generally a voltage difference value expected in the high voltage domain, such as 5V.

[0028] The charge pump 13 has a first terminal, a second terminal and a third terminal. The first terminal of the charge pump 13 is coupled to the first terminal of the bootstrap capacitor CBST to receive the node voltage VSW. The second terminal of the charge pump 13 receives the clock signal CLK. The third terminal of the charge pump 13 is coupled to the second terminal of the bootstrap capacitor CBST. When the enable signal EN is invalid, the charge pump 13 raises the node voltage VSW by a preset voltage difference Vd according to the clock signal CLK to generate a bootstrap voltage VBST at its third terminal. In one embodiment, the clock signal CLK is a logic high-low level signal in the low voltage domain, having a logic high level state and a logic low level state. In one embodiment, the voltage value of the logic high level of the clock signal CLK is equal to the preset voltage difference Vd. The charge pump 13 raises the node voltage VSW input to the first terminal of the charge pump 13 by the preset voltage difference Vd according to the clock signal CLK, and outputs the bootstrap voltage VBST at the third terminal of the charge pump 13. Therefore, the voltage difference between the bootstrap voltage VBST and the node voltage VSW can be stabilized at the preset voltage difference Vd.

[0029] In one embodiment, the clock signal CLK can be generated by the oscillator 15. The oscillator 15 receives the enable signal EN. When the enable signal EN is invalid, the clock signal CLK is generated. The waveform of the clock signal CLK is as shown in FIG. Figure 4 As shown, it can be seen that the clock signal CLK is a logic high-low level signal, the logic high level of the clock signal CLK is equal to the preset voltage difference Vd, and the logic low level of the clock signal CLK is equal to the reference ground. In addition, the clock signal CLK can be in various forms, such as Figure 4 In one embodiment, the clock signal CLK is as shown in FIG. Figure 4 As shown in the waveform of CLK1 in FIG. 1 , the clock signal CLK may be a continuous periodic high and low pulse signal; in another embodiment, the clock signal CLK may also be as follows Figure 4 As shown in the waveform of CLK2 in Figure 1, in one cycle, continuous high and low pulse signals appear only in the effective time period. Figure 4 For any of the two waveforms, the frequency or effective period of the clock signal can be adjusted according to the voltage required to be supplemented by the bootstrap voltage VBST in the bootstrap circuit 1 .

[0030] It can be understood that the focus of the present disclosure is on how the bootstrap circuit 1 works at a low static operating current and maintains a stable voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW, so the bootstrap capacitor CBST is not a necessary technical feature of the bootstrap circuit 1 and can exist independently of the bootstrap circuit 1. In some embodiments, the bootstrap capacitor CBST can be placed outside the chip.

[0031] In this embodiment, the first transistor M1 is illustrated as an NMOS tube, the first end of the first transistor M1 is illustrated as the drain of the NMOS, the second end of the first transistor M1 is illustrated as the source of the NMOS, and the control end of the first transistor M1 is illustrated as the gate of the NMOS. It can be understood that this is not a limitation on the type of the first transistor M1, and it can also include other suitable controllable semiconductor switch tube devices.

[0032] exist Figure 1 In the illustrated embodiment, when the switching converter does not enter the HZ state, the enable signal EN is valid. At this time, the input voltage VIN charges the bootstrap capacitor CBST through the first transistor M1 and the diode D, and the voltage feedback circuit 12 works normally, sampling the actual voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW in real time (i.e., the voltage difference across the bootstrap capacitor CBST), thereby generating a sampling signal IFB. The sampling signal IFB is sent to the error amplifier EA for comparison with the reference signal Iref and outputs an error signal VG. When the actual voltage difference Vd represented by the sampling signal IFB does not meet the preset voltage difference Vd requirement, the error signal VG adjusts the on-resistance of the first transistor M1, and then adjusts the voltage difference between the first end and the second end of the first transistor M1, and finally stabilizes the voltage difference Vd at the preset voltage difference Vd. Among them, the diode D is used to prevent the bootstrap capacitor CBST from reverse discharge.

[0033] When the switching converter enters the HZ state, the enable signal EN is invalid. At this time, the voltage feedback circuit 12 does not work. Since the sampling signal IFB is not generated, the first transistor M1 remains in the off state. At this time, the static current consumed by the voltage feedback circuit 12 is completely removed in the first voltage domain. Since the value of the first voltage domain will switch rapidly with the change of the node voltage VSW, in order to accurately sample, the voltage feedback circuit 12 needs sufficient noise resistance, so a sufficiently large static current is required to support the operation of the negative feedback loop. If the current is too low, it will be submerged by the noise generated by the switching process. Saving this part of the static current can significantly reduce the power consumption of the switching converter.

[0034] However, since there is still leakage in the circuit, although the leakage current (nanoampere level) is much lower than the quiescent current (microampere level) when the feedback loop is working, the actual voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW will still slowly decrease. If no energy is replenished, the system will have an undervoltage fault. Therefore, the design enables the oscillator 15 to generate the clock signal CLK when the enable signal EN is in an invalid state, and the clock signal CLK is input to the charge pump 13, and the bootstrap voltage VBST is charged and replenished by the charge pump 13 using the clock signal CLK. Among them, the working charging capacity and self-loss of the charge pump 13 can be designed to be very low. It is only necessary to make the charging capacity of the charge pump 13 greater than the leakage capacity of the first voltage domain to ensure that the system does not have the risk of undervoltage. In a specific embodiment, after the voltage feedback circuit 12 is turned off, the leakage in the first voltage domain is less than 5nA, that is, the quiescent current is reduced by 1000 times, and the charge pump 13 can be made to provide only 5nA of replenishment capacity, and the overall consumption of the system is within 10nA. In some embodiments, the charge pump 13 and the oscillator 15 can also be designed to work in time periods, for example, Figure 4 The clock signal CLK shown in the CLK2 waveform can further reduce the system power consumption.

[0035] Continue reading Figure 1 In general, the switching converter further includes a driver 40, which has a first power supply terminal, a second power supply terminal, an input terminal and an output terminal. The first power supply terminal receives the bootstrap voltage VBST, the second power supply terminal receives the node voltage VSW, the input terminal receives the conversion signal HS_on_HS of the high-side switch control signal, and the output terminal is coupled to the gate of the high-side switch tube HS to provide a drive signal DRV. Among them, the conversion signal HS_on_HS of the high-side switch control signal, that is, the high-side switch control signal HS_on in the low voltage domain is converted into a signal in the high voltage domain after level conversion. The specific conversion method is well known to those skilled in the art and will not be repeated here.

[0036] In some embodiments, the bootstrap circuit further includes an undervoltage detection circuit. When the switching converter does not enter the HZ state, the undervoltage detection circuit detects the voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW, and determines the magnitude of the voltage difference Vd and the undervoltage threshold to generate an undervoltage indication signal. Since the conversion signal HS_on_HS of the high-side switch control signal may have an inaccurate voltage during the conversion process, it is impossible to ensure that the high-side switch tube HS remains turned off reliably when the switching converter enters the HZ state. Therefore, the undervoltage indication signal generated by the undervoltage detection circuit can be used to lock the high-side switch tube HS to remain turned off when the switching converter enters the HZ state. When the switching converter enters the HZ state, the undervoltage detection circuit is disabled to further reduce the static operating current.

[0037] like Figure 2 As shown, an undervoltage detection circuit 14 is set in the bootstrap circuit 1, and the undervoltage detection circuit 14 receives an enable signal EN. When the enable signal EN is invalid, the undervoltage detection circuit 14 does not work; when the enable signal EN is valid, the undervoltage detection circuit 14 detects the voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW, and determines the size of the voltage difference Vd and the undervoltage threshold to generate an undervoltage indication signal UV.

[0038] Continue reading Figure 2 , the input end of the driver 40 does not directly receive the conversion signal of the high-side switch control signal HS_on at this time, but is coupled to the output end of the NOR gate, and the NOR gate has a first input end and a second input end, the first input end of which is connected to the output end of the undervoltage detection circuit 14 to receive the undervoltage indication signal UV, and the second input end of which receives the inverted signal of the conversion signal HS_on_HS of the high-side switch control signal (for example, the conversion signal HS_on_HS of the high-side switch control signal is input to the second input end of the NOR gate after passing through the inverter INV1). When the undervoltage detection circuit 14 is not working, the output end of the undervoltage detection circuit 14 is pulled high, and the high-side switch tube HS remains closed at this time; when the undervoltage detection circuit 14 is working, the logic state of the undervoltage indication signal UV changes according to the voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW, specifically, when the voltage difference Vd is lower than the undervoltage threshold, the undervoltage indication signal UV turns high. It can be understood that the above-mentioned NOR gate is only an example given in the present disclosure, and those skilled in the art can adjust the logic device according to the control logic of the present disclosure.

[0039] To further illustrate the working principle of each circuit module in the bootstrap circuit 1 of the present disclosure, some embodiments of the present disclosure provide specific circuit structures of each circuit module.

[0040] In some embodiments, the enable signal generating circuit 11 has a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal and an output terminal; wherein the first input terminal of the enable signal generating circuit 11 receives the high-side switch control signal HS_on, the second input terminal of the enable signal generating circuit 11 receives the low-side switch control signal LS_on, the first power supply terminal of the enable signal generating circuit 11 receives the bootstrap voltage VBST, the second power supply terminal of the enable signal generating circuit 11 receives the node voltage VSW, and the enable signal generating circuit 11 generates the enable signal EN at the output terminal according to the high-side switch control signal HS_on and the low-side switch control signal LS_on. It should be noted that the high-side switch control signal HS_on and the low-side switch control signal LS_on are both signals in the low voltage domain, and the enable signal EN is a signal in the high voltage domain, that is, the enable signal generating circuit 11 generates the enable signal EN in the high voltage domain according to the high-side switch control signal HS_on and the low-side switch control signal LS_on in the low voltage domain.

[0041] In a specific embodiment, Figure 3 As shown, the enable signal generating circuit 11 includes a logic judgment unit, a second transistor M2, a first resistor R1, a third transistor P3, a fourth transistor P4 and a second resistor R2.

[0042] The logic judgment unit receives the high-side switch control signal HS_on and the low-side switch control signal LS_on and generates a high-impedance signal Specifically, in Figure 3 In the illustrated embodiment, the logic judgment unit is shown as an OR gate. When the high-side switch control signal HS_on and the low-side switch control signal LS_on are both at a low level, the high-impedance signal Is low.

[0043] The second transistor M2 has a first terminal, a second terminal and a control terminal. The second terminal of the second transistor M2 is coupled to the ground through the first current source I1. The control terminal of the second transistor M2 receives a high impedance signal. The first resistor R1 has a first end and a second end, the first end of the first resistor R1 receives the bootstrap voltage VBST, and the second end of the first resistor R1 is coupled to the second end of the second transistor M2; the third transistor P3 has a first end, a second end and a control end, the second end of the third transistor P3 receives the bootstrap voltage VBST, and the first end and the control end of the third transistor P3 are both coupled to the first end of the second transistor M2; the fourth transistor P4 has a first end, a second end and a control end, the second end of the fourth transistor P4 receives the bootstrap voltage VBST, and the control end of the fourth transistor P4 is coupled to the control end of the third transistor P3; the second resistor R2 has a first end and a second end, the first end of the second resistor R2 is coupled to the first end of the fourth transistor P4, and the second end of the second resistor R2 receives the node voltage VSW.

[0044] In another embodiment, a third capacitor C3 may be connected in parallel across the second resistor R2 as required, so that after the switch converter enters the HZ state, the enable signal EN is turned to a logic high state after a delay period of time. The delay period can be set by flexibly setting the values ​​of the second resistor R2 and the third capacitor C3.

[0045] When the switching converter does not enter the HZ state, the high impedance signal is high level, the second transistor M2 is turned on, so that the third transistor P3 and the fourth transistor P4 are turned on, and the enable signal EN is equal to the bootstrap voltage VBST, that is, a high level in the high voltage domain, that is, a valid state.

[0046] When the switching converter enters the HZ state, the high impedance signal is low level, the second transistor M2 is turned off, so that the third transistor P3 and the fourth transistor P4 are turned off, and the enable signal EN is equal to the node voltage VSW, that is, the low level in the high voltage domain, that is, the invalid state.

[0047] In this embodiment, the second transistor M2 is schematically shown as NMOS, the third transistor P3 and the fourth transistor P4 are schematically shown as PMOS, the first end of the second transistor M2, the third transistor P3 and the fourth transistor P4 is the drain of the MOS tube, the second end of the second transistor M2, the third transistor P3 and the fourth transistor P4 is the source of the MOS tube, and the control end of the second transistor M2, the third transistor P3 and the fourth transistor P4 is the gate of the MOS tube. It can be understood that the second transistor M2, the third transistor P3 and the fourth transistor P4 can also be other suitable controllable semiconductor switch tube devices.

[0048] Continue reading Figure 3 In one embodiment, the voltage feedback circuit 12 includes: a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor M8 and a third resistor R3.

[0049] The fifth transistor P5 has a first end, a second end and a control end, the second end of the fifth transistor P5 receives the bootstrap voltage VBST, and the first end of the fifth transistor P5 generates a sampling signal IFB; the sixth transistor P6 has a first end, a second end and a control end, the second end of the sixth transistor P6 receives the bootstrap voltage VBST, the control end of the sixth transistor P6 is coupled to the control end of the fifth transistor P5 and coupled to the first end of the sixth transistor P6; the seventh transistor P7 has a first end, a second end and a control end, the second end of the seventh transistor P7 receives the bootstrap voltage VBST, the first end of the seventh transistor P7 is coupled to the first end of the sixth transistor P6, and the control end of the seventh transistor P7 receives the enable signal EN; the eighth transistor M8 has a first end, a second end and a control end, the second end of the eighth transistor M8 receives the node voltage VSW through the third resistor R3, the first end of the eighth transistor M8 is coupled to the first end of the sixth transistor P6, and the control end of the eighth transistor M8 receives the enable signal EN; the on-off states of the seventh transistor P7 and the eighth transistor M8 are opposite.

[0050] When the enable signal EN is valid (high level), the seventh transistor P7 is turned off, the eighth transistor M8 is turned on, the voltage feedback circuit 12 is enabled to work normally, the fifth transistor P5 and the sixth transistor P6 are turned on, and the first end of the fifth transistor P5 generates a current, that is, generates a sampling signal IFB, and the sampling signal IFB represents the voltage difference Vd between the bootstrap voltage VBST and the node voltage VSW. In another embodiment, the voltage feedback circuit 12 may further include a fourth resistor, coupled to the first end of the fifth transistor P5, for converting the current generated at the end into a voltage and outputting it as a sampling signal.

[0051] When the enable signal EN is invalid (low level), the seventh transistor P7 is turned on, the eighth transistor M8 is turned off, the voltage feedback circuit 12 will be turned off and disabled, the fifth transistor P5 and the sixth transistor P6 are turned off, and no current is generated at the first end of the fifth transistor P5, that is, the voltage feedback circuit 12 does not work.

[0052] In this embodiment, the fifth transistor P5, the sixth transistor P6 and the seventh transistor P7 are indicated as PMOS, and the eighth transistor M8 is indicated as NMOS; the first end of the fifth transistor P5, the sixth transistor P6, the seventh transistor P7 and the eighth transistor M8 is indicated as the drain of the MOS tube, the second end of the fifth transistor P5, the sixth transistor P6, the seventh transistor P7 and the eighth transistor M8 is indicated as the source of the MOS tube, and the control end of the fifth transistor P5, the sixth transistor P6, the seventh transistor P7 and the eighth transistor M8 is indicated as the gate of the MOS tube. It can be understood that the fifth transistor P5, the sixth transistor P6, the seventh transistor P7 and the eighth transistor M8 can also be other suitable controllable semiconductor switch tube devices.

[0053] Continue reading Figure 3 In one embodiment, the undervoltage detection circuit 14 includes: a ninth transistor P9, a tenth transistor M10 and an eleventh transistor P11.

[0054] The ninth transistor P9 has a first end, a second end and a control end, the second end of the ninth transistor P9 receives the bootstrap voltage VBST, and the control end of the ninth transistor P9 is coupled to the common end of the eighth transistor M8 and the sixth transistor P6; the tenth transistor M10 has a first end, a second end and a control end, the second end of the tenth transistor M10 receives the node voltage VSW, the first end of the tenth transistor M10 is coupled to the first end of the ninth transistor P9, and the control end of the tenth transistor M10 is coupled to the second end of the eighth transistor M8; the eleventh transistor P11 has a first end, a second end and a control end, the second end of the eleventh transistor P11 receives the bootstrap voltage VBST, and the first end of the eleventh transistor P11 is coupled to the common end of the tenth transistor M10 and the ninth transistor P9; wherein the common end of the tenth transistor M10 and the ninth transistor P9 generates an undervoltage indication signal UV; when the undervoltage indication signal UV is valid, the high-side switch tube HS is locked in an off state.

[0055] When the enable signal EN is valid (high level), the eleventh transistor P11 is turned off, and the undervoltage detection circuit 14 is enabled to work normally. When the bootstrap voltage VBST is normal, the ninth transistor P9 is turned off, the tenth transistor M10 is turned on, and the undervoltage indication signal UV is equal to the node voltage VSW, that is, the low level in the high voltage domain; when the bootstrap voltage VBST is undervoltage, the ninth transistor P9 is turned on, the tenth transistor M10 is turned off, and the undervoltage indication signal UV is equal to the bootstrap voltage VBST, that is, the high level in the high voltage domain.

[0056] When the enable signal EN is invalid (low level), the eleventh transistor P11 is turned on, and the output end of the undervoltage detection circuit 14 is locked to the bootstrap voltage VBST, that is, the high level in the high voltage domain, so that the high-side switch tube HS remains disconnected.

[0057] In this embodiment, the ninth transistor P9 and the eleventh transistor P11 are indicated as PMOS, and the tenth transistor M10 is indicated as NMOS; the first end of the ninth transistor P9, the tenth transistor M10 and the eleventh transistor P11 is indicated as the drain of the MOS tube, the second end of the ninth transistor P9, the tenth transistor M10 and the eleventh transistor P11 is indicated as the source of the MOS tube, and the control end of the ninth transistor P9, the tenth transistor M10 and the eleventh transistor P11 is indicated as the gate of the MOS tube. It can be understood that the ninth transistor P9, the tenth transistor M10 and the eleventh transistor P11 can also be other suitable controllable semiconductor switch tube devices.

[0058] It can be understood that the specific circuit of the above-mentioned undervoltage detection circuit is only an illustrative method given in the present disclosure, and those skilled in the art may also adopt other design methods to implement undervoltage detection.

[0059] Figure 5 FIG. 1 shows a circuit schematic diagram of a charge pump 13 according to an embodiment of the present invention. Figure 5 As shown, the charge pump 13 includes: a twelfth transistor P12, a thirteenth transistor M13, a fourteenth transistor P14, a fifteenth transistor M15, a first capacitor C1, a second capacitor C2 and an inverter INV2.

[0060] Among them, the twelfth transistor P12, the thirteenth transistor M13, the fourteenth transistor P14, and the fifteenth transistor M15 all have a first end, a second end, and a control end; the second end of the twelfth transistor P12 and the second end of the fourteenth transistor P14 are both coupled to the third end of the charge pump 13 to provide a bootstrap voltage VBST; the first end of the twelfth transistor P12 is coupled to the first end of the thirteenth transistor M13; the first end of the fourteenth transistor P14 is coupled to the first end of the fifteenth transistor M15; the second end of the thirteenth transistor M13 and the second end of the fifteenth transistor M15 are both coupled to the first end of the charge pump 13 to receive the node voltage VSW; the control end of the twelfth transistor P12 and the control end of the thirteenth transistor M13 are coupled together and coupled to the fourteenth transistor P14. a common terminal of the first terminal of the transistor P14 and the first terminal of the fifteenth transistor M15; a control terminal of the fourteenth transistor P14 and the control terminal of the fifteenth transistor M15 are coupled together, and coupled to a common terminal of the first terminal of the twelfth transistor P12 and the first terminal of the thirteenth transistor M13; one end of the first capacitor C1 is coupled to the second end of the charge pump 13 to receive the clock signal CLK, and the other end of the first capacitor C1 is coupled to the common terminal of the control terminal of the fourteenth transistor P14 and the control terminal of the fifteenth transistor M15; one end of the second capacitor C2 is coupled to the second end of the charge pump 13 through the inverter INV2 to receive the clock signal CLK, and the other end of the second capacitor C2 is coupled to the common terminal of the control terminal of the twelfth transistor P12 and the control terminal of the thirteenth transistor M13.

[0061] exist Figure 5In the illustrated embodiment, the twelfth transistor P12 and the fourteenth transistor P14 are indicated as PMOS, and the thirteenth transistor M13 and the fifteenth transistor M15 are indicated as NMOS; the first ends of the twelfth transistor P12, the thirteenth transistor M13, the fourteenth transistor P14 and the fifteenth transistor M15 are indicated as the drain of the MOS tube, the second ends of the twelfth transistor P12, the thirteenth transistor M13, the fourteenth transistor P14 and the fifteenth transistor M15 are indicated as the source of the MOS tube, and the control ends of the twelfth transistor P12, the thirteenth transistor M13, the fourteenth transistor P14 and the fifteenth transistor M15 are indicated as the gate of the MOS tube. It can be understood that the twelfth transistor P12, the thirteenth transistor M13, the fourteenth transistor P14 and the fifteenth transistor M15 can also be other suitable controllable semiconductor switch tube devices.

[0062] When the clock signal CLK is at a logic high level "1", the voltage of the clock signal CLK is equal to the preset voltage difference Vd, the fifteenth transistor M15 is turned on, and the node voltage VSW charges the second capacitor C2 through the fifteenth transistor M15 so that the voltage on the second capacitor C2 is equal to the node voltage VSW; at the same time, the twelfth transistor P12 is turned on, and the voltage (VSW) on the first capacitor C1 superimposed on the high level voltage (voltage difference Vd) of the clock signal CLK is the bootstrap voltage VBST on the output end of the charge pump 13. When the clock signal CLK is at a logic low level "0", the voltage of the clock signal CLK is equal to the reference ground, the thirteenth transistor M13 is turned on, and the node voltage VSW charges the first capacitor C1 through the thirteenth transistor M13 so that the voltage on the first capacitor C1 is equal to the node voltage VSW; at the same time, the fourteenth transistor P14 is turned on, and the voltage (VSW) on the second capacitor C2 superimposed on the low level voltage (voltage difference Vd) of the clock signal CLK is the bootstrap voltage VBST on the output end of the charge pump 13. As the logic high and low levels of the clock signal CLK alternate, the first capacitor C1 and the second capacitor C2 are charged in turn to maintain the value of the bootstrap voltage VBST.

[0063] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0064] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A bootstrap circuit for a switching converter, wherein the switching converter comprises a high-side switch tube and a low-side switch tube, wherein a voltage at a common node of the high-side switch tube and the low-side switch tube is a node voltage, It is characterized in that The bootstrap circuit comprises: An enable signal generating circuit is used to generate an enable signal, wherein when both the high-side switch tube and the low-side switch tube are turned off, the enable signal is invalid, otherwise the enable signal is valid; A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the input terminal of the switching converter to receive an input voltage, and the control terminal of the first transistor receives an error signal; A bootstrap capacitor, wherein a first end of the bootstrap capacitor is coupled to a common node of the high-side switch tube and the low-side switch tube, and a second end of the bootstrap capacitor is coupled to a second end of the first transistor through a diode, wherein a voltage at the second end of the bootstrap capacitor is a bootstrap voltage; A voltage feedback circuit receives an enable signal. When the enable signal is invalid, the voltage feedback circuit does not work. When the enable signal is valid, the voltage feedback circuit samples a voltage difference between the bootstrap voltage and the node voltage, and generates a sampling signal according to the voltage difference, wherein the sampling signal represents the voltage difference. an error amplifier, receiving a sampling signal and a reference signal, the error amplifier compares the sampling signal and the reference signal and amplifies the error between the two to generate the error signal, wherein the reference signal represents a preset voltage difference between the bootstrap voltage and the node voltage; A charge pump has a first end, a second end and a third end, wherein the first end of the charge pump is coupled to the first end of a bootstrap capacitor to receive a node voltage, the second end of the charge pump receives a clock signal, and the third end of the charge pump is coupled to the second end of the bootstrap capacitor, wherein when an enable signal is invalid, the charge pump raises the node voltage by a preset voltage difference according to the clock signal to generate a bootstrap voltage at its third end.

2. The bootstrap circuit for a switching converter according to claim 1, It is characterized in that The preset voltage difference is equal to the voltage value of the high level of the clock signal.

3. The bootstrap circuit for a switching converter according to claim 1, It is characterized in that The bootstrap circuit further comprises: The oscillator receives an enable signal and generates a clock signal when the enable signal is invalid, wherein the clock signal is a logic high-low level signal, the logic high level of the clock signal is equal to a preset voltage difference, and the logic low level of the clock signal is equal to a reference ground.

4. The bootstrap circuit for a switching converter according to claim 1, It is characterized in that The bootstrap circuit further comprises: The undervoltage detection circuit receives an enable signal. When the enable signal is invalid, the undervoltage detection circuit does not work; when the enable signal is valid, the undervoltage detection circuit detects the voltage difference between the bootstrap voltage and the node voltage, and determines the size of the voltage difference and the undervoltage threshold to generate an undervoltage indication signal.

5. The bootstrap circuit for a switching converter according to claim 1, It is characterized in that The enable signal generating circuit has a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal and an output terminal; Among them, the first input end of the enable signal generating circuit receives the high-side switch control signal, the second input end of the enable signal generating circuit receives the low-side switch control signal, the first power supply end of the enable signal generating circuit receives the bootstrap voltage, the second power supply end of the enable signal generating circuit receives the node voltage, and the enable signal generating circuit generates an enable signal at its output end according to the high-side switch control signal and the low-side switch control signal, wherein the high-side switch control signal is also used to control the high-side switch tube to be turned on and off, and the low-side switch control signal is also used to control the low-side switch tube to be turned on and off.

6. The bootstrap circuit for a switching converter according to claim 5, It is characterized in that The enable signal generating circuit comprises: A logic judgment unit receives a high-side switch control signal and a low-side switch control signal and generates a high-impedance signal; A second transistor has a first end, a second end and a control end, the second end of the second transistor is coupled to the ground via the first current source, and the control end of the second transistor receives a high impedance signal; A first resistor having a first end and a second end, the first end of the first resistor receiving the bootstrap voltage, the second end of the first resistor coupled to the second end of the second transistor; A third transistor has a first terminal, a second terminal and a control terminal, the second terminal of the third transistor receives a bootstrap voltage, and the first terminal and the control terminal of the third transistor are both coupled to the first terminal of the second transistor; a fourth transistor having a first terminal, a second terminal and a control terminal, the second terminal of the fourth transistor receiving a bootstrap voltage, and the control terminal of the fourth transistor being coupled to the control terminal of the third transistor; The second resistor has a first end and a second end. The first end of the second resistor is coupled to the first end of the fourth transistor, and the second end of the second resistor receives the node voltage.

7. The bootstrap circuit for a switching converter according to claim 6, It is characterized in that The enable signal generating circuit further comprises: A delay capacitor, wherein two ends of the delay capacitor are respectively coupled to the first end and the second end of the second resistor.

8. The bootstrap circuit for a switching converter according to claim 1, It is characterized in that The voltage feedback circuit comprises: a fifth transistor having a first terminal, a second terminal and a control terminal, the second terminal of the fifth transistor receiving a bootstrap voltage, and the first terminal of the fifth transistor generating a sampling signal; a sixth transistor having a first terminal, a second terminal and a control terminal, the second terminal of the sixth transistor receiving the bootstrap voltage, the control terminal of the sixth transistor being coupled to the control terminal of the fifth transistor and coupled to the first terminal of the sixth transistor; a seventh transistor having a first terminal, a second terminal and a control terminal, the second terminal of the seventh transistor receiving a bootstrap voltage, the first terminal of the seventh transistor being coupled to the first terminal of the sixth transistor, and the control terminal of the seventh transistor receiving an enable signal; an eighth transistor having a first end, a second end and a control end, the second end of the eighth transistor receiving a node voltage through a third resistor, the first end of the eighth transistor being coupled to the first end of the sixth transistor, and the control end of the eighth transistor receiving an enable signal; The on-off states of the seventh transistor and the eighth transistor are opposite.

9. The bootstrap circuit for a switching converter according to claim 8, It is characterized in that The bootstrap circuit further includes an undervoltage detection circuit, and the undervoltage detection circuit includes: a ninth transistor having a first terminal, a second terminal and a control terminal, the second terminal of the ninth transistor receiving a bootstrap voltage, and the control terminal of the ninth transistor coupled to a common terminal of the eighth transistor and the sixth transistor; a tenth transistor having a first terminal, a second terminal and a control terminal, the second terminal of the tenth transistor receiving the node voltage, the first terminal of the tenth transistor being coupled to the first terminal of the ninth transistor, and the control terminal of the tenth transistor being coupled to the second terminal of the eighth transistor; an eleventh transistor having a first terminal, a second terminal and a control terminal, the second terminal of the eleventh transistor receiving a bootstrap voltage, and the first terminal of the eleventh transistor coupled to a common terminal of the tenth transistor and the ninth transistor; The common terminal of the tenth transistor and the ninth transistor generates an undervoltage indication signal.

10. A bootstrap circuit for a switching converter, the switching converter comprising a high-side switch tube, a low-side switch tube and a first voltage domain, the first voltage domain having a high potential and a low potential, the voltage at a common node of the high-side switch tube and the low-side switch tube being the low potential of the first voltage domain, the bootstrap circuit being used to generate a high potential of the first voltage domain, It is characterized in that The bootstrap circuit comprises: An enable signal generating circuit is used to generate an enable signal, wherein when both the high-side switch tube and the low-side switch tube are turned off, the enable signal is invalid, otherwise the enable signal is valid; A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the input terminal of the switching converter to receive an input voltage, the control terminal of the first transistor receives an error signal, and the second terminal of the first transistor is coupled to a high potential of the first voltage domain through a diode; A voltage feedback circuit, when the enable signal is invalid, the voltage feedback circuit does not work; when the enable signal is valid, the voltage feedback circuit samples the voltage difference between the high potential and the low potential of the first voltage domain, and generates a sampling signal according to the voltage difference, wherein the sampling signal represents the voltage difference; an error amplifier, receiving a sampling signal and a reference signal, the error amplifier compares the sampling signal and the reference signal and amplifies the error between the two to generate the error signal, wherein the reference signal represents a preset voltage difference between a high potential and a low potential of the first voltage domain; A charge pump has a first end, a second end and a third end. The first end of the charge pump receives a low potential in a first voltage domain, and the second end of the charge pump receives a clock signal. When the enable signal is invalid, the charge pump raises the low potential in the first voltage domain by a preset voltage difference according to the clock signal to generate a high potential in the first voltage domain at its third end.

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