Charge pump circuit and charge pump system

Abstract

The invention discloses a charge pump circuit and a charge pump system, and the charge pump circuit comprises a comparison unit which is suitable for receiving a reference signal and a voltage division signal, and comparing the reference signal with the voltage division signal to obtain a feedback signal; the signal processing unit is connected with the comparison unit and is suitable for receiving the feedback signal and processing the feedback signal to obtain a processed feedback signal; the driving unit is connected with the signal processing unit and is suitable for receiving a clock signal and the processed feedback signal and carrying out NOR operation on the clock signal and the processed feedback signal to obtain a driving signal; and the charge pump unit is connected with the driving unit, is suitable for receiving the driving signal, and is turned on or off under the control of the driving signal. The feedback signal is adjusted through the signal processing unit, the processed feedback signal with the increased duty ratio can be obtained, and therefore the boosting performance of the charge pump can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor design, and in particular to a charge pump circuit and a charge pump system. Background Art

[0002] A charge pump circuit is a device used for voltage conversion, which can realize voltage conversion, such as boost, buck, inversion, etc.

[0003] The charge pump circuit achieves voltage boost by charging and discharging the capacitor through switches. The charge pump circuit has no inductive element to store energy and has weak driving capability. It can be used in small current situations, so it is often used for voltage conversion in flash memory.

[0004] However, the boost performance of current charge pump circuits is relatively poor. Summary of the invention

[0005] The technical problem solved by the present invention is how to improve the voltage boosting performance of a charge pump circuit.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a charge pump circuit, comprising:

[0007] A comparison unit, adapted to receive a reference signal and a voltage-divided signal, and compare the reference signal with the voltage-divided signal to obtain a feedback signal;

[0008] a signal processing unit connected to the comparison unit, adapted to receive the feedback signal and process the feedback signal to obtain a processed feedback signal, wherein the duty cycle of the processed feedback signal is greater than the duty cycle of the feedback signal;

[0009] a driving unit connected to the signal processing unit, adapted to receive a clock signal and a processed feedback signal, and perform an OR operation on the clock signal and the processed feedback signal to obtain a driving signal;

[0010] and a charge pump unit connected to the driving unit, adapted to receive the driving signal and be turned on or off under the control of the driving signal;

[0011] Wherein, while the clock signal is in the second level state, the processed feedback signal remains in the first level state; the first level state and the second level state are logically opposite.

[0012] Optionally, the signal processing unit is further adapted to receive a processed signal, and perform delay processing on the feedback signal based on the processed signal to obtain the processed feedback signal.

[0013] Optionally, the processed feedback signal is synchronized with the clock signal.

[0014] Optionally, the signal processing unit includes: a pulse signal generating module connected to the comparison unit, suitable for receiving a processed signal and generating a pulse signal based on the processed signal; a sampling module connected to the pulse signal generating module, suitable for receiving the feedback signal and the pulse signal, and sampling the feedback signal according to the pulse signal to obtain the processed feedback signal synchronized with the clock signal.

[0015] Optionally, the pulse signal generating module includes: a first sub-module, suitable for receiving the processed signal, and processing the rising edge of the processed signal to obtain a first sub-pulse signal; a second sub-module, connected in parallel with the first sub-module, suitable for receiving the processed signal, and processing the falling edge of the processed signal to obtain a second sub-pulse signal; a merging sub-module, connected to the first sub-module and the second sub-module, suitable for receiving the first sub-pulse signal and the second sub-pulse signal, and merging the first sub-pulse signal and the second sub-pulse signal to obtain the pulse signal.

[0016] Optionally, the first submodule includes: a first inverter, a first delay, and a first NOR gate; wherein: the input end of the first inverter is suitable for receiving the processing signal, and the output end of the first inverter is connected to the input end of the first delay; the output end of the first delay is connected to the second input end of the first NOR gate; the first input end of the first NOR gate is suitable for receiving the processing signal, and the output end of the first NOR gate is suitable for outputting a first sub-pulse signal.

[0017] Optionally, the second submodule includes: a second inverter, a second delay, and a second NOR gate; wherein: the input end of the second inverter is suitable for receiving the processing signal, and the output end of the second inverter is connected to the input end of the second delay; the output end of the second delay is connected to the second input end of the second NOR gate; the first input end of the second NOR gate is suitable for receiving the processing signal, and the output end of the second NOR gate is suitable for outputting a second sub-pulse signal.

[0018] Optionally, the merging submodule includes: a third NOR gate; the first input end of the third NOR gate is suitable for receiving the first sub-pulse signal, the second input end of the third NOR gate is suitable for receiving the second sub-pulse signal, and the output end of the third NOR gate is suitable for outputting the pulse signal.

[0019] Optionally, the sampling module includes: a trigger; a first input end of the trigger is suitable for receiving the feedback signal, a second input end of the trigger is suitable for receiving a pulse signal, and an output end of the trigger is suitable for outputting a feedback signal after synchronization processing.

[0020] Optionally, the driving unit includes: a fourth NOR gate and a third inverter; wherein: the first input end of the fourth NOR gate is suitable for receiving the clock signal, the second input end of the fourth NOR gate is suitable for receiving the processed feedback signal, the output end of the fourth NOR gate is connected to the input end of the third inverter; the output end of the third inverter is connected to the charge pump unit.

[0021] Optionally, the comparison unit includes: a comparator; a first input terminal of the comparator is suitable for receiving a reference signal, a second input terminal of the comparator is suitable for receiving a voltage-divided signal, and an output terminal of the comparator is suitable for outputting a feedback signal.

[0022] Optionally, the charge pump circuit further includes: a voltage divider circuit connected to the second input terminal of the comparator and suitable for generating a voltage divider signal.

[0023] Optionally, the charge pump circuit further includes: a reference circuit connected to the first input terminal of the comparator and suitable for generating a reference signal.

[0024] Correspondingly, the present invention also provides a charge pump system, comprising a plurality of the above-mentioned charge pump circuits cascaded to each other, each of the charge pump circuits comprising an input end and an output end, and the output end of the charge pump circuit of the previous stage is connected to the input end of the charge pump circuit of the next stage.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the technical solution of the present invention, a signal processing unit is added to the charge pump circuit, and the feedback signal is adjusted by the signal processing unit to obtain a processed feedback signal with an increased duty cycle. Since the processed feedback signal remains in the first level state during the period when the clock signal is in the second level state, the driving signal can drive the charge pump unit to remain in the on state and perform a boost process until the preset voltage value is reached during the period when the clock signal is in the second level state, and the charge pump unit will not be converted from the on state to the off state due to the change in the state of the processed feedback signal, resulting in a reduction in the boost time of the charge pump unit and failure to reach the preset voltage value, thereby improving the boost performance of the charge pump.

[0027] Furthermore, since the processed feedback signal is synchronized with the clock signal, the time length that the clock signal is in the second level state is equal to the time length that the processed feedback signal remains in the first level state, thereby reducing the increase in power consumption caused by the processed feedback signal remaining in the first level state for too long, thereby reducing the power consumption of the charge pump as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1It is a schematic diagram of the structure of a charge pump circuit;

[0029] Figure 2 It is a timing diagram of some signals of a charge pump circuit;

[0030] Figure 3 is a schematic structural diagram of a charge pump circuit in an embodiment of the present invention;

[0031] Figure 4 is a schematic structural diagram of another charge pump circuit in an embodiment of the present invention;

[0032] Figure 5 is a timing diagram of some signals of a charge pump circuit in an embodiment of the present invention;

[0033] Figure 6 is a schematic structural diagram of a charge pump circuit when a clock signal and a processed feedback signal are synchronized in an embodiment of the present invention;

[0034] Figure 7 is a schematic structural diagram of another charge pump circuit when the clock signal and the processed feedback signal are synchronized in an embodiment of the present invention;

[0035] Figure 8 is a structural schematic diagram of another charge pump circuit when the clock signal and the processed feedback signal are synchronized in an embodiment of the present invention;

[0036] Fig. 9 is a timing diagram of part of the signals of another charge pump circuit in an embodiment of the present invention;

[0037] Fig.10 It is a structural schematic diagram of a charge pump system in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The current charge pump circuit has poor voltage boosting performance, which reduces the voltage boosting performance of the charge pump circuit.

[0039] Figure 1 This is a schematic diagram of the structure of a charge pump circuit. Figure 1 The charge pump circuit includes: a comparator 11, adapted to receive a reference signal VREF and a voltage-divided signal VDET, and compare the reference signal VREF with the voltage-divided signal VDET to obtain a feedback signal F1; a driving unit 12, connected to the comparator 11, adapted to receive the feedback signal F1 and a clock signal CLK, and output a driving signal based on the feedback signal F1 and the clock signal CLK; a charge pump unit 13, connected to the driving unit 12, adapted to receive the driving signal D1, and turned on or off according to the driving signal D1.

[0040] Figure 2Schematic diagram of the timing of some signals of the charge pump circuit.

[0041] The boost performance of the charge pump unit in the above scheme is poor. For details, refer to Figure 2 , between t1 and t3, the feedback signal F1 is at a low level, and between t1 and t2, the clock signal CLK is at a high level. It can be seen that the time when the feedback signal F1 is at a low level is shorter than the time when the clock signal CLK is at a high level. Since the feedback signal F1 is at a low level when the clock signal CLK is at a high level, the drive signal D1 is also at a high level during the period when the clock signal CLK is at a high level, thereby driving the charge pump unit to remain in the on state and perform a voltage boost process until the preset voltage value is reached. However, the feedback signal F1 in this solution is converted from a low level to a high level at t3, so that the drive signal D1 is converted from a high level to a low level at t3, causing the drive signal D1 to turn off the charge pump unit in advance at t3, so that the charge pump unit is converted from the on state to the off state, thereby reducing the boost time of the charge pump unit, failing to reach the preset voltage value, and reducing the boost performance of the charge pump unit.

[0042] In order to solve the above technical problems, the present invention provides a charge pump circuit, by setting a signal processing unit between a comparison unit and a driving unit, and the signal processing unit adjusts the feedback signal, increases the duty cycle of the feedback signal, and thus increases the time that the feedback signal is in the first level state. During the period when the clock signal is in the second level state, the processed feedback signal remains in the first level state, and the driving signal can turn on the charge pump unit during the period when the clock signal is in the second level state, and perform a voltage boost process until a preset voltage value is reached, so as to avoid the charge pump unit being converted from an on state to an off state due to a change in the state of the processed feedback signal, resulting in a reduction in the boost time of the charge pump unit and failure to reach the preset voltage value, thereby improving the boost performance of the charge pump.

[0043] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0044] refer to Figure 3 , an embodiment of the present invention provides a charge pump circuit, the charge pump circuit comprising:

[0045] The comparison unit 21 is adapted to receive a reference signal VREF and a voltage-divided signal VDET, and compare the reference signal VREF with the voltage-divided signal VDET to obtain a feedback signal F1;

[0046] a signal processing unit 22 connected to the comparison unit 21, adapted to receive the feedback signal F1, and process the feedback signal F1 to obtain a processed feedback signal F2, wherein the duty cycle of the processed feedback signal F2 is greater than the duty cycle of the feedback signal F1;

[0047] The driving unit 23 is connected to the signal processing unit 22, and is adapted to receive the clock signal CLK and the processed feedback signal F2, and perform an OR operation on the clock signal CLK and the processed feedback signal F2 to obtain a driving signal D1;

[0048] and a charge pump unit 24 connected to the driving unit 23, adapted to receive the driving signal D1, and to be turned on or off under the control of the driving signal D1;

[0049] Wherein, while the clock signal CLK is in the second level state, the processed feedback signal F2 is maintained in the first level state; the first level state and the second level state are logically opposite.

[0050] In one embodiment, the first level state is a low level, and the second level state is a high level.

[0051] In another embodiment, the first level state is a high level, and the second level state is a low level.

[0052] In some embodiments of the present invention, the signal processing unit 22 is further adapted to receive a processing signal, and perform delay processing on the feedback signal F1 based on the processing signal to obtain the processed feedback signal F2.

[0053] In a specific embodiment, the signal processing unit 22 can perform multiple logical operations on the feedback signal F1 and the processed signal to obtain a processed feedback signal F2, such as NOR operation, NAND operation, OR operation and AND operation, etc., which can be specifically set as needed.

[0054] In an embodiment of the present invention, the driving unit 23 may perform a NOR operation on the clock signal CLK and the processed feedback signal F2 to obtain the driving signal D1 .

[0055] The duty cycle of the processed feedback signal F2 is: the ratio of the time that the processed feedback signal F2 is in the first level state to the entire cycle time within one cycle; the duty cycle of the feedback signal F1 is: the ratio of the time that the feedback signal F1 is in the first level state to the entire cycle time within one cycle.

[0056] In one embodiment, the duty cycle of the processing signal is greater than the duty cycle of the clock signal CLK.

[0057] Among them, the duty cycle of the processing signal is: the ratio of the time that the processing signal is in the second level state to the entire cycle time in one cycle; the duty cycle of the clock signal CLK is: the ratio of the time that the clock signal CLK is in the second level state to the entire cycle time in one cycle.

[0058] It can be seen that the time that the processed feedback signal F2 is in the first level state is greater than the time that the feedback signal is in the first level state, and while the clock signal CLK is in the second level state, the processed feedback signal F2 remains in the first level state, so that during the period when the clock signal CLK is in the second level state, the drive signal D1 can drive the charge pump unit to remain in the on state, and the charge pump unit will not be converted from the on state to the off state due to the change in the state of the processed feedback signal F2, resulting in a reduction in the boost time of the charge pump unit and failure to reach the preset voltage value, thereby improving the boost performance of the charge pump.

[0059] In one embodiment of the present invention, reference Figure 4 The comparison unit may be a comparator COMP, a first input terminal of the comparator COMP is suitable for receiving a reference signal VREF, a second input terminal of the comparator COMP is suitable for receiving a voltage-divided signal VDET, and an output terminal of the comparator COMP is suitable for outputting a feedback signal F1.

[0060] In one embodiment, the comparator COMP further includes a power supply voltage terminal VCC and a ground terminal GND, wherein the power supply voltage terminal VCC is suitable for pulling up the output terminal of the comparator COMP to a high level, and the ground terminal GND is suitable for pulling down the output terminal of the comparator COMP to a low level.

[0061] In a specific embodiment, the comparator COMP is suitable for comparing the reference voltage and the divided voltage, and outputting a feedback signal of a first level state when the divided voltage is smaller than the reference voltage, and outputting a feedback signal of a second level state when the divided voltage is larger than the reference voltage.

[0062] In one embodiment, the driving unit 23 includes: a fourth NOR gate NOR4 and a third inverter INV3; wherein:

[0063] The first input end of the fourth NOR gate NOR4 is suitable for receiving the clock signal CLK, the second input end of the fourth NOR gate NOR4 is suitable for receiving the processed feedback signal F2, the output end of the fourth NOR gate NOR4 is connected to the input end of the third inverter INV3; the output end of the third inverter INV3 is connected to the charge pump unit 24.

[0064] In one embodiment, the charge pump circuit further includes: a voltage divider circuit connected to the second input terminal of the comparator COMP and adapted to generate a voltage divider signal VDET; and a reference circuit connected to the first input terminal of the comparator COMP and adapted to generate a reference signal VREF.

[0065] The voltage division signal is generated by a voltage division circuit. Specifically, the voltage division signal may be a voltage division voltage signal.

[0066] The reference signal is generated by a comparator. Specifically, the reference signal may be a reference voltage signal.

[0067] The comparison unit may generate a feedback signal by comparing the voltage of the voltage-divided signal with the voltage of the reference signal. The feedback signal may be a continuous square wave signal.

[0068] In a specific embodiment, the comparison unit can control the feedback signal to be in a first level state when the divided voltage is less than the reference voltage, and control the feedback signal to be in a second level state when the divided voltage is greater than the reference voltage, so that the feedback signal F1 obtained is a continuous square wave signal.

[0069] In a specific embodiment, the voltage divider circuit may include: a first resistor R1 and a second resistor R2, the charge pump includes an output end, the first end of the first resistor R1 is connected to the output end OUT of the charge pump, that is, suitable for inputting the output voltage of the charge pump, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and is suitable for outputting the divided voltage VDET, and the second end of the second resistor R2 is grounded GND.

[0070] The first resistor R1 and the second resistor R2 divide the output voltage of the charge pump to obtain a divided voltage VDET, and the voltage value of the divided voltage VDET is related to the output voltage of the charge pump and the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0071] In one embodiment, the charge pump unit 24 is a charge pump PUMP.

[0072] In a specific embodiment, the charge pump circuit can adjust the output voltage of the charge pump PUMP through a comparator so that it is stabilized at a set target value. Specifically, the comparator COMP compares the output voltage of the charge pump PUMP with a reference voltage, and then adjusts the working state of the charge pump PUMP according to the comparison result to achieve the purpose of stabilizing the output voltage.

[0073] In some embodiments of the present invention, the charge pump circuit further includes: a third delayer Delay3 , wherein the third delayer Delay3 is connected to the signal processing unit 22 .

[0074] In some embodiments of the present invention, the processing signal S1 is generated by the clock signal CLK, and the clock signal CLK is delayed by a third delayer Delay3 to obtain the processing signal S1.

[0075] Figure 5 1 is a timing diagram of some signals of a charge pump circuit according to an embodiment of the present invention. Figure 5 , taking the first level state as a low level (i.e., logic "0") and the second level state as a high level (i.e., logic "1") as an example, between time t1 and time t2, the processed feedback signal F2 is a low level, and between time t3 and time t4, the clock signal CLK is a high level. It can be seen that the time when the processed feedback signal F2 is a low level is longer than that when the clock signal CLK is a high level, and time t1 is earlier than time t3, and time t2 is later than time t4. Therefore, during the period when the clock signal CLK is a high level, the processed feedback signal F2 is a low level. After the subsequent NOR operation of the fourth NOR gate NOR4 and the inversion processing of the third inverter INV3, the obtained drive signal D1 is a high level, which can drive the charge pump unit to remain in the on state and perform a boost process until the preset voltage value is reached, thereby ensuring the boost performance of the charge pump. In the embodiment of the present invention, the processed feedback signal F2 is converted from a low level to a high level at time t2, and the drive signal D1 is at a low level at this time. The drive signal D1 maintains a low level state from time t4 to time t2, that is, the charge pump unit 24 is in an off state from time t4 to time t2, thereby avoiding the charge pump unit 24 from continuously converting from an on state to an off state due to the state change of the processed feedback signal F2, thereby improving the boost performance of the charge pump.

[0076] In another embodiment of the present invention, the processed feedback signal F3 is synchronized with the clock signal CLK. Specifically, the duty cycle of the processed feedback signal F3 is the same as the duty cycle of the clock signal CLK, and the falling edge of the processed feedback signal F3 is aligned with the rising edge of the clock signal CLK, and the rising edge of the processed feedback signal F3 is aligned with the falling edge of the clock signal CLK.

[0077] Among them, the duty cycle of the processed feedback signal F3 is: the ratio of the time that the processed feedback signal F3 is in the first level state to the entire cycle time in one cycle; the duty cycle of the clock signal CLK is: the ratio of the time that the clock signal CLK is in the second level state to the entire cycle time in one cycle.

[0078] Specifically, refer to Figure 6 , the signal processing unit 22 includes:

[0079] A pulse signal generating module 221, connected to the comparing unit 21, adapted to receive the processed signal S1 and generate a pulse signal according to the processed signal S1;

[0080] The sampling module 222 is connected to the pulse signal generating module 221, and is adapted to receive the feedback signal F1 and the pulse signal, and to sample the feedback signal F1 according to the pulse signal to obtain the processed feedback signal F3 synchronized with the clock signal CLK.

[0081] In one embodiment, the duty cycle of the processing signal S1 is equal to the duty cycle of the clock signal CLK, that is, the processing signal S1 at this time is the clock signal CLK.

[0082] In one embodiment of the present invention, reference Figure 7 , the pulse signal generating module 221 includes:

[0083] The first submodule 2211 is adapted to receive the processing signal S1 and process the rising edge of the processing signal S1 to obtain a first sub-pulse signal;

[0084] The second submodule 2212 is connected in parallel with the first submodule 2211, and is adapted to receive the processing signal S1, and process the falling edge of the processing signal S1 to obtain a second sub-pulse signal;

[0085] The merging submodule 2213 is connected to the first submodule 2211 and the second submodule 2212, and is suitable for receiving the first sub-pulse signal and the second sub-pulse signal, and merging the first sub-pulse signal and the second sub-pulse signal to obtain the pulse signal.

[0086] In one embodiment of the present invention, reference Figure 8 , the first submodule 2211 includes: a first inverter INV1, a first delayer Delay1, and a first NOR gate NOR1; wherein:

[0087] The input end of the first inverter INV1 is suitable for receiving the processing signal S1, the output end of the first inverter INV1 is connected to the input end of the first delayer Delay1; the output end of the first delayer Delay1 is connected to the second input end of the first NOR gate NOR1;

[0088] The first input terminal of the first NOR gate NOR1 is suitable for receiving the processing signal S1 , and the output terminal of the first NOR gate NOR1 is suitable for outputting a first sub-pulse signal.

[0089] In a specific embodiment, the first delay device Delay1 is suitable for generating a pulse when the processed signal is at a falling edge, and the feedback signal can be subsequently sampled according to this pulse, and the time between adjacent pulses can be adjusted so that the falling edge of the processed feedback signal can be aligned with the rising edge of the processed signal, and the rising edge of the processed feedback signal can be aligned with the falling edge of the processed signal.

[0090] In one embodiment of the present invention, the second submodule 2212 includes: a second inverter INV2, a second delayer Delay2, and a second NOR gate NOR2; wherein:

[0091] The input end of the second inverter INV2 is suitable for receiving the processing signal S1, the output end of the second inverter INV2 is connected to the input end of the second delayer Delay2; the output end of the second delayer Delay2 is connected to the second input end of the second NOR gate NOR2;

[0092] The first input terminal of the second NOR gate NOR2 is suitable for receiving the processing signal S1 , and the output terminal of the second NOR gate NOR2 is suitable for outputting a second sub-pulse signal.

[0093] In a specific embodiment, the second delay device Delay2 is suitable for generating a pulse when the processed signal is at a rising edge, and the feedback signal can be subsequently sampled according to this pulse, and the time between adjacent pulses can be adjusted so that the falling edge of the processed feedback signal can be aligned with the rising edge of the processed signal, and the rising edge of the processed feedback signal can be aligned with the falling edge of the processed signal.

[0094] In one embodiment of the present invention, the merging submodule 2213 includes: a third NOR gate NOR3;

[0095] The first input end of the third NOR gate NOR3 is suitable for receiving the first sub-pulse signal, the second input end of the third NOR gate NOR3 is suitable for receiving the second sub-pulse signal, and the output end of the third NOR gate NOR3 is suitable for outputting the pulse signal.

[0096] In one embodiment of the present invention, the sampling module 222 includes: a trigger 2221;

[0097] The first input terminal of the trigger 2221 is suitable for receiving the feedback signal F1, the second input terminal of the trigger 2221 is suitable for receiving a pulse signal, and the output terminal of the trigger 2221 is suitable for outputting the feedback signal F3 after synchronization processing.

[0098] In one embodiment, the trigger 2221 further includes a reset terminal RN.

[0099] Fig. 9 FIG. 1 is a timing diagram of part of the signals of another charge pump circuit according to an embodiment of the present invention. Fig. 9 , taking the first level state as a low level (i.e., logic "0") and the second level state as a high level (i.e., logic "1") as an example, between time t1 and time t2, the processed feedback signal F3 is a low level, and between time t1 and time t2, the clock signal CLK is a high level. It can be seen that the time when the processed feedback signal F3 is a low level is equal to the time when the clock signal CLK is a high level. Therefore, during the period when the clock signal CLK is a high level, the processed feedback signal F3 is a low level. After the subsequent NOR operation of the fourth NOR gate NOR4 and the inversion processing of the third inverter INV3, the obtained driving signal is a high level, which can drive the charge pump unit to remain in the on state and perform a boost processing until the preset voltage value is reached, thereby ensuring the boost performance of the charge pump. The processed feedback signal F3 is converted from a high level to a low level at time t1, and the corresponding clock signal CLK is converted from a low level to a high level at time t1. The processed feedback signal F3 is converted from a low level to a high level at time t2, and the corresponding clock signal CLK is converted from a high level to a low level at time t2, that is, the processed feedback signal F3 is synchronized with the clock signal CLK, thereby reducing the increase in power consumption of the charge pump circuit due to the long time that the processed feedback signal F3 remains at a high level, thereby reducing the power consumption of the charge pump circuit as much as possible.

[0100] In one embodiment, when the above-mentioned charge pump circuit is adopted and the processed feedback signal F3 is synchronized with the clock signal CLK, the power consumption of the charge pump circuit can be reduced from 900 microamperes to 700 microamperes.

[0101] In summary, the present invention can obtain a processed feedback signal with an increased duty cycle by setting a signal processing unit and adjusting the feedback signal through the signal processing unit. Since the processed feedback signal remains in the first level state during the period when the clock signal is in the second level state, the driving signal can drive the charge pump unit to remain in the on state and perform a boost process until the preset voltage value is reached during the period when the clock signal is in the second level state, and the charge pump unit will not be converted from the on state to the off state due to the change in the state of the processed feedback signal, resulting in a reduction in the boost time of the charge pump unit and failure to reach the preset voltage value, thereby improving the boost performance of the charge pump.

[0102] The embodiment of the present invention further provides a charge pump system, referring to Fig.10The charge pump system may include a plurality of the charge pump circuits 20 described above which are cascaded with each other, each of the charge pump circuits 20 including an input terminal and an output terminal, the output terminal of the charge pump circuit of the previous stage is connected to the input terminal of the charge pump circuit of the next stage, and the input terminal VIN of the charge pump circuit of the first stage is suitable for receiving an initial voltage.

[0103] In a specific embodiment, the charge pump circuit further includes a driving input terminal, a power input terminal VDD and a ground terminal GND, wherein the driving input terminal is used to receive a driving signal D1.

[0104] In the above scheme, after the charge pump system adopts the above-mentioned charge pump circuit, the charge pump circuits at each level in the charge pump system can realize that when the clock signal is in the second level state, the driving signal can drive the charge pump unit to remain in the on state and perform a voltage boosting process until the preset voltage value is reached, and provide sufficient input voltage for the next level charge pump circuit, thereby ensuring the voltage boosting performance of the charge pump system; and the time duration that the clock signal in each level of the charge pump circuit in the charge pump system is in the second level state is equal to the time duration that the processed feedback signal remains in the first level state, thereby reducing the power consumption of the charge pump circuits at each level due to the excessively long time duration that the processed feedback signal remains in the first level state, thereby reducing the power consumption of the charge pump circuits at each level, thereby reducing the power consumption of the charge pump system.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A charge pump circuit, It is characterized in that include: A comparison unit, adapted to receive a reference signal and a voltage-divided signal, and compare the reference signal with the voltage-divided signal to obtain a feedback signal; a signal processing unit connected to the comparison unit, adapted to receive the feedback signal and process the feedback signal to obtain a processed feedback signal, wherein the duty cycle of the processed feedback signal is greater than the duty cycle of the feedback signal; a driving unit connected to the signal processing unit, adapted to receive a clock signal and a processed feedback signal, and perform an OR operation on the clock signal and the processed feedback signal to obtain a driving signal; and a charge pump unit connected to the driving unit, adapted to receive the driving signal and be turned on or off under the control of the driving signal; Wherein, while the clock signal is in the second level state, the processed feedback signal remains in the first level state; the first level state and the second level state are logically opposite.

2. The charge pump circuit according to claim 1, It is characterized in that The signal processing unit is further adapted to receive a processing signal, and perform delay processing on the feedback signal based on the processing signal to obtain the processed feedback signal.

3. The charge pump circuit as claimed in claim 2, It is characterized in that The processed feedback signal is synchronized with the clock signal.

4. The charge pump circuit as claimed in claim 3, It is characterized in that The signal processing unit comprises: a pulse signal generating module connected to the comparison unit, adapted to receive a processing signal and generate a pulse signal according to the processing signal; The sampling module is connected to the pulse signal generating module, and is suitable for receiving the feedback signal and the pulse signal, and sampling the feedback signal according to the pulse signal to obtain the processed feedback signal synchronized with the clock signal.

5. The charge pump circuit as claimed in claim 4, It is characterized in that The pulse signal generating module comprises: A first submodule, adapted to receive the processing signal and process the rising edge of the processing signal to obtain a first sub-pulse signal; A second submodule, connected in parallel with the first submodule, adapted to receive the processing signal and process the falling edge of the processing signal to obtain a second sub-pulse signal; The merging submodule is connected to the first submodule and the second submodule, and is suitable for receiving the first sub-pulse signal and the second sub-pulse signal, and merging the first sub-pulse signal and the second sub-pulse signal to obtain the pulse signal.

6. The charge pump circuit as claimed in claim 5, It is characterized in that The first submodule includes: a first inverter, a first delayer, and a first NOR gate; wherein: The input end of the first inverter is suitable for receiving the processing signal, the output end of the first inverter is connected to the input end of the first delayer; the output end of the first delayer is connected to the second input end of the first NOR gate; The first input end of the first NOR gate is suitable for receiving the processing signal, and the output end of the first NOR gate is suitable for outputting a first sub-pulse signal.

7. The charge pump circuit as claimed in claim 5, It is characterized in that The second submodule includes: a second inverter, a second delayer, and a second NOR gate; wherein: The input end of the second inverter is suitable for receiving the processing signal, the output end of the second inverter is connected to the input end of the second delayer; the output end of the second delayer is connected to the second input end of the second NOR gate; The first input terminal of the second NOR gate is suitable for receiving the processing signal, and the output terminal of the second NOR gate is suitable for outputting a second sub-pulse signal.

8. The charge pump circuit as claimed in claim 5, It is characterized in that The merging submodule comprises: a third NOR gate; The first input end of the third NOR gate is suitable for receiving the first sub-pulse signal, the second input end of the third NOR gate is suitable for receiving the second sub-pulse signal, and the output end of the third NOR gate is suitable for outputting the pulse signal.

9. The charge pump circuit as claimed in claim 4, It is characterized in that The sampling module includes: a trigger; The first input terminal of the trigger is suitable for receiving the feedback signal, the second input terminal of the trigger is suitable for receiving a pulse signal, and the output terminal of the trigger is suitable for outputting the feedback signal after synchronization processing.

10. The charge pump circuit according to claim 1, It is characterized in that The driving unit comprises: a fourth NOR gate and a third inverter; wherein: The first input end of the fourth NOR gate is suitable for receiving the clock signal, the second input end of the fourth NOR gate is suitable for receiving the processed feedback signal, and the output end of the fourth NOR gate is connected to the input end of the third inverter; An output terminal of the third inverter is connected to the charge pump unit.

11. The charge pump circuit according to claim 1, It is characterized in that The comparison unit comprises: a comparator; a first input terminal of the comparator is suitable for receiving a reference signal, a second input terminal of the comparator is suitable for receiving a voltage-divided signal, and an output terminal of the comparator is suitable for outputting a feedback signal.

12. The charge pump circuit according to claim 1, It is characterized in that Also includes: The voltage divider circuit is connected to the second input terminal of the comparator and is suitable for generating a voltage divider signal.

13. The charge pump circuit according to claim 1, It is characterized in that Also includes: The reference circuit is connected to the first input terminal of the comparator and is suitable for generating a reference signal.

14. A charge pump system, It is characterized in that Comprising a plurality of charge pump circuits as claimed in any one of claims 1 to 13 which are cascaded to each other, each of the charge pump circuits comprising an input terminal and an output terminal, and the output terminal of the charge pump circuit of the previous stage is connected to the input terminal of the charge pump circuit of the next stage.

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