Self-biased LVDS drive circuit, serial circuit chip and electronic equipment

Abstract

The present invention discloses a self-biased LVDS driving circuit, a serial circuit chip and an electronic device, and relates to the field of semiconductor circuit technology. The self-biased LVDS driving circuit includes a current source module, a transmitter module and a common-mode feedback circuit module. The common-mode feedback circuit is constructed by parallel transistors, and the common-mode voltage is extracted and input into the parallel transistor gate through a transmission gate. When the common-mode voltage changes, the gate voltage of the parallel transistor changes accordingly, and the parallel transistor on-resistance also changes accordingly, thereby realizing negative feedback control of the common-mode voltage, and finally realizing the clamping of the common-mode voltage. At the same time, the control range can be autonomously adjusted by changing the number of parallel transistors turned on. The present invention does not need to use an amplifier and a compensation capacitor to design a common-mode feedback circuit, which can effectively avoid loop stability problems, while reducing the area and power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor circuits, and in particular to a self-biased LVDS driving circuit, a serial circuit chip and an electronic device. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) is a differential signaling technology with low power consumption, low bit error rate, low crosstalk and low radiation. LVDS technology uses extremely low voltage swing to transmit data at high speed differentially, and can achieve point-to-point or point-to-multipoint connection. In order to reduce the impact of common-mode voltage jitter on the signal receiving end during data transmission and make the common-mode voltage more stable, the LVDS drive circuit usually uses a common-mode feedback circuit to control the common-mode voltage of the output signal. In the prior art, the common-mode feedback circuit usually designs an amplifier and a larger-sized Maitreya compensation capacitor, and places the main pole of the loop at the output end of the amplifier to ensure the stability of the loop. At the same time, it also requires a larger operating current, so there are problems of large area and high power consumption. If the amplifier and compensation capacitor are not designed reasonably, there will be loop stability problems. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a self-biased LVDS drive circuit, a serial circuit chip and an electronic device, which construct a common-mode feedback circuit by using parallel transistors to achieve negative feedback control of the common-mode voltage, and adjust the common-mode voltage control range by changing the number of parallel transistors turned on, while reducing the area and reducing power consumption.

[0004] In a first aspect, an embodiment of the present invention provides a self-biased LVDS driving circuit, comprising: a current source module, a transmitter module and a common-mode feedback circuit module;

[0005] The first end of the current source module is connected to the external bias current, the second end of the current source module is connected to the first end of the transmitter module, the second end of the transmitter module is connected to a reverse differential signal, the third end of the transmitter module is connected to a forward differential signal, the fifth end of the transmitter module outputs a reverse differential signal, the sixth end of the transmitter module outputs a forward differential signal, the fourth end of the transmitter module is connected to the first end of the common mode feedback circuit module, the second end of the common mode feedback circuit module is connected to the fifth end of the transmitter module, and the third end of the common mode feedback circuit module is connected to the sixth end of the transmitter module;

[0006] The current source module is used to provide driving current for the transmitter module and the common-mode feedback circuit module; the transmitter module sends the connected forward differential signal and reverse differential signal to the downstream receiver through the driving current; the common-mode feedback circuit module is used to feedback and adjust the common-mode voltage.

[0007] Optionally, in some embodiments of the present invention, the current source module includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0008] The first end of the first transistor is connected to an external bias current, the second end of the first transistor is connected to the first end of the first transistor and the second end of the second transistor, the third end of the first transistor is grounded, the third end of the second transistor is grounded, the first end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the first end of the third transistor and the second end of the fourth transistor, the third end of the third transistor is connected to a power supply, the third end of the fourth transistor is connected to a power supply, and the first end of the fourth transistor is connected to the first end of the transmitter module.

[0009] Optionally, in some embodiments of the present invention, the transmitter module includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0010] The third end of the fifth transistor is connected to the second end of the current source module, the second end of the fifth transistor is connected to the second end of the seventh transistor and is connected to a reverse differential signal, the first end of the fifth transistor is connected to the first end of the seventh transistor and outputs a forward differential signal, the third end of the sixth transistor is connected to the second end of the current source module, the second end of the sixth transistor is connected to the second end of the eighth transistor and is connected to a forward differential signal, the first end of the sixth transistor is connected to the first end of the eighth transistor and outputs a reverse differential signal, and the third end of the seventh transistor and the third end of the eighth transistor are connected to the first end of the common-mode feedback circuit module.

[0011] Optionally, in some embodiments of the present invention, the common-mode feedback circuit module includes a ninth transistor, a tenth transistor, an eleventh transistor, a first transmission gate, a second transmission gate, a third transmission gate, a first resistor, and a second resistor;

[0012] A first end of the ninth transistor is connected to a fourth end of the transmitter module, a second end of the ninth transistor is connected to a second end of the first transmission gate, a third end of the ninth transistor is grounded, a first end of the first transmission gate is connected to a second end of the first resistor and a second end of the second resistor, a first end of the tenth transistor is connected to a fourth end of the transmitter module, a second end of the tenth transistor is connected to a second end of the second transmission gate, a third end of the tenth transistor is grounded, a first end of the second transmission gate is connected to a second end of the first resistor and a second end of the second resistor, a first end of the eleventh transistor is connected to a fourth end of the transmitter module, a second end of the eleventh transistor is connected to a second end of the third transmission gate, a third end of the eleventh transistor is grounded, a first end of the third transmission gate is connected to a second end of the first resistor and a second end of the second resistor, a first end of the first resistor is connected to a sixth end of the transmitter module, and a first end of the second resistor is connected to a fifth end of the transmitter module.

[0013] Optionally, in some embodiments of the present invention, the first transistor and the second transistor are both NMOS transistors, and the third transistor and the fourth transistor are both PMOS transistors;

[0014] The first ends of the first transistor and the second transistor are both drains of the NMOS tube, the second ends are both gates of the NMOS tube, and the third ends are both sources of the NMOS tube. The first ends of the third transistor and the fourth transistor are both drains of the PMOS tube, the second ends are both gates of the PMOS tube, and the third ends are both sources of the PMOS tube.

[0015] Optionally, in some embodiments of the present invention, the fifth transistor and the sixth transistor are both PMOS transistors, and the seventh transistor and the eighth transistor are both NMOS transistors;

[0016] The first ends of the fifth transistor and the sixth transistor are both drains of the PMOS tube, the second ends are both gates of the PMOS tube, and the third ends are both sources of the PMOS tube. The first ends of the seventh transistor and the eighth transistor are both drains of the NMOS tube, the second ends are both gates of the NMOS tube, and the third ends are both sources of the NMOS tube.

[0017] Optionally, in some embodiments of the present invention, the ninth transistor, the tenth transistor and the eleventh transistor are all NMOS transistors, the first ends of the ninth transistor, the tenth transistor and the eleventh transistor are all drains of the NMOS tubes, the second ends are all gates of the NMOS tubes, and the third ends are all sources of the NMOS tubes.

[0018] The first transmission gate, the second transmission gate and the third transmission gate are all composed of a CMOS transmission gate and an internal NMOS tube, wherein the output end of the CMOS transmission gate is connected to the drain of the internal NMOS tube, the gate of the internal NMOS tube is connected to the low level effective end of the CMOS transmission gate, and the source of the internal NMOS tube is grounded;

[0019] The first ends of the first transmission gate, the second transmission gate and the third transmission gate are all input ends of the CMOS transmission gate, and the second ends are all output ends of the CMOS transmission gate.

[0020] Optionally, in some embodiments of the present invention, the current source module includes a twelfth transistor and a thirteenth transistor; the twelfth transistor and the thirteenth transistor are both NMOS transistors;

[0021] The transmitter module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor; the fourteenth transistor and the fifteenth transistor are both NMOS transistors, and the sixteenth transistor and the seventeenth transistor are both PMOS transistors;

[0022] The common-mode feedback circuit module includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a third resistor and a fourth resistor; the eighteenth transistor, the nineteenth transistor and the twentieth transistor are all PMOS transistors; the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are all composed of CMOS transmission gates and internal PMOS transistors.

[0023] In a second aspect, an embodiment of the present invention provides a serial circuit chip, wherein the serial circuit chip comprises the self-biased LVDS driving circuit described in any one of the first aspects.

[0024] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the serial circuit chip, transmission medium and deserialization circuit chip described in the second aspect, wherein the transmission medium is arranged between the serial circuit chip and the deserialization circuit chip.

[0025] It can be seen from the above technical solutions that the embodiments of the present invention have the following advantages:

[0026] The embodiment of the present invention provides a self-biased LVDS drive circuit, a serial circuit chip and an electronic device. A common-mode feedback circuit is constructed by parallel transistors, and the common-mode voltage is extracted and input into the gate of the parallel transistor through a transmission gate. When the common-mode voltage changes, the gate voltage of the parallel transistor changes accordingly, and the on-resistance of the parallel transistor also changes accordingly, thereby realizing negative feedback control of the common-mode voltage, and finally realizing the clamping of the common-mode voltage. By changing the number of parallel transistors turned on, the control range can be adjusted autonomously, and there is no need to use amplifiers and compensation capacitors to design the common-mode feedback circuit, which can effectively avoid loop stability problems, while reducing area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0028] Figure 1 It is a structural block diagram of a self-biased LVDS driving circuit provided by an embodiment of the present invention;

[0029] Figure 2 It is a first specific example of a self-biased LVDS driving circuit provided by an embodiment of the present invention;

[0030] Figure 3 It is a schematic diagram of a transmission gate structure in a first specific example of a self-biased LVDS driving circuit provided by an embodiment of the present invention;

[0031] Figure 4 is a second specific example of a self-biased LVDS driving circuit provided by an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a transmission gate structure in a second specific example of a self-biased LVDS driving circuit provided by an embodiment of the present invention;

[0033] Figure 6 A structural block diagram of a serial circuit chip provided by an embodiment of the present invention;

[0034] Figure 7 A structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0037] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0038] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0039] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0040] See also Figure 1 The embodiment of the present invention provides a self-biased LVDS driving circuit 1, which includes a current source module 11, a transmitter module 12 and a common-mode feedback circuit module 13. The first end of the current source module 11 is connected to the external bias current ibias_input, the second end of the current source module 11 is connected to the first end of the transmitter module 12, the second end of the transmitter module 12 is connected to a reverse differential signal through the terminal pin TX_IN, the third end of the transmitter module 12 is connected to a forward differential signal through the terminal pin TX_IP, the fifth end of the transmitter module 12 outputs a reverse differential signal through the terminal pin TX_ON, the sixth end of the transmitter module 12 outputs a forward differential signal through the terminal pin TX_OP, the fourth end of the transmitter module 12 is connected to the first end of the common-mode feedback circuit module 13, the second end of the common-mode feedback circuit module 13 is connected to the fifth end of the transmitter module 12, and the third end of the common-mode feedback circuit module 13 is connected to the sixth end of the transmitter module 12;

[0041] The current source module 11 provides a stable driving current for the transmitter module 12 and the common-mode feedback circuit module 13; the transmitter module 12 sends the connected differential signal to the downstream receiver through the driving current; the common-mode feedback circuit module 13 is used to feedback and adjust the common-mode voltage.

[0042] refer to Figure 1 , 2 The embodiment of the present invention provides a self-biased LVDS driving circuit 1, which is composed of parallel NMOS tubes to construct a common-mode feedback circuit module. The specific circuit structure of each component module is described below.

[0043] Exemplarily, the current source module 11 may include but is not limited to a transistor Q1, a transistor Q2, a transistor Q3 and a transistor Q4;

[0044] Among them, the first end of the transistor Q1 (corresponding to the first end of the current source module 11) is connected to the external bias current, the second end of the transistor Q1 is connected to the first end of the transistor Q1 and the second end of the transistor Q2, the third end of the transistor Q1 is grounded, the third end of the transistor Q2 is grounded, the first end of the transistor Q2 is connected to the first end of the transistor Q3, the second end of the transistor Q3 is connected to the first end of the transistor Q3 and the second end of the transistor Q4, the third end of the transistor Q3 is connected to the power supply VDD, the third end of the transistor Q4 is connected to the power supply VDD, and the first end of the transistor Q4 (corresponding to the second end of the current source module 11) is connected to the first end of the transmitter module 12.

[0045] Optionally, in an embodiment of the present invention, transistor Q1 and transistor Q2 are both NMOS tubes, and transistor Q3 and transistor Q4 are both PMOS tubes; the first ends of transistor Q1 and transistor Q2 are both drains of the NMOS tubes, the second ends are both gates of the NMOS tubes, and the third ends are both sources of the NMOS tubes, and the first ends of transistor Q3 and transistor Q4 are both drains of the PMOS tubes, the second ends are both gates of the PMOS tubes, and the third ends are both sources of the PMOS tubes.

[0046] Exemplarily, the transmitter module 12 may include, but is not limited to, a transistor Q5 , a transistor Q6 , a transistor Q7 , and a transistor Q8 ;

[0047] The third end of transistor Q5 (corresponding to the first end of the transmitter module 12) is connected to the second end of the current source module 11, the second end of transistor Q5 is connected to the second end of transistor Q7 (corresponding to the second end of the transmitter module 12), and the reverse differential signal is connected through the terminal pin TX_IN, the first end of transistor Q5 is connected to the first end of transistor Q7 (corresponding to the sixth end of the transmitter module 12), and the forward differential signal is output through the terminal pin TX_OP, the third end of transistor Q6 (corresponding to the first end of the transmitter module 12) is connected to the second end of the current source module 11, the second end of transistor Q6 is connected to the second end of transistor Q8 (corresponding to the third end of the transmitter module 12), and the forward differential signal is connected through the terminal pin TX_IP, the first end of transistor Q6 is connected to the first end of transistor Q8 (corresponding to the fifth end of the transmitter module 12), and the reverse differential signal is output through the terminal pin TX_ON, and the third end of transistor Q7 and the third end of transistor Q8 (corresponding to the fourth end of the transmitter module 12) are connected to the first end of the common-mode feedback circuit module 13.

[0048] Optionally, in the embodiment of the present invention, both transistor Q5 and transistor Q6 are PMOS tubes, and both transistor Q7 and transistor Q8 are NMOS tubes; both first ends of transistor Q5 and transistor Q6 are drains of the PMOS tubes, both second ends are gates of the PMOS tubes, and both third ends are sources of the PMOS tubes; both first ends of transistor Q7 and transistor Q8 are drains of the NMOS tubes, both second ends are gates of the NMOS tubes, and both third ends are sources of the NMOS tubes;

[0049] Exemplarily, the common mode feedback circuit module 13 may include, but is not limited to, a transistor Q9, a transistor Q10, a transistor Q11, a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a resistor R1, and a resistor R2;

[0050] A first end of the transistor Q9 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, a second end of the transistor Q9 is connected to the second end of the transmission gate TG1, a third end of the transistor Q9 is grounded, a first end of the transmission gate TG1 is connected to the second end of the resistor R1 and the second end of the resistor R2, a first end of the transistor Q10 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, a second end of the transistor Q10 is connected to the second end of the transmission gate TG1, a third end of the transistor Q10 is grounded, a first end of the transmission gate TG2 is connected to the second end of the resistor R1 and the second end of the resistor R2, a first end of the transistor Q11 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, a second end of the transistor Q11 is connected to the second end of the transmission gate TG3, a third end of the transistor Q11 is grounded, a first end of the transmission gate TG3 is connected to the second end of the resistor R1 and the second end of the resistor R2, a first end of the resistor R1 is connected to the sixth end of the transmitter module 12, and a first end of the resistor R2 is connected to the fifth end of the transmitter module 12;

[0051] Among them, transistor Q9, transistor Q10 and transistor Q11 are all NMOS tubes, and the first ends of transistor Q9, transistor Q10 and transistor Q11 are all drains of the NMOS tubes, the second ends are all gates of the NMOS tubes, and the third ends are all sources of the NMOS tubes.

[0052] Among them, the transmission gate TG1, the transmission gate TG2 and the transmission gate TG3 are all composed of a transmission gate TG and an NMOS tube TG_N, see Figure 3 , wherein the output end of the transmission gate TG is connected to the drain of the NMOS tube TG_N, the gate of the NMOS tube TG_N is connected to the low level effective end of the transmission gate TG, and the source of the NMOS tube TG_N is grounded; the first ends of the transmission gates TG1, TG2 and TG3 are all the input ends of the transmission gate TG, and the second ends are all the output ends of the transmission gate TG.

[0053] The working process of the self-biased LVDS driving circuit 1 provided in this embodiment is as follows: the high-speed differential serial signal sent by the upper-level circuit is input into the self-biased LVDS driving circuit 1, the positive differential signal is input through the terminal pin TX_IP, and the reverse differential signal is input through the terminal pin TX_IN. By way of example, when the differential signal of the input terminal pin TX_IP is at a high level and the differential signal of the input terminal pin TX_IN is at a low level, transistors Q5 and Q8 are turned on, transistors Q6 and Q7 are turned off, and the output current of the current source module 11 is output through the drain of transistor Q4, and flows through the load resistor RL_100ohm at the next-level receiver end through the terminal pin TX_OP via transistor Q5, and then flows through the terminal pin TX_ON via transistor Q8, parallel transistors Q9, Q10, and Q11 to the ground. Conversely, the voltage generated by the load resistor RL_100ohm is the output signal. Different positive and negative levels are generated by changing the direction of the current flowing through the load resistor RL_100ohm to realize signal transmission. The common-mode voltage of the output signal is extracted through resistors R1 and R2, and the gates of the parallel NMOS tubes Q9, Q10, and Q11 are controlled to be connected to the extracted common-mode voltage or to ground through transmission gates TG1, TG2, and TG3. In the on-state, when the common-mode voltage increases, the gate voltages of the parallel NMOS tubes Q9, Q10, and Q11 increase accordingly, and their on-resistance decreases as the gate voltage increases, thereby reducing the common-mode voltage of the output signal. Conversely, the common-mode voltage is controlled by negative feedback through the change of the on-resistance of the parallel NMOS tubes, thereby clamping the common-mode voltage. At the same time, by controlling the transmission gate to change the number of parallel NMOS tubes turned on, the adjustment range of the common-mode voltage can be adjusted. In the embodiment of the present invention, the parallel NMOS tubes use three NMOS tubes. According to the actual process conditions and the accuracy of the adjustment range, it is not limited to using only three NMOS tubes. Preferably, the number of NMOS tubes in parallel is configured by Efuse (electronic fuse).

[0054] refer to Figure 1 , 4 5. The embodiment of the present invention further provides a self-biased LVDS driving circuit 1, in which a common-mode feedback circuit module is constructed by parallel PMOS tubes. The specific circuit structure of each component module is described below.

[0055] Exemplarily, the current source module 11 includes a transistor Q12 and a transistor Q13; the first end of the transistor Q12 (corresponding to the first end of the current source module 11) is connected to an external bias current, the second end of the transistor Q12 is connected to the first end of the transistor Q12 and the second end of the transistor Q13, the third end of the transistor Q12 is grounded, the first end of the transistor Q13 (corresponding to the second end of the current source module 11) is connected to the first end of the transmitter module 12, and the third end of the transistor Q13 is grounded; the transistor Q12 and the transistor Q13 are both NMOS tubes, the first ends of the transistor Q12 and the transistor Q13 are both drains of the NMOS tubes, the second ends are both gates of the NMOS tubes, and the third ends are both sources of the NMOS tubes;

[0056] Exemplarily, the transmitter module 12 includes a transistor Q14, a transistor Q15, a transistor Q16, and a transistor Q17; the third end of the transistor Q14 (corresponding to the first end of the transmitter module 12) is connected to the second end of the current source module 11, the second end of the transistor Q14 is connected to the second end of the transistor Q16, and is connected to a reverse differential signal, the first end of the transistor Q14 is connected to the first end of the transistor Q16, and outputs a forward differential signal, the third end of the transistor Q15 (corresponding to the first end of the transmitter module 12) is connected to the second end of the current source module 11, the second end of the transistor Q15 is connected to the second end of the transistor Q17, and is connected to a forward differential signal, the first end of the transistor Q15 is connected to the second end of the transistor Q17, and is connected to a forward differential signal, One end is connected to the first end of the transistor Q17 and outputs a reverse differential signal, and the third end of the transistor Q16 and the third end of the transistor Q17 (corresponding to the fourth end of the transmitter module 12) are connected to the first end of the common-mode feedback circuit module 13; the transistor Q14 and the transistor Q15 are both NMOS tubes, and the transistor Q16 and the transistor Q17 are both PMOS tubes; the first end of the transistor Q14 and the transistor Q15 are both the drain of the NMOS tube, the second end is both the gate of the NMOS tube, and the third end is both the source of the NMOS tube, the first end of the transistor Q16 and the transistor Q17 are both the drain of the PMOS tube, the second end is both the gate of the PMOS tube, and the third end is both the source of the PMOS tube;

[0057] Exemplarily, the common-mode feedback circuit module 13 includes a transistor Q18, a transistor Q19, a transistor Q20, a transmission gate TG4, a transmission gate TG5, a transmission gate TG6, a resistor R3 and a resistor R4; a first end of the transistor Q18 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, a second end of the transistor Q18 is connected to the second end of the transmission gate TG4, a third end of the transistor Q18 is connected to the power supply VDD, a first end of the transmission gate TG4 is connected to the second end of the resistor R3 and the second end of the resistor R4, a first end of the transistor Q19 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, a second end of the transistor Q19 is connected to the second end of the transmission gate TG5, a third end of the transistor Q19 is connected to the power supply VDD, and a first end of the transmission gate TG5 is connected to the second end of the transmission gate TG6. One end is connected to the second end of the resistor R3 and the second end of the resistor R4, the first end of the transistor Q20 (corresponding to the first end of the common-mode feedback circuit module 13) is connected to the fourth end of the transmitter module 12, the second end of the transistor Q20 is connected to the second end of the transmission gate TG6, the third end of the transistor Q20 is connected to the power supply VDD, and the first end of the transmission gate TG6 is connected to the second end of the resistor R3 and the second end of the resistor R4; wherein, the transistor Q18, the transistor Q19 and the transistor Q20 are all PMOS tubes, the first ends of the transistor Q18, the transistor Q19 and the transistor Q20 are all drains of the PMOS tubes, the second ends are all gates of the PMOS tubes, and the third ends are all sources of the PMOS tubes; the transmission gates TG4, the transmission gates TG5 and the transmission gates TG6 are all composed of the transmission gate TG and the PMOS tube TG_P, see Figure 5 , wherein the output end of the transmission gate TG is connected to the drain of the PMOS tube TG_P, the gate of the PMOS tube TG_P is connected to the high level effective end of the transmission gate TG, and the source of the PMOS tube TG_P is connected to the power supply; the first ends of the transmission gates TG4, TG5 and TG6 are all the input ends of the transmission gate TG, and the second ends are all the output ends of the transmission gate TG.

[0058] In this embodiment, the common mode voltage of the output signal is extracted through the resistor R3 and the resistor R4, and the gates of the parallel PMOS tubes Q18, Q19, and Q20 are controlled to be connected to the extracted common mode voltage or the power supply VDD through the transmission gates TG4, TG5, and TG6. In the on state, when the common mode voltage decreases, the gate voltage of the parallel PMOS tubes Q18, Q19, and Q20 decreases accordingly, and its on resistance decreases with the decrease of the gate voltage, thereby increasing the common mode voltage of the output signal, and vice versa, thereby realizing the control of the common mode voltage through the negative feedback of the parallel PMOS tubes, and realizing the clamping of the common mode voltage. At the same time, by controlling the transmission gate to change the number of parallel PMOS tubes turned on, the adjustment range of the common mode voltage can be adjusted.

[0059] In this embodiment, three PMOS tubes are used as the parallel PMOS tubes. According to the actual process conditions and the adjustment range accuracy, it is not limited to use only three PMOS tubes. Preferably, the number of parallel PMOS tubes is configured by Efuse.

[0060] See also Figure 6 The embodiment of the present invention further provides a serial circuit chip, and the serial circuit chip 2 may include but is not limited to the self-biased LVDS driving circuit 1 in the aforementioned embodiment.

[0061] See also Figure 7 The embodiment of the present invention further provides an electronic device, the electronic device 3 may include Figure 6 In the corresponding embodiment, the serial circuit chip 2, the transmission medium 31 and the deserialization circuit chip 32. The transmission medium 31 is arranged between the serial circuit chip 2 and the deserialization circuit chip 32, for example, the transmission medium 31 can be a copper PCB connection or a balanced cable.

[0062] The embodiment of the present invention provides a self-biased LVDS drive circuit, serial circuit chip and electronic device, which constructs a common-mode feedback circuit by connecting parallel transistors, extracts the common-mode voltage and inputs it into the gate of the parallel transistor through a transmission gate. When the common-mode voltage changes, the gate voltage of the parallel transistor changes accordingly, and the on-resistance of the parallel transistor also changes accordingly, thereby realizing negative feedback control of the common-mode voltage, and finally achieving the clamping of the common-mode voltage. Autonomous adjustment of the control range can be achieved by changing the number of parallel transistors that are turned on. There is no need to use amplifiers and compensation capacitors to design the common-mode feedback circuit, which can effectively avoid loop stability problems, while reducing area and power consumption.

[0063] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A self-biased LVDS driving circuit, characterized in that: include: A current source module, a transmitter module and a common mode feedback circuit module; The first end of the current source module is connected to the external bias current, the second end of the current source module is connected to the first end of the transmitter module, the second end of the transmitter module is connected to a reverse differential signal, the third end of the transmitter module is connected to a forward differential signal, the fifth end of the transmitter module outputs a reverse differential signal, the sixth end of the transmitter module outputs a forward differential signal, the fourth end of the transmitter module is connected to the first end of the common mode feedback circuit module, the second end of the common mode feedback circuit module is connected to the fifth end of the transmitter module, and the third end of the common mode feedback circuit module is connected to the sixth end of the transmitter module; The current source module is used to provide driving current for the transmitter module and the common mode feedback circuit module; the transmitter module sends the connected positive differential signal and reverse differential signal to the downstream receiver through the driving current; the common mode feedback circuit module is used to feedback and adjust the common mode voltage; The current source module includes a first transistor, a second transistor, a third transistor and a fourth transistor; The first end of the first transistor is connected to an external bias current, the second end of the first transistor is connected to the first end of the first transistor and the second end of the second transistor, the third end of the first transistor is grounded, the third end of the second transistor is grounded, the first end of the second transistor is connected to the first end of the third transistor, the second end of the third transistor is connected to the first end of the third transistor and the second end of the fourth transistor, the third end of the third transistor is connected to a power supply, the third end of the fourth transistor is connected to a power supply, and the first end of the fourth transistor is connected to the first end of the transmitter module; The transmitter module includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The third end of the fifth transistor is connected to the second end of the current source module, the second end of the fifth transistor is connected to the second end of the seventh transistor, and is connected to a reverse differential signal, the first end of the fifth transistor is connected to the first end of the seventh transistor, and outputs a forward differential signal, the third end of the sixth transistor is connected to the second end of the current source module, the second end of the sixth transistor is connected to the second end of the eighth transistor, and is connected to a forward differential signal, the first end of the sixth transistor is connected to the first end of the eighth transistor, and outputs a reverse differential signal, and the third end of the seventh transistor and the third end of the eighth transistor are connected to the first end of the common-mode feedback circuit module; The common-mode feedback circuit module includes a ninth transistor, a tenth transistor, an eleventh transistor, a first transmission gate, a second transmission gate, a third transmission gate, a first resistor and a second resistor; The first end of the ninth transistor is connected to the fourth end of the transmitter module, the second end of the ninth transistor is connected to the second end of the first transmission gate, the third end of the ninth transistor is grounded, the first end of the first transmission gate is connected to the second end of the first resistor and the second end of the second resistor, the first end of the tenth transistor is connected to the fourth end of the transmitter module, the second end of the tenth transistor is connected to the second end of the second transmission gate, the third end of the tenth transistor is grounded, the first end of the second transmission gate is connected to the second end of the first resistor and the second end of the second resistor, the first end of the eleventh transistor is connected to the fourth end of the transmitter module, the second end of the eleventh transistor is connected to the second end of the third transmission gate, the third end of the eleventh transistor is grounded, the first end of the third transmission gate is connected to the second end of the first resistor and the second end of the second resistor, the first end of the first resistor is connected to the sixth end of the transmitter module, and the first end of the second resistor is connected to the fifth end of the transmitter module; The first transistor and the second transistor are both NMOS transistors, and the third transistor and the fourth transistor are both PMOS transistors; The first end of the first transistor and the second transistor are both drains of NMOS tubes, the second ends are both gates of NMOS tubes, and the third ends are both sources of NMOS tubes; the first ends of the third transistor and the fourth transistor are both drains of PMOS tubes, the second ends are both gates of PMOS tubes, and the third ends are both sources of PMOS tubes; The fifth transistor and the sixth transistor are both PMOS transistors, and the seventh transistor and the eighth transistor are both NMOS transistors; The first ends of the fifth transistor and the sixth transistor are both drains of the PMOS tube, the second ends are both gates of the PMOS tube, and the third ends are both sources of the PMOS tube; the first ends of the seventh transistor and the eighth transistor are both drains of the NMOS tube, the second ends are both gates of the NMOS tube, and the third ends are both sources of the NMOS tube; The ninth transistor, the tenth transistor and the eleventh transistor are all NMOS transistors, the first ends of the ninth transistor, the tenth transistor and the eleventh transistor are all drains of the NMOS transistors, the second ends are all gates of the NMOS transistors, and the third ends are all sources of the NMOS transistors; The first transmission gate, the second transmission gate and the third transmission gate are all composed of a CMOS transmission gate and an internal NMOS tube, wherein the output end of the CMOS transmission gate is connected to the drain of the internal NMOS tube, the gate of the internal NMOS tube is connected to the low level effective end of the CMOS transmission gate, and the source of the internal NMOS tube is grounded; The first ends of the first transmission gate, the second transmission gate and the third transmission gate are all input ends of the CMOS transmission gate, and the second ends are all output ends of the CMOS transmission gate.

2. A self-biased LVDS driving circuit, characterized in that: include: A current source module, a transmitter module and a common mode feedback circuit module; The first end of the current source module is connected to the external bias current, the second end of the current source module is connected to the first end of the transmitter module, the second end of the transmitter module is connected to a reverse differential signal, the third end of the transmitter module is connected to a forward differential signal, the fifth end of the transmitter module outputs a reverse differential signal, the sixth end of the transmitter module outputs a forward differential signal, the fourth end of the transmitter module is connected to the first end of the common mode feedback circuit module, the second end of the common mode feedback circuit module is connected to the fifth end of the transmitter module, and the third end of the common mode feedback circuit module is connected to the sixth end of the transmitter module; The current source module is used to provide driving current for the transmitter module and the common mode feedback circuit module; the transmitter module sends the connected forward differential signal and reverse differential signal to the downstream receiver through the driving current; The common mode feedback circuit module is used for feedback adjustment of the common mode voltage; The current source module includes a twelfth transistor and a thirteenth transistor; the first end of the twelfth transistor is connected to an external bias current, the second end of the twelfth transistor is connected to the first end of the twelfth transistor and the second end of the thirteenth transistor, the third end of the twelfth transistor is grounded, the first end of the thirteenth transistor is connected to the first end of the transmitter module, and the third end of the thirteenth transistor is grounded; the twelfth transistor and the thirteenth transistor are both NMOS transistors, the first ends of the twelfth transistor and the thirteenth transistor are both drains of the NMOS transistors, the second ends are both gates of the NMOS transistors, and the third ends are both sources of the NMOS transistors; The transmitter module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor; the third end of the fourteenth transistor is connected to the second end of the current source module, the second end of the fourteenth transistor is connected to the second end of the sixteenth transistor, and is connected to a reverse differential signal, the first end of the fourteenth transistor is connected to the first end of the sixteenth transistor, and outputs a forward differential signal, the third end of the fifteenth transistor is connected to the second end of the current source module, the second end of the fifteenth transistor is connected to the second end of the seventeenth transistor, and is connected to a forward differential signal, the first end of the fifteenth transistor is connected to the first end of the seventeenth transistor The first end of the common-mode feedback circuit module is connected to the first end of the common-mode feedback circuit module, and a reverse differential signal is outputted; the third end of the sixteenth transistor and the third end of the seventeenth transistor are connected to the first end of the common-mode feedback circuit module; the fourteenth transistor and the fifteenth transistor are both NMOS transistors, and the sixteenth transistor and the seventeenth transistor are both PMOS transistors; the first end of the fourteenth transistor and the fifteenth transistor are both the drain of the NMOS tube, the second end are both the gate of the NMOS tube, and the third end are both the source of the NMOS tube, the first end of the sixteenth transistor and the seventeenth transistor are both the drain of the PMOS tube, the second end are both the gate of the PMOS tube, and the third end are both the source of the PMOS tube; The common-mode feedback circuit module includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a third resistor and a fourth resistor; a first end of the eighteenth transistor is connected to the fourth end of the transmitter module, a second end of the eighteenth transistor is connected to the second end of the fourth transmission gate, a third end of the eighteenth transistor is connected to a power supply, a first end of the fourth transmission gate is connected to the second end of the third resistor and the second end of the fourth resistor, a first end of the nineteenth transistor is connected to the fourth end of the transmitter module, a second end of the nineteenth transistor is connected to the second end of the fifth transmission gate, a third end of the nineteenth transistor is connected to a power supply, a first end of the fifth transmission gate is connected to the second end of the third resistor and the second end of the fourth resistor, a first end of the twentieth transistor is connected to the fourth end of the transmitter module, a second end of the twentieth transistor is connected to the second end of the sixth transmission gate, The third terminal is connected to a power supply, and the first terminal of the sixth transmission gate is connected to the second terminal of the third resistor and the second terminal of the fourth resistor; the eighteenth transistor, the nineteenth transistor and the twentieth transistor are all PMOS tubes, and the first terminals of the eighteenth transistor, the nineteenth transistor and the twentieth transistor are all drain terminals of the PMOS tube, the second terminals are all gate terminals of the PMOS tube, and the third terminals are all sources of the PMOS tube; the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are all composed of a CMOS transmission gate and an internal PMOS tube, wherein the output terminal of the CMOS transmission gate is connected to the drain terminal of the internal PMOS tube, the gate terminal of the internal PMOS tube is connected to the high level effective terminal of the CMOS transmission gate, and the source terminal of the internal PMOS tube is connected to a power supply; the first terminals of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are all input terminals of the CMOS transmission gate, and the second terminals are all output terminals of the CMOS transmission gate.

3. A serial circuit chip, characterized in that: The serial circuit chip includes the self-biased LVDS driving circuit as described in any one of claims 1 or 2.

4. An electronic device, characterized in that: The electronic device comprises the serial circuit chip according to claim 3, a transmission medium, and a deserialization circuit chip, wherein the transmission medium is arranged between the serial circuit chip and the deserialization circuit chip.

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