Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure which comprises a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer and a plurality of semiconductor strip groups which are located on the first sacrificial layer and extend along a first direction; wherein each semiconductor strip group comprises a first semiconductor strip and a second semiconductor strip which are arranged in parallel along a second direction, a first groove is arranged between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is arranged between two adjacent semiconductor strip groups; the first direction and the second direction are parallel to the first semiconductor layer and intersect with each other; removing the first sacrificial layer through the first groove and the second groove to form a first gap; sequentially forming a first gate dielectric layer and a first channel layer in the first gap; and forming a threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device on the first channel layer exposed at the bottom of the first groove.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The storage unit of the traditional dynamic random access memory (DRAM) includes a transistor and a capacitor (1 transistor 1 capacitor, 1T1C), the gate of the transistor is connected to the word line, the source of the transistor is connected to the bit line, and the drain of the transistor is connected to the capacitor. The 1T1C storage unit relies on the capacitor for storage and needs to be refreshed frequently, which will undoubtedly significantly increase power consumption. In addition, the cut-off current of the reduced-size silicon transistor is too large, which may cause charge leakage; and the capacitor occupies too large an area.

[0003] The 2T0C memory cell includes two transistors, namely, a write transistor and a read transistor. Instead of using a capacitor to store data, the gate of the read transistor is used to store data, which can avoid the problems caused by the capacitor in the traditional 1T1C memory cell. The cut-off current of the 2T0C memory cell is very low, which can improve the data retention capability of the memory cell.

[0004] Currently, there are still challenges in improving DRAM with 2T0C memory cells to balance the integration and performance of DRAM. Summary of the invention

[0005] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A semiconductor structure is provided, comprising a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer, and a plurality of semiconductor strip groups located on the first sacrificial layer and extending along a first direction; wherein each of the semiconductor strip groups comprises a first semiconductor strip and a second semiconductor strip arranged in parallel along a second direction, a first groove is provided between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is provided between two adjacent semiconductor strip groups; the first direction and the second direction are both parallel to the first semiconductor layer and intersect with each other;

[0008] removing the first sacrificial layer through the first groove and the second groove to form a first gap;

[0009] sequentially forming a first gate dielectric layer and a first channel layer in the first gap;

[0010] A threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove.

[0011] In some embodiments, the first semiconductor strip and the second semiconductor strip each include a second semiconductor layer, a second sacrificial layer, and a third semiconductor layer sequentially stacked along a third direction; the third direction is perpendicular to the first semiconductor layer;

[0012] The threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove, comprising:

[0013] Performing epitaxial growth on the second semiconductor layer exposed by the sidewall of the first groove to form a fourth semiconductor material layer;

[0014] Etching the fourth semiconductor material layer to form a third groove; wherein the fourth semiconductor layer is exposed at the bottom of the third groove, and the fourth semiconductor layer is substantially flush with the second sacrificial layer; and the third groove and the first groove have the same size in a direction parallel to the first semiconductor layer;

[0015] The fourth semiconductor layer exposed at the bottom of the third groove is doped to form a threshold voltage adjustment layer.

[0016] In some embodiments, after forming a threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device on the first channel layer exposed at the bottom of the first groove, the manufacturing method further includes:

[0017] removing the second sacrificial layer through the second groove to form a second gap;

[0018] A first isolation layer is formed in the second gap.

[0019] In some embodiments, after forming the first isolation layer in the second gap, the manufacturing method further includes:

[0020] The second semiconductor layer and the third semiconductor layer of the first semiconductor strip, and the second semiconductor layer and the third semiconductor layer of the second semiconductor strip are doped to form a first source electrode and a second source electrode, and a first drain electrode and a second drain electrode, respectively.

[0021] In some embodiments, after doping the second semiconductor layer and the third semiconductor layer of the first semiconductor strip, and the second semiconductor layer and the third semiconductor layer of the second semiconductor strip, the manufacturing method further includes:

[0022] forming a second channel layer covering the sidewalls and bottom of the third groove;

[0023] The third groove is filled to form a second gate dielectric layer.

[0024] In some embodiments, materials of the first channel layer and the second channel layer both include indium gallium zinc oxide (IGZO).

[0025] In some embodiments, after filling the third groove to form the second gate dielectric layer, the manufacturing method further includes:

[0026] forming a fifth semiconductor layer, wherein the fifth semiconductor layer fills the second groove;

[0027] Sequentially etching the fifth semiconductor layer and the first channel layer along the third direction to form a first gate groove; wherein the bottom of the first gate groove exposes the first gate dielectric layer;

[0028] forming an insulating layer covering at least the sidewall of the first gate groove;

[0029] The first gate groove is filled with a conductive material to form a first gate.

[0030] In some embodiments, after filling the first gate groove to form the first gate, the manufacturing method further includes:

[0031] forming a conductive material layer at least covering the second gate dielectric layer and the first gate;

[0032] The conductive material layer is etched to form a second gate contacting the second gate dielectric layer and a first gate contact structure contacting the first gate.

[0033] In some embodiments, the first gate, the first channel layer, the first source and the first drain form a first transistor; the second gate, the second channel layer, the second source and the second drain form a second transistor; wherein the first transistor and the second transistor together form a read transistor, the first source and the second source are connected, and the first drain and the second drain are connected; the threshold voltage adjustment layer is used to adjust the threshold voltage of the first transistor and / or the second transistor;

[0034] The manufacturing method further comprises:

[0035] A read word line is formed, and the read word line is connected to the second gate.

[0036] In some embodiments, the manufacturing method further comprises:

[0037] forming a write transistor, wherein the read transistor and the write transistor together form a storage unit; the drain of the write transistor is connected to the first gate contact structure;

[0038] forming a write word line, wherein the write word line is connected to the gate of the write transistor;

[0039] forming a bit line, wherein the bit line is connected to sources of the read transistor and the write transistor;

[0040] A ground line is formed, and the ground line is connected to the drain of the read transistor.

[0041] In some embodiments, the manufacturing method further comprises:

[0042] Etching along the third direction to form grid-shaped grooves exposing the first semiconductor layer;

[0043] The grid-shaped grooves are filled with an isolation material to form a second isolation layer; wherein the second isolation layer in the grid-shaped grooves isolates the plurality of storage units.

[0044] In some embodiments, providing a semiconductor structure includes:

[0045] forming a first sacrificial layer, a second semiconductor layer, a second sacrificial layer and a third semiconductor layer in sequence on the first semiconductor layer;

[0046] The third semiconductor layer, the second sacrificial layer and the second semiconductor layer are sequentially etched along the third direction to form a first groove and a second groove extending along the first direction; wherein the first groove and the second groove are alternately arranged along the second direction.

[0047] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0048] A first semiconductor layer, a first gate dielectric layer and a first channel layer stacked in sequence;

[0049] A plurality of semiconductor column groups located on the first channel layer and arranged in an array along a first direction and a second direction; wherein each of the semiconductor column groups comprises a first semiconductor column and a second semiconductor column arranged in parallel along the second direction, the first semiconductor column comprises a first source electrode, a first isolation layer, and a second source electrode in sequence along a third direction, and the second semiconductor column comprises a first drain electrode, a first isolation layer, and a second drain in sequence along the third direction; the first direction and the second direction are both parallel to the first semiconductor layer and intersect with the first direction, and the third direction is perpendicular to the first semiconductor layer;

[0050] A threshold voltage adjustment layer is located on the first channel layer and between the first semiconductor column and the second semiconductor column in the semiconductor column group; wherein the threshold voltage adjustment layer is used to adjust the threshold voltage of the semiconductor device.

[0051] In some embodiments, the semiconductor device further comprises:

[0052] a fifth semiconductor layer located on the first channel layer and between two adjacent semiconductor column groups;

[0053] A first gate sequentially penetrating the fifth semiconductor layer and the first channel layer;

[0054] an insulating layer covering at least a side wall of the first gate;

[0055] A first gate contact structure is located on the first gate; wherein the first gate, the first channel layer, the first source and the first drain form a first transistor.

[0056] In some embodiments, the semiconductor device further comprises:

[0057] A second channel layer covering the surface of the threshold voltage adjustment layer and covering the side walls of the second source and the second drain;

[0058] a second gate dielectric layer covering the second channel layer;

[0059] A second gate is located on the second gate dielectric layer; wherein the second gate, the second channel layer, the second source and the second drain form a second transistor; and the threshold voltage adjustment layer is used to adjust the threshold voltage of the first transistor and / or the second transistor.

[0060] In some embodiments, the first transistor and the second transistor jointly form a read transistor, the first source and the second source are connected, and the first drain and the second drain are connected; the semiconductor device further includes:

[0061] A read word line is connected to the second gate.

[0062] In some embodiments, the semiconductor device further comprises:

[0063] A write transistor, wherein the read transistor and the write transistor together form a storage unit; a drain of the write transistor is connected to a first gate contact structure;

[0064] a write word line connected to the gate of the write transistor;

[0065] a bit line connected to sources of the read transistor and the write transistor;

[0066] A ground line is connected to the drain of the read transistor.

[0067] In some embodiments, the semiconductor device further comprises:

[0068] A second isolation layer is used to isolate a plurality of the storage units arranged in an array along the first direction and the second direction.

[0069] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method includes: providing a semiconductor structure, including a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer, and a plurality of semiconductor strip groups located on the first sacrificial layer and extending along a first direction; wherein each semiconductor strip group includes a first semiconductor strip and a second semiconductor strip arranged in parallel along a second direction, a first groove is provided between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is provided between two adjacent semiconductor strip groups; the first direction and the second direction are both parallel to the first semiconductor layer and the first direction and the second direction intersect; the first sacrificial layer is removed through the first groove and the second groove to form a first gap; a first gate dielectric layer and a first channel layer are formed in sequence in the first gap; a threshold voltage adjustment layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove. In the embodiment of the present disclosure, the threshold voltage adjustment layer is formed on the first channel layer exposed at the bottom of the first groove to achieve dynamic adjustment of the threshold voltage of the semiconductor device, thereby optimizing the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 Schematic diagram of a 2T0C storage unit in a related technical solution;

[0071] Figure 2 A schematic diagram of a dual-gate 2T0C memory cell provided in an embodiment of the present disclosure;

[0072] Figure 3 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0073] FIG. 4A to FIG. 4J A cross-sectional view of a semiconductor device during manufacturing provided by an embodiment of the present disclosure;

[0074] Figure 5 A cross-sectional view of a semiconductor device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0076] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0077] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0078] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0079] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0080] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0081] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0082] refer to Figure 1 , Figure 1 FIG. 2 is a schematic diagram of a 2T0C storage unit in a related technical solution. Figure 1 As shown, the 2T0C memory cell includes two transistors, namely, a write transistor (Wtr) and a read transistor (Rtr). The gate of the write transistor Wtr is connected to the write word line (WWL), the source of the write transistor Wtr is connected to the write bit line (WBL), and the drain of the write transistor Wtr is connected to the gate of the read transistor Rtr. The source of the read transistor Rtr is connected to the read bit line (RBL), and the drain of the read transistor Rtr is connected to the read word line (RWL). Among them, the connection point between the drain of the write transistor Wtr and the gate of the read transistor Rtr is used as a storage node (Storage Node, SN).

[0083] At a certain size (and with the right dopants), small transistors can also store charge without any capacitors. Storing charge on the gate of the transistor means that current can flow through it. Writing and reading involve different transistors, so data can be read from a 2T0C memory cell without erasing and rewriting the data. When there is a charge on the gate of the read transistor, it means that current flows and the transistor is turned on; when there is no charge on the gate of the read transistor, it means that no current flows and the transistor is turned off.

[0084] However, for the above 2TOC memory cell, data writing and data reading are implemented using a writing transistor and a reading transistor respectively. The writing operation requires a writing bit line signal and a writing word line signal, and the reading operation requires a reading bit line signal and a reading word line signal.

[0085] refer to Figure 2 , Figure 2 Schematic diagram of a dual-gate 2T0C memory cell provided by an embodiment of the present disclosure. Figure 2 As shown, the dual-gate 2T0C memory cell includes two transistors, namely, a write transistor (Wtr) and a read transistor (Rtr), wherein the read transistor Rtr has two gates (Dual-date, DG). One gate of the read transistor Rtr is connected to the read word line RWL for controlling the read operation; the other gate is connected to the drain of the write transistor Wtr for storing charge using the gate capacitance. Usually, the connection point between the gate of the read transistor Rtr and the drain of the write transistor Wtr is used as the location for charge storage, also known as the storage node SN.

[0086] Still refer to Figure 2 , the source of the write transistor Wtr and the read transistor Rtr are connected to the bit line (BL), the gate of the write transistor Wtr is connected to the write word line WWL, and the drain of the read transistor Rtr is grounded. The dual-gate 2T0C memory cell is coupled to the same bit line BL, which is conducive to high-density design. And the current in the dual-gate 2T0C memory cell flows into the ground through the bit line BL and the read transistor Rtr, so that the current in the read word line RWL is very small and almost negligible, so the problem of voltage drop (IR Drop) can be alleviated.

[0087] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a threshold voltage adjustment layer is formed on the first channel layer exposed at the bottom of the first groove to achieve dynamic adjustment of the threshold voltage of the semiconductor device, thereby optimizing the performance of the semiconductor device.

[0088] refer to Figure 3 , Figure 3A schematic diagram of a process flow of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure. An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0089] Step S301: providing a semiconductor structure, comprising a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer, and a plurality of semiconductor strip groups located on the first sacrificial layer and extending along a first direction; wherein each semiconductor strip group comprises a first semiconductor strip and a second semiconductor strip arranged in parallel along a second direction, a first groove is provided between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is provided between two adjacent semiconductor strip groups; the first direction and the second direction are both parallel to the first semiconductor layer and intersect with each other;

[0090] Step S302: removing the first sacrificial layer through the first groove and the second groove to form a first gap;

[0091] Step S303: sequentially forming a first gate dielectric layer and a first channel layer in the first gap;

[0092] Step S304: forming a threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device on the first channel layer exposed at the bottom of the first groove.

[0093] refer to FIG. 4A to FIG. 4J , FIG. 4A to FIG. 4J A cross-sectional view of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. FIG. 4A to FIG. 4J , which describes in detail the manufacturing process of semiconductor devices.

[0094] In the embodiment of the present disclosure, step S301 includes:

[0095] A first sacrificial layer 102, a second semiconductor layer 104, a second sacrificial layer 106 and a third semiconductor layer 108 are sequentially formed on the first semiconductor layer 100;

[0096] The third semiconductor layer 108 , the second sacrificial layer 106 and the second semiconductor layer 104 are sequentially etched along the third direction to form first grooves 118 and second grooves 120 extending along the first direction; wherein the first grooves 118 and the second grooves 120 are alternately arranged along the second direction.

[0097] like Figure 4A As shown, a first sacrificial layer 102 , a second semiconductor layer 104 , a second sacrificial layer 106 and a third semiconductor layer 108 are sequentially stacked on the first semiconductor layer 100 to form a stacked structure 110 .

[0098] In some embodiments, the materials of the first semiconductor layer 100 , the second semiconductor layer 104 , and the third semiconductor layer 108 may be the same or different; the materials of the first sacrificial layer 102 and the second sacrificial layer 106 may be the same or different.

[0099] For ease of explanation, FIG. 4A to FIG. 4J It is shown that the materials of the first semiconductor layer 100, the second semiconductor layer 104 and the third semiconductor layer 108 are the same, and the materials of the first sacrificial layer 102 and the second sacrificial layer 106 are the same. In this way, the process of forming the first semiconductor layer 100, the second semiconductor layer 104 and the third semiconductor layer 108, and the process of forming the first sacrificial layer 102 and the second sacrificial layer 106 can be simplified.

[0100] In a specific example, the materials of the first semiconductor layer 100 , the second semiconductor layer 104 and the third semiconductor layer 108 may all be silicon (Si), and the materials of the first sacrificial layer 102 and the second sacrificial layer 106 may all be silicon germanium (SiGe).

[0101] Here, a first direction and a second direction parallel to the first semiconductor layer are defined, and the first direction and the second direction intersect; a third direction perpendicular to the first semiconductor layer is defined. The first direction and the second direction are both perpendicular to the third direction. Of course, the first direction and the second direction may also be perpendicular to each other. The first direction is the X direction, the second direction is the Y direction, and the third direction is the Z direction. FIG. 4A to FIG. 4J The diagrams shown are all cross-sectional views of the YZ plane.

[0102] like Figure 4B As shown, a photoresist layer 112 is formed on the third semiconductor layer 108 , and the photoresist layer 112 has a first opening 114 and a second opening 116 .

[0103] like Figure 4C As shown, the third semiconductor layer 108, the second sacrificial layer 106 and the second semiconductor layer 104 are sequentially etched along the Z direction using the first opening 114 and the second opening 116 of the photoresist layer 112 to form a first groove 118 and a second groove 120 extending along the X direction, respectively; wherein the first groove 118 and the second groove 120 are alternately arranged along the Y direction.

[0104] Here, the etching process stops at the surface of the first sacrificial layer 102. In other words, the bottoms of the first and second grooves 118 and 120 expose the surface of the first sacrificial layer 102. The sidewalls of the first and second grooves 118 and 120 expose the second semiconductor layer 104, the second sacrificial layer 106 and the third semiconductor layer 108.

[0105] In the embodiment of the present disclosure, in step S301, a semiconductor structure is provided, including a first semiconductor layer 100, a first sacrificial layer 102 located on the first semiconductor layer 100, and a plurality of semiconductor strip groups 122 located on the first sacrificial layer 102 and extending along a first direction; wherein each semiconductor strip group 122 includes a first semiconductor strip 124 and a second semiconductor strip 126 arranged in parallel along a second direction, a first groove 118 is provided between the first semiconductor strip 124 and the second semiconductor strip 126 in the semiconductor strip group 122, and a second groove 120 is provided between two adjacent semiconductor strip groups 122.

[0106] Here, the stacked structure 110 is divided into a plurality of semiconductor strip groups 122 according to a plurality of second grooves 120 extending along the X direction. Each semiconductor strip group 122 includes first semiconductor strips 124 arranged in parallel along the Y direction (eg, Figure 4C The second semiconductor strip 126 (shown in the dashed box) Figure 4C There is a first groove 118 between the first semiconductor strip 124 and the second semiconductor strip 126 in the semiconductor strip group 122, and there is a second groove 120 between two adjacent semiconductor strip groups 122. The first semiconductor strip 124 and the second semiconductor strip 126 both include a second semiconductor layer 104, a second sacrificial layer 106, and a third semiconductor layer 108 stacked in sequence along the Z direction.

[0107] In some embodiments, the sizes of the first groove 118 and the second groove 120 along the Y direction may be the same or different.

[0108] For ease of explanation, Figure 4C Only one first groove 118 and one second groove 120 arranged in parallel along the Y direction are illustrated. In fact, the embodiment of the present disclosure has no special limitation on the number of the first groove 118 and the second groove 120, and a plurality of first grooves 118 and second grooves 120 can be alternately arranged along the Y direction.

[0109] like Figure 4D As shown, a protection layer 128 is formed to cover the sidewalls and bottom of the first groove 118 and the second groove 120 , and the protection layer 128 covering the bottom of the first groove 118 and the second groove 120 is removed by etching, leaving only the protection layer 128 covering the sidewalls of the first groove 118 and the second groove 120 .

[0110] Here, the purpose of forming a protective layer 128 covering the side walls of the first groove 118 and the second groove 120 is to protect the second semiconductor layer 104, the second sacrificial layer 106 and the third semiconductor layer 108 exposed by the side walls of the first groove 118 and the second groove 120, especially to protect the second sacrificial layer 106 exposed by the side walls of the first groove 118 and the second groove 120, so as to avoid damaging the second sacrificial layer 106 during the removal of the first sacrificial layer 102.

[0111] In a specific example, the material of the protection layer 128 includes silicon nitride (Si 3 N 4 ).

[0112] like Figure 4D and Figure 4E As shown, in the embodiment of the present disclosure, in step S302, the first sacrificial layer 102 is removed through the first groove 118 and the second groove 120 to form a first gap 130 (eg, Figure 4E In step S303 , a first gate dielectric layer 132 and a first channel layer 134 are sequentially formed in the first gap 130 ; wherein the first gate dielectric layer 132 covers the first semiconductor layer 100 , and the first channel layer 134 covers the first gate dielectric layer 132 .

[0113] In other words, the first gate dielectric layer 132 is located above the first semiconductor layer 100 and is in direct contact with the first semiconductor layer 100 , and the first channel layer 134 is located above the first gate dielectric layer 132 and is in direct contact with the first gate dielectric layer 132 .

[0114] In the disclosed embodiment, a multilayer stacking structure (i.e., a stacked structure) of semiconductor layers and sacrificial layers is formed using 3D DRAM technology, and the sacrificial layer (i.e., the first sacrificial layer) is removed in a subsequent process to form a functional film layer (i.e., the first gate dielectric layer and the first channel layer). The use of 3D stacking technology can effectively save lateral area and provide a solution for reducing the size of semiconductor devices.

[0115] Here, for example, a wet etching process may be used to inject an etching liquid into the first groove 118 and the second groove 120 to remove the first sacrificial layer 102 , so as to form the first gap 130 .

[0116] It should be noted that the semiconductor structure includes a support structure, and the support structure is used to support the second semiconductor layer, the second sacrificial layer and the third semiconductor layer located on the first sacrificial layer to prevent the stacked structure from collapsing during the removal of the first sacrificial layer. The disclosed embodiment has no special restrictions on the number of support structures, the shape of the support structures and the arrangement of the support structures, as long as the support structure can play a supporting role and prevent the stacked structure from collapsing during the formation of the first gap.

[0117] Here, a first gate dielectric layer 132 and a first channel layer 134 are formed in the first gap 130. The process of forming the first gate dielectric layer 132 and the first channel layer 134 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0118] In the disclosed embodiment, the material of the first channel layer 134 may include indium gallium zinc oxide (IGZO). IGZO refers to an oxide containing indium (In), gallium (Ga) and zinc (Zn) as main components, and may also contain metal elements other than In, Ga and Zn. For example, IGZO may also include at least one element of tin (Sn), hafnium (Hf), zirconium (Zr), titanium (Ti, scandium (Sc), yttrium (Y), etc. Using the amorphous material IGZO as the first channel layer 134 can effectively reduce leakage current.

[0119] In one specific example, the material of the first gate dielectric layer 132 includes silicon dioxide (SiO2). In another specific example, the material of the first gate dielectric layer 132 includes hafnium dioxide (HfO2).

[0120] In the embodiment of the present disclosure, step S304 includes:

[0121] Performing epitaxial growth on the second semiconductor layer 104 exposed by the sidewall of the first groove 118 to form a fourth semiconductor material layer;

[0122] The fourth semiconductor material layer is etched to form a third groove 136; wherein the fourth semiconductor layer 138 is exposed at the bottom of the third groove 136, and the fourth semiconductor layer 138 is substantially flush with the second sacrificial layer 106; the third groove 136 and the first groove 118 have the same size in a direction parallel to the first semiconductor layer 100;

[0123] The fourth semiconductor layer 138 exposed at the bottom of the third groove 136 is doped to form a threshold voltage adjustment layer 140 .

[0124] like Figure 4E and Figure 4FAs shown, the protective layer 128 covering the sidewall of the first groove 118 is removed to expose the second semiconductor layer 104, the second sacrificial layer 106 and the third semiconductor layer 108 on the sidewall of the first groove 118; the second semiconductor layer 104 (for example, silicon material) exposed by the sidewall of the first groove 118 is used for epitaxial growth to form a fourth semiconductor material layer (for example, silicon material layer); the fourth semiconductor material layer is etched along the Z direction to form a third groove 136 in the first groove 118; wherein the bottom of the third groove 136 exposes the fourth semiconductor layer 138, the fourth semiconductor layer 138 and the surface of the second sacrificial layer 106 are substantially flush, the third groove 136 and the first groove 118 have the same size along the X direction, and the third groove 136 and the first groove 118 have the same size along the Y direction.

[0125] It should be noted that the fourth semiconductor layer 138 exposed at the bottom of the third groove 136 is substantially flush with the surface of the second sacrificial layer 106, which means that the height difference between the surface of the fourth semiconductor layer 138 and the surface of the second sacrificial layer 106 along the Z direction is less than a preset value, that is, the height difference between the surface of the fourth semiconductor layer 138 and the surface of the second sacrificial layer 106 in the Z direction meets the process error range requirement. In some embodiments, the height difference between the surface of the fourth semiconductor layer 138 and the surface of the second sacrificial layer 106 in the Z direction may be 0. In other words, the sidewall of the third groove 136 exposes the third semiconductor layer 108.

[0126] In some embodiments, the fourth semiconductor material layer is formed by epitaxial growth of the second semiconductor layer 104, and then etched to form the fourth semiconductor layer 138. That is, the second semiconductor layer 104 and the fourth semiconductor layer 138 are made of the same material.

[0127] like Figure 4F and Figure 4G As shown, the fourth semiconductor layer 138 exposed at the bottom of the third groove 136 is doped to form a threshold voltage adjustment layer 140. The threshold voltage adjustment layer 140 is located above the first channel layer 134 and the threshold voltage adjustment layer 140 and the first channel layer 134 are in direct contact.

[0128] In some embodiments, the fourth semiconductor layer 138 exposed at the bottom of the third groove 136 may be doped using methods including but not limited to ion implantation.

[0129] In a specific example, the doping element may include an oxygen element. In the embodiment of the present disclosure, an oxygen element is doped into the fourth semiconductor layer 138 by ion implantation, and oxygen vacancies are formed in the fourth semiconductor layer 138 after annealing to form a threshold voltage adjustment layer 140. By adjusting the process parameters of the doping process, such as the doping concentration, the doping depth, and the doping element distribution, the threshold voltage of the semiconductor device can be adjusted, thereby optimizing the performance of the semiconductor device.

[0130] In the embodiment of the present disclosure, after step S304, the manufacturing method further includes:

[0131] Removing the second sacrificial layer 106 through the second groove 120 to form a second gap 142;

[0132] A first isolation layer 144 is formed in the second gap 142 .

[0133] Still Figure 4F and Figure 4G As shown, the protection layer 128 covering the sidewall of the second groove 120 is removed; the second sacrificial layer 106 is removed through the second groove 120 to form a second gap 142; and a first isolation layer 144 is formed in the second gap 142.

[0134] Here, for example, a wet etching process may be used to inject an etching liquid into the second groove 120 to remove the second sacrificial layer 106 , so as to form the second gap 142 .

[0135] Here, the process of forming the first isolation layer 144 in the second gap 142 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0136] In a specific example, the material of the first isolation layer 144 includes silicon nitride (Si 3 N 4 ).

[0137] In the embodiment of the present disclosure, after forming the first isolation layer 144 in the second gap 142, the manufacturing method further includes:

[0138] The second semiconductor layer 104 and the third semiconductor layer 108 of the first semiconductor strip 124 and the second semiconductor layer 104 and the third semiconductor layer 108 of the second semiconductor strip 126 are doped to form the first source 146 and the second source 148 and the first drain 150 and the second drain 152 , respectively.

[0139] like Figure 4G and Figure 4HAs shown, the second semiconductor layer 104 and the third semiconductor layer 108 of the first semiconductor strip 124 are doped to form a first source 146 and a second source 148, respectively; the second semiconductor layer 104 and the third semiconductor layer 108 of the second semiconductor strip 126 are doped to form a first drain 150 and a second drain 152, respectively.

[0140] In the embodiment of the present disclosure, after doping the second semiconductor layer 104 and the third semiconductor layer 108 of the first semiconductor strip 124 and the second semiconductor layer 104 and the third semiconductor layer 108 of the second semiconductor strip 126, the manufacturing method further includes:

[0141] forming a second channel layer 154 covering the sidewall and bottom of the third groove 136;

[0142] The third groove 136 is filled to form a second gate dielectric layer 156 .

[0143] Still Figure 4G and Figure 4H As shown, a second channel layer 154 is formed to cover the sidewalls and the bottom of the third groove 136 , but the second channel layer 154 does not fill up the third groove 136 ; a second gate dielectric layer 156 is formed, but the second gate dielectric layer 156 fills up the third groove 136 .

[0144] In the disclosed embodiment, the second channel layer covers the sidewalls and the bottom of the third groove, which can effectively increase the channel area and improve the driving current.

[0145] Here, the surfaces of the second gate dielectric layer 156 , the second channel layer 154 and the third semiconductor layer 108 are substantially flush. More specifically, the height difference between the surfaces of the second gate dielectric layer 156 , the second channel layer 154 and the third semiconductor layer 108 along the Z direction meets the process error range requirement.

[0146] Here, the process of forming the second channel layer 154 and the second gate dielectric layer 156 in the third groove 136 includes, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0147] In the embodiment of the present disclosure, the material of the second channel layer 154 may include IGZO. Here, using the amorphous material IGZO as the second channel layer 154 can effectively reduce leakage current.

[0148] In a specific example, the material of the second gate dielectric layer 156 includes hafnium dioxide (HfO 2 ).

[0149] In the embodiment of the present disclosure, after the third groove 136 is filled to form the second gate dielectric layer 156, the manufacturing method further includes:

[0150] forming a fifth semiconductor layer 158 , wherein the fifth semiconductor layer 158 fills the second groove 120 ;

[0151] The fifth semiconductor layer 158 and the first channel layer 134 are sequentially etched along the third direction to form a first gate groove 160 ; wherein the bottom of the first gate groove 160 exposes the first gate dielectric layer 132 ;

[0152] forming an insulating layer 162 covering at least the sidewall of the first gate groove 160;

[0153] The first gate groove 160 is filled with a conductive material to form a first gate 164 .

[0154] Still Figure 4G and Figure 4H As shown, a fifth semiconductor layer 158 is formed in the second groove 120 , and the fifth semiconductor layer 158 fills up the second groove 120 .

[0155] Here, the process of forming the fifth semiconductor layer 158 includes, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0156] like Figure 4H and Fig. 4I As shown, the fifth semiconductor layer 158 and the first channel layer 134 are sequentially etched along the Z direction to form a first gate groove 160 extending along the Z direction (as shown in FIG. Fig. 4I forming an insulating layer 162 covering at least the sidewall of the first gate groove 160; and filling the first gate groove 160 with a conductive material to form a first gate 164.

[0157] Here, the etching process stops at the surface of the first gate dielectric layer 132 , in other words, the bottom of the first gate groove 160 exposes the first gate dielectric layer 132 . The sidewall of the first gate groove 160 exposes the fifth semiconductor layer 158 and the first channel layer 134 .

[0158] Here, the insulating layer 162 at least covers the sidewalls of the first gate groove 160 . Of course, the insulating layer 162 may also cover the sidewalls and the bottom of the first gate groove 160 .

[0159] Here, the surfaces of the insulating layer 162 , the first gate 164 and the fifth semiconductor layer 158 are substantially flush, that is, the height difference of the insulating layer 162 , the first gate 164 and the fifth semiconductor layer 158 along the Z direction meets the process error range requirement.

[0160] In some embodiments, the material of the insulating layer 162 includes, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, or hafnium dioxide.

[0161] In some embodiments, the material of the first gate 164 includes but is not limited to metal materials, such as tungsten, titanium, copper, gold, cobalt, or nickel.

[0162] In the embodiment of the present disclosure, after the first gate groove 160 is filled to form the first gate 164, the manufacturing method further includes:

[0163] forming a conductive material layer covering at least the second gate dielectric layer 156 and the first gate 164;

[0164] The conductive material layer is etched to form a second gate 166 contacting the second gate dielectric layer 156 and a first gate contact structure 168 contacting the first gate 164 .

[0165] like Figure 4J As shown, a conductive material layer is formed to at least cover the second gate dielectric layer 156 and the first gate 164; the conductive material layer is etched to form a second gate 166 located above the second gate dielectric layer 156 and a first gate contact structure 168 located above the first gate 164. The second gate 166 is in direct contact with the second gate dielectric layer 156 and the second gate 166 is not in contact with the second channel layer 154, and the second gate 166 can be used as the second gate 166 and the second gate contact structure at the same time; the first gate contact structure 168 is in direct contact with the first gate 164.

[0166] In the embodiment of the present disclosure, after forming the conductive material layer, the second gate 166 (ie, the second gate contact structure) contacting the second gate dielectric layer 156 and the first gate contact structure 168 contacting the first gate 164 can be formed by etching in one step.

[0167] In some embodiments, the materials of the first gate 164 , the second gate 166 , and the first gate contact structure 168 may be the same.

[0168] In the embodiment of the present disclosure, the first gate 164, the first channel layer 134, the first source 146 and the first drain 150 form a first transistor; the second gate 166, the second channel layer 154, the second source 148 and the second drain 152 form a second transistor; wherein the first transistor and the second transistor together form a read transistor, the first source 146 and the second source 148 are connected, and the first drain 150 and the second drain 152 are connected.

[0169] In the embodiment of the present disclosure, two surfaces of the threshold voltage adjustment layer 140 that are relatively arranged along the Z direction are in direct contact with the first channel layer 134 and the second channel layer 154 respectively. In other words, by controlling the process parameters of the doping treatment, such as the doping depth, the doping concentration and the distribution of the doping elements, the distribution of oxygen holes in the threshold voltage adjustment layer 140 can be adjusted, thereby adjusting the threshold voltage and switching characteristics of the first transistor and / or the second transistor, and further optimizing the performance of the first transistor and / or the second transistor.

[0170] In the disclosed embodiment, the first transistor is also referred to as a bottom transistor (Bottom Gate), and the second transistor is also referred to as a top transistor (Top Gate). The first gate contact structure is also referred to as a bottom electrode contact (Bottom Electrode Contact, BEC), and the second gate as a second gate contact structure is also referred to as a top electrode contact (Top Electrode Contact, TEC).

[0171] In the embodiment of the present disclosure, the manufacturing method further includes:

[0172] A read word line is formed, and the read word line is connected to the second gate 166 .

[0173] A write transistor is formed, and the read transistor and the write transistor together form a memory cell; the drain of the write transistor is connected to the first gate contact structure 168;

[0174] forming a write word line, the write word line and the gate of the write transistor are connected;

[0175] forming a bit line, the bit line and source connections of the read transistor and the write transistor;

[0176] A ground line is formed, and the ground line and the drain connection of the read transistor are formed.

[0177] Here, the first source 146 of the first transistor is connected to the second source 148 of the second transistor, and the first source 146 and the second source 148 are connected to the bit line together; the first drain 150 of the first transistor is connected to the second drain 152 of the second transistor, and the first drain 150 and the second drain 152 are connected to the ground line together; the first gate 164 (or the first gate contact structure 168) of the first transistor is connected to the drain of the write transistor, and the connection point between the first gate 164 (or the first gate contact structure 168) and the drain of the write transistor serves as the storage node SN; the second gate 166 of the second transistor is connected to the read word line. The gate of the write transistor is connected to the write word line, and the source of the write transistor is also connected to the bit line.

[0178] In the embodiment of the present disclosure, the manufacturing method further includes:

[0179] Etching along a third direction to form a grid-shaped groove exposing the first semiconductor layer;

[0180] The grid-shaped grooves are filled with an isolation material to form a second isolation layer; wherein the second isolation layer in the grid-shaped grooves isolates a plurality of storage units.

[0181] Here, a grid-like groove is formed to expose the first semiconductor layer; wherein the grid-like groove may include a first sub-groove extending along a first direction and a second sub-groove extending along a second direction; the grid-like groove is filled with an isolation material to form a second isolation layer, wherein the second isolation layer isolates a plurality of memory cells to form a memory cell array.

[0182] In some embodiments, the first direction and the second direction are perpendicular to each other, and the second isolation layer isolates the plurality of memory cells to form a memory cell array arranged in a square array.

[0183] In some other embodiments, the first direction and the second direction intersect but are not perpendicular, and the second isolation layer isolates the plurality of memory cells to form a memory cell array arranged in a hexagonal array.

[0184] refer to Figure 5 , Figure 5 1 is a cross-sectional view of a semiconductor device provided by an embodiment of the present disclosure. Figure 5 As shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0185] A first semiconductor layer 100, a first gate dielectric layer 132 and a first channel layer 134 are sequentially stacked;

[0186] A plurality of semiconductor column groups 170 are arranged in an array along the first direction and the second direction on the first channel layer 134; wherein each semiconductor column group 170 includes first semiconductor columns 172 arranged in parallel along the second direction (such as Figure 5 The second semiconductor column 174 (shown in the dashed box) Figure 5 The first semiconductor column 172 includes a first source 146, a first isolation layer 144, and a second source 148 in sequence along the third direction, and the second semiconductor column 174 includes a first drain 150, a first isolation layer 144, and a second drain 152 in sequence along the third direction; the first direction and the second direction are both parallel to the first semiconductor layer 100 and intersect with each other, and the third direction is perpendicular to the first semiconductor layer 100;

[0187] A threshold voltage adjustment layer 140 is located on the first channel layer 134 and between the first semiconductor pillar 172 and the second semiconductor pillar 174 in the semiconductor pillar group 170 ; wherein the threshold voltage adjustment layer 140 is used to adjust the threshold voltage of the semiconductor device.

[0188] like Figure 5 As shown, the surface of the threshold voltage adjustment layer 140 is substantially flush with the surface of the first isolation layer 144. More specifically, the height difference between the surface of the threshold voltage adjustment layer 140 and the surface of the first isolation layer 144 along the Z direction is less than a preset value, that is, the height difference between the surface of the threshold voltage adjustment layer 140 and the surface of the first isolation layer 144 along the Z direction meets the process error range requirement.

[0189] In the embodiment of the present disclosure, the threshold voltage adjustment layer 140 is located above the first channel layer 134 and the threshold voltage adjustment layer 140 is in direct contact with the first channel layer 134. The threshold voltage adjustment layer 140 can be formed by a doping process, and the distribution of oxygen vacancies in the threshold voltage adjustment layer 140 can be adjusted by controlling the process parameters of the doping process, such as the doping depth, doping concentration, and doping element distribution, so as to achieve dynamic adjustment of the threshold voltage of the semiconductor device, thereby optimizing the performance of the semiconductor device.

[0190] In the embodiment of the present disclosure, the semiconductor device further includes:

[0191] a fifth semiconductor layer 158 located on the first channel layer 134 and between two adjacent semiconductor column groups 170 ;

[0192] A first gate 164 sequentially penetrating the fifth semiconductor layer 158 and the first channel layer 134;

[0193] an insulating layer 162 covering at least a sidewall of the first gate 164;

[0194] A first gate contact structure 168 is located on the first gate 164 ; wherein the first gate 164 , the first channel layer 134 , the first source 146 and the first drain 150 form a first transistor.

[0195] Here, the insulating layer 162 at least covers the sidewalls of the first gate 164 . Of course, the insulating layer 162 may also cover the sidewalls and the bottom of the first gate 164 .

[0196] In the embodiment of the present disclosure, the semiconductor device further includes:

[0197] A second channel layer 154 covering the surface of the threshold voltage adjustment layer 140 and covering the sidewalls of the second source 148 and the second drain 152;

[0198] A second gate dielectric layer 156 covering the second channel layer 154;

[0199] A second gate 166 is located on the second gate dielectric layer 156; wherein the second gate 166, the second channel layer 154, the second source 148 and the second drain 152 form a second transistor; and the threshold voltage adjustment layer 140 is used to adjust the threshold voltage of the first transistor and / or the second transistor.

[0200] Here, the second gate 166 is located on the second gate dielectric layer 156 and directly contacts the second gate dielectric layer 156, and does not contact the second channel layer 154. The second gate 166 can also serve as a second gate contact structure to facilitate the extraction of electrical signals.

[0201] like Figure 5 As shown, the second channel layer 154 covers the sidewalls of the second source 148 and the second drain 152 and the surface of the threshold voltage adjustment layer 140, and the second channel layer 154 is in a groove shape. The second gate dielectric layer 156 can fill the groove of the second channel layer 154, which can effectively increase the channel area and improve the driving current.

[0202] In the embodiment of the present disclosure, two surfaces of the threshold voltage adjustment layer 140 that are relatively arranged along the Z direction are in direct contact with the first channel layer 134 and the second channel layer 154 respectively. In other words, by controlling the process parameters of the doping treatment, such as the doping depth, the doping concentration and the distribution of the doping elements, the distribution of oxygen holes in the threshold voltage adjustment layer 140 can be adjusted, thereby adjusting the threshold voltage and switching characteristics of the first transistor and / or the second transistor, and further optimizing the performance of the first transistor and / or the second transistor.

[0203] In the embodiment of the present disclosure, the first transistor and the second transistor together form a read transistor, the first source 146 and the second source 148 are connected, and the first drain 150 and the second drain 152 are connected; the semiconductor device further includes:

[0204] A read word line connected to the second gate 166 .

[0205] In the embodiment of the present disclosure, the semiconductor device further includes:

[0206] The write transistor, the read transistor and the write transistor together form a storage unit; the drain of the write transistor is connected to the first gate contact structure;

[0207] A write word line connected to the gate of the write transistor;

[0208] A bit line connected to sources of the read transistor and the write transistor;

[0209] The ground line connected to the drain of the read transistor.

[0210] Here, the first source 146 of the first transistor is connected to the second source 148 of the second transistor, and the first source 146 and the second source 148 are connected to the bit line together; the first drain 150 of the first transistor is connected to the second drain 152 of the second transistor, and the first drain 150 and the second drain 152 are connected to the ground line together; the first gate 164 (or the first gate contact structure 168) of the first transistor is connected to the drain of the write transistor, and the connection point between the first gate 164 (or the first gate contact structure 168) and the drain of the write transistor serves as the storage node SN; the second gate 166 of the second transistor is connected to the read word line. The gate of the write transistor is connected to the write word line, and the source of the write transistor is also connected to the bit line.

[0211] In the embodiment of the present disclosure, the semiconductor device further includes:

[0212] The second isolation layer isolates a plurality of storage units arranged in an array along the first direction and the second direction.

[0213] Here, the second isolation layer may include a first sub-isolation layer extending along the first direction and a second sub-isolation layer extending along the second direction; wherein the second isolation layer isolates a plurality of memory cells to form a memory cell array.

[0214] In some embodiments, the first direction and the second direction are perpendicular to each other, and the second isolation layer isolates the plurality of memory cells to form a memory cell array arranged in a square array.

[0215] In some other embodiments, the first direction and the second direction intersect but are not perpendicular, and the second isolation layer isolates the plurality of memory cells to form a memory cell array arranged in a hexagonal array.

[0216] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method includes: providing a semiconductor structure, including a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer, and a plurality of semiconductor strip groups located on the first sacrificial layer and extending along a first direction; wherein each semiconductor strip group includes a first semiconductor strip and a second semiconductor strip arranged in parallel along a second direction, a first groove is provided between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is provided between two adjacent semiconductor strip groups; the first direction and the second direction are both parallel to the first semiconductor layer and the first direction and the second direction intersect; the first sacrificial layer is removed through the first groove and the second groove to form a first gap; a first gate dielectric layer and a first channel layer are formed in sequence in the first gap; a threshold voltage adjustment layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove. In the embodiment of the present disclosure, the threshold voltage adjustment layer is formed on the first channel layer exposed at the bottom of the first groove to achieve dynamic adjustment of the threshold voltage of the semiconductor device, thereby optimizing the performance of the semiconductor device.

[0217] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0218] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A semiconductor structure is provided, comprising a first semiconductor layer, a first sacrificial layer located on the first semiconductor layer, and a plurality of semiconductor strip groups located on the first sacrificial layer and extending along a first direction; wherein each of the semiconductor strip groups comprises a first semiconductor strip and a second semiconductor strip arranged in parallel along a second direction, a first groove is provided between the first semiconductor strip and the second semiconductor strip in the semiconductor strip group, and a second groove is provided between two adjacent semiconductor strip groups; the first direction and the second direction are both parallel to the first semiconductor layer and intersect with each other; removing the first sacrificial layer through the first groove and the second groove to form a first gap; sequentially forming a first gate dielectric layer and a first channel layer in the first gap; A threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first semiconductor strip and the second semiconductor strip each include a second semiconductor layer, a second sacrificial layer and a third semiconductor layer stacked in sequence along a third direction; the third direction is perpendicular to the first semiconductor layer; The threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device is formed on the first channel layer exposed at the bottom of the first groove, comprising: Performing epitaxial growth on the second semiconductor layer exposed by the sidewall of the first groove to form a fourth semiconductor material layer; Etching the fourth semiconductor material layer to form a third groove; wherein the fourth semiconductor layer is exposed at the bottom of the third groove, and the fourth semiconductor layer is substantially flush with the second sacrificial layer; and the third groove and the first groove have the same size in a direction parallel to the first semiconductor layer; The fourth semiconductor layer exposed at the bottom of the third groove is doped to form a threshold voltage adjustment layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: After forming a threshold voltage adjusting layer for adjusting the threshold voltage of the semiconductor device on the first channel layer exposed at the bottom of the first groove, the manufacturing method further includes: removing the second sacrificial layer through the second groove to form a second gap; A first isolation layer is formed in the second gap.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After forming the first isolation layer in the second gap, the manufacturing method further includes: The second semiconductor layer and the third semiconductor layer of the first semiconductor strip, and the second semiconductor layer and the third semiconductor layer of the second semiconductor strip are doped to form a first source electrode and a second source electrode, and a first drain electrode and a second drain electrode, respectively.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: After the second semiconductor layer and the third semiconductor layer of the first semiconductor strip, and the second semiconductor layer and the third semiconductor layer of the second semiconductor strip are doped, the manufacturing method further comprises: forming a second channel layer covering the sidewalls and the bottom of the third groove; The third groove is filled to form a second gate dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Materials of the first channel layer and the second channel layer both include indium gallium zinc oxide (IGZO).

7. The method for manufacturing a semiconductor device according to claim 5, wherein: After the third groove is filled to form a second gate dielectric layer, the manufacturing method further includes: forming a fifth semiconductor layer, wherein the fifth semiconductor layer fills the second groove; Sequentially etching the fifth semiconductor layer and the first channel layer along the third direction to form a first gate groove; wherein the bottom of the first gate groove exposes the first gate dielectric layer; forming an insulating layer covering at least the sidewall of the first gate groove; The first gate groove is filled with a conductive material to form a first gate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After filling the first gate groove to form the first gate, the manufacturing method further includes: forming a conductive material layer at least covering the second gate dielectric layer and the first gate; The conductive material layer is etched to form a second gate contacting the second gate dielectric layer and a first gate contact structure contacting the first gate.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The first gate, the first channel layer, the first source and the first drain form a first transistor; the second gate, the second channel layer, the second source and the second drain form a second transistor; wherein the first transistor and the second transistor together form a read transistor, the first source and the second source are connected, and the first drain and the second drain are connected; the threshold voltage adjustment layer is used to adjust the threshold voltage of the first transistor and / or the second transistor; The manufacturing method further comprises: A read word line is formed, and the read word line is connected to the second gate.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The manufacturing method further comprises: forming a write transistor, wherein the read transistor and the write transistor together form a storage unit; the drain of the write transistor is connected to the first gate contact structure; forming a write word line, wherein the write word line is connected to the gate of the write transistor; forming a bit line, wherein the bit line is connected to sources of the read transistor and the write transistor; A ground line is formed, and the ground line is connected to the drain of the read transistor.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The manufacturing method further comprises: Etching along the third direction to form grid-shaped grooves exposing the first semiconductor layer; The grid-shaped grooves are filled with an isolation material to form a second isolation layer; wherein the second isolation layer in the grid-shaped grooves isolates the plurality of storage units.

12. The method for manufacturing a semiconductor device according to claim 2, wherein: The semiconductor structure provided comprises: forming a first sacrificial layer, a second semiconductor layer, a second sacrificial layer and a third semiconductor layer in sequence on the first semiconductor layer; The third semiconductor layer, the second sacrificial layer and the second semiconductor layer are sequentially etched along the third direction to form a first groove and a second groove extending along the first direction; wherein the first groove and the second groove are alternately arranged along the second direction.

13. A semiconductor device, characterized in that: The semiconductor device comprises: A first semiconductor layer, a first gate dielectric layer and a first channel layer stacked in sequence; A plurality of semiconductor column groups located on the first channel layer and arranged in an array along a first direction and a second direction; wherein each of the semiconductor column groups comprises a first semiconductor column and a second semiconductor column arranged in parallel along the second direction, the first semiconductor column comprises a first source electrode, a first isolation layer, and a second source electrode in sequence along a third direction, and the second semiconductor column comprises a first drain electrode, a first isolation layer, and a second drain in sequence along the third direction; the first direction and the second direction are both parallel to the first semiconductor layer and intersect with the first direction, and the third direction is perpendicular to the first semiconductor layer; A threshold voltage adjustment layer is located on the first channel layer and between the first semiconductor column and the second semiconductor column in the semiconductor column group; wherein the threshold voltage adjustment layer is used to adjust the threshold voltage of the semiconductor device.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: a fifth semiconductor layer located on the first channel layer and between two adjacent semiconductor column groups; A first gate sequentially penetrating the fifth semiconductor layer and the first channel layer; an insulating layer covering at least a side wall of the first gate; A first gate contact structure is located on the first gate; wherein the first gate, the first channel layer, the first source and the first drain form a first transistor.

15. The semiconductor device according to claim 14, characterized in that The semiconductor device further comprises: A second channel layer covering the surface of the threshold voltage adjustment layer and covering the side walls of the second source and the second drain; a second gate dielectric layer covering the second channel layer; A second gate is located on the second gate dielectric layer; wherein the second gate, the second channel layer, the second source and the second drain form a second transistor; and the threshold voltage adjustment layer is used to adjust the threshold voltage of the first transistor and / or the second transistor.

16. The semiconductor device according to claim 15, characterized in that The first transistor and the second transistor together form a read transistor, the first source and the second source are connected, and the first drain and the second drain are connected; the semiconductor device further includes: A read word line is connected to the second gate.

17. The semiconductor device according to claim 16, characterized in that The semiconductor device further comprises: A write transistor, wherein the read transistor and the write transistor together form a storage unit; a drain of the write transistor is connected to a first gate contact structure; a write word line connected to the gate of the write transistor; a bit line connected to sources of the read transistor and the write transistor; A ground line is connected to the drain of the read transistor.

18. The semiconductor device according to claim 17, wherein: The semiconductor device further comprises: A second isolation layer is used to isolate a plurality of the storage units arranged in an array along the first direction and the second direction.

Images