Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate including a device isolation film defining an active region; and a cell gate structure in the trench including the first region and the second region, the cell gate structure extending to cross the active region, each of the cell gate structures includes a cell gate insulating layer extending along an inner sidewall of the trench, a first gate dielectric film on a sidewall of the cell gate insulating layer in a first region of the trench, a second gate dielectric film on a sidewall of the cell gate insulating layer in a second region of the trench, and a cell gate electrode structure including a first gate electrode layer on a sidewall of the first gate dielectric film in the first region and a second gate electrode layer on a sidewall of the second gate dielectric film in the second region.

Description

Technical Field

[0001] Embodiments relate to a semiconductor memory device. Background Art

[0002] As semiconductor devices continue to advance in miniaturization, individual circuit patterns are becoming increasingly finer to accommodate more semiconductor components in the same area. As the integration density of devices including buried channel array transistors (BCAT) grows, the pitch of multiple word lines embedded in the substrate of the BCAT is gradually reduced. Summary of the invention

[0003] An embodiment may be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a substrate including a device isolation film defining an active region; and a cell gate structure in a trench, the trench including a first region in the substrate and a second region on the first region, the cell gate structure extending to intersect the active region, wherein each of the cell gate structures includes a cell gate insulating layer extending along an inner sidewall of its corresponding trench, a first gate dielectric film on a sidewall of the cell gate insulating layer in a first region of the corresponding trench, a second gate dielectric film on a sidewall of the cell gate insulating layer in a second region of the corresponding trench, and a cell gate electrode structure, the cell gate electrode structure including a first gate electrode layer on a sidewall of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on a sidewall of the second gate dielectric film in the second region of the corresponding trench, the second gate dielectric film having a thickness greater than the first gate dielectric film relative to the inner sidewall of the corresponding trench.

[0004] An embodiment may be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a substrate including a device isolation film defining an active region; and a gate structure in a trench, the trench including a first region in the substrate and a second region on the first region, the gate structure extending to intersect the active region, wherein each of the gate structures includes a first gate insulating layer extending along the sidewall and bottom surface of its corresponding trench, a first gate dielectric film on the sidewall of the first gate insulating layer in the first region of the corresponding trench, a second gate dielectric film on the sidewall of the first gate insulating layer in the second region of the corresponding trench, a barrier layer between the first gate dielectric film and the second gate dielectric film, a gate electrode structure and a capping film, the gate electrode structure including a first gate electrode layer on the sidewall of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on the sidewall of the second gate dielectric film in the second region of the corresponding trench, the capping film on the second gate electrode layer, and the barrier layer in contact with the bottom surface of the second gate dielectric film and the top surface of the first gate dielectric film.

[0005] An embodiment may be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a substrate including a device isolation film defining an active region; and a gate structure in a trench, the trench including a first region in the substrate and a second region on the first region, the gate structure extending to intersect the active region, wherein each of the gate structures includes a first gate insulating layer extending along the sidewall and bottom surface of its corresponding trench, a first gate dielectric film on the sidewall of the first gate insulating layer in the first region of the corresponding trench, a second gate dielectric film on the sidewall of the first gate insulating layer in the second region of the corresponding trench, a barrier layer between the first gate dielectric film and the second gate dielectric film, a gate electrode structure, an insertion insulating layer and a capping film, the gate electrode structure including a first gate electrode layer on the sidewall of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on the sidewall of the second gate dielectric film in the second region of the corresponding trench, the insertion insulating layer between the barrier layer and the second gate electrode layer, the capping film on the second gate electrode layer, and the second gate dielectric film having a thickness greater than the first gate dielectric film relative to the sidewall of the corresponding trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will be apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure;

[0008] Figure 2 Only depicts Figure 1 A layout diagram of word lines and active areas;

[0009] Figure 3 is along Figure 1 A cross-sectional view taken along line AA;

[0010] Figure 4 is along Figure 1 A cross-sectional view taken along line BB;

[0011] Figure 5 is along Figure 1 A cross-sectional view taken along line CC;

[0012] Figure 6 is along Figure 1 A cross-sectional view taken along line DD;

[0013] Figure 7 yes Figure 6 An exemplary enlarged cross-sectional view of a portion P of;

[0014] Figures 8 to 11 yes Figure 6Other exemplary enlarged cross-sectional views of portion P; and

[0015] Figures 12 to 18 are layout diagrams or cross-sectional views of various stages in a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Figure 1 is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure. Figure 2 Only depicts Figure 1 Layout diagram of the word lines and active areas. Figure 3 is along Figure 1 A cross-sectional view taken along line AA.

[0017] Figure 4 is along Figure 1 A cross-sectional view taken along line BB. Figure 5 is along Figure 1 A cross-sectional view taken along line CC. Figure 6 is along Figure 1 A cross-sectional view taken along line DD.

[0018] The semiconductor memory device according to some embodiments of the present disclosure may be, for example, a dynamic random access memory (DRAM) device.

[0019] Reference Figure 1 and Figure 2 , a semiconductor memory device according to some embodiments of the present disclosure may include a plurality of unit active regions ACT.

[0020] The cell active area ACT may be defined by the cell device isolation film 105. According to the reduction of the semiconductor memory device (eg, its size) according to some embodiments of the present disclosure, the cell active area ACT may be arranged as a diagonal strip or an inclined strip. For example, the cell active area ACT may extend in the third direction DR3.

[0021] A plurality of gate electrodes may be arranged, extending across the cell active area ACT in a first direction DR1. The gate electrodes may extend parallel to each other. The gate electrodes may be, for example, word lines WL. The word lines WL may be arranged at equal intervals. According to some embodiments of the present disclosure, the width of the word lines WL or the spacing between the word lines WL may be determined by the design rules of the semiconductor memory device.

[0022] Each of the cell active areas ACT may be divided into three sections by two adjacent word lines WL extending in the first direction DR1. Each of the cell active areas ACT may include a storage connection portion 103b and a bit line connection portion 103a. The bit line connection portion 103a may be located at the center of its corresponding cell active area ACT, and the storage connection portion 103b may be located at the end of the corresponding cell active area ACT.

[0023] In an implementation, the bit line connection portion 103a may be a portion of the corresponding cell active region ACT connected to the bit line BL, and the storage connection portion 103b may be a portion of the corresponding cell active region ACT connected to the information storage unit ( Figure 3 In an implementation, the bit line connection portion 103a may correspond to a common drain region, and the storage connection portion 103b may correspond to a source region. Each word line WL may form a transistor together with its adjacent bit line connection portion 103a and storage connection portion 103b.

[0024] A plurality of bit lines BL extending in a second direction DR2 perpendicular to the word line WL may be on the word line WL. The bit lines BL may extend parallel to each other. The bit lines BL may be arranged at equal intervals. The width of the bit lines BL and the spacing between the bit lines BL may be determined by the design rules of the semiconductor memory device according to some embodiments of the present disclosure.

[0025] The fourth direction DR4 may be perpendicular to the first direction DR1, the second direction DR2, and the third direction DR3. The fourth direction DR4 may correspond to a thickness direction of the substrate 100.

[0026] The semiconductor memory device according to some embodiments of the present disclosure may include various contact arrays on the cell active area ACT. The contact array may include, for example, a direct contact DC, a buried contact BC, or a landing pad LP.

[0027] The direct contact DC may refer to a contact that electrically connects the cell active region ACT to the bit line BL. The buried contact BC may refer to a contact that connects the cell active region ACT to the lower electrode ( Figure 3 The contact area between the buried contact BC and the cell active area ACT may be relatively small. In order to increase the contact area with the cell active area ACT and the contact area with the lower electrode 191, a conductive landing pad LP may be provided.

[0028] The landing pad LP may be between the cell active area ACT and the buried contact BC. In an implementation, the landing pad LP may be between the buried contact BC and the lower electrode 191. The landing pad LP may increase a contact area with the cell active area ACT and a contact area with the lower electrode 191, and a contact resistance between the cell active area ACT and the lower electrode 191 may be reduced.

[0029] The direct contact DC may be connected to the bit line connection portion 103a of the cell active area ACT. The buried contact BC may be connected to the storage connection portion 103b of the cell active area ACT. The buried contact BC may be located near the respective ends of the cell active area ACT, and the landing pad LP may overlap the buried contact BC portion near the respective ends of each of the cell active areas ACT. In an implementation, the buried contact BC may overlap the cell active area ACT and the cell device isolation film 105 between the word lines WL and between the bit lines BL.

[0030] The word line WL may be buried in the substrate 100. The word line WL may extend across the cell active area ACT between the direct contacts DC or between the buried contacts BC. Two word lines WL may extend across a single cell active area ACT. The cell active area ACT may extend in a third direction DR3, and the word line WL may form an angle less than 90 degrees with the cell active area ACT.

[0031] The direct contact DC and the buried contact BC may be arranged symmetrically. The direct contact DC and the buried contact BC may be arranged in a straight line along the first direction DR1 and the second direction DR2. Unlike the direct contact DC and the buried contact BC, the landing pads LP may be arranged in a zigzag pattern along (i.e., in) the second direction DR2, which corresponds to the extension direction of the bit lines BL. The landing pads LP may overlap with the same side of their respective bit lines BL in the first direction DR1, which corresponds to the extension direction of the word lines WL.

[0032] In an implementation, in a first row, the landing pads LP may overlap the left sides of their respective bit lines BL, and in a second row, the landing pads LP may overlap the right sides of their respective bit lines BL.

[0033] Reference Figures 1 to 7 , a semiconductor memory device according to some embodiments of the present disclosure may include a plurality of cell gate structures 110 , a plurality of bit line structures 140ST, a plurality of bit line contacts 146 , and an information storage unit 190 .

[0034] The substrate 100 may be a silicon (Si) or silicon-on-insulator (SOI) substrate. In an implementation, the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium nitride, gallium arsenide, or gallium antimonide. As used herein, the term "or" is not necessarily an exclusive term, for example, "A or B" will include A, B, or A and B.

[0035] The cell device isolation film 105 may be in the substrate 100. The cell device isolation film 105 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell device isolation film 105 may define a cell active region ACT in a memory cell region.

[0036] The cell active region ACT defined by the cell device isolation film 105 may have a long island shape having both a long axis and a short axis, such as Figure 1 and Figure 2 The cell active region ACT may have an inclined shape, forming an angle less than 90 degrees with respect to the word line WL formed in the cell device isolation film 105. The cell active region ACT may also have an inclined shape, forming an angle less than 90 degrees with respect to the bit line BL in the cell device isolation film 105.

[0037] The cell device isolation film 105 may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0038] In an implementation, the cell device isolation film 105 may be a single insulating film. In an implementation, the cell device isolation film 105 may be a single insulating film or a stack of multiple insulating films according to a spacing between the cell active regions ACT.

[0039] In the implementation, Figure 3 As shown, the top surface of the cell device isolation film 105 and the top surface of the substrate 100 can be on the same plane. Figure 3 The height of the top surface of the cell device isolation film 105 depicted in FIG. 1 may be different from Figure 4 . The height of the top surface of the cell device isolation film 105 is depicted in FIG.

[0040] The cell gate structure 110 may be in the substrate 100 and the cell device isolation film 105. The cell gate structure 110 may be formed across the cell device isolation film 105 and the cell active region ACT defined by the cell device isolation film 105.

[0041] The cell gate structure 110 may include a cell gate trench 110T, a cell gate insulating layer 111 , a cell gate electrode 112 , a first gate dielectric film 113 , a second gate dielectric film 114 , and a cell gate capping film 116 , and may further include a barrier layer 115 .

[0042] In an implementation, the cell gate electrode 112 may correspond to a word line WL. In an implementation, the cell gate electrode 112 may be Figure 1 The word line WL.

[0043] In the implementation, Figure 5 As depicted, the cell gate trench 110T may be relatively deep in the cell device isolation film 105 and relatively shallow in the cell active area ACT. The bottom surface of the word line WL may be curved. In an implementation, the depth of the cell gate trench 110T may be greater in the cell device isolation film 105 than in the cell active area ACT.

[0044] The cell gate trench 110T may include a first region A1 in the substrate 100 and a second region A2 on the first region A1. The second region A2 may be closer to the top surface of the substrate 100 than the first region A1 in the fourth direction DR4.

[0045] The cell gate insulating layer 111 may extend along the sidewalls and bottom surface of each of the cell gate trenches 110T. The cell gate insulating layer 111 may extend along at least a portion of the outline of the cell gate trenches 110T. In an implementation, the sidewalls and bottom surface of the cell gate trenches 110T may also be referred to as inner sidewalls of the cell gate trenches 110T.

[0046] The cell gate insulating layer 111 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0047] The first gate dielectric film 113 may be on a sidewall of the cell gate insulating layer 111 in each first region A1 of the cell gate trench 110T. A top surface of the first gate dielectric film 113 may be on the same plane as a top surface of the first gate electrode layer 112A.

[0048] The second gate dielectric film 114 may be on the sidewall of the cell gate insulating layer 111 in each second region A2 of the cell gate trench 110T. A top surface of the second gate dielectric film 114 may be on the same plane as a top surface of the cell gate insulating layer 111.

[0049] Reference Figure 7, with respect to the sidewall of the cell gate trench 110T, the sum T2 of the thickness of the cell gate insulating layer 111 and the second gate dielectric film 114 may be greater than the sum T1b of the thickness of the cell gate insulating layer 111 and the first gate dielectric film 113. The sum T2 of the thickness of the cell gate insulating layer 111 and the second gate dielectric film 114 from the sidewall of the cell gate trench 110T may be greater than the sum T1a of the thickness of the cell gate insulating layer 111 and the first gate dielectric film 113 from the bottom surface of the cell gate trench 110T.

[0050] In an implementation, the sum T2 of the thickness of the cell gate insulating layer 111 and the second gate dielectric film 114 may be or greater, the sum T1a of the thickness of the cell gate insulating layer 111 and the first gate dielectric film 113 may be to

[0051] With respect to the sidewall of the cell gate trench 110T, the thickness of the second gate dielectric film 114 may be greater than the thickness of the first gate dielectric film 113. The thickness of the second gate dielectric film 114 from the sidewall of the cell gate trench 110T may be greater than the thickness of the first gate dielectric film 113 from the bottom surface of the cell gate trench 110T.

[0052] In an implementation, the first gate dielectric film 113 may include a high-k material having a larger dielectric constant than silicon oxide, and the second gate dielectric film 114 may include a dielectric material having a smaller dielectric constant than silicon oxide.

[0053] The first gate dielectric film 113 may include HfSiO 2 , HfSiON or AlO. The second gate dielectric film 114 may include a dielectric material having a smaller dielectric constant than the first gate dielectric film 113. In an implementation, the second gate dielectric film 114 may include silicon oxide (SiO 2 ) or dielectric constant is less than SiO 2 In an implementation, the second gate dielectric film 114 may include porous silicon oxide. The second gate dielectric film 114 may include porous silicate, such as SiCOH.

[0054] In an implementation, the second gate dielectric film 114 may include a dielectric material having a larger dielectric constant than silicon oxide.

[0055] The use of the first gate dielectric film 113 can help improve insulation breakdown characteristics and increase current near the channel region by preventing damage to the lower portion of the cell gate insulating layer 111. However, this may also increase the possibility of gate induced drain leakage (GIDL) as leakage current to the drain region.

[0056] Meanwhile, the use of the second gate dielectric film 114 can help to relax the electric field above the cell gate trench 110T, thereby reducing GIDL and preventing refresh time characteristics from being degraded.

[0057] The cell gate electrode 112 may be on the cell gate insulating layer 111. The cell gate electrode 112 may at least partially fill the cell gate trench 110T.

[0058] The cell gate electrode 112 may include a first gate electrode layer 112A and a second gate electrode layer 112B on the first gate electrode layer 112A. The first gate electrode layer 112A may be on the sidewall of the first gate dielectric film 113 in each first region A1 of the cell gate trench 110T. The second gate electrode layer 112B may be on the sidewall of the second gate dielectric film 114 in each second region A2 of the cell gate trench 110T.

[0059] In an implementation, the thickness of the second gate dielectric film 114 may be greater than the thickness of the first gate dielectric film 113 , and the width W2 of the second gate electrode layer 112B may be smaller than the width W1 of the first gate electrode layer 112A.

[0060] The second gate electrode layer 112B may not be in contact with the first gate dielectric film 113 .

[0061] The first gate electrode layer 112A may include a metal, a metal alloy, or a conductive metal nitride. In an implementation, the first gate electrode layer 112A may include titanium nitride. In an implementation, the second gate electrode layer 112B may include a conductive material such as polysilicon.

[0062] In an implementation, the first gate electrode layer 112A and the second gate electrode layer 112B may include a work function control material. In an implementation, the work function of the first gate electrode layer 112A may be different from the work function of the second gate electrode layer 112B.

[0063] The barrier layer 115 may be between the first gate dielectric film 113 and the second gate dielectric film 114 .

[0064] The top surface of the barrier layer 115 may contact the bottom surfaces of the second gate dielectric film 114 and the second gate electrode layer 112B. The bottom surface of the barrier layer 115 may contact the top surface of the first gate dielectric film 113 and the top surface of the first gate electrode layer 112A.

[0065] In an implementation, the barrier layer 115 may include titanium nitride, silicon nitride, tungsten oxide, or silicon oxide.

[0066] The use of the barrier layer 115 may help prevent the first gate dielectric film 113 and the second gate electrode layer 112B from contacting each other, thereby effectively preventing Fermi level pinning.

[0067] The cell gate capping film 116 may be on the second gate electrode layer 112B and on the sidewalls of the second gate dielectric film 114. After forming the cell gate electrode 112 and the second gate dielectric film 114, the cell gate capping film 116 may fill the remaining area of ​​the cell gate trench 110T. At least a portion of the top surface of the second gate dielectric film 114 may be on the same plane as the top surface of the cell gate capping film 116.

[0068] The cell gate capping film 116 may include, for example, silicon nitride (SiN), silicon nitride oxide (SiON), SiO 2 , silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0069] In the implementation, Figure 4 As shown, the top surface of the cell gate capping film 116 may be on the same plane as the top surface of the cell device isolation film 105 .

[0070] Reference Figure 6 The impurity doped region may be at least one side of each of the cell gate structures 110. The impurity doped region may be a source / drain region of a transistor. The impurity doped region may be at least one side of each of the cell gate structures 110. Figure 2 The storage connection portion 103b and the bit line connection portion 103a.

[0071] In the implementation, refer to Figure 2 , the transistor including the word line WL, the bit line connection portion 103a and the storage connection portion 103b may be an n-type metal oxide semiconductor (NMOS) transistor, and the storage connection portion 103b and the bit line connection portion 103a may be a region doped with an n-type impurity, such as phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi). In an implementation, the transistor including the word line WL, the bit line connection portion 103a and the storage connection portion 103b may be a p-type metal oxide semiconductor (PMOS) transistor, and the storage connection portion 103b and the bit line connection portion 103a may be a region doped with a p-type impurity such as boron (B).

[0072] The bit line structure 140ST may include a cell conductive line 140 , a cell line capping film 144 , and a bit line spacer 150 .

[0073] The cell conductive line 140 may be located on the cell device isolation film 105 having the cell gate structure 110 thereon and the substrate 100. The cell conductive line 140 may cross the cell device isolation film 105 and the cell active area ACT defined by the cell device isolation film 105. The cell conductive line 140 may cross the cell gate structure 110. The cell conductive line 140 may correspond to the bit line BL. In an implementation, the cell conductive line 140 may be Figure 1 The bit line BL.

[0074] The unit conductive line 140 may include, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, a metal, or a metal alloy. The 2D material may be a metal material or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, such as graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) or tungsten disulfide (WS 2 ).

[0075] In an implementation, the unit conductive line 140 may be a single film. In an implementation, the unit conductive line 140 may include a stack of a plurality of conductive films.

[0076] The cell line cover film 144 may be on the cell conductive line 140. The cell line cover film 144 may extend in the second direction DR2 along the top surface of the cell conductive line 140. The cell line cover film 144 may include, for example, a silicon nitride film, a silicon oxynitride film, a silicon carbon nitride film, or a silicon oxycarbon nitride film.

[0077] The cell line cover film 144 may include a silicon nitride film. In an implementation, as shown in the figure, the cell line cover film 144 may be a single film.

[0078] The bit line spacer 150 may be on a sidewall of the cell conductive line 140 and a sidewall of the cell line capping film 144. The bit line spacer 150 may extend in the second direction DR2.

[0079] In an implementation, as shown, the bit line spacer 150 may be a single film. In an implementation, the bit line spacer 150 may have a multi-layer structure. The bit line spacer 150 may include, for example, silicon oxide, silicon nitride, SiON, SiOCN, air, or a combination thereof.

[0080] The cell insulating film 130 may be on the substrate 100 and the cell device isolation film 105. In an implementation, the cell insulating film 130 may be on a portion of the substrate 100 where the bit line contact 146 and the storage contact 120 are not formed and on a top surface of the cell device isolation film 105. The cell insulating film 130 may be between the substrate 100 and the cell conductive line 140 and between the cell device isolation film 105 and the cell conductive line 140.

[0081] In an implementation, as shown in the figure, the unit insulating film 130 may be a single film, or the unit insulating film 130 may be a multi-layer film including a first unit insulating film 131 and a second unit insulating film 132. In an implementation, the first unit insulating film 131 may include a silicon oxide film, and the second unit insulating film 132 may include a silicon nitride film. In an implementation, the unit insulating film 130 may be a silicon oxide film, a silicon nitride film, or a three-layer film including a silicon oxide film.

[0082] The bit line contact 146 may be between the cell conductive line 140 and the substrate 100. The cell conductive line 140 may be on the bit line contact 146.

[0083] The bit line contact 146 may be between the bit line connection portion 103a of the cell active region ACT and the cell conductive line 140. The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100. The bit line contact 146 may be connected to the bit line connection portion 103a.

[0084] The bit line contact 146 may include a top surface connected to the cell conductive line 140. In an implementation, as shown, the width of the bit line contact 146 measured in the first direction DR1 may be uniform in a direction away from the top surface of the bit line contact 146.

[0085] The bit line contact 146 may correspond to a direct contact DC. The bit line contact 146 may include, for example, a semiconductor material doped with impurities, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a metal, or a metal alloy.

[0086] On some cell conductive lines 140 formed with bit line contacts 146, bit line spacers 150 may be on the substrate 100 and the cell device isolation film 105. The bit line spacers 150 may be on sidewalls of the cell conductive lines 140, the cell line capping film 144, and the bit line contacts 146.

[0087] On other cell conductive lines 140 where the bit line contacts 146 are not formed, the bit line spacers 150 may be on the cell insulating film 130. The bit line spacers 150 may be on the sidewalls of the cell conductive lines 140 and the sidewalls of the cell line capping film 144.

[0088] The fence pattern 170 may be on the substrate 100 and the cell device isolation film 105. The fence pattern 170 may overlap with the cell gate structure 110, and the cell gate structure 110 may be in the substrate 100 and the cell device isolation film 105.

[0089] The fence pattern 170 may be between the bit line structures 140ST extending in the second direction DR2. The fence pattern 170 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0090] The storage contact 120 may be between the cell conductive lines 140 adjacent to each other in the first direction DR1. The storage contact 120 may be at both sides of each of the cell conductive lines 140. In an implementation, the storage contact 120 may be between the bit line structures 140ST. The storage contact 120 may be between the fence patterns 170 adjacent to each other in the second direction DR2.

[0091] The storage contact 120 may overlap the substrate 100 and the cell device isolation film 105 between the cell conductive lines 140. The storage contact 120 may be connected to the cell active region ACT. In an implementation, the storage contact 120 may correspond to the storage connection portion 103b. In an implementation, the storage contact 120 may correspond to the storage connection portion 103b. Figure 1 The buried contact BC.

[0092] The storage contact 120 may include, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0093] The storage pad 160 may be on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may be connected to the storage connection portion 103b. In an implementation, the storage pad 160 may correspond to a landing pad LP.

[0094] The storage pad 160 may overlap a portion of a top surface of the bit line structure 140ST. The storage pad 160 may include, for example, a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.

[0095] The pad isolation insulating film 180 may be on the storage pad 160 and the bit line structure 140ST. In an implementation, the pad isolation insulating film 180 may be on the cell line cover film 144. The pad isolation insulating film 180 may define the storage pad 160, and the pad isolation insulating film 180 forms a plurality of isolation regions. The pad isolation insulating film 180 may not cover the top surface of the storage pad 160. In an implementation, the height of the top surface of the storage pad 160 may be the same as the height of the top surface of the pad isolation insulating film 180 relative to the top surface of the substrate 100.

[0096] Pad isolation insulating film 180 may include an insulating material and may electrically insulate storage pad 160. In an implementation, pad isolation insulating film 180 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbon nitride film, or a silicon carbon nitride film.

[0097] The etch stop film 292 may be on the top surface of the storage pad 160 and the top surface of the pad isolation insulating film 180. The etch stop film 292 may include, for example, SiN, SiCN, SiOCN, SiOC, or SiBN.

[0098] The information storage unit 190 may be on the storage pad 160. The information storage unit 190 may be connected to the storage pad 160. The information storage unit 190 may be partially in the etch stop film 292.

[0099] The information storage unit 190 may include, for example, a capacitor. The information storage unit 190 may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. In an implementation, the upper electrode 193 may include a plate-shaped upper electrode having a plate shape.

[0100] The lower electrode 191 may be on the storage pad 160. The lower electrode 191 may have, for example, a pillar shape.

[0101] The capacitor dielectric film 192 may be on the lower electrode 191. The capacitor dielectric film 192 may follow the contour of the lower electrode 191. The upper electrode 193 may be on the capacitor dielectric film 192. The upper electrode 193 may surround the outer sidewall of each of the lower electrodes 191. In an implementation, as shown in the figure, the upper electrode 193 may be, for example, a single film.

[0102] The lower electrode 191 and the upper electrode 193 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (e.g., iridium oxide or niobium oxide).

[0103] The capacitor dielectric film 192 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The capacitor dielectric film 192 may have a structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence. The capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). The capacitor dielectric film 192 may have a stacked film structure in which a ferroelectric material film and a paraelectric material film are stacked.

[0104] Figures 8 to 11 yes Figure 6 Other exemplary enlarged cross-sectional views of the portion P of FIG. Figures 8 to 11 implementation methods, highlighting Figures 1 to 7 The difference in implementation methods.

[0105] Reference Figure 8 , there may be no barrier layer between the first gate dielectric film 113 and the second gate dielectric film 114. In an implementation, with respect to the inner sidewall of the unit gate trench 110T, the sum T2 of the thickness of the unit gate insulating layer 111 and the second gate dielectric film 114 may be greater than the sum T1b of the thickness of the unit gate insulating layer 111 and the first gate dielectric film 113. The second gate electrode layer 112B may not be in contact with the first gate dielectric film 113.

[0106] Reference Fig. 9 The cell gate structure 110 may further include an insertion insulating layer 117 which may be between the barrier layer 115 and the second gate electrode layer 112B. The insertion insulating layer 117 may have a width smaller than that of the barrier layer 115 .

[0107] The insertion insulating layer 117 may include the same material as the second gate dielectric film 114. In an implementation, as shown in FIG. Fig. 9 As shown, the interface between the insertion insulating layer 117 and the second gate dielectric film 114 may be clear. In an implementation, the insertion insulating layer 117 and the second gate dielectric film 114 may be integrally formed together.

[0108] In an implementation, the insertion insulating layer 117 may include a material having a smaller dielectric constant than silicon oxide and the first gate dielectric film 113. In an implementation, the insertion insulating layer 117 may include a material having a larger dielectric constant than silicon oxide. In an implementation, the thickness T3 of the insertion insulating layer 117 may be or smaller.

[0109] Reference Fig.10 , the unit gate structure 110 may not include the barrier layer 115. In an implementation, the insertion insulating layer 117 may be between the first gate electrode layer 112A and the second gate electrode layer 112B, and may contact the first gate electrode layer 112A and the second gate electrode layer 112B. In an implementation, the thickness T3 of the insertion insulating layer 117 may be or smaller.

[0110] Reference Fig.11 , the first gate dielectric film 113 may be further disposed between the unit gate insulating layer 111 and the second gate dielectric film 114. In an implementation, the first gate dielectric film 113 may be further disposed in the second region ( Figure 6The top surface of the first gate dielectric film 114 may be on the same plane as the top surface of the cell gate insulating layer 111. In an implementation, the upper portion of the first gate dielectric film 113 may not be removed but may remain.

[0111] Figures 12 to 18 1 is a layout diagram or cross-sectional view of various stages in a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Figures 12 to 18 implementation methods, highlighting Figures 1 to 11 The difference in implementation methods.

[0112] Fig.12 is a layout diagram showing stages in a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Figures 13 to 18 is along Fig.12 A cross-sectional view taken along line EE.

[0113] Reference Fig.12 , a cell device isolation film 105 may be formed in the substrate 100. The cell device isolation film 105 may have a shallow trench isolation (STI) structure. The cell device isolation film 105 may define a cell active region ACT in the memory cell region.

[0114] The cell device isolation film 105 may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0115] In an implementation, as shown in the figure, the unit device isolation film 105 may be formed as a single insulating film. In an implementation, the unit device isolation film 105 may be formed as a single insulating film or a stack of a plurality of insulating films.

[0116] Reference Fig.12 and Fig.13 , a first trench 110T may be formed in the substrate 100 and the cell device isolation film 105. In an implementation, the first trench 110T may be formed by forming a mask pattern on the substrate 100 and etching the substrate 100 using the mask pattern as an etching mask. The first trench 110T may extend in the first direction DR1. The first trench 110T may be formed across the cell device isolation film 105 and the cell active area ACT defined by the cell device isolation film 105.

[0117] A cell gate insulating layer 111 may be formed in the first trench 110T and on the top surface of the substrate 100. The cell gate insulating layer 111 may be formed by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. The cell gate insulating layer 111 may be formed along the sidewall and bottom surface of each of the first trenches 110T. The cell gate insulating layer 111 may include silicon oxide.

[0118] Reference Fig.14 , a first gate dielectric film 113 may be formed on the cell gate insulating layer 111. The first gate dielectric film 113 may be formed along the sidewall and bottom surface of each of the first trenches 110T, filling the inside of the first trenches 110T.

[0119] The first gate dielectric film 113 may include, for example, HfSiO 2 , HfSiON or AlO.

[0120] Reference Fig.15 , a first pre-cell gate electrode 112P may be formed on the first gate dielectric film 113 .

[0121] A conductive material may be deposited on the first gate dielectric film 113. The conductive material may fill the first trench 110T. The deposition of the conductive material may be performed by a CVD process. The conductive material may include, for example, a metal, a metal alloy, or a conductive metal nitride.

[0122] Reference Fig.16 , the lower pre-cell gate electrode 112PA may be formed by partially etching the first pre-cell gate electrode 112P. In an implementation, the conductive material may be etched by an etch-back process.

[0123] The etch-back process may be performed using an etching selectivity between a metal material present in the first pre-cell gate electrode 112P and an oxide present in the cell gate insulating layer 111 and the first gate dielectric film 113 .

[0124] As a result of the etch-back process, a second trench 120T may be formed on the lower pre-cell gate electrode 112PA and the first gate dielectric film 113 .

[0125] Thereafter, the lower pre-cell gate electrode 112PA may be thermally treated. As a result of the thermal treatment, impurities present in the lower pre-cell gate electrode 112PA may be removed.

[0126] Reference Fig.17 At least a portion of the first gate dielectric film 113 that exceeds the top surface of the lower pre-cell gate electrode 112PA may be removed. Thereafter, a barrier layer 115 may be formed on the top surface of the lower pre-cell gate electrode 112PA.

[0127] Thus, a third trench 130T exposing a portion of the sidewall of the cell gate insulating layer 111 and the top surface of the barrier layer 115 may be formed.

[0128] Reference Fig.18 , a second gate dielectric film 114 and an insertion insulating layer 117 may be formed along the sidewall and bottom surface of the third trench 130T.

[0129] In an implementation, the insertion insulating layer 117 may include a material having a smaller dielectric constant than silicon oxide and the first gate dielectric film 113. In an implementation, the insertion insulating layer 117 may include a material having a larger dielectric constant than silicon oxide.

[0130] The second gate dielectric film 114 may be formed only on the sidewalls of the third trench 130T, but not on the bottom surface of the third trench 130T. In an implementation, a portion of the second gate dielectric film 114 formed on the bottom surface of the third trench 130T may be removed. In an implementation, as shown in FIG. Fig. 9 As shown, the second gate dielectric film 114 may be formed on the sidewalls of the third trench 130T, and the insertion insulating layer 117 may be formed on the bottom surface of the third trench 130T.

[0131] Thereafter, a second pre-cell gate electrode may be deposited on the second gate dielectric film 114. In an implementation, the second pre-cell gate electrode may include a conductive material such as polysilicon.

[0132] The upper pre-cell gate electrode 112PB may be formed by partially etching the second pre-cell gate electrode. In an implementation, the conductive material may be etched through an etch-back process.

[0133] As a result of the etch-back process, a fourth trench 140T may be formed on the upper pre-cell gate electrode 112PB and the second gate dielectric film 114 .

[0134] Thereafter, the upper pre-cell gate electrode 112PB may be heat-treated.

[0135] Thereafter, a cell gate capping film 116 may be formed on the upper pre-cell gate electrode 112PB and the second gate dielectric film 114, filling the fourth trench 114T. In an implementation, the cell gate capping film 116 may be formed by forming a capping film on the entire surface of the substrate 100 and performing a planarization process. The cell gate capping film 116 may include, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. In this process, a portion of the cell gate insulating layer 111 covering the substrate 100 may be removed.

[0136] As a result of the planarization process, a cell gate structure 110 may be formed. The cell gate structure 110 may include a cell gate trench 110T, a cell gate insulating layer 111, a cell gate electrode 112, a first gate dielectric film 113, a second gate dielectric film 114, a barrier layer 115, an insertion insulating layer 117, and a cell gate capping film 116. The cell gate electrode 112 may correspond to a word line WL.

[0137] Thereafter, a bit line structure 140ST that may extend in the second direction DR2 may be formed on the substrate 100 . The bit line structure 140ST may include a cell conductive line 140 , a cell line capping film 144 , and a bit line spacer 150 .

[0138] A storage contact 120 , a storage pad 160 , and an information storage unit 190 may be formed on the storage connection portion 103 b of each cell active region ACT. The information storage unit 190 may include a lower electrode 191 , a capacitor dielectric film 192 , and an upper electrode 193 .

[0139] By summarizing and reviewing, the reduction of pitch can lead to an increase in gate-induced drain leakage (GIDL), which can negatively affect the refresh characteristics of the device. To solve this problem, a technology has been developed that uses heterogeneous materials with different work functions as components of the gate electrode to suppress leakage current and accurately control the threshold voltage of the gate electrode.

[0140] One or more embodiments may provide a semiconductor memory device capable of improving reliability and performance.

[0141] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted only in a general and descriptive sense and not for limiting purposes. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

[0142] This application claims the priority of Korean Patent Application No. 10-2023-0077635 filed in the Korean Intellectual Property Office on June 16, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, include: A substrate including a device isolation film defining an active area; as well as a cell gate structure in a trench, the trench including a first region in the substrate and a second region on the first region, the cell gate structure extending to intersect the active region, in: Each of the cell gate structures includes a cell gate insulating layer extending along an inner sidewall of its corresponding trench, a first gate dielectric film on the sidewall of the cell gate insulating layer in a first region of the corresponding trench, a second gate dielectric film on the sidewall of the cell gate insulating layer in a second region of the corresponding trench, and a cell gate electrode structure including a first gate electrode layer on the sidewall of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on the sidewall of the second gate dielectric film in the second region of the corresponding trench, and The second gate dielectric film has a greater thickness than the first gate dielectric film with respect to the inner sidewall of the corresponding trench. 2 . The semiconductor memory device according to claim 1 , wherein the second gate electrode layer and the first gate dielectric film are not in contact with each other. 3 . The semiconductor memory device according to claim 1 , wherein a top surface of the second gate dielectric film is on the same plane as a top surface of the cell gate insulating layer.

4. The semiconductor memory device according to claim 1, in: Each of the unit gate structures further includes an intervening insulating layer between the first gate electrode layer and the second gate electrode layer, and The insertion insulating layer includes the same material as the second gate dielectric film.

5. The semiconductor memory device according to claim 1, in: The first gate dielectric film is further disposed between the sidewall of the cell gate insulating layer and the sidewall of the second gate dielectric film, and A top surface of the first gate dielectric film is on the same plane as a top surface of the cell gate insulating layer. 6 . The semiconductor memory device according to claim 1 , wherein the second gate dielectric film includes a material having a smaller dielectric constant than that of the first gate dielectric film. 7 . The semiconductor memory device according to claim 1 , wherein each of the cell gate structures further comprises a barrier layer between the first gate dielectric film and the second gate dielectric film.

8. The semiconductor memory device according to claim 7, in: A top surface of the barrier layer contacts a bottom surface of the second gate dielectric film and a bottom surface of the second gate electrode layer, and A bottom surface of the barrier layer contacts a top surface of the first gate dielectric film and a top surface of the first gate electrode layer. 9 . The semiconductor memory device according to claim 7 , wherein the barrier layer comprises titanium nitride, silicon nitride, tungsten oxide, or silicon oxide. 10 . The semiconductor memory device according to claim 1 , wherein each of the unit gate structures further includes a capping film on the second gate electrode layer.

11. The semiconductor memory device according to claim 1, further comprising: include: a first source / drain region and a second source / drain region in the active region; a bit line structure on the substrate and connected to the first source / drain region; as well as An information storage unit is on the substrate and connected to the second source / drain region.

12. A semiconductor memory device, include: A substrate including a device isolation film defining an active area; as well as a gate structure in a trench, the trench comprising a first region in the substrate and a second region on the first region, the gate structure extending to intersect the active region, in: Each of the gate structures includes a first gate insulating layer extending along the sidewalls and bottom surface of its corresponding trench, a first gate dielectric film on the sidewalls of the first gate insulating layer in a first region of the corresponding trench, a second gate dielectric film on the sidewalls of the first gate insulating layer in a second region of the corresponding trench, a barrier layer between the first gate dielectric film and the second gate dielectric film, a gate electrode structure, and a capping film, the gate electrode structure including a first gate electrode layer on the sidewalls of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on the sidewalls of the second gate dielectric film in the second region of the corresponding trench, the capping film on the second gate electrode layer, and The barrier layer contacts a bottom surface of the second gate dielectric film and a top surface of the first gate dielectric film.

13. The semiconductor memory device according to claim 12, in: a thickness of the second gate dielectric film from the sidewall of the corresponding trench is greater than a thickness of the first gate dielectric film from the bottom surface of the corresponding trench, and The second gate electrode layer has a width smaller than that of the first gate electrode layer.

14. The semiconductor memory device according to claim 13, in: The sum of the thicknesses of the first gate insulating layer and the second gate dielectric film is or greater, and The sum of the thickness of the first gate insulating layer and the first gate dielectric film is to 15 . The semiconductor memory device according to claim 12 , wherein at least a portion of a top surface of the second gate dielectric film is on the same plane as a top surface of the capping film. 16 . The semiconductor memory device according to claim 12 , wherein the first gate dielectric film includes a material having a larger dielectric constant than the second gate dielectric film.

17. The semiconductor memory device according to claim 12, in: Each of the gate structures further includes an intervening insulating layer between the barrier layer and the second gate electrode layer, and The insertion insulating layer has a width smaller than that of the barrier layer.

18. The semiconductor memory device according to claim 17, wherein the thickness of the insertion insulating layer is or smaller.

19. The semiconductor memory device according to claim 12, in: The first gate dielectric film is further disposed between the sidewall of the first gate insulating layer and the sidewall of the second gate dielectric film, and A top surface of the first gate dielectric film is on the same plane as a top surface of the first gate insulating layer.

20. A semiconductor memory device, include: A substrate including a device isolation film defining an active area; as well as a gate structure in a trench, the trench comprising a first region in the substrate and a second region on the first region, the gate structure extending to intersect the active region, in: Each of the gate structures includes a first gate insulating layer extending along the sidewalls and bottom surface of its corresponding trench, a first gate dielectric film on the sidewalls of the first gate insulating layer in a first region of the corresponding trench, a second gate dielectric film on the sidewalls of the first gate insulating layer in a second region of the corresponding trench, a barrier layer between the first gate dielectric film and the second gate dielectric film, a gate electrode structure, an insertion insulating layer, and a capping film, the gate electrode structure including a first gate electrode layer on the sidewalls of the first gate dielectric film in the first region of the corresponding trench and a second gate electrode layer on the sidewalls of the second gate dielectric film in the second region of the corresponding trench, the insertion insulating layer between the barrier layer and the second gate electrode layer, the capping film on the second gate electrode layer, and The second gate dielectric film has a greater thickness than the first gate dielectric film with respect to the sidewall of the corresponding trench.

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