Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, where the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and where the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite the first side and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first switch and the second switch, and the second terminal is coupled to a second node between the third switch and the fourth switch.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As integrated circuits continue to shrink, more and more devices are integrated into a single chip. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device is disclosed, comprising: a first switch, a second switch, a third switch and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and the second reference voltage; and a capacitor formed on a second side of the substrate opposite to the first side and having a first terminal and a second terminal; wherein the first terminal is coupled to a first node between the first switch and the second switch, and the second terminal is coupled to a second node between the third switch and the fourth switch.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is disclosed, comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor formed on a first side of a substrate, wherein each of the first to fourth transistors has a first source / drain terminal and a second source / drain terminal; and a plurality of first metal tracks and a plurality of second metal tracks formed on a second side of the substrate opposite to the first side; wherein each of the first metal tracks has a second source / drain terminal electrically coupled to the first transistor and a first portion electrically coupled to the first source / drain terminal of the second transistor; wherein each of the second metal tracks has a second source / drain terminal electrically coupled to the third transistor and a second portion electrically coupled to the first source / drain terminal of the fourth transistor; and wherein each of the first metal tracks is physically spaced apart from one or more adjacent second metal tracks.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is disclosed, comprising: forming a first transistor, a second transistor, a third transistor, and a fourth transistor on a front side of a substrate, wherein the first transistor and the second transistor are connected to each other, wherein a first source / drain terminal of the first transistor and a first source / drain terminal of the second transistor are connected to each other at a first common node, and the third transistor and the fourth transistor are connected to each other, wherein a first source / drain terminal of the third transistor and a first source / drain terminal of the fourth transistor are connected to each other at a second common node; forming a plurality of front side metal tracks above the first transistor to the fourth transistor, wherein the front side metal tracks A first front side metal track in the substrate is coupled to respective second source / drain terminals of the first transistor and the third transistor, and a second front side metal track in the front side metal tracks is coupled to respective second source / drain terminals of the second transistor and the fourth transistor; and a plurality of back side metal tracks are formed on a back side of the substrate, wherein the plurality of back side metal tracks are separated from each other by at least one dielectric, and wherein a first subset of the plurality of back side metal tracks is coupled to the first source / drain terminal of the first transistor and the first source / drain terminal of the second transistor, and a second subset of the plurality of back side metal tracks is coupled to the first source / drain terminal of the third transistor and the first source / drain terminal of the fourth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device including a charge pump circuit is shown in accordance with some embodiments.

[0008] Figure 2 It is shown that according to some embodiments, it may be included in Figure 1 An example schematic diagram of a charge pump circuit in a memory device of FIG.

[0009] Figure 3 shows a device configured to form a Figure 2 An example layout of a charge pump circuit.

[0010] Figure 4 and Figure 5 The following are respectively shown based on some embodiments Figure 3 A cross-sectional view of a semiconductor device formed by a layout.

[0011] Figure 6 and Figure 7The following are respectively shown based on some embodiments Figure 3 A cross-sectional view of another semiconductor device formed by a layout.

[0012] Figure 8 and Fig. 9 The following are respectively shown based on some embodiments Figure 3 A cross-sectional view of another semiconductor device formed by a layout.

[0013] Fig.10 and Fig.11 The following are respectively shown based on some embodiments Figure 3 A cross-sectional view of another semiconductor device formed by a layout.

[0014] Fig.12 and Fig.13 The following are respectively shown based on some embodiments Figure 3 A cross-sectional view of another semiconductor device formed by a layout.

[0015] Fig.14 shows a device configured to form a Figure 2 Another example layout of a charge pump circuit.

[0016] Fig.15 and Fig.16 The following are respectively shown based on some embodiments Fig.14 A cross-sectional view of a semiconductor device formed by a layout.

[0017] Fig.17 It is shown that according to some embodiments, it may be included in Figure 1 Another example schematic diagram of a charge pump circuit in a memory device of FIG.

[0018] Fig.18 shows a device configured to form a Fig.17 An example layout of a charge pump circuit.

[0019] Fig.19 and Fig. 20 The following are respectively shown based on some embodiments Fig.18 A cross-sectional view of a semiconductor device formed by a layout.

[0020] Fig.21 According to some embodiments, Fig.18 A cross-sectional view of another semiconductor device formed by a layout.

[0021] Fig. 22 A flow chart is shown of an example method for fabricating a charge pump circuit having a flying capacitor formed on a backside of a substrate in accordance with some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0024] As technology nodes shrink, the integration of semiconductor memory devices becomes higher and higher, and low operating power supply voltages are also widely used. However, even memory devices operating at low voltages may sometimes require high voltage power supplies for certain internal circuits and operations (such as driving bit lines and word lines). To this end, various voltage supply circuits (e.g., voltage or charge pump circuits) have been developed for generating high voltages. Typically, a charge pump circuit consists of a capacitor and a switch. By controlling the on / off of these switches and the corresponding timing of alternately charging and discharging the capacitor, the charge pump circuit can double the power supply voltage to boost or pump the output voltage to a relatively high level. In addition to memory devices (or systems), charge pump circuits also have a wide range of applications, such as liquid crystal display (LCD) drivers, microelectromechanical systems (MEMS), power generation, and the like.

[0025] In the prior art, the switches and capacitors of the charge pump circuit are usually formed on the same side of the substrate. However, as the technology nodes continue to shrink, the relatively high area percentage occupied by the capacitor becomes a problem. For example, in order to effectively provide a sufficiently high boost voltage, it is usually necessary for the capacitor to occupy a certain area, which may disadvantageously squeeze the area that can be used to form other device components. As the technology nodes shrink, this trade-off between the performance of the charge pump circuit and its occupied area becomes more critical. Therefore, the existing charge pump circuit is not completely satisfactory in some aspects.

[0026] The present disclosure provides various embodiments of a charge pump circuit, which includes a plurality of switches and at least one capacitor, wherein the switch and the at least one electrostatic capacitor are formed on different sides of a semiconductor substrate, respectively. For example, each switch that can be implemented as a clocked field effect transistor can be formed along the main (e.g., front side) surface of the substrate, on which a plurality of front side metallization layers are disposed, and the capacitor can be formed across one or more back side metallization layers disposed on the back side of the substrate. By forming the capacitor on the back side, a considerable area can be obtained on the front side, which can advantageously allow more device components to be formed on the front side. In addition, the capacitor can be formed directly below the switch. In this way, the total area of ​​the disclosed charge pump circuit can be significantly reduced. In addition, since the capacitor can be formed by a plurality of back side interconnect structures (e.g., metal tracks), these back side interconnect structures generally present a lower resistance than the front side interconnect structures. Therefore, the parasitic resistance of the capacitor associated with the disclosed charge pump circuit can be greatly reduced. Therefore, the amount of ripple present on the output voltage (e.g., boost voltage) of the disclosed charge pump circuit can be advantageously reduced.

[0027] Figure 1 FIG. 1 is a diagram of a memory device 100 including a memory controller 105 and a memory array 120 according to various embodiments. In one aspect, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 also includes word lines WL 0 , WL 1 …WL J and bit line BL 0 BL 1 …BL K , each word line extends in a first direction (e.g., X direction), and each bit line extends in a second direction (e.g., Y direction). The word line WL and the bit line BL can each be a conductive metal or a conductive rail. In some embodiments, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL, BLB, which is coupled to one or more memory cells 125 in a group of memory cells 125 arranged along a second direction (e.g., Y direction). The bit lines BL, BLB can receive and / or provide differential signals.

[0028] Each memory cell 125 may include a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell 125 is implemented as a static random access memory (SRAM) cell. However, it should be understood that the memory cell 125 can be implemented as any of a variety of other non-volatile memory cells, such as a resistance random access memory (RRAM) cell, a magnetoresistive random access memory cell (MRAM), a phase change random access memory cell (PCRAM), an eFuse, an antifuse, etc., while remaining within the scope of the present disclosure. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0029] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line (BL) controller 112, a word line (WL) controller 114, and a voltage supply circuit 110. The BL controller 112, the WL controller 114, and the voltage supply circuit 110 may be implemented as logic circuits, analog circuits, or a combination thereof. In one configuration, the WL controller 114 is a circuit that provides a voltage or current through one or more word lines WL of the memory array 120, and the BL controller 112 is a circuit that provides or senses a voltage or current through one or more bit lines BL of the memory array 120. In one configuration, the voltage supply circuit 110 is a circuit that provides a voltage signal to the BL controller 112 and / or the WL controller 114. The BL controller 112 may be coupled to the bit lines BL of the memory array 120, and the WL controller 114 may be coupled to the word lines WL of the memory array 120. In some embodiments, the memory controller 105 includes a logic circuit, an analog circuit, or a combination thereof. Figure 1 More, fewer or different components may be shown.

[0030] In various embodiments, the voltage providing circuit 110 may include one or more charge pump circuits, each of which is configured to generate a boosted voltage signal to the BL controller 112 and / or the WL controller 114 to obtain the desired read / write performance. For example, to write data at the memory cell 125, the voltage providing circuit 110 may provide a boosted write voltage (or bias voltage) to the WL controller 114 so that the boosted write voltage is sent to the memory cell 125 through the corresponding word line WL. This allows the bit line and / or complementary bit line of the memory cell 125 to discharge faster. Therefore, when the voltage on the word line is increased, the VCC required for the memory cell 125 (and the memory array 120 as a whole) at a specific write speed can be reduced. min (minimum operating voltage). In another example, during a read operation of the memory cell 125, the voltage on the word line may be boosted to be greater than VCCmin , which allows the voltage present on the bit line to discharge more quickly. Thus, the read speed of the memory cell 125 (and the memory array 120 as a whole) can be increased.

[0031] Figure 2 The voltage supply circuit 110 ( Figure 1 ) of a charge pump circuit. Figure 2 The charge pump circuit shown is referred to as charge pump circuit 200. It should be understood that the circuit is simplified for illustrative purposes. Figure 2 Schematic diagram 200 , therefore, the charge pump circuit of the voltage providing circuit 110 may be implemented in any of a variety of other configurations (as long as it can boost the input voltage to a higher voltage level via a capacitor) while remaining within the scope of the present disclosure.

[0032] As shown, the charge pump circuit 200 includes transistors M1, M2, M3, and M4, and at least one charge transfer capacitor (sometimes referred to as a flying capacitor) C F .exist Figure 2 In the illustrative example, transistors M1 to M4 are each implemented as an n-type field effect transistor. However, it should be understood that transistors M1 to M4 can be implemented as other types of transistors while remaining within the scope of the present disclosure. Specifically, transistors M1 and M2 are connected in series with each other at a first common node "X", and transistors M3 and M4 are connected in parallel with each other at a second common node "Y", wherein the source terminal of transistor M1 and the drain terminal of transistor M2 are connected to each other, and the drain terminal of transistor M3 and the source terminal of transistor M4 are connected to each other. In addition, the input node of the charge pump circuit 200 configured to receive an input voltage Vin (or a first reference voltage) is connected to the drain terminal of transistor M1 and the source terminal of transistor M3; and the output node of the charge pump circuit 200 configured to provide an output voltage Vout is connected to the source terminal of transistor M2. The drain terminal of transistor M4 is connected to ground VSS (or a second reference voltage). The input node and the output node can be connected to the ground VSS (or a second reference voltage) through capacitors C, respectively. in and C out Connect to ground.

[0033] In various embodiments, each of transistors M1 to M4 is operable to function as a switch, and further as a clock-controlled switch. For example, the gate terminal of transistor M1 is connected to a clock CLK signal; the gate terminal of transistor M2 is connected to a logic-inverted clock CLKB signal; the gate terminal of transistor M3 is connected to a logic-inverted clock CLKB signal; and the gate terminal of transistor M4 is connected to the clock CLK signal. In this way, transistors M1 and transistor M4 can be alternately turned on / off relative to transistors M2 and transistor M3. In other words, each of transistors M1 to M4 is operable to function as a switch controlled by a clock signal (and its inverse clock signal). Therefore, transistors M1 to M4 can be replaced with any of a variety of other switches while remaining within the scope of the present disclosure.

[0034] Capacitor C F is connected between node X and node Y. Specifically, capacitor C F The charge pump circuit 200 has a first (e.g., positive) terminal connected to the node X and a second (e.g., negative) terminal connected to the node Y. When the coupled transistors M1 to M4 are alternately activated, the charge pump circuit 200 can provide an output voltage that is a double of the difference between the first reference voltage and the second reference voltage. For example, Figure 2 In the embodiment, the charge pump circuit 200 can provide an output voltage Vout of 2×Vin. In operation, transistors M1 and M4 can be turned on first, and transistors M2 and M3 can be turned off. Therefore, capacitor C F The first terminal and the second terminal are connected to Vin and ground respectively, which is a pair of capacitors C F The capacitor C is charged until the voltage between its first and second terminals is equal to Vin. Next, transistors M2 and M3 can be turned on, while transistors M1 and M4 are turned off. Therefore, capacitor C F The second terminal of the capacitor is connected to Vin, and the capacitor C F The first terminal of the capacitor is connected to Vout. Since the voltage across the capacitor cannot change instantly, the capacitor C F The equivalent voltage Vin across it will be maintained. In order to maintain Vin across it, the capacitor C F Forcing the voltage at the output node (Vout) to be equal to 2×Vin causes the capacitor C F The equivalent voltage across both ends is equal to Vin.

[0035] Figure 3 FIG. 1 shows a circuit that can be used to form a charge pump circuit (eg, Figure 2 In one aspect, the layout 300 includes a plurality of patterns configured to form transistors M1 to M4 and capacitors C FIn addition, the transistors M1 to M4 may be formed on a first side (eg, front side) of the substrate, and the capacitor C F It may be formed on a second side (eg, backside) opposite the substrate, as will be discussed below. It should be noted that layout 300 is simplified for illustrative purposes, and thus, layout 300 may include any of a variety of other components (eg, patterns) while remaining within the scope of the present disclosure.

[0036] As shown, layout 300 includes patterns 302 and 304, each of which is configured to form an active region (hereinafter, "active region 302" and "active region 304", respectively); and patterns 306, 308, 310, and 312, each of which is configured to form a gate structure (hereinafter, "gate structure 306", "gate structure 308", "gate structure 310", and "gate structure 312", respectively). In some embodiments, active regions 302 to 304 may each extend along a first lateral direction (e.g., X direction), and gate structures 306 to 312 may each extend along a different second lateral direction (e.g., Y direction). It should be understood that layout 300 may include any number of each active region and gate structure while remaining within the scope of the present disclosure.

[0037] In some embodiments, each of the active regions 302 to 304 is formed by a stacked structure protruding from a main (e.g., front side) surface of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The portion of the semiconductor structure in the stacked structure covered by the gate structure is retained, while the other portion is replaced with a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., bridging) the other portion of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0038] For example, in Figure 3 , the portion of the active area 302 covered by the gate structure 306 may include multiple nanostructures separated vertically from each other, which may serve as a channel of a first sub-transistor. The portion of the active area 302 disposed on the opposite side of the gate structure 306 is replaced with an epitaxial structure. Such an epitaxial structure may serve as a source / drain terminal of the first sub-transistor. The gate structure 306 may serve as a gate terminal of the first sub-transistor. A second sub-transistor may be formed by the active area 304 and the same gate structure 306. Such a first sub-transistor and a second sub-transistor (coupled in parallel with each other) may together form a transistor M4. Similarly, transistors M1 to M3 may be formed by corresponding active areas and gate structures, such as Figure 3 shown.

[0039] For transistors M1 to M4 formed by active regions 302-304 and gate structures 306-312, node X may be formed by or coupled to a portion of active region 302 between gate structures 310-312 and a portion of active region 304 between gate structures 310-312; and node Y may be formed by or coupled to a portion of active region 302 between gate structures 306-308 and a portion of active region 304 between gate structures 306-308. In addition, a portion of the active region 302 between the gate structures 308-310 and a portion of the active region 304 between the gate structures 308 to 310 can be coupled to the input node / first reference voltage (Vin); a portion of the active region 302 opposite to the intervening portion between the gate structures 306-308 and a portion of the active region 304 opposite to the intervening portion between the gate structures 306-308 can be coupled to a second reference voltage (ground Vss); and a portion of the active region 302 opposite to the intervening portion between the gate structures 310-312 and a portion of the active region 304 opposite to the intervening portion between the gate structures 310-312 can be coupled to the output node (Vout).

[0040] In order to electrically connect each of these transistors to one or more corresponding nodes or signals, the layout 300 may also include a plurality of patterns (not shown), each of which is configured to form a front metal structure / track. In some embodiments, these front metal tracks are formed across a plurality of front metallization layers disposed on the front surface of the substrate. Such front metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., wherein the M0 layer may be the layer closest to the main surface of the substrate. Each front metallization layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetallic dielectric (IMD) materials. The metal track in the corresponding metallization layer (e.g., M0 layer) may sometimes be referred to as M0 track. In some embodiments, each of the input node (Vin), the output node (Vout), and the ground node (GND / VSS) may be coupled to a metal track in a corresponding one of the metallization layers or carried by a metal track, and each of the gate structures 306 to 312 may be coupled to a metal track carrying a clock signal or its inverted signal.

[0041] Layout 300 also includes patterns 314, 316, 318, and 320, each of which is configured to form a via structure (hereinafter, "via structure 314," "via structure 316," "via structure 318," and "via structure 320," respectively); patterns 322, 324, 326, and 328, each of which is configured to form a backside metal track (hereinafter, "metal track 322," "metal track 324," "metal track 326," and "metal track 328," respectively); and patterns 330 and 332, each of which is configured to form a backside metal track (hereinafter, "metal track 330" and "metal track 332," respectively). Each of via structures 314 to 320 may extend partially through the substrate to electrically couple one of the source / drain terminals (formed on the front side) to a corresponding backside metal track. Such via structures 314 to 320 may sometimes be referred to as VB structures. Similar to the front side, on the back side of the substrate, multiple backside metallization layers may be formed, which are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc. Each backside metal layer includes multiple metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetallic dielectric (IMD) materials. Metal tracks 322 to 328 may be formed in the BM0 layer, and metal tracks 330 to 332 may be formed in the BM1 layer. Therefore, metal tracks 322 to 328 may sometimes be referred to as BM0 metal tracks, and metal tracks 330 to 332 may sometimes be referred to as BM1 metal tracks.

[0042] In some embodiments, via structures 314 and 316 may couple node Y to metal tracks 322 and 326, respectively, and via structures 318 and 320 may couple node X to metal tracks 324 and 328. Via structures 318 and 320 (or corresponding portions of metal tracks 324 and 328 coupled to active regions on the front side) may be aligned with each other along the Y direction, and via structures 314 and 316 (or corresponding portions of metal tracks 322 and 326 coupled to active regions on the back side) may be aligned with each other along the Y direction.

[0043] Metal tracks 324 and 328 may collectively function as a capacitor C F The first (positive) terminal of the metal tracks 322 and 326 may collectively function as a capacitor C F The second (negative) terminal of the capacitor C is coupled to F The metal track of the positive terminal (sometimes called the positive rail) and is coupled to the container C F The metal tracks of the negative terminals (sometimes referred to as negative tracks) may be arranged alternately with each other along the Y direction. Figure 3In the embodiment, each of the positive rails (e.g., 324, 328) is inserted between adjacent negative rails (e.g., 322, 326) along the Y direction, or is disposed next to the negative rails along the Y direction. Alternatively, the via structures 318 and 320 may couple the source terminal of transistor M1 and the drain terminal of transistor M2 to capacitor C F and the via structures 314 and 316 can couple the drain terminal of transistor M3 and the source terminal of transistor M4 to the capacitor C F The second (negative) terminal of

[0044] By alternately arranging multiple positive rails and negative rails, multiple sub-capacitors can be formed as capacitor C F For example, in Figure 3 In the first sub-capacitor C F1 The second sub-capacitor C may be formed by the negative rail 322 and the positive rail 324 and the IMD / ILD material therebetween; F2 The third sub-capacitor C may be formed by the positive rail 324 and the negative rail 326 and the IMD / ILD material therebetween; F3 The sub-capacitor C may be formed by the negative rail 326 and the positive rail 328 and the IMD / ILD material therebetween. F1 To C F3 can be coupled in parallel with each other to form a capacitor C F , that is, C F =C F1 +C F2 +C F3 Although four positive / negative metal tracks are shown in the BM0 layer, it should be understood that layout 300 may include any number of positive tracks and negative tracks within the BM0 layer to form capacitor C F Therefore, the capacitor C F It can be the sum of any corresponding number of sub-capacitors in the BM0 layer.

[0045] Furthermore, in some embodiments, the capacitor C F It can also be formed by positive / negative tracks in one or more other backside metallization layers. For example, metal track 332 in BM1 layer can be coupled to capacitor C F The positive terminal (node ​​X) of , which in turn serves as another positive rail; and the metal track 330 in the BM1 layer can be coupled to the capacitor C F The negative terminal (node ​​Y) of the capacitor C is used as another negative rail. In this way, the metal rails 330 and 332 and the IMD / ILD material between them can be used as a capacitor C F The other sub-capacitor C F4 .

[0046] Figure 4 and Figure 5 The following are respectively shown based on some embodiments of the present disclosure. Figure 3 300 is a cross-sectional view of a semiconductor device 400 formed by the layout 300. Therefore, the semiconductor device 400 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Figure 4 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 324, and Figure 5 The cross-sectional view is taken along the length direction (eg, the Y direction) of the gate structure between the gate structures 306 and 308 .

[0047] First reference Figure 4 , along the active region 302, a plurality of channels 410 and epitaxial structures 420 may be formed. Each of the channels 410 may be covered or wrapped by a corresponding one of the gate structures (e.g., 306, 308, 310, 312), and some of the epitaxial structures may be covered by a corresponding MD (e.g., 430). In some embodiments, the MD is a metal track formed on the front side that couples the corresponding source / drain terminal (e.g., epitaxial structure) to a higher metal track (e.g., M0 track 460) via VD (e.g., 440). In addition, each gate structure may be coupled to a higher metal track (e.g., M0 track 460) via VG (e.g., 450).

[0048] For example, one of the source / drain terminals of transistor M4 is coupled to M0 rail 460-1 (e.g., carrying GND / VSS) via MD 430-1 and VD 440-1; gate terminal 306 of transistor M4 is coupled to M0 rail 460-2 (e.g., coupled to CLK signal) via VG 450-1; gate terminal 308 of transistor M3 is coupled to M0 rail 460-3 (e.g., coupled to CLKB signal) via VG 450-2; one of the source / drain terminals of transistor M3 is coupled to M0 rail 460-4 (e.g., carrying Vin) via MD 430-2 and VD 440-2; gate terminal 310 of transistor M1 is coupled to M0 rail 460-5 (e.g., coupled to CLK signal) via VG 450-3; gate terminal 312 of transistor M2 is coupled to M0 rail 460-6 (e.g., coupled to CLK signal) via VG 450-1; 450-4 is coupled to M0 rail 460-6 (eg, coupled to the CLKB signal); and one of the source / drain terminals of transistor M2 is coupled to M0 rail 460-7 (eg, carrying Vout) through MD 430-3 and VD 440-4.

[0049] On the back side of the substrate (or active area 302), a positive rail 324 is shown, which is coupled through VB 318 to the common source / drain terminal connecting transistors M1 and M2, as shown in FIG. Figure 4 Although not shown, it should be understood that the other positive track 328 ( Figure 3 ) is also formed on the back side of the substrate (or active region 304) and is coupled to the common source / drain terminal connecting transistors M1 and M2 through VB320. Figure 4 , the semiconductor device 400 further includes a negative rail 330 and a positive rail 332 formed in the BM1 layer, wherein the positive rail 332 of the BM1 layer is coupled to the positive rail 324 in the BM0 layer through a via structure, while the negative rail 330 in the BM1 layer is not coupled to the positive rail 324 in the BM0 layer. In some embodiments, the positive rail 332 and the negative rail 330 are operable to form a sub-capacitor C F4 , as shown.

[0050] exist Figure 5 In the cross-sectional view of FIG. 3 (taken along the Y direction between gate structures 306 and 308), negative rails 322 and 326 are shown as being coupled to active regions 302 and 304 (or source / drain terminals of transistors M3 and M4) through VB314 and VB316, respectively. By using the negative rails 322 and 326 and the positive rails 324 and 328 arranged alternately with each other, a sub-transistor C can be formed. F1 , C F2 , C F3 Although not shown, it should be understood that in a cross-sectional view taken along the Y direction between gate structures 310 and 312, positive rails 324 and 328 are coupled to active regions 302 and 304 (or source / drain terminals of transistors M1 and M2) through VB318 and VB320, respectively.

[0051] Figure 6 and Figure 7 The following are respectively shown based on some embodiments of the present disclosure. Figure 3 FIG. 6 is a cross-sectional view of another semiconductor device 600 formed by the layout 300 of FIG. 6. Thus, the semiconductor device 600 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C ) formed on the back side of the substrate. F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Figure 6 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 324, and Figure 7 The cross-sectional view is taken along the length direction (eg, the Y direction) of the gate structure between the gate structures 306 and 308 .

[0052] Figure 6 and Figure 7 The cross-sectional diagrams are Figure 4 and Figure 5 The cross-sectional view is substantially similar to that of FIG. 6 , except that the semiconductor device 600 further includes a capacitor C formed on the F The high-k dielectric material on the sidewalls of each positive / negative track. Therefore, the following discussion will focus on the differences. For example, in Figure 6 In the embodiment, the semiconductor device 600 may include a high-k dielectric material 610 extending along each sidewall of the positive track 324 (towards or away from the Y direction), which may be Figure 7 As shown, along each sidewall of each positive / negative rail 322 to 328, a high-k dielectric material 610 is formed. In some embodiments, the capacitor C can be further increased by inserting such additional high-k dielectric material laterally between a corresponding pair of positive and negative rails. F Examples of high-k dielectric material 610 include, but are not limited to, TiN, Al 2 O 3 、 2 O 5 wait.

[0053] Figure 8 and Fig. 9 The following are respectively shown based on some embodiments of the present disclosure. Figure 3 FIG. 8 is a cross-sectional view of another semiconductor device 800 formed by the layout 300 of FIG. 8. Thus, the semiconductor device 800 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C ) formed on the back side of the substrate. F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Figure 8 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 324, and Fig. 9 The cross-sectional view is taken along the length direction (eg, the Y direction) of the gate structure between the gate structures 306 and 308 .

[0054] Figure 8 and Fig. 9 The cross-sectional diagrams are Figure 4 and Figure 5 The cross-sectional view is substantially similar to that of FIG. 8 , except that the semiconductor device 800 further includes a capacitor C formed on the F The following discussion will therefore focus on the differences. For example, in Figure 8, the semiconductor device 800 may include a high-k dielectric material 810 extending along the bottom surface of the positive rail 324, which may form another sub-capacitor C between the positive rail 324 in the BM0 layer and the negative rail 330 in the BM1 layer. F5 (For capacitor C F ).like Fig. 9 As further shown in FIG. 1 , along each bottom surface of each positive / negative rail 322 to 330, a high-k dielectric material 810 is formed. In some embodiments, the capacitor C can be further increased by utilizing this additional high-k dielectric material underneath each of the positive and negative rails. F For example, a further sub-capacitor C may be formed between the positive rail 324 in the BM0 layer and the negative rail 330 in the BM1 layer. F6 (For capacitor C F ) and yet another sub-capacitor C between the positive rail 328 in the BM0 layer and the negative rail 330 in the BM1 layer F7 (for capacitor CF). Examples of high-k dielectric material 810 include, but are not limited to, TiN, Al 2 O 3 、 2 O 5 wait.

[0055] Fig.10 and Fig.11 The following are respectively shown based on some embodiments of the present disclosure. Figure 3 FIG. 1 is a cross-sectional view of another semiconductor device 1000 formed by the layout 300 of FIG. 1. Thus, the semiconductor device 1000 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C ) formed on the back side of the substrate. F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Fig.10 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 324, and Fig.11 The cross-sectional view is taken along the length direction (eg, the Y direction) of the gate structure between the gate structures 306 and 308 .

[0056] Fig.10 and Fig.11 The cross-sectional diagrams are Figure 4 and Figure 5 The cross-sectional view of is substantially similar, except that the semiconductor device 1000 further includes a plurality of via structures, each of which directly couples the positive / negative rails in the BM0 layer to the corresponding M0 rails. Therefore, the following discussion will focus on the differences. For example, in Fig.10, semiconductor device 1000 includes a via structure 1010 coupling a positive rail 324 in the BM0 layer to an M0 rail 1015. In some embodiments, the via structure 1010 can extend from the positive rail 324, through the substrate (or active region 302), and to the M0 rail 1015, which can be configured as a node X (capacitor C F The via structure 1010 may have a liner 1012 lining the sidewalls and top surface of the via structure 1010. Although not shown, it is understood that the semiconductor device 1000 may include another similar via structure coupling another positive rail 328 to another M0 rail. Fig.11 As further shown in FIG. 1 , each of the negative rails 322 and 326 may be coupled to a capacitor configured as a node Y (capacitor C ) via a corresponding via structure 1010. F The negative terminal of the corresponding M0 rail.

[0057] Fig.12 and Fig.13 The following are respectively shown based on some embodiments of the present disclosure. Figure 3 FIG. 1 is a cross-sectional view of another semiconductor device 1200 formed by the layout 300 of FIG. 1. Thus, the semiconductor device 1200 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C ) formed on the back side of the substrate. F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Fig.12 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 324, and Fig.13 The cross-sectional view is taken along the length direction (eg, the Y direction) of the gate structure between the gate structures 306 and 308 .

[0058] Fig.12 and Fig.13 The cross-sectional diagrams are Figure 4 and Figure 5 The cross-sectional view of is substantially similar, except that the semiconductor device 1200 further includes a plurality of via structures, each of which directly couples the positive / negative rails in the BM0 layer to the corresponding MD. Therefore, the following discussion will focus on the differences. For example, in Fig.12 1 , semiconductor device 1200 includes a via structure 1210 that couples a positive rail 324 in the BM0 layer to a MD 430-4 formed on an active region 302 (or source / drain terminals). In some embodiments, via structure 1210 may extend from positive rail 324, through the substrate (or active region 302), and to MD 430-4, which may be configured as a node X (capacitor C FAlthough not shown, it is understood that the semiconductor device 1200 may include another similar via structure coupling another positive rail 328 to the same MD or another MD. Fig.13 As further shown in FIG. 1 , negative rails 322 and 326 may be coupled to a capacitor configured as node Y (capacitor C ) via respective via structures 1210. F The negative terminal of the MD 430-5.

[0059] Fig.14 FIG. 1 shows a circuit that can be used to form a charge pump circuit (eg, Figure 2 In one aspect, the layout 1400 includes a plurality of patterns configured to form transistors M1 to M4 and capacitors C F In addition, the transistors M1 to M4 may be formed on a first side (eg, front side) of the substrate, and the capacitor C F It may be formed on a second side (eg, backside) opposite the substrate, as will be discussed below. It should be noted that layout 1400 is simplified for illustrative purposes, and thus, layout 1400 may include any of a variety of other components (eg, patterns) while remaining within the scope of the present disclosure.

[0060] As shown, layout 1400 includes patterns 1402, 1404, 1406, and 1408, each of which is configured to form an active region (hereinafter, "active region 1402", "active region 1404", "active region 1406", and "active region 1408", respectively); and patterns 1410, 1412, 1414, and 1416, each of which is configured to form a gate structure (hereinafter, "gate structure 1410", "gate structure 1412", "gate structure 1414", and "gate structure 1416", respectively). In some embodiments, active regions 1402 to 1408 may each extend along a first lateral direction (e.g., X direction), and gate structures 1410 to 1416 may each extend along a different second lateral direction (e.g., Y direction). In addition, active regions 1402 and 1404 may be spaced apart from each other along the X direction; and active regions 1406 and 1408 may be spaced apart from each other along the X direction. It should be understood that layout 1400 may include any number of each active region and gate structure while remaining within the scope of the present disclosure.

[0061] In some embodiments, each of the active regions 1402 to 1408 is formed by a stacked structure protruding from a main (e.g., front side) surface of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The portion of the semiconductor structure in the stacked structure covered by the gate structure is retained, while the other portion is replaced with a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., crossing) the other portion of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0062] For example, Fig.14 , the portion of the active area 1402 covered by the gate structure 1410 may include a plurality of nanostructures vertically separated from each other, which may be used as a channel of a first sub-transistor. The portion of the active area 1402 disposed on the opposite side of the gate structure 1410 is replaced with an epitaxial structure. Such an epitaxial structure may be used as a source / drain terminal of a first sub-transistor. The gate structure 1410 may be used as a gate terminal of the first sub-transistor. A second sub-transistor may be formed by the active area 1406 and the same gate structure 1410. Such a first sub-transistor and a second sub-transistor (coupled in parallel with each other) may together form a transistor M3. Similarly, transistors M1, M2, and M4 may be formed by respective active areas and gate structures, as shown in FIG. Fig.14 shown.

[0063] Using transistors M1 to M4 formed by active regions 1402-1408 and gate structures 1410-1416, node Y can be formed by or coupled to the portion between the inserted gate structures 1410-1412 of active region 1402 and the portion between the inserted gate structures 1410-1412 of active region 1406; node X can be formed by or coupled to the portion between the inserted gate structures 1414-1416 of active region 1404 and the portion between the inserted gate structures 1414-1416 of active region 1408. In addition, a portion of active region 1402 that is opposite to gate structure 1410 and an intervening portion between gate structures 1410-1412, a portion of active region 1406 that is opposite to gate structure 1410 and an intervening portion between gate structures 1410-1412, a portion of active region 1404 that is opposite to gate structure 1414 and an intervening portion between gate structures 1414-1416, and a portion of active region 1408 that is opposite to gate structure 1414 and an intervening portion between gate structures 1414-1416 may be coupled to input node Vin; active region 1402 The portion of the active area 1406 relative to the gate structure 1412 and the inserted portion between the gate structures 1410-1412 can be coupled to a second reference voltage (ground); and the portion of the active area 1404 relative to the gate structure 1416 and the inserted portion between the gate structures 1414-1416 and the portion of the active area 1408 relative to the gate structure 1416 and the inserted portion between the gate structures 1414-1416 can be coupled to the output node Vout.

[0064] In order to electrically connect each of these transistors to one or more corresponding nodes or signals, the layout 1400 may also include a plurality of patterns (not shown), each of which is configured to form a front metal structure / track. In some embodiments, these front metal tracks are formed across a plurality of front metallization layers disposed on the front surface of the substrate. Such front metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., wherein the M0 layer may be the layer closest to the main surface of the substrate. Each front metallization layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetallic dielectric (IMD) materials. In some embodiments, each of the input node (Vin), the output node (Vout), and the ground node (GND / VSS) may be coupled to a metal track in a corresponding one of the metallization layers or carried by a metal track, and each of the gate structures 1410 to 1416 may be coupled to a metal track carrying a clock signal or its inverted signal.

[0065] Layout 1400 also includes patterns 1418, 1420, 1422, and 1424, each of which is configured to form a via structure (hereinafter, "via structure 1418," "via structure 1420," "via structure 1422," and "via structure 1424," respectively); patterns 1426, 1428, 1430, and 1432, each of which is configured to form a backside metal track (hereinafter, "metal track 1426," "metal track 1428," "gold track 1430," and "metal track 1432," respectively); and patterns 1434 and 1436, each of which is configured to form a backside metal track (hereinafter, "metal track 1434" and "metal track 1436," respectively). Each of via structures 1418 to 1424 may extend partially through the substrate to electrically couple one of the source / drain terminals (formed on the front side) to a corresponding backside metal track. Such via structures 1418 to 1424 may sometimes be referred to as VB structures. Similar to the front side, on the back side of the substrate, a plurality of backside metallization layers may be formed, which are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc. Each backside metal layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetallic dielectric (IMD) materials. Metal tracks 1426 to 1432 may be formed in the BM0 layer, and metal tracks 1434 to 1436 may be formed in the BM1 layer. Therefore, metal tracks 1426 to 1432 may sometimes be referred to as BM0 metal tracks, and metal tracks 1434 to 1436 may sometimes be referred to as BM1 metal tracks.

[0066] In some embodiments, via structures 1418 and 1420 may couple node Y to metal tracks 1426 and 1430, respectively, and via structures 1422 and 1424 may couple node X to metal tracks 1428 and 1432. Via structures 1422 and 1424 (or corresponding portions of metal tracks 1428 and 1432 coupled to active regions on the front side) may be aligned with each other along the Y direction, and via structures 1418 and 1420 (or corresponding portions of metal tracks 1426 and 1430 coupled to active regions on the back side) may be aligned with each other along the Y direction.

[0067] Metal tracks 1428 and 1432 may collectively function as a capacitor C F The first (positive) terminal of the metal tracks 1426 and 1430 can be used together as a container C F The second (negative) terminal of the capacitor C is coupled to F The metal track of the positive terminal (sometimes called the positive rail) and is coupled to the container C F The metal tracks of the negative terminals (sometimes also referred to as negative tracks) may be arranged alternately with each other along the Y direction. Fig.14In the embodiment of the present invention, each of the positive rails (e.g., 1428, 1432) is inserted between adjacent negative rails (e.g., 1426, 1430) along the Y direction, or is disposed next to the negative rails along the Y direction. Alternatively, the via structures 1422 and 1424 can couple the source terminal of transistor M1 and the drain terminal of transistor M2 to capacitor C F and via structures 1418 and 1420 can couple the drain terminal of transistor M3 and the source terminal of transistor M4 to capacitor C F The second (negative) terminal of

[0068] By alternately arranging multiple positive rails and negative rails, multiple sub-capacitors can be formed as capacitor C F For example, in Fig.14 In the first sub-capacitor C F1 The second sub-capacitor C may be formed by the negative rail 1426 and the positive rail 1428 and the IMD / ILD material therebetween; F2 The third sub-capacitor C may be formed by the positive rail 1428 and the negative rail 1430 and the IMD / ILD material therebetween; F3 The sub-capacitor C may be formed by the negative rail 1430 and the positive rail 1432 and the IMD / ILD material therebetween. F1 To C F3 can be coupled in parallel with each other to form a capacitor C F , that is. Although four positive / negative metal tracks are shown in the BM0 layer, it should be understood that the layout 1400 may include any number of positive tracks and negative tracks within the BM0 layer to form the capacitor C F Therefore, the capacitor C F It can be the sum of any corresponding number of sub-capacitors in the BM0 layer.

[0069] Furthermore, in some embodiments, the capacitor C F It can also be formed by positive / negative tracks in one or more other backside metallization layers. For example, metal track 1436 in BM1 layer can be coupled to capacitor C F The positive terminal (node ​​X) of , which in turn serves as another positive rail; and the metal track 1434 in the BM1 layer can be coupled to the capacitor C F The negative terminal (node ​​Y) of the capacitor C is used as another negative rail. In this way, the metal rails 1434 and 1436 and the IMD / ILD material between them can be used as a capacitor C F The other sub-capacitor C F4 .

[0070] Fig.15 and Fig.16The following are respectively shown based on some embodiments of the present disclosure. Fig.14 1400 is a cross-sectional view of a semiconductor device 1500 formed by the layout 1400. Therefore, the semiconductor device 1500 may include at least four switches formed on the front side of the substrate and a flying capacitor (eg, capacitor C ) formed on the back side of the substrate. F ), where each switch is formed as a clock controller transistor (e.g., transistors M1 to M4). Fig.15 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 1428, and Fig.16 The cross-sectional view is taken along the length direction of the gate structure between the gate structures 1410 and 1412 (eg, the Y direction).

[0071] First reference Fig.15 , along each of the active regions 1402-1404, a plurality of channels 1510 and epitaxial structures 1520 may be formed. Each of the channels 1510 may be covered or wrapped by a corresponding one of the gate structures (e.g., 1410, 1424, 1414, 1416), and some of the epitaxial structures may be covered by corresponding MDs (e.g., 1530). In some embodiments, MDs are metal tracks formed on the front side that couple the corresponding source / drain terminals (e.g., epitaxial structures) to higher metal tracks (e.g., M0 tracks 1560) via VDs (e.g., 1540). In addition, each gate structure may be coupled to a higher metal track (e.g., M0 track 1560) via VGs (e.g., 1550).

[0072] For example, one of the source / drain terminals of transistor M3 is coupled to M0 rail 1560-1 (e.g., carrying Vin) through MD 1530-1 and VD 1540-1; the gate terminal 1410 of transistor M3 is coupled to M0 rail 1560-2 (e.g., coupled to CLKB signal) through VG 1550-1; the gate terminal 1412 of transistor M4 is coupled to M0 rail 1560-3 (e.g., coupled to CLK signal) through VG 1550-2; one of the source / drain terminals of transistor M4 is coupled to M0 rail 1560-4 (e.g., carrying GND / VSS) through MD 1530-2 and VD 1540-2; one of the source / drain terminals of transistor M1 is coupled to M0 rail 1560-5 (e.g., carrying Vin) through MD 1530-3 and VD 1540-3; the gate terminal 1414 of transistor M1 is coupled to M0 rail 1560-6 (e.g., carrying Vin) through VG 1550-1. 1550-3 is coupled to M0 rail 1560-6 (e.g., coupled to the CLK signal); the gate terminal 1416 of transistor M2 is coupled to M0 rail 1560-7 (e.g., coupled to the CLKB signal) through VG 1550-4; and one of the source / drain terminals of transistor M2 is coupled to M0 rail 1560-8 (e.g., carrying Vout) through MD 1530-4 and VD 1540-4.

[0073] On the back side of the substrate (or active regions 1402-1404), a positive rail 1428 is shown, which is coupled through VB 1422 to the common source / drain terminal connecting transistors M1 and M2, as shown in FIG. Fig.15 Although not shown, it should be understood that another positive track 1432 ( Fig.14 ) is also formed on the back side of the substrate (or active regions 1406-1408) and is coupled to the common source / drain terminal connecting transistors M1 and M2 through VB 1424. Fig.15 , the semiconductor device 1500 further includes a negative rail 1434 and a positive rail 1436 formed in the BM1 layer, wherein the positive rail 1434 of the BM1 layer is coupled to the positive rail 1428 of the BM0 layer through a via structure, while the negative rail 1434 in the BM1 layer is not coupled to the positive rail 1428 in the BM0 layer. In some embodiments, the positive rail 1436 and the negative rail 1434 are operable to form a sub-capacitor C F4 , as shown.

[0074] exist Fig.16In the cross-sectional view of FIG. 1 (taken along the Y direction between gate structures 1410 and 1412), negative rails 1426 and 1430 are shown as being coupled to active regions 1402 and 1404 (or source / drain terminals of transistors M3 and M4) through VBs 1418 and 1420, respectively. By using the negative rails 1426 and 1430 and the positive rails 1428 and 1432 arranged alternately with each other, a sub-transistor C can be formed. F1 , C F2 , C F3 Although not shown, it is understood that in a cross-sectional view taken along the Y direction between gate structures 1414 and 1416, positive rails 1428 and 1432 are coupled to active regions 1404 and 1408 (or source / drain terminals of transistors M1 and M2) through VBs 1422 and 1424, respectively.

[0075] Fig.17 The voltage supply circuit 110 ( Figure 1 ) of a charge pump circuit. Fig.17 The charge pump circuit shown is referred to as charge pump circuit 1700. It should be understood that the circuit is simplified for illustrative purposes. Fig.15 1700 , therefore, the charge pump circuit of the voltage providing circuit 110 may be implemented in any of a variety of other configurations (as long as it can boost the input voltage to a higher voltage level via a capacitor) while remaining within the scope of the present disclosure.

[0076] In some embodiments, in addition to the charge pump circuit 1700, the charge pump circuit 1700 also includes a capacitor C F Except for the transistor M5, the charge pump circuit 1700 is substantially similar to the charge pump circuit 200. Therefore, the following discussion of the charge pump circuit 1500 will focus on this difference. F Connected between node X and node Y, transistor M5 is coupled to capacitor C F or between any of the nodes X or Y. Therefore, capacitor C F It has a first (eg, positive) terminal coupled to node X through transistor M5 and a second (eg, negative) terminal connected to node Y. In some embodiments, transistor M5 can be gated by a fixed voltage (eg, ground / VSS).

[0077] Fig.18 FIG. 1 shows a circuit that can be used to form a charge pump circuit (eg, Fig.17 In one aspect, the layout 1800 includes a plurality of patterns configured to form transistors M1 to M5 and capacitors C FIn addition, the transistors M1 to M5 may be formed on a first side (eg, front side) of the substrate, and the capacitor C F It may be formed on a second side (eg, backside) opposite the substrate, as will be discussed below. It should be noted that layout 1800 is simplified for illustrative purposes, and thus, layout 1800 may include any of a variety of other components (eg, patterns) while remaining within the scope of the present disclosure.

[0078] As shown, layout 1800 includes patterns 1802, 1804, 1806, 1808, 1810, and 1812, each of which is configured to form an active region (hereinafter, "active region 1802", "active region 1804", "active region 1806", "active region 1808", "active region 1810", and "active region 1812", respectively); and patterns 1814, 1816, 1818, 1820, and 1822, each of which is configured to form a gate structure (hereinafter, "gate structure 1814", "gate structure 1816", "gate structure 1818", "gate structure 1820", and "gate structure 1822", respectively). In some embodiments, each of active regions 1802 to 1812 may extend along a first lateral direction (e.g., X direction), and each of gate structures 1814 to 1822 may extend along a different second lateral direction (e.g., Y direction). and active regions 1808 , 1810 , and 1812 may be spaced apart from each other along the X direction. It should be appreciated that layout 1800 may include any number of each active region and gate structure while remaining within the scope of the present disclosure.

[0079] In some embodiments, each of the active regions 1802 to 1812 is formed by a stacked structure protruding from a main (e.g., front side) surface of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The portion of the semiconductor structure in the stacked structure covered by the gate structure is retained, while the other portion is replaced with a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., crossing) the other portion of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0080] For example, in Fig.18, the portion of the active area 1802 covered by the gate structure 1814 may include multiple nanostructures separated vertically from each other, which may serve as a channel of a first sub-transistor. The portion of the active area 1802 disposed on the opposite side of the gate structure 1814 is replaced with an epitaxial structure. Such an epitaxial structure may serve as a source / drain terminal of the first sub-transistor. The gate structure 1814 may serve as a gate terminal of the first sub-transistor. A second sub-transistor may be formed by the active area 1808 and the same gate structure 1814. Such a first sub-transistor and a second sub-transistor (coupled in parallel with each other) may together form a transistor M3. Similarly, transistors M1, M2, M4, and M5 may be formed by respective active areas and gate structures, as shown in FIG. Fig.18 shown.

[0081] Using transistors M1 to M5 formed by active regions 1802-1812 and gate structures 1814-1822, node Y can be formed by or coupled to the portion of active region 1802 between the inserted gate structures 1814-1816, the portion of active region 1808 between the inserted gate structures 1814-1816, and the portion of active region 1804 on the left side of gate structure 1818; node X can be formed by or coupled to the portion of active region 1806 between the inserted gate structures 1820-1822, the portion of active region 1812 between the inserted gate structures 1820-1822, and the portion of active region 1804 on the right side of gate structure 1818.

[0082] In addition, a portion of active region 1802 that is opposite to gate structure 1814 and an intervening portion between gate structures 1814-1816, a portion of active region 1808 that is opposite to gate structure 1814 and an intervening portion between gate structures 1814-1816, a portion of active region 1806 that is opposite to gate structure 1820 and an intervening portion between gate structures 1820-1822, and a portion of active region 1812 that is opposite to gate structure 1820 and an intervening portion between gate structures 1820-1822 may be coupled to input node Vin; active region 1808 that is opposite to gate structure 1814 and an intervening portion between gate structures 1814-1816 may be coupled to input node Vin; 2 relative to the gate structure 1816 and the inserted portion between the gate structures 1814-1816, and the portion of the active area 1808 relative to the gate structure 1816 and the inserted portion between the gate structures 1814-1816 can be coupled to a second reference voltage (ground); and the portion of the active area 1806 relative to the gate structure 1822 and the inserted portion between the gate structures 1820-1822 and the portion of the active area 1812 relative to the gate structure 1822 and the inserted portion between the gate structures 1820-1822 can be coupled to the output node Vout.

[0083] In order to electrically connect each of these transistors to one or more corresponding nodes or signals, the layout 1800 may also include a plurality of patterns (not shown), each of which is configured to form a front metal structure / track. In some embodiments, these front metal tracks are formed across a plurality of front metallization layers disposed on the front surface of the substrate. Such front metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., wherein the M0 layer may be the layer closest to the main surface of the substrate. Each front metallization layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetallic dielectric (IMD) materials. In some embodiments, the input node (Vin), the output node (Vout), and the ground node (GND / VSS) may each be coupled to a metal track in a corresponding one of the metallization layers or carried by a metal track, and the gate structures 1814-1816 and 1820-1822 may each be coupled to a metal track carrying a clock signal or its inverted signal, and the gate structure 1818 may be coupled to a metal track carrying VSS.

[0084] Layout 1800 also includes patterns 1830, 1832, 1834, 1836, 1838, 1840, 1842, and 1844, each of which is configured to form a via structure (hereinafter, respectively, “via structure 1830,” “via structure 1832,” “via structure 1834,” “via structure 1836,” “via structure 1838,” “via structure 1840,” “via structure 1842,” and “via structure 1844”); patterns 1850, 1851, 1852, and 1854. 2, 1854 and 1856, each pattern is configured to form a backside metal track (hereinafter referred to as "metal track 1850", "metal track 1852", "gold track 1854" and "metal track 1856", respectively); and patterns 1858, 1860, 1862 and 1864, each pattern is configured to form a backside metal track (hereinafter referred to as "metal track 1858", "metal track 1860", "metal track 1862" and "metal track 1864", respectively). Each of the via structures 1830 to 1844 can partially extend through the substrate to electrically couple one of the source / drain terminals (formed on the front side) to the corresponding backside metal track. Such via structures 1830 to 1844 can sometimes be referred to as VB structures. Similar to the front side, on the back side of the substrate, multiple backside metallization layers can be formed, which are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc. Each backside metal layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetal dielectric (IMD) materials. Metal tracks 1850 to 1856 may be formed in the BM0 layer, and metal tracks 1858 to 1864 may be formed in the BM1 layer. Thus, metal tracks 1850 to 1856 may sometimes be referred to as BM0 metal tracks, and metal tracks 1858 to 1864 may sometimes be referred to as BM1 metal tracks.

[0085] In some embodiments, via structures 1830 / 1834 and 1832 / 1836 may couple node Y to metal tracks 1850 and 1854 , respectively; and via structures 1838 / 1842 and 1840 / 1484 may couple node X to metal tracks 1852 and 1856 . Via structures 1842 and 1844 (or corresponding portions of metal tracks 1852 and 1856 coupled to the active area on the front side) can be aligned with each other along the Y direction, via structures 1838 and 1840 (or corresponding portions of metal tracks 1852 and 1856 coupled to the active area on the front side) can be aligned with each other along the Y direction, via structures 1834 and 1836 (or corresponding portions of metal tracks 1852 and 1856 coupled to the active area on the front side) can be aligned with each other along the Y direction, and via structures 1830 and 1832 (or corresponding portions of metal tracks 1850 and 1854 coupled to the active area on the front side) can be aligned with each other along the Y direction.

[0086] Metal tracks 1852 and 1856 can be used together as a capacitor C F The first (positive) terminal of the metal tracks 1850 and 1854 can be used together as a capacitor C F The second (negative) terminal of the capacitor C F The positive terminal of the metal track (sometimes called the positive rail) is coupled to the capacitor C F The metal tracks of the negative terminals (sometimes referred to as negative tracks) can be arranged alternately with each other along the Y direction. Fig.18 In the embodiment of the present invention, each positive track (e.g., 1852, 1856) is inserted between adjacent negative tracks (e.g., 1850, 1854) along the Y direction, or is arranged next to the negative track along the Y direction. Alternatively, the via structures 1842 and 1844 can couple the source terminal of transistor M1 and the drain terminal of transistor M2 to capacitor C F and via structures 1830 and 1832 can couple the drain terminal of transistor M3 and the source terminal of transistor M4 to capacitor C F The second (negative) terminal of

[0087] By alternately arranging multiple positive rails and negative rails, multiple sub-capacitors can be formed as capacitor C F For example, in Fig.18 In the first sub-capacitor C F1 The second sub-capacitor C may be formed by the negative rail 1850 and the positive rail 1852 and the IMD / ILD material therebetween; F2 The third sub-capacitor C may be formed by the positive rail 1852 and the negative rail 1854 and the IMD / ILD material therebetween; F3The sub-capacitor C may be formed by the negative rail 1854 and the positive rail 1856 and the IMD / ILD material therebetween. F1 To C F3 can be coupled in parallel with each other to form a capacitor C F , that is, C F =C F1 +C F2 +C F3 Although four positive / negative metal tracks are shown in the BM0 layer, it should be understood that layout 1800 may include any number of positive tracks and negative tracks within the BM0 layer to form capacitor C F Therefore, capacitor CF can be the sum of any corresponding number of sub-capacitors in the BM0 layer.

[0088] Furthermore, in some embodiments, the capacitor C F can be further formed by positive / negative tracks in one or more other backside metallization layers. For example, metal track 1862 in BM1 layer can be coupled to capacitor C F The positive terminal (node ​​X) of , which in turn serves as another positive rail; and the metal track 1860 in the BM1 layer can be coupled to the capacitor C F The negative terminal (node ​​Y) of the capacitor C is used as another negative rail. In this way, the metal rails 1860 and 1862 and the IMD / ILD material between them can be used as a capacitor C F The other sub-capacitor C F4 .

[0089] Fig.19 and Fig. 20 The following are respectively shown based on some embodiments of the present disclosure. Fig.18 1800 is a cross-sectional view of a semiconductor device 1900 formed by the layout 1800. Thus, the semiconductor device 1900 may include at least four switches formed on the front side of the substrate, each switch being formed as a clock controller transistor (e.g., transistors M1 to M4), a normally-off transistor also formed on the front side (e.g., transistor M5), and a flying capacitor (e.g., capacitor C ) formed on the back side of the substrate. F ). Fig.19 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 1852, and Fig. 20 The cross-sectional view is taken along the length direction of the gate structure between gate structures 1814 and 1816 (eg, the Y direction).

[0090] First reference Fig.19, along each of the active regions 1802-1806, a plurality of channels 1910 and epitaxial structures 1920 may be formed. Each of the channels 1910 may be covered or wrapped by a corresponding one of the gate structures (e.g., 1814, 1816, 1818, 1820, and 1822), and some of the epitaxial structures may be covered by a corresponding MD (e.g., 1930). In some embodiments, the MD is a metal track formed on the front side that couples the corresponding source / drain terminal (e.g., epitaxial structure) to a higher metal track (e.g., M0 track 1960) via VD (e.g., 1940). In addition, each gate structure may be coupled to a higher metal track (e.g., M0 track 1960) via VG (e.g., 1950).

[0091] For example, one of the source / drain terminals of transistor M3 is coupled to M0 rail 1960-1 (e.g., carrying Vin) via MD 1930-1 and VD 1940-1; gate terminal 1814 of transistor M3 is coupled to M0 rail 1960-2 (e.g., coupled to CLKB signal) via VG 1950-1; gate terminal 1816 of transistor M4 is coupled to M0 rail 1960-3 (e.g., coupled to CLK signal) via VG 1950-2; one of the source / drain terminals of transistor M4 is coupled to M0 rail 1960-4 (e.g., carrying GND / VSS) via MD 1930-2 and VD 1940-2; gate terminal 1816 of transistor M4 is coupled to M0 rail 1960-5 (e.g., carrying GND / VSS) via MD 1930-3 and VD 1940-2; gate terminal 1817 of transistor M5 is coupled to M0 rail 1960-6 via VG 1950-7; and gate terminal 1818 of transistor M1 is coupled to M0 rail 1960-8 via MD 1930-9 and VD 1940-1. 1940-3 is coupled to M0 rail 1960-6 (e.g., carrying Vin); the gate terminal 1820 of transistor M1 is coupled to M0 rail 1960-6 (e.g., coupled to the CLK signal) through VG 1950-4; the gate terminal 1822 of transistor M2 is coupled to M0 rail 1960-7 (e.g., coupled to the CLKB signal) through VG1950-5; and one of the source / drain terminals of transistor M2 is coupled to M0 rail 1960-8 (e.g., carrying Vout) through MD 1930-4 and VD 1940-4.

[0092] On the back side of the substrate (or active regions 1802-1806), a positive rail 1852 is shown, which is coupled to the common source / drain terminal connecting transistors M1 and M2 through VB 1842, and further coupled to one of the source / drain terminals of transistor M5 through VB 1838, as shown. Fig.19 Although not shown, it should be understood that another positive track 1856 ( Fig.18) is also formed on the back side of the substrate (or active regions 1808-1812) and is coupled to the common source / drain terminal connecting transistors M1 and M2 through VB 1844. Fig.19 , the semiconductor device 1900 further includes negative rails 1858-1860 and positive rails 1862-1864 formed in the BM1 layer, wherein each of the positive rails 1862-1864 of the BM1 layer is coupled to the positive rail 1852 in the BM0 layer through a via structure, while any of the negative rails 1858-1860 in the BM1 layer is not coupled to the positive rail 1852 in the BM0 layer. In some embodiments, the positive rail 1862 and the negative rail 1860 are operable to form a sub-capacitor C F4 , as shown.

[0093] exist Fig. 20 In the cross-sectional view of FIG. 1 (taken along the Y direction between gate structures 1814 and 1816), negative rails 1850 and 1854 are shown as being coupled to active regions 1802 and 1808 (or source / drain terminals of transistors M3 and M4) through VBs 1830 and 1832, respectively. By using the alternating negative rails 1850 and 1854 and positive rails 1852 and 1856, a sub-transistor C can be formed. F1 , C F2 , C F3 , as shown. Although not shown, it should be understood that in a cross-sectional view taken along the Y direction between gate structures 1820 and 1822, positive rails 1852 and 1856 are coupled to active regions 1806 and 1812 (or source / drain terminals of transistors M1 and M2) through VB1842 and 1844, respectively; in another cross-sectional view taken along the Y direction adjacent to gate structure 1818, positive rails 1852 and 1856 are coupled to active regions 1804 and 1810 (or one of the source / drain terminals of transistor M5) through VB1838 and 1840, respectively; and in yet another cross-sectional view taken along the Y direction adjacent to gate structure 1818, negative rails 1850 and 1854 are coupled to active regions 1804 and 1810 (or the other of the source / drain terminals of transistor M5) through VB1834 and 1836, respectively.

[0094] Fig.21 It shows some embodiments of the present disclosure based on Fig.18 1800 is a cross-sectional view of another semiconductor device 2100 formed by the layout 1800. Thus, the semiconductor device 2100 may include at least four switches formed on the front side of the substrate, each switch being formed as a clock controller transistor (e.g., transistors M1 to M4), a normally-off transistor also formed on the front side (e.g., transistor M5), and a flying capacitor (e.g., capacitor C 200) formed on the back side of the substrate. F). Fig.21 The cross-sectional view is taken along the length direction (eg, X direction) of the active region above the positive track 1852. As shown in FIG.

[0095] Fig.21 The cross-sectional view of Fig.19 The cross-sectional view of FIG. 21 is substantially similar, except that the semiconductor device 2100 further includes a plurality of positive rails and a plurality of negative rails on the front side, which can be operated to form a capacitor C F Therefore, the following discussion will focus on the differences. Fig.21 , the semiconductor device 2100 may include an M0 track 2160-1 coupled to one of the source / drain terminals of the transistor M5 through corresponding MD and VD, wherein the M0 track 2160-1 may function as a capacitor C F In addition, the semiconductor device 2100 may include another M0 track 2160-2 coupled to another of the source / drain terminals of the transistor M5, wherein the M0 track 2160-2 may function as a capacitor C F The other negative track.

[0096] It should be noted that the M0 track 2160-2 (and its corresponding MD and VD) is Fig.21 1850, because in some embodiments, the M0 track 2160-2 may only be observed in another cross-sectional view of the semiconductor device 2100 cut along the length direction of the active area above the negative track 1850. In addition, each of the M0 tracks 2160-1 and 2160-2 can be parallel to each other. In other words, the M0 tracks 2160-1 and 2160-2 and the IMD / ILD material therebetween can operably form a capacitor C F Part of C F5 .

[0097] Fig. 22 2200 is a flow chart showing an example method 2200 for forming a charge pump circuit with a backside flying capacitor according to some embodiments. Figure 2 200 Fig.17 1700) may include at least four switches formed on the front side of the substrate, and at least one flying capacitor formed on the back side of the substrate. In some embodiments, the method 2200 may be performed to respectively Figure 3 , Fig.14 and Fig.18 2200 to form a charge pump circuit, and therefore, in the following discussion of method 2200, some of the above references may be reused. It should be noted that method 2200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the charge pump circuit may be formed in Fig. 22 Additional operations are provided before, during, and after method 2200, and some other operations may be only briefly described herein.

[0098] According to various embodiments, method 2200 starts from operation 2202, where a substrate is provided. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0099] Method 2200 continues to operation 2204, in which, according to various embodiments, a stack comprising an alternating series of first and second nanostructures is formed. Such a stack may be formed based on one of the (active region) patterns discussed above. The stack may be formed in the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be 25% SiGe. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials have different etching characteristics (e.g., etching rates), respectively.

[0100] An alternating series of nanostructures can be formed by epitaxially growing one layer and then the next until the desired number and desired thickness of nanostructures are obtained. Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) can be doped (in-situ doping) during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0101] According to various embodiments, the method 2200 continues to operation 2206, in which a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-mentioned (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and the stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, so that the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0102] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on the flattened a-Si and patterned. The hard mask can be formed by a nitride layer or an oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After forming the pseudo gate structure, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any appropriate combination of these materials) followed by directional etching (e.g., RIE).

[0103] Method 2200 proceeds to operation 2208, in which, according to various embodiments, internal spacers are formed by replacing the ends of each SiGe sacrificial nanostructure with a dielectric material. When forming a pseudo gate structure covering certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacers are formed by filling these recesses of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0104] According to various embodiments, method 2200 proceeds to operation 2210, in which a plurality of epitaxial structures are formed. When forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form the doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type FETs and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and p-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0105] According to various embodiments, method 2200 proceeds to operation 2212, in which the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with corresponding active gate structures. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructure is removed while keeping the Si channel nanostructure substantially intact by applying selective etching (e.g., hydrochloric acid (HCl)). After removing the SiGe sacrificial nanostructure, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls that contact the dielectric fin structure. Next, multiple active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls that contact the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer).

[0106] When forming the active gate structure, at least four switches (e.g., transistors M1, M2, M3, and M4) of the disclosed charge pump circuit may be formed, each switch being implemented as a clocked transistor. In some embodiments, transistors M1 and M2 may be connected in series with each other, and transistors M3 and M4 may be connected in series with each other. In addition, transistors M1 and M2 may each have respective source / drain terminals connected to each other at a first common node (e.g., node X), and transistors M3 and M4 may each have respective drain / source terminals connected to each other at a second common node (e.g., node Y).

[0107] Method 2200 proceeds to operation 2214, in which a plurality of front-side interconnect structures are formed according to various embodiments. When forming the switch, a plurality of mid-end interconnect structures (e.g., VG, VD, MD) are formed on the switch. For example, a plurality of VGs (e.g., 450, 1550, 1950) may be formed to be respectively connected to the gate terminals of the switch, and a plurality of MDs (e.g., 430, 1530, 1930) may be formed to be respectively connected to the source / drain terminals of the switch through a plurality of VDs (e.g., 440, 1540, 1940). In addition, a plurality of back-end interconnect structures may be formed above the mid-end interconnect structure. Such a back-end interconnect structure includes the above-mentioned M0 track (e.g., 460, 1560, 1960, 2160) and other metal tracks (e.g., M1 track, M2 track, etc.) disposed in the upper metallization layer. Through the VG, each switch can be gated with a clock signal or its inverted signal conducted through one or more back-end metal tracks. Through VD and MD, each switch can be depleted or powered by a corresponding voltage signal (eg, Vin, VSS, Vout).

[0108] The front-side interconnect structure is formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure may be formed by covering the front side of the substrate with the above metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0109] The method 2200 proceeds to operation 2216, in which a plurality of backside interconnect structures are formed according to various embodiments. When forming the back-end metal track, the substrate is flipped, and a plurality of backside interconnect structures (e.g., BM0 track, BM1 track) are formed on the back side of the substrate. For example, after the substrate is flipped, a polishing process can be performed on the back side of the substrate until the bottom surface of the epitaxial structure (e.g., the source / drain terminals formed in operation 2210) is exposed. Next, one or more dielectric layers are formed on the polished backside surface, followed by the formation of the above-mentioned backside via structures (e.g., 314-320, 1418-1424, 1830-1844), each of which can extend through one or more dielectric layers to reach the bottom surface of the corresponding epitaxial structure. Next, backside interconnect structures (eg, 322 - 328 , 330 - 332 , 1426 - 1432 , 1434 - 1436 , 1850 - 1856 , 1858 - 1864 ) may be formed in corresponding backside metallization layers.

[0110] In some embodiments, the backside interconnect structures in each backside metallization layer may have a first subset and a second subset, wherein each of the backside interconnect structures of the first subset is coupled to a first common node (node ​​X) and each of the backside interconnect structures of the second subset is coupled to a second common node (node ​​Y). F ) can be operably formed by the backside interconnect structure (positive rail) of the first subset, and the flying capacitor C F The second terminal of can be operably formed by the backside interconnect structure (negative rail) of the second subset. In addition, the backside interconnect structures of the first subset and the backside interconnect structures of the second subset can be arranged alternately relative to each other, for example, each of the backside interconnect structures of the first subset is laterally adjacent to a corresponding one of the backside interconnect structures of the second subset, or is laterally interposed between corresponding pairs of the backside interconnect structures of the second subset. Thus, in each backside metallization layer, a flying capacitor C can be formed by different subsets of the backside interconnect structures. F In addition, across different backside metallization layers, flying capacitors C can also be formed by different subgroups of backside interconnect structures. F Multiple additional sub-capacitors.

[0111] The backside interconnect structure is formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The backside interconnect structure can be formed by covering the back side of the substrate with the above metal material by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0112] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and the second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first switch and the second switch, and the second terminal is coupled to a second node between the third switch and the fourth switch.

[0113] In some embodiments, the first switch and the fourth switch are configured to be activated, and the second switch and the third switch are configured to be deactivated, so that the voltages at the first terminal and the second terminal are equal to the first reference voltage and the second reference voltage, respectively.

[0114] In some embodiments, after the voltage at the first terminal is equal to the first reference voltage, the first switch and the fourth switch are configured to be deactivated, and the second switch and the third switch are configured to be activated, so that the voltage at the first terminal and the voltage at the second terminal are equal to multiples of the first reference voltage and the second reference voltage, respectively.

[0115] In some embodiments, the semiconductor device further includes: a plurality of first metal tracks disposed in a first metallization layer of the plurality of metallization layers on the second side; and a plurality of second metal tracks disposed in the first metallization layer.

[0116] In some embodiments, the plurality of first metal tracks collectively function as a first terminal of a capacitor, and the plurality of second metal tracks collectively function as a second terminal of the capacitor.

[0117] In some embodiments, the plurality of first metal tracks and the plurality of second metal tracks are arranged alternately with each other along the first lateral direction.

[0118] In some embodiments, the semiconductor device further includes: a plurality of first via structures coupling the first nodes to a plurality of first metal tracks, respectively; and a plurality of second via structures coupling the second nodes to a plurality of second metal tracks.

[0119] In some embodiments, the semiconductor device further includes: a plurality of third metal tracks disposed in a second metallization layer of the plurality of metallization layers on the second side; and a plurality of fourth metal tracks disposed in the second metallization layer.

[0120] In some embodiments, the plurality of third metal tracks collectively function as a first terminal of the capacitor, and the plurality of fourth metal tracks collectively function as a second terminal of the capacitor.

[0121] In some embodiments, the plurality of first metal tracks and the plurality of second metal tracks are disposed directly below the first to fourth switches.

[0122] In some embodiments, each of the first to fourth switches includes a transistor having a source terminal and a drain terminal, wherein the source terminal or the drain terminal is coupled to one of the first terminal or the second terminal of the capacitor.

[0123] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor formed on a first side of a substrate, wherein each of the first to fourth transistors has a first source / drain terminal and a second source / drain terminal. The semiconductor device includes a plurality of first metal tracks and a plurality of second metal tracks formed on a second side of the substrate opposite to the first side. Each of the first metal tracks has a second source / drain terminal electrically coupled to the first transistor and a first portion electrically coupled to the first source / drain terminal of the second transistor. Each of the second metal tracks has a second source / drain terminal electrically coupled to the third transistor and a second portion electrically coupled to the first source / drain terminal of the fourth transistor. Each of the first metal tracks is physically spaced apart from one or more adjacent second metal tracks of the second metal tracks.

[0124] In some embodiments, each of the first metal tracks is physically spaced apart from one or more adjacent second metal tracks, and an inter-metal dielectric IMD is interposed between each of the first metal tracks and the one or more adjacent second metal tracks.

[0125] In some embodiments, each of the first metal tracks is physically spaced apart from one or more adjacent second metal tracks, with an intermetallic dielectric (IMD) and a high-k dielectric interposed between each of the first metal tracks and the one or more adjacent second metal tracks.

[0126] In some embodiments, the first metal tracks collectively function as a first terminal of a capacitor and the second metal tracks collectively function as a second terminal of the capacitor.

[0127] In some embodiments, the first transistor and the fourth transistor are configured to be activated, and the second transistor and the third transistor are configured to be deactivated, so that the voltage at the first terminal and the voltage at the second terminal of the capacitor are equal to the first reference voltage and the second reference voltage, respectively.

[0128] In some embodiments, after the voltage at the first terminal is equal to the first reference voltage, the first transistor and the fourth transistor are configured to be deactivated, and the second transistor and the third transistor are configured to be activated, so that the voltage at the first terminal and the voltage at the second terminal are equal to multiples of the first reference voltage and the second reference voltage, respectively.

[0129] In some embodiments, the respective first portions of the first metal track are aligned with each other along a lateral direction perpendicular to the length direction of the first and second metal tracks, and wherein the respective second portions of the second metal track are also aligned with each other along the lateral direction.

[0130] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes: forming a first transistor, a second transistor, a third transistor, and a fourth transistor on the front side of a substrate, wherein the first transistor and the second transistor are connected to each other, wherein a first source / drain terminal of the first transistor and a first source / drain terminal of the second transistor are connected to each other at a first common node, and the third transistor and the fourth transistor are connected to each other, wherein a first source / drain terminal of the third transistor and a first source / drain terminal of the fourth transistor are connected to each other at a second common node. The method includes: forming a plurality of front side metal tracks above the first transistor to the fourth transistor, wherein a first front side metal track of the front side metal tracks is coupled to the corresponding second source / drain terminals of the first transistor and the third transistor, and a second front side metal track of the front side metal tracks is coupled to the corresponding second source / drain terminals of the second transistor and the fourth transistor. The method includes forming a plurality of backside metal tracks on a backside of a substrate, wherein the plurality of backside metal tracks are spaced apart from one another using at least one dielectric, and wherein a first subset of the plurality of backside metal tracks are coupled to a first source / drain terminal of a first transistor and a first source / drain terminal of a second transistor, and a second subset of the plurality of backside metal tracks are coupled to a first source / drain terminal of a third transistor and a first source / drain terminal of a fourth transistor.

[0131] In some embodiments, a first subset of the backside metal tracks is operable to function as a first terminal of a capacitor, and a second subset of the backside metal tracks is operable to function as a second terminal of the capacitor.

[0132] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0133] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and the second reference voltage; and a capacitor formed on a second side of the substrate opposite the first side and having a first terminal and a second terminal; The first terminal is coupled to a first node between the first switch and the second switch, and the second terminal is coupled to a second node between the third switch and the fourth switch.

2. The semiconductor device according to claim 1, wherein The first switch and the fourth switch are configured to be activated, and the second switch and the third switch are configured to be deactivated, so that the voltages at the first terminal and the second terminal are equal to the first reference voltage and the second reference voltage, respectively.

3. The semiconductor device according to claim 2, wherein: After the voltage at the first terminal is equal to the first reference voltage, the first switch and the fourth switch are configured to be deactivated, and the second switch and the third switch are configured to be activated, so that the voltage at the first terminal and the voltage at the second terminal are respectively equal to the first reference voltage and a multiple of the first reference voltage.

4. The semiconductor device according to claim 1, further comprising: a plurality of first metal tracks disposed in a first metallization layer of the plurality of metallization layers on the second side; as well as A plurality of second metal tracks are disposed in the first metallization layer.

5. The semiconductor device according to claim 4, wherein: The plurality of first metal tracks collectively function as the first terminal of the capacitor, and the plurality of second metal tracks collectively function as the second terminal of the capacitor.

6. The semiconductor device according to claim 1, wherein Each of the first to fourth switches includes a transistor having a source terminal and a drain terminal, wherein the source terminal or the drain terminal is coupled to one of the first terminal or the second terminal of the capacitor.

7. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor formed on a first side of a substrate, wherein each of the first to fourth transistors has a first source / drain terminal and a second source / drain terminal; and a plurality of first metal tracks and a plurality of second metal tracks formed on a second side of the substrate opposite the first side; wherein each of the first metal tracks has a first portion electrically coupled to the second source / drain terminal of the first transistor and electrically coupled to the first source / drain terminal of the second transistor; wherein each of the second metal tracks has a second portion electrically coupled to the second source / drain terminal of the third transistor and electrically coupled to the first source / drain terminal of the fourth transistor; and Wherein each of the first metal tracks is physically separated from one or more adjacent second metal tracks of the second metal tracks.

8. The semiconductor device according to claim 7, wherein: Each of the first metal tracks is physically spaced apart from the one or more adjacent second metal tracks, with an intermetallic dielectric and a high-k dielectric interposed between each of the first metal tracks and the one or more adjacent second metal tracks.

9. The semiconductor device according to claim 7, wherein: The respective first portions of the first metal tracks are aligned with each other along a transverse direction perpendicular to the length direction of the first and second metal tracks, and wherein the respective second portions of the second metal tracks are also aligned with each other along the transverse direction.

10. A method for manufacturing a semiconductor device, comprising: forming a first transistor, a second transistor, a third transistor, and a fourth transistor on the front side of the substrate, wherein the first transistor and the second transistor are connected to each other, wherein a first source / drain terminal of the first transistor and a first source / drain terminal of the second transistor are connected to each other at a first common node, and the third transistor and the fourth transistor are connected to each other, wherein a first source / drain terminal of the third transistor and a first source / drain terminal of the fourth transistor are connected to each other at a second common node; forming a plurality of frontside metal tracks over the first to fourth transistors, wherein a first one of the frontside metal tracks is coupled to respective second source / drain terminals of the first and third transistors, and a second one of the frontside metal tracks is coupled to respective second source / drain terminals of the second and fourth transistors; and A plurality of backside metal tracks are formed on a backside of the substrate, wherein the plurality of backside metal tracks are spaced apart from each other using at least one dielectric, and wherein a first subset of the plurality of backside metal tracks are coupled to the first source / drain terminal of the first transistor and the first source / drain terminal of the second transistor, and a second subset of the plurality of backside metal tracks are coupled to the first source / drain terminal of the third transistor and the first source / drain terminal of the fourth transistor.

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