Memory device and method of manufacturing the same

Abstract

A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on a first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of a substrate. The memory device includes a plurality of second sub-transistors disposed in the second region of the substrate. The memory device also includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to a first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first and second via structures each have a first cross-sectional region, and the third via structure has a second cross-sectional region different from the first cross-sectional region. The embodiment of the invention also relates to a memory device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and a method for manufacturing the same. Background Art

[0002] Developments in electronic devices such as computers, portable devices, smart phones, Internet of Things (IoT) devices, etc. have promoted an increased demand for memory devices. Generally, memory devices may be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data when power is supplied, but may lose the stored data once the power is disconnected. Unlike volatile memory devices, non-volatile memory devices can retain data even after the power is disconnected, but may be slower than volatile memory devices.

[0003] An eFuse is a device for reprogramming an integrated circuit (IC) chip (such as a computer chip). In some instances, an eFuse can be used to provide on-chip performance adjustments. If a component of an IC chip fails, for example, an eFuse can be blown to change behavior or switch in a backup system. The IC chip can be provided with an array of eFuse cells each having a one-transistor-one-resistor or 1T1R architecture. For example, each eFuse cell can include a MOS (e.g., n-type MOS or NMOS) transistor (1T) operably coupled to a fuse element or resistor (1R). An eFuse can typically be implemented by coupling a weak trace to a power source in a current path, so that when a sufficiently high level of voltage (power) or current is provided to the eFuse, the eFuse will fail before other circuits (or other circuit components) fail, thereby adjusting the behavior of the IC chip. Although existing eFuse devices are generally adequate, they are not completely satisfactory in all aspects. Summary of the invention

[0004] Some embodiments of the present application provide a memory device, comprising: a substrate having a first side opposite to a second side; a memory cell comprising a transistor and a resistor coupled in series with each other, the memory cell being arranged on the first side, the transistor further comprising a plurality of first sub-transistors arranged in a first region of the substrate; a plurality of second sub-transistors arranged in a second region of the substrate; and a first interconnect structure arranged on the second side, wherein: each of the first sub-transistors is coupled to the first interconnect structure through a plurality of first through-hole structures, and each of the second sub-transistors is coupled to the first interconnect structure through a plurality of second through-hole structures and at least a third through-hole structure, each of the first through-hole structure and the second through-hole structure having a first cross-sectional area, and the third through-hole structure having a second cross-sectional area different from the first cross-sectional area.

[0005] Some other embodiments of the present application provide a memory device, comprising: a substrate, comprising a first region and a second region, each of the first region and the second region extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction; a first active region formed in the first region and on a front side of the substrate, the first active region extending longitudinally along the first direction; a first interconnect structure formed on the front side and coupled to one or more first portions of the first active region; a second interconnect structure formed on a back side of the substrate opposite to the front side; a plurality of first through-hole structures coupling one or more second portions of the first active region to the second interconnect structure; a second active region formed in the second region and on the first side of the substrate, the second active region extending longitudinally along the first direction; a plurality of second through-hole structures coupling one or more portions of the second active region to the second interconnect structure; and at least one third through-hole structure coupling the first interconnect structure to the second interconnect structure in the second region, wherein: each of the first through-hole structure and the second through-hole structure extends a first length along the first direction, and the third through-hole structure extends a second length along the first direction, the second length being longer than the first length.

[0006] Some further embodiments of the present application provide a method for manufacturing a memory device, comprising: providing a substrate having a first portion and a second portion adjacent to the first portion; forming a first sub-transistor in the first portion and a second sub-transistor in the second portion on a front side of the substrate, wherein adjacent first sub-transistors and second sub-transistors are arranged along a first direction, respectively; forming a first interconnect structure in the first portion and the second portion on the front side of the substrate, wherein the first interconnect structure includes a fuse resistor electrically coupled to the first sub-transistor; forming a first through-hole structure coupled to at least a portion of each of the first sub-transistor and the second sub-transistor on a back side of the substrate opposite to the front side; forming a second through-hole structure extending along the first direction in the second portion on the back side of the substrate, wherein the second through-hole structure is coupled to the first interconnect structure and is formed adjacent to the second sub-transistor along a second direction perpendicular to the first direction; and forming a second interconnect structure extending along the first direction and coupled to the first through-hole structure and the second through-hole structure on the back side of the substrate, the second interconnect structure including a power rail configured to provide a supply voltage to the first sub-transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A block diagram of an exemplary semiconductor device in accordance with some embodiments is shown.

[0009] Figure 2 According to some embodiments Figure 1 An exemplary circuit diagram of an exemplary memory cell of a semiconductor device.

[0010] Figure 3 , Figure 8 , Fig.12 , Fig.16 , Fig.19 , Fig. 22 and Fig.23 Each shows a front-side layout design of an exemplary memory cell coupled to a back-side interconnect structure (eg, power rails) according to some embodiments.

[0011] Figure 4 According to some embodiments, Figure 3 Schematic cross-sectional view of line AA′ of an exemplary memory cell.

[0012] Figure 5 According to some embodiments, Figure 3 Schematic cross-sectional view of line BB' of an exemplary memory cell.

[0013] Figure 6 , Fig. 9 , Fig.13 and Fig.17 Each shows a diagram according to some embodiments. Figure 3 , Figure 8 , Fig.12 and Fig.16 Schematic cross-sectional view of line CC' of an exemplary memory cell.

[0014] Figure 7 , Fig.10 , Fig.14 , Fig.18 and Fig. 20 Each shows a diagram according to some embodiments. Figure 3 , Figure 8 , Fig.12 , Fig.16 and Fig.19 Schematic cross-sectional view of line DD′ of an exemplary memory cell.

[0015] Fig.11 , Fig.15 and Fig.21 Each shows a diagram according to some embodiments. Figure 8 , Fig.12 and Fig.19 Schematic cross-sectional view of line EE' of an exemplary memory cell.

[0016] Fig.24 According to some embodiments, a method comprising selecting Figures 3 to 23 An exemplary layout design of multiple memory cells of the exemplary memory cell shown in FIG.

[0017] Fig.25 A flow chart of a method of manufacturing a semiconductor device according to some embodiments is shown.

[0018] Fig.26 A block diagram of a system for generating an IC layout design according to some embodiments is shown.

[0019] Fig. 27 A block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith is shown according to some embodiments.

[0020] Fig.28 A flow chart of an exemplary method for fabricating one or more memory cells on a front side of a substrate coupled with an interconnect structure on a back side of the substrate is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," "top," "bottom," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] A one-time programmable (OTP) memory device is a non-volatile memory device used in an integrated circuit for adjusting the circuit after the integrated circuit is manufactured. For example, an OTP memory device is used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is for adjusting analog circuits by trimming the capacitance or resistance values ​​of analog circuits or enabling and disabling parts of the system. A recent trend is that the same product may be manufactured in different manufacturing facilities but with a common process technology. Despite the best engineering efforts, it is likely that each facility will have a slightly different process. The use of OTP memory devices allows product functionality to be optimized independently for each manufacturing facility.

[0024] As IC technology advances, component sizes (e.g., the width of interconnect structures) have been reduced, allowing more circuits to be implemented in ICs. There are challenges associated with implementing OTP memory devices (such as, for example, electric fuses) in ICs. In applications where components of electric fuses (or electric fuse units, electric fuse memory units) are formed above the front side of an IC chip and power (or voltage) is provided to the fuse element of the electric fuse from the back side of the IC chip (substrate), one or more through holes configured to transmit power from the back side of the chip to the front side may exhibit higher resistance due to the small diameter of the through hole (i.e., cross-sectional area). Such an increase in resistance makes it difficult for the current in the through hole to rise to a sufficiently high level and causes the fuse element to malfunction. Therefore, it becomes challenging to program the IC components coupled to the electric fuse. Therefore, existing electric fuses in OTP memory devices are not entirely satisfactory.

[0025] Embodiments of the present disclosure provide various embodiments of a semiconductor device, which includes an electrical fuse coupled to a backside power rail (or backside interconnect structure) through a plurality of through-hole structures disposed in a device region and / or an adjacent tap region to reduce resistance and power dissipation along the conduction path of the electrical fuse. As used herein, the terms "coupled" and "connected" refer to an electrical connection or otherwise operational connection between two components, with or without any intermediate layers or components formed therebetween. Therefore, unless expressly stated otherwise, the terms "coupled", "connected", "electrically coupled", and "operably coupled" may be used interchangeably in embodiments of the present disclosure.

[0026] Figure 1 1 shows an exemplary block diagram of a semiconductor (eg, memory) device 100 according to various embodiments. Figure 1 In the illustrated embodiment of FIG. 1 , semiconductor device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, and control logic circuit 110. Although not shown in FIG. Figure 1 Although not explicitly shown in FIG. 1 , components of semiconductor device 100 may be operably coupled to each other and to control logic circuit 110. For example, control logic circuit 110, I / O circuit 108, column decoder 106, and row decoder 104 may be electrically coupled to memory array 102. Figure 1 In the illustrated example, for the purpose of clarity, the components are shown as separate blocks, but in some other embodiments, some or all of the components may be integrated together. For example, the memory array 102 may include embedded I / O circuits 108.

[0027] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R1 each extending in a first direction (e.g., X direction). M and a plurality of columns C1, C2, C3, ... C each extending in a second direction (eg, the Y direction). N Each of the rows / columns may include one or more conductive structures. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through the corresponding conductive structures of the column and row.

[0028] According to various embodiments of the present disclosure, each memory cell 103 is implemented as an OTP memory cell, such as an electric fuse cell including a fuse resistor and an access transistor coupled in series with each other (hereinafter referred to as an electric fuse cell 103 or an electric fuse memory cell 103). The access transistor can be coupled to (e.g., gated by) a word line (WL). The access transistor can be turned on / off to enable / disable access (e.g., programming, reading) to the corresponding fuse resistor. For example, when selected, the access transistor of the selected fuse cell is turned on to generate a programming or reading path that is conducted through its fuse resistor and itself.

[0029] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a bit line, a source line) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the electrical fuse cells 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0030] Figure 2 An electrical fuse memory cell (eg, Figure 1 103) is an exemplary configuration. Figure 2 In the example of FIG. 1 , the e-fuse memory cell 103 is implemented as a one-transistor-one-resistor (1T1R) configuration, e.g., a fuse resistor 150 and an access transistor 160 connected in series with each other. However, it should be understood that any of a variety of other fuse configurations exhibiting fuse characteristics may be used by the e-fuse memory cell 103, such as, for example, a 2-diode-1-resistor (2D1R) configuration, a multi-transistor-one-resistor (multi-T1R) configuration, etc., while remaining within the scope of the disclosed embodiments.

[0031] According to various embodiments of the present disclosure, the fuse resistor 150 and the access transistor 160 are formed on the same side, for example, the front side of the semiconductor substrate (or substrate), and the supply voltage (V SS ) is provided from a power rail disposed on the opposite side (ie, the back side) of the substrate through various types of through-hole structures. Throughout the disclosed embodiments, such a backside power rail (which includes a backside metallization layer) may be optionally referred to as a backside interconnect structure.

[0032] In an exemplary embodiment, the access transistor 160 is formed on the front side of the substrate, which is sometimes referred to as part of the front end of line (FEOL) process, and a plurality of metallization layers are formed above the FEOL process on the front side as part of the front side interconnect structure of the back end of line (BEOL) process, each of the plurality of metallization layers including a plurality of metal structures (e.g., metal lines). The fuse resistor 150 may be formed by one or more of the metal structures in one of the metallization layers (e.g., the M2 metallization layer), which is disposed above the access transistor 160 as part of the front side interconnect structure. Thus, the access transistor 160 and the fuse resistor 150 may be formed by the FEOL process and the BEOL process (on the front side), respectively. In some embodiments, the fuse resistor 150 includes other types of conductive materials, such as polysilicon. In some embodiments, the fuse resistor 150 includes a conductive material having a higher resistance than the conductive material in the other metal structures of the BEOL process, thereby allowing the fuse resistor 150 to be blown more easily. For the purpose of clarity, the metal structure configured as the fuse resistor 150 and the metal structure configured as the backside power rail are referred to herein as the frontside metal structure and the backside metal structure, respectively.

[0033] In the case where the fuse resistor 150 of the e-fuse memory cell 103 is embodied as a (front side) metal structure, the fuse resistor 150 may present an initial resistance value (or resistivity) such as when manufactured. To program the e-fuse memory cell 103, a (e.g., voltage) signal corresponding to a logic high state is applied to the gate terminal of the access transistor 160 via the word line (WL) to turn on the access transistor 160 (e.g., embodied as an n-type transistor). Simultaneously or subsequently, with the access transistor 160 turned on, a sufficiently high (e.g., voltage / current) signal (such as a programming voltage) is applied to one of the terminals of the fuse resistor 150 via the bit line (BL) 170, and a supply voltage is applied to the source line (SL) 180, thereby establishing a first conduction (e.g., programming) path. In the present embodiment, the supply voltage is applied from the back side of the substrate (e.g., in a back side interconnect structure). In this regard, according to some embodiments, a first conduction (e.g., programming) path extends from BL 170, through a first end of fuse resistor 150, fuse resistor 150, a second end of fuse resistor, access transistor 160, a plurality of via structures (such as backside vias and / or feedthrough vias), and to SL 180 disposed on the back side of the substrate. This configuration is consistent with a supply voltage V SS Unlike existing conventional e-fuse memory cell designs that are typically applied from the front side (such as through a front side interconnect structure), the e-fuse memory cell 103 of the disclosed embodiments at least benefits from additional wiring options from the back side of the substrate, thereby improving flexibility in cell design and / or ease of manufacturing related to the manufacturing process.

[0034] In some embodiments, additional via structures are incorporated along the conduction path between the access transistor 160 and the backside power rail (i.e., the backside interconnect structure) to reduce the resistance of the conduction path and improve the device performance in the electric fuse memory cell 103. For example, the disclosed embodiments provide electric fuse memory cells (e.g., electric fuse memory cells 103), each of which includes a device region adjacent to a tap (e.g., pickup, dummy, guard ring, etc.) region, wherein the device region includes a plurality of sub-transistors each serving as an access transistor (e.g., access transistor 160), and the tap region includes a plurality of dummy sub-transistors. Each of the functional sub-transistors has a first source / drain terminal coupled to a fuse resistor (e.g., fuse resistor 150) disposed in a frontside metallization layer (in the frontside interconnect structure) and a second source / drain terminal coupled to a supply voltage source (e.g., SL 180) disposed in a backside metallization layer (in the backside interconnect structure) through at least one of the via structures described above. Each of the dummy sub-transistors has its source terminal, drain terminal, and gate terminal coupled to a supply voltage source disposed in the backside metallization layer through at least one of the via structures. In this regard, for a given applied supply voltage, the resistance of the conduction path between the access transistor and the supply voltage source can be adjusted (e.g., reduced).

[0035] In some embodiments, the placement of the via structures for connecting the functional sub-transistor and the pseudo-sub-transistor is determined based on, for example, the size of each via structure relative to the size of the cell area where the via structure can be placed. For example, the backside via coupled to the source / drain terminal of the access transistor and overlapping with the source / drain terminal of the access transistor has a smaller cross-sectional area than the feedthrough via, which generally has an elongated shape extending parallel to the active area (e.g., fin) of the electric fuse memory cell in a top view. Because the resistance generally varies inversely with the cross-sectional area of ​​the conductor, the resistance of the backside via is higher than the resistance of the feedthrough via. In some instances, the resistance of the feedthrough via can be as low as 1 / 8 of the resistance of the backside via. Therefore, for device areas where the cell area is more restricted than the tap area, more area-efficient backside vias can be utilized, and more feedthrough vias can be utilized in the tap area. In some embodiments, backside vias and feedthrough vias are utilized in the device area and the tap area.

[0036] Figure 3 2 shows a front side layout design of a portion of an exemplary semiconductor device 200. The semiconductor device 200 includes a semiconductor substrate (or substrate) 202 (eg, see Figure 4 ) above a front side 202A of the device. Figure 3An embodiment of an e-fuse memory cell 201A is depicted in FIG. In some embodiments, the substrate 202 includes a plurality of doped wells, such as a p-type well and an n-type well for providing an n-type device (e.g., an NMOS device) and a p-type device (e.g., a PMOS device), respectively. It should be noted that Figure 3 2 and subsequent figures remove various dielectric components (eg, the FEOL isolation region of the e-fuse memory cell 201A) to make the depiction of the various components of the e-fuse memory cell 201A clearer.

[0037] In the present embodiment, the substrate 202 includes a first region (e.g., area, portion, etc.) P1, a second region P2, and a third region P3 between the first region P1 and the second region P2 along a first lateral direction (e.g., X-axis). In some embodiments, the first region P1 is configured as a device region for providing active components of the electric fuse memory cell 201A, and the second region P2 is configured as a tap region adjacent to or surrounding the first region P1, for separating the first region P1 of adjacent electric fuse memory cells 201A in a given layout of the semiconductor device 200, and other functions. The third region P3 may be configured as a dummy region (e.g., without any device), and may include at least one dummy gate structure 222 and at least one source / drain contact 232 each extending longitudinally along a second lateral direction (e.g., Y-axis) and between vertical boundaries of the first region P1 and the second region P2 along the first lateral direction. In some embodiments, as depicted herein, the second region P2 extends adjacent to the first region P1 along the second lateral direction.

[0038] The first region P1 has a first cell height H1, and the second region P2 has a second cell height H2, each of which is defined along the second lateral direction. In some embodiments, the cell heights H1 and H2 are the same. In some embodiments, the cell height H1 is greater than the cell height H2. In some embodiments, the cell height H2 is greater than the cell height H1. In some examples, the cell heights H1 and H2 are each at least about 156 nm. Figure 3 In the depicted embodiment of , cell heights H1 and H2 are both about 208 nm.

[0039] In the first region P1, the electric fuse memory cell 201A includes a plurality of active regions (each also referred to as oxide diffusion or OD regions) 204 located above the front side 202A of the substrate 202 and separated by isolation regions (not separately depicted). The active regions 204 each extend longitudinally along a first lateral direction and are separated from each other along a second lateral direction. The active regions 204 may each include a monolithic structure for providing a fin field effect transistor (FinFET), such as a fin active region. Optionally, the active regions 204 may each include a stack of nanostructures (e.g., nanosheets, nanorods, etc.) for providing a gate-all-around (GAA) FET. According to some embodiments of the present disclosure, other configurations of the active regions 204 may also be applicable to the electric fuse memory cell 201A. The active regions 204 each have a height W1 defined along the second lateral direction, such as Figure 3 As depicted in , adjacent active regions 204 are separated by a distance M, which is also referred to as the height of the dummy regions 203 of the substrate 202 .

[0040] The e-fuse memory cell 201A includes a plurality of gate structures (e.g., functional gate structures) 220 oriented perpendicular to a portion of the active region 204 and located above a portion of the active region 204 to define a channel region therein, wherein each channel region is between a pair of source / drain regions (e.g., source / drain terminals) 216 / 218 along a first lateral direction. In this regard, the gate structure 220 is joined to each pair of source / drain regions 216 / 218 to form a sub-transistor t1, wherein the sub-transistor t1 is a functional transistor. In some embodiments, the gate structures 220 spaced apart along a second lateral direction are separated by a dummy region 203. The e-fuse memory cell 201A also includes a plurality of source / drain contacts 230 extending longitudinally along the second lateral direction and spaced apart from each other along the first lateral direction, each between adjacent gate structures 220. Each of the source / drain contacts 230 is electrically coupled to each of the source / drain regions 216 / 218 of the sub-transistor t1. In the depicted embodiment, each source / drain contact 230 protrudes from one of the long edges of the active region 204 along the second lateral direction toward the horizontal boundary L1 of the first region P1 .

[0041] Each of the sub-transistors t1 (e.g., FinFET, GAA FET, etc.) is used as an access transistor, which is an embodiment of the access transistor 160 described above. The plurality of sub-transistors t1 are collectively referred to as transistors T1 in the electrical fuse memory cell 201A. Specifically, each sub-transistor t1 has a voltage coupled to an applied voltage V SSThe electric fuse memory cell 201A includes one of the source / drain terminals (i.e., one of the source / drain regions 216 / 218) of the supply voltage source (e.g., the backside interconnect structure 250) and the other of the source / drain terminals coupled to the fuse resistor (e.g., the fuse resistor 356 in the frontside interconnect structure 300). In some embodiments, the sub-transistor t1 is an n-type device formed in a p-type well in the substrate 202. As depicted herein, the electric fuse memory cell includes four sub-transistors t1. It should be noted that according to embodiments of the present disclosure, more or fewer sub-transistors t1 may be included in the electric fuse memory cell 201A.

[0042] The e-fuse memory cell 201A also includes a front-side interconnect structure 300 coupled to the source / drain contacts 230 and the gate structure 220. The front-side interconnect structure 300 includes, for example, vias 260 configured to couple at least some of the source / drain contacts 230 to a front-side metallization layer 310 (M0), which includes, for example, metal lines (e.g., metal traces) 310A ( Figure 6 )、310B( Figure 6 )、310C( Figure 6 ) and 310D( Figure 7 ). The e-fuse memory cell 201A further includes a gate contact 262 configured to couple at least some of the gate structures 220 to a front side metallization layer 310. The front side metallization layer 310 may be a plurality of metallization layers (e.g., such as Figure 6 and Figure 7 The first of the front side metallization layers 330 and 350 depicted in FIG. Figure 6 and Figure 7 Details of the front-side interconnect structure 300 are described.

[0043] In some embodiments, reference Figure 3 , the second region P2 is a tap region that electrically couples a specific doped well in the substrate 202 (e.g., an n-type well for forming a PMOS device or a p-type well for forming an NMOS device) to a voltage source. In the depicted embodiment, because the sub-transistor t1 is an n-type device, the second region P2 is configured to electrically couple the p-type well in the e-fuse memory cell 201A to the supply voltage V SS The p-type tap (or P-tap) region, supply voltage V SS Provided on the back side 202B of the substrate 202. In further embodiments, the concentration of the p-type dopant in the P-tap region (i.e., the second region P2) is higher than the concentration of the p-type dopant in the p-type well in the first region P1. In some embodiments, the second region P2 is implemented in the e-fuse memory cell 201A to reduce or prevent an undesired short circuit caused by latch-up.

[0044] Still reference Figure 3 , in the second region P2, the e-fuse memory cell 201A includes a plurality of active regions 206 above the front side 202A of the substrate 202. The active regions 206 are similar to the active regions 204. For example, each of the active regions 206 extends longitudinally along the first lateral direction and is separated from each other along the second lateral direction. Two adjacent active regions 206 are separated by a dummy region 205 in the substrate 202, similar to the dummy region 203 between two adjacent active regions 204.

[0045] Each of the active regions 206 has a height W2 defined along the second lateral direction, wherein the height W2 may be the same as or different from the height W1. In some embodiments, the height W1 is greater than or equal to the height W2. In some embodiments, the height W1 and the height W2 are each about 32nm, 42nm, or 58nm. For example, the height W1 may be about 42nm, and the height W2 may be about 32nm. The separation distance N extending between two adjacent active regions 206 to the height of the dummy region 205 may be the same as or different from the distance M of the dummy region 203. In some instances, the distance (or height) M is at least about 62nm, and the distance (or height) N is at least about 72nm. As will be discussed in detail below, when the height M and the height N are respectively greater than the height of the feedthrough hole defined along the second lateral direction, it is possible to form a feedthrough hole between two adjacent active regions 204 and / or between adjacent active regions 206. As depicted herein, the cell height H1 is the sum of the total height of the active region 204 (e.g., 2*W1), the height M of the dummy region 203, and the total separation distance between each of the active regions 204 of the first region P1 and the corresponding horizontal boundary L1, which can be calculated as the sum of x*M and (1-x)*M, where x is a fraction between 0 and 1. In other words, the total separation distance between each of the active regions 204 and the corresponding horizontal boundary L1 is equal to the height M. Similarly, the cell height H2 is the sum of the total height of the active region 206 (e.g., 2*W2), the height N of the dummy region 205, and the total separation distance between each of the active regions 206 of the second region P2 and each corresponding horizontal boundary L2, which can be calculated as the sum of y*N and (1-y)*N, where y is a fraction between 0 and 1.

[0046] Similar to region P1, region P2 of semiconductor device 200 includes a plurality of gate structures 224 oriented perpendicular to a portion of each active region 206 and located above a portion of each active region 206 to define a channel region between a pair of source / drain regions 226 / 228 along a first lateral direction. Thus, gate structure 224 is joined to each pair of source / drain regions 226 / 228 to form a sub-transistor t2 (e.g., FinFET, GAA FET, etc.). Semiconductor device 200 also includes a plurality of source / drain contacts 234 extending along a second lateral direction and between adjacent gate structures 224. Each of source / drain contacts 234 is electrically coupled to each of source / drain regions 226 / 228 of sub-transistor t2. In the depicted embodiment, each source / drain contact 234 protrudes from one of the long edges of active region 206 toward horizontal boundary L2 of second region P2 along the second lateral direction.

[0047] In this embodiment, the source / drain terminals of each sub-transistor t2 (i.e., both of the source / drain regions 226 / 228) and the gate terminal between the source / drain terminals are coupled to the applied V SS The supply voltage source makes each sub-transistor t2 a pseudo-OR non-functional transistor. This is in contrast to the sub-transistors t1, which are access transistors each having one of the source / drain regions 216 / 218 coupled to the fuse resistor 356 and the other of the source / drain regions 216 / 218 coupled to the supply voltage source. The semiconductor device 200 in this embodiment includes a plurality of sub-transistors t2 coupled together in parallel.

[0048] Similar to the first region P1, a portion of the sub-transistor t2 in the second region P2 is coupled to the front-side interconnect structure 300. For example, the via 260 is configured to couple each of the source / drain contacts 234 to the front-side metallization layer 310, and the gate contact 262 is configured to couple each of the gate structures 224 to the front-side metallization layer 310.

[0049] refer to Figure 4 , Figure 4 The electrical fuse memory cell 201A is shown as Figure 3 , the semiconductor device 200 includes a backside via 240 coupled to a portion of the e-fuse memory cell 201A located in the first region P1. The backside via 240 extends vertically (e.g., along the Z axis) through at least the substrate 202 and the active region 204 to couple a metal line 252A of a backside metallization layer (BM0) 252 to one of the source / drain regions 216 / 218 of the sub-transistor t1 in the e-fuse memory cell 201A, wherein the metal line 252A (also at Figure 32 (depicted in FIG. 2 ) is formed over the back side 202B of the substrate 202. The metal line 252A is considered to be part of the back side interconnect structure 250 (eg, an embodiment of the supply voltage source or SL 180; see FIG. 2 ). Figure 6 and Figure 7 ), which provides power to the front side components (e.g., source / drain regions 216 / 218) of the electrical fuse memory cell 201A through the back side via 240. In the present embodiment, the back side via 240 directly contacts the metal line 252A and the source / drain region 216 / 218 of the sub-transistor t1, which is further coupled to the fuse resistor 356 in the front side interconnect structure 300. In this regard, the back side via 240 partially penetrates the active region 204 in the vertical direction (e.g., along the Z axis). As discussed above, the back side interconnect structure 250 is configured to provide a supply voltage V from the back side 202B of the substrate 202 to the front side 202A. SS , to establish a conduction (eg, programming) path for the e-fuse memory cell 201A.

[0050] The backside via 240 has a width 241 defined along the first lateral direction. Although not depicted, the backside via 240 may include a metal filling layer (not depicted separately) located above the barrier layer (not depicted separately). The metal filling layer may include any suitable conductive material, including, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), cobalt (Co), ruthenium (Ru), etc., or a combination thereof. In some examples, the metal filling layer may include a seed layer. The barrier layer may include Ti, Ta, TiN, TaN, etc., or a combination thereof. In some embodiments, although not depicted, the electrical fuse memory cell 201A also includes a first metal silicide layer disposed between the backside via 240 and the source / drain region 216 / 218 and a second metal silicide layer disposed between the front side (or top surface) of the source / drain region 216 / 218 and the source / drain contact 230.

[0051] Figure 5 The semiconductor device 200 is shown along Figure 3 The feed-through hole 280 in the cross-sectional view of the line BB' in the second region P2 of FIG. Figure 3As shown in the layout design of FIG. 2 , the feedthrough via 280 extends longitudinally along a first lateral direction and is separated from the adjacent active area 206 along a second lateral direction in the top view. Specifically, the feedthrough via 280 is disposed between two adjacent active areas 206. The feedthrough via 280 extends at least through the substrate 202 to couple the metal line 252C (which is similar to the metal line 252A) to the contact feature 236 on the front side 202A of the e-fuse memory cell 201A, and then to the front side interconnect structure 300. Unlike the backside via 240, the feedthrough via 280 couples the metal line 252C directly to the contact feature 236 and is therefore not coupled to any portion of the sub-transistor t2. The feedthrough via 280 may include a metal fill layer (not separately depicted) located above a barrier layer (not separately depicted), similar to the backside via 240.

[0052] The feedthrough via 280 has a width 281 defined along a first lateral direction, wherein the width 281 is greater than Figure 4 241 of the backside via 240 depicted in FIG. Thus, the cross-sectional area of ​​the feed-through via 280 in the XY plane is larger than the cross-sectional area of ​​the backside via 240, resulting in a lower resistance than the backside via 240. The compositions of the metal fill layer and the barrier layer may be similar to those of the metal fill layer and the barrier layer of the backside via 240, respectively, as discussed above.

[0053] Figure 6 The sub-transistor t1 in the E-fuse memory cell 201A is shown along Figure 3 The backside via 240 couples the backside interconnect structure 250 to the sub-transistor t1 at one of the source / drain regions 216 / 218, thereby establishing a supply voltage V SS A connection is transmitted from the back side 202B (e.g., from SL) to the e-fuse memory cell 201A. The other of the source / drain regions 216 / 218 is coupled to the front side interconnect structure 300, which in the depicted embodiment includes an interconnect structure (e.g., metal structure, metal line) that serves as a fuse resistor 356 (e.g., an embodiment of the fuse resistor 150 described above) disposed in the front side metallization layer 350 (M2). The fuse resistor 356 is also coupled to a programming voltage V transmitted from the front side interconnect structure 300 (e.g., from BL). DD It should be noted that the fuse resistor 356 may alternatively be disposed in a different portion of the front-side interconnect structure 300 .

[0054] Figure 7 A portion of the semiconductor device 200 is shown. Figure 3 The cross-sectional view of the line DD'. Figure 6 A cross-sectional view of the sub-transistor t1 along the direction of the active region 204 is depicted, but Figure 7 A portion of the second region P2 that spans the active region 206 and the adjacent dummy region 205 is shown. The e-fuse memory cell 201A in the second region P2 includes a backside via 244 (also in FIG. Figure 3 ), a backside via 244 extends vertically (e.g., along the Z-axis) through a portion of the substrate 202 and the active region 206 to couple a backside metallization layer (BM0) 252B to one of the source / drain regions 226 / 228 of the sub-transistor t2, wherein the metal line 252B (also in Figure 3 The backside through hole 244 extends longitudinally along the second lateral direction, as shown in FIG. Figure 3 The backside via 244 couples the backside interconnect structure 250 to the frontside interconnect structure 300 through the sub-transistor t2, and then to the sub-transistor t1, thereby establishing a conductive path between the sub-transistor t1, the sub-transistor t2 and the backside interconnect structure 250, and applying the supply voltage V from the backside interconnect structure 250. SS In some embodiments, the backside via 244 is similar in structure and size to the backside via 240 of the e-fuse memory cell 201A. In some embodiments, the backside vias 240 and 244 have the same structure and size. For example, the backside vias 240 and 244 both have a width 241 as described above.

[0055] In addition, still refer to Figure 7 , the semiconductor device 200 in the second region P2 includes a feedthrough via 280 extending vertically through the dummy region 205 (i.e., the substrate 202) to couple the backside metallization layer 252 (e.g., metal line 252C) to the contact feature 236, which is further coupled to the frontside interconnect structure 300. This is in contrast to the backside via 244, which couples the metal line 252B to one of the source / drain regions 226 / 228 of the sub-transistor t2. In the depicted embodiment, the metal lines 252B and 252C are separated from each other along the second lateral direction, as shown in FIG. Figure 3 Through the contact feature 236, the feed-through via 280 couples the backside interconnect structure 250 to the frontside interconnect structure 300, and then to the sub-transistor t1, thereby establishing a conduction path between the sub-transistor t1, the sub-transistor t2, and the backside interconnect structure 250, and applying a supply voltage V from the backside interconnect structure 250. SS As described above, feedthrough vias generally exhibit lower resistance than backside vias due to the larger cross-sectional area, by incorporating feedthrough vias 280 in the second region P2, the resistance of the conductive path may be further reduced.

[0056] In some embodiments, the feedthrough via 280 has a height W3 extending along the second lateral direction. In this regard, the placement of the feedthrough via 280 between the active regions 206 indicates that the height N of the dummy region 205 exceeds the height W3 of the feedthrough via 280. In some embodiments, the height W3 is about 70 nm, and the height N is at least about 72 nm. In some embodiments, given a constant cell height H2 of the second region P2, the height W3 is determined based on the height N or the height W2 of the active region 206. In the depicted embodiment, because the height M of the dummy region 203 in the e-fuse memory cell 201A is less than the height W3, the first region P1 does not include any feedthrough vias.

[0057] Common Reference Figure 6 and Figure 7 , additional details of the front side interconnect structure 300 and the back side interconnect structure 250 are also shown. For example, the front side interconnect structure 300 also includes a front side metallization layer 330 disposed above the front side metallization layer 310 and interconnected to the front side metallization layer 310 through vias 320A, 320B, 320C, 320D, and 320E (collectively referred to as vias 320 (V0)). Additional front side metallization layers above the front side metallization layer 310 (M0) may be designated as M1, M2, ..., and M n , wherein the adjacent front metallization layers are respectively connected through vias V1, V2...V n-1 Interconnect. Each of the front side metallization layers includes one or more metal lines electrically coupled to corresponding vias. In the depicted embodiment, the front side metallization layers M1 and M2 correspond to the front side metallization layers 330 (including metal lines 330A, 330B, and 330C) and 350 (including metal lines 350A, 350B, and 350C), respectively, and the via V1 corresponds to the via 340 (including vias 340A, 340B, and 340C). In some embodiments, the sub-transistor t1, the sub-transistor t2, and the feedthrough via 280 are coupled to a common metal line in the front side interconnect structure 300, such as the metal line 330A, thereby forming a parallel connection therebetween.

[0058] Similarly, the backside interconnect structure 250 includes through-holes (such as BV0, BV1 . . . BV n-1 ) are multiple backside metallization layers coupled together, such as BM0, BM1 ... and BM n For example, backside metallization layer 252 (BM0) (which includes metal lines 252A, 252B, and 252C) is interconnected to backside metallization layer 254 (BM1) (which includes metal lines 254A, 254B, and 254C) through one or more of vias 272A, 272B, 272C, and 272D (which are collectively referred to as vias 272 (BV0)).

[0059] It should be noted that, for the purpose of simplicity and clarity, the various dielectric (e.g., insulating) layers within which the front and back metallization layers (including interconnect structures) are formed have been omitted from the description of the various embodiments of the e-fuse memory cells in the disclosed embodiments. These dielectric layers may include, for example, etch stop layers (ESLs), interlayer dielectric (ILD) layers, and intermetallic dielectric (IMD) layers. In addition, in Figure 6 , Figure 7 , Figures 9 to 11 , Figures 13 to 15 , Fig.17 , Fig.18 , Fig. 20 and Fig.21 The cross-sectional view of each e-fuse memory cell depicted in FIG. 1 also omits the substrate 202 extending below the active regions 204 and 206 and the dummy regions 203 and 205. It should also be noted that for the purpose of clarity, in the subsequent Figures 9 to 11 , Figures 13 to 15 , Fig.17 , Fig.18 , Fig. 20 and Fig.21 The front-side interconnect structure 300 and the back-side interconnect structure 250 (as they are shown in the cross-sectional views of the respective electrical fuse memory cells) are not repeated. Figure 6 and Figure 7 Detailed reference to the individual metal lines and vias in the FIG.

[0060] In some embodiments, reference Figures 8 to 11 , the semiconductor device 200 includes a plurality of electric fuse memory cells 201B. In some embodiments, the electric fuse memory cells 201B are similar to the electric fuse memory cells 201A. For example, Fig. 9 and Fig.10 The cross-sectional views of the electrical fuse memory cell 201B along the lines CC′ and DD′ respectively depicted in FIG. Figure 6 and Figure 7 Those of the electric fuse memory cell 201A are depicted respectively in FIG.

[0061] However, with Figure 3 , Figure 6 and Figure 7 Unlike the E-fuse memory cell 201A depicted in FIG. 2 , the dummy region 203 of the E-fuse memory cell 201B includes a feedthrough via 286. Figure 8 ( Figure 8 Depicts the front layout design) and reference Fig.11 ( Fig.11 Depicted along Figure 8EE'), the dummy region 203 in the first region P1 is configured to have a height M that exceeds the height W3 of the feedthrough via 286. In this regard, for a given cell height H1, which is substantially the same as the cell height H2 in the depicted embodiment, the height W1 of the active region 204 is reduced to expand the area of ​​the dummy region 203, thereby allowing the layout of the first region P1 to accommodate the placement of the feedthrough via 286. In some embodiments, the reduced height W1 does not exceed the height W2 of the active region 206 in the second region P2. In some embodiments, the reduced height W1 does not exceed the height W2 of the active region 206 in the second region P2. In some embodiments, the reduced height W1 is greater than the height W2 of the active region 206. In some embodiments, instead of reducing the height W1, the active regions 204 are further spaced apart along the second lateral direction to expand the height M of the dummy region 203.

[0062] In some embodiments, feedthrough via 286 is similar in structure and size to feedthrough via 280 of electrical fuse memory cell 201A. In some embodiments, feedthrough vias 280 and 286 have the same structure and size. For example, feedthrough vias 280 and 286 have the same height W3 and width 281 as described above. Fig.10 and Fig.11 By comparison, feedthrough via 286 couples backside interconnect structure 250 (e.g., metal line 252C) to contact feature 238, which is further coupled to frontside interconnect structure 300 (e.g., coupled to metal line 330A through, for example, vias 320F and 320G), while feedthrough via 280 couples backside interconnect structure 250 (e.g., metal line 252C) to contact feature 236. Incorporating feedthrough via 286 in first region P1 further reduces the resistance of the conduction path between sub-transistor t1, sub-transistor t2, and backside interconnect structure 250, from which supply voltage V is applied. SS .

[0063] In some embodiments, reference Figures 12 to 15 , the semiconductor device 200 includes a plurality of electrical fuse memory cells 201C, wherein Fig.12 depicts the front side layout design of the e-fuse memory cell 201C, and Fig.14 The electrical fuse memory cell 201C is depicted along Fig.12 DD'. In some embodiments, the electric fuse memory cell 201C is similar to the electric fuse memory cell 201B. For example, Fig.13 and Fig.15 The cross-sectional views of the electrical fuse memory cell 201C along the lines CC′ and EE′ respectively described in FIG. Fig. 9 and Fig.11In this regard, the dummy region 203 in the first region P1 of the e-fuse memory cell 201C is configured to have a height M exceeding the height W3 of the feedthrough via 286, and the height W1 of the active region 204 does not exceed the height W2 of the active region 206.

[0064] However, with Figures 8 to 11 The electrical fuse memory cell 201B depicted in FIG. Fig.12 and Fig.14 , the dummy region 205 of the E-fuse memory cell 201C does not include any feedthrough vias 280. Therefore, the resistance of the conduction path between the sub-transistor t1, the sub-transistor t2, and the backside interconnect structure 250 in the E-fuse memory cell 201C may be similar to the resistance of the E-fuse memory cell 201A, but greater than the resistance of the E-fuse memory cell 201B.

[0065] In some embodiments, reference Figures 16 to 18 , the semiconductor device 200 includes a plurality of electrical fuse memory cells 201D, wherein Fig.16 depicts the front side layout design of the e-fuse memory cell 201D, and Fig.18 The electrical fuse memory cell 201D is depicted along Fig.16 DD'. In some embodiments, the electric fuse memory cell 201D is similar to the electric fuse memory cell 201A. For example, Fig.17 The cross-sectional view of the electric fuse memory cell 201D along line CC' in FIG. Figure 6 A cross-sectional view of an electric fuse memory cell 201A is depicted in FIG.

[0066] and Figure 3 , Figure 6 and Figure 7 The electrical fuse memory cell 201A depicted in FIG. Fig.16 and Fig.18 , the dummy region 205 of the e-fuse memory cell 201D does not include any feedthrough vias 280. Therefore, the resistance of the conduction path between the sub-transistor t1, the sub-transistor t2, and the backside interconnect structure 250 in the e-fuse memory cell 201D may be greater than the resistance of the e-fuse memory cells 201A-201C. However, omitting the feedthrough vias 280 and 286 may have at least the benefit of reducing the complexity and cost of the manufacturing process by using one less mask (or photomask) to perform the photolithography process in forming the feedthrough vias.

[0067] In some embodiments, reference Figures 19 to 21 , the semiconductor device 200 includes a plurality of electrical fuse memory cells 201E, wherein Fig.19depicts the front side layout design of the E-fuse memory cell 201E, Fig. 20 The electrical fuse memory cell 201E is depicted along Fig.19 A cross-sectional view of line DD', and Fig.21 The electrical fuse memory cell 201E is depicted along Fig.19 ' is a cross-sectional view of line EE' of the electric fuse memory cell 201E. In some embodiments, the electric fuse memory cell 201E is similar to the electric fuse memory cell 201B. For example, the dummy regions 203 and 205 of the electric fuse memory cell 201E include feedthrough vias 280 and 286, respectively. However, unlike the electric fuse memory cell 201B, neither the first region P1 nor the second region P2 of the electric fuse memory cell 201E has any backside vias, i.e., the backside vias 240 and 244, respectively, present in the electric fuse memory cell 201B. In this regard, although the resistance of the conduction path between the sub-transistor t1, the sub-transistor t2, and the backside interconnect structure 250 in the electric fuse memory cell 201E may be greater than the resistance of the electric fuse memory cell 201B, omitting the backside vias 240 and 244 may at least have the benefit of reducing the complexity and cost of the manufacturing process, similar to the benefit of omitting the feedthrough vias 280 and 286 in the structure of the electric fuse memory cell 201D.

[0068] In some embodiments, the semiconductor device 200 includes a plurality of electrical fuse memory cells 201F, wherein Fig. 22 The front side layout design of the E-fuse memory cell 201F is depicted. In some embodiments, the E-fuse memory cell 201F is similar to the E-fuse memory cell 201E. For example, Fig.19 and Fig. 22 In comparison, each of the e-fuse memory cells 201E and 201F includes the feedthrough via 286 in the first region P1 and the feedthrough via 280 in the second region P2 , but does not have any of the backside vias 240 and 244 .

[0069] However, unlike the e-fuse memory cell 201E, in the e-fuse memory cell 201F, the cell height H1 of the first region P1 is greater than the cell height H2 of the second region P2. The increase in the cell height H1 may be due to an increase in the height W1 of the active region 204 (which may have the benefit of improving the speed of the sub-transistor t1), an increase in the height M of the dummy region 203 (which may have the benefit of reducing the resistance of the feedthrough via 286), or both. In some embodiments, the height W1 of the active region 204 is at least the same as (i.e., equal to or greater than) the height W2 of the active region 206, and the height M of the dummy region 203 is at least the same as the height N of the dummy region 205 in the e-fuse memory cell 201F. In some embodiments, the height M is less than the height N of the dummy region 205. In further embodiments, the presence of the feedthrough vias 280 and 286 indicates that both the height M and the height N are greater than the height W3 of the feedthrough vias 280 / 286.

[0070] Fig.23 A schematic top view of an exemplary e-fuse memory cell 201G is depicted. The e-fuse memory cell 201G can be similar to any of the e-fuse memory cells 201A-201F as described above, except that the second region P2 surrounds or encloses the first region P1, rather than extending beside the first region P1 as in the case for the e-fuse memory cells 201A-201F. In this regard, the second region P2 can serve as a guard ring structure coupled to the first region P1.

[0071] refer to Fig.24, depicting a front-side layout design of an example semiconductor device 290. The semiconductor device 290 includes a plurality of e-fuse memory cells 292A, 292B, 292C, and 292D arranged in the layout design as depicted. The e-fuse memory cells 292A-292D are identical in configuration and may be similar to any of the e-fuse memory cells 201A-201G as described above. In the depicted embodiment, the e-fuse memory cells 292A-292D are arranged in a two-by-two (2×2) layout, wherein the e-fuse memory cells 292A and 292B are adjacent to each other along a first lateral direction (e.g., X-axis) and mirrored to each other with respect to a second lateral direction (e.g., Y-axis), and the e-fuse memory cells 292C and 292D are adjacent to each other along the first lateral direction and mirrored to each other with respect to the second lateral direction. Similarly, the e-fuse memory cells 292A and 292C are adjacent to each other along the second lateral direction and mirror each other with respect to the first lateral direction, and the e-fuse memory cells 292B and 292D are adjacent to each other along the second lateral direction and mirror each other with respect to the first lateral direction. It should be noted that according to some embodiments of the present disclosure, the e-fuse memory cells 292A-292D can be arranged in any other suitable layout.

[0072] Fig.25 is a flow chart of a method 400 of forming or manufacturing a semiconductor device such as semiconductor devices 200 and 290 according to some embodiments. It should be understood that in Fig.25 Additional operations may be performed before, during, and / or after the method 400 depicted in FIG. 4. In some embodiments, the method 400 may be used to form a semiconductor device according to various layouts (designs) as disclosed herein.

[0073] In operation 410 of method 400, a layout design of a semiconductor device (eg, semiconductor device 200 having a layout corresponding to a structure of any one of e-fuse memory cells 201A-201G; see Figures 3 to 24 Operation 410 is performed by a processing device (eg, Fig.26 In one approach, the layout design is generated by placing the layout design of one or more standard cells through a user interface. In one approach, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a Graphical Database System (GDSII) file format.

[0074] In operation 420 of method 400, a semiconductor device is manufactured based on the layout design. In some embodiments, operation 420 of method 400 includes: manufacturing at least one mask based on the layout design; and manufacturing the semiconductor device based on the at least one mask. Fig.28 Method 700 discusses several exemplary manufacturing operations of operation 420 .

[0075] In some embodiments, method 400 is implemented as a standalone software application executed by a processor. In some embodiments, method 400 is implemented as a software application that is part of an additional software application. In some embodiments, method 400 is implemented as a plug-in to a software application. In some embodiments, method 400 is implemented as a software application that is part of an EDA tool. In some embodiments, method 400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer readable medium. In some embodiments, the layout design is stored using a computer program such as a computer program. In some embodiments, the layout design is generated based on a netlist, which is created based on a schematic design.

[0076] Fig.26 5 is a schematic diagram of a system 500 for designing and manufacturing IC layout designs according to some embodiments. System 500 generates or places one or more IC layout designs, as described herein. In some embodiments, system 500 manufactures one or more semiconductor devices based on one or more IC layout designs, as described herein. System 500 includes (e.g., hardware) processor 502 and non-transitory computer-readable storage medium 504 encoded with, for example, stored computer program code 506 (e.g., executable instruction group). Computer-readable storage medium 504 is configured to interface with a manufacturing machine for producing semiconductor devices. Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to I / O interface 510 via bus 508. Network interface 512 is also electrically connected to processor 502 via bus 508. Network interface 512 is connected to network 514 so that processor 502 and computer-readable storage medium 504 can be connected to external elements via network 514. The processor 502 is configured to execute computer program code 506 encoded in the computer-readable storage medium 504 so that the system 500 can be used to implement some or all of the operations described in the method 400 .

[0077] In some embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0078] In some embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 504 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0079] In some embodiments, computer readable storage medium 504 stores computer program code 506 configured to cause system 500 to implement method 400. In some embodiments, computer readable storage medium 504 also stores information required to implement method 400 and information generated during implementation of method 400, such as layout design 516, user interface 518, manufacturing unit 520, and / or executable instruction groups that implement the operations of method 400.

[0080] In some embodiments, computer readable storage medium 504 stores instructions (e.g., computer program code 506) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 506) enable processor 502 to generate manufacturing instructions readable by the manufacturing machine to effectively implement method 400 during a manufacturing process.

[0081] System 500 includes an I / O interface 510. I / O interface 510 is coupled to external circuits. In some embodiments, I / O interface 510 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor direction keys for transmitting information and commands to processor 502.

[0082] The system 500 also includes a network interface 512 coupled to the processor 502. The network interface 512 allows the system 500 to communicate with a network 514 to which one or more other computer systems are connected. The network interface 512 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-13154. In some embodiments, the method 400 is implemented in two or more systems 500, and information such as layout design, user interface, and manufacturing unit is exchanged between different systems 500 via the network 514.

[0083] The system 500 is configured to receive information related to the layout design through the I / O interface 510 or the network interface 512. The information is transmitted to the processor 502 through the bus 508 to determine the layout design for producing the IC. The layout design is then stored in the computer-readable storage medium 504 as the layout design 516. The system 500 is configured to receive information related to the user interface through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as the user interface 518. The system 500 is configured to receive information related to the manufacturing unit through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as the manufacturing unit 520. In some embodiments, the manufacturing unit 520 includes manufacturing information utilized by the system 500.

[0084] In some embodiments, method 400 is implemented by a manufacturing device to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs generated by system 500. In some embodiments, system 500 includes a manufacturing device (e.g., manufacturing tool 522) to manufacture an integrated circuit using a mask set manufactured based on one or more layout designs of the present disclosure. In some embodiments, Fig.26 The system 500 generates a layout design for an IC that is smaller than other methods. In some embodiments, Fig.26 The system 500 generates a layout design for a semiconductor device that occupies less area than other methods.

[0085] Fig. 27 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 600 and an IC manufacturing flow associated therewith, according to at least one embodiment of the present disclosure.

[0086] exist Fig. 27In the embodiment, the IC manufacturing system 600 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices (semiconductor devices) 660 (e.g., corresponding to semiconductor devices 200 or 290), such as design rooms 620, mask rooms 630 and IC manufacturers / fabrication plants ("fabs") 640. The entities in the IC manufacturing system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design room 620, mask room 630 and IC fabrication plant 640 are owned by a single company. In some embodiments, two or more of the design room 620, mask room 630 and IC fabrication plant 640 coexist in a common facility and use common resources.

[0087] The design office (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 660. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 660 to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 622 includes various IC components, such as active regions, gate structures, source / drain regions, interconnect structures, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 620 implements an appropriate design program to form the IC design layout 622. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout 622 is presented in one or more data files having information of the geometric patterns. For example, the IC design layout 622 can be represented in a GDSII file format or a DFII file format.

[0088] The mask chamber 630 includes mask data preparation 632 and mask manufacturing 634. The mask chamber 630 uses the IC design layout drawing 622 to manufacture one or more masks for manufacturing various layers of the IC device 660 according to the IC design layout 622. The mask chamber 630 implements mask data preparation 632, wherein the IC design layout 622 is converted into a representative data file ("RDF"). The mask data preparation 632 provides the RDF to the mask manufacturing 634. The mask manufacturing 634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 632 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 640. In Fig. 27 , mask data preparation 632 and mask manufacturing 634 are shown as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 634 may be collectively referred to as mask data preparation.

[0089] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 622. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0090] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that checks the IC design layout that has undergone the process in OPC with a mask creation rule set that contains certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 634, which can undo a portion of the modifications implemented by OPC to satisfy the mask creation rules.

[0091] In some embodiments, mask data preparation 632 includes a lithography process check (LPC) that simulates a process to be performed by an IC fabrication plant 640 to fabricate an IC device 660. LPC simulates the process based on IC design layout 622 to create a simulated fabricated device, such as IC device 660. Process parameters in the LPC simulation may include parameters associated with various processes of an IC fabrication cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the fabrication process. LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after a simulated fabricated device has been created by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC may be repeated to further refine the IC design layout 622.

[0092] It should be understood that the above description of mask data preparation 632 has been simplified for the purpose of clarity. In some embodiments, mask data preparation 632 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 622 during mask data preparation 632 can be performed in a variety of different orders.

[0093] After mask data preparation 632 and during mask manufacturing 634, a mask or mask set is manufactured based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or multi-electron beam mechanism is used to form a pattern on a mask (photomask or intermediate mask) based on the modified IC design layout. The mask can be formed with various techniques. In some embodiments, the mask is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. The radiation beam (such as an ultraviolet (UV) beam) used to expose the image sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque area and passes through the transparent area. In one example, the binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, the mask is formed using a phase shifting technique. In a phase shift mask (PSM), the various components in the pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 634 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0094] IC fabrication plant 640 is an IC fabrication entity that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fabrication plant 640 is a semiconductor foundry. For example, there may be a first fabrication facility for front-end fabrication of multiple IC products (e.g., source / drain regions, gate structures), while a second fabrication facility may provide mid-end fabrication of interconnects for IC products (e.g., contacts, vias, gate contacts, etc.), and a third fabrication facility may provide front-end fabrication of IC products (e.g., front-side metallization layers such as M0, M1, M2, ..., and M3). n , backside metallization layers such as BM0, BM1 ... and BM n etc., through holes such as V0, V1, V2... and V n-1 , and through holes such as BV0, BV1... and BV n-1 etc.), and the fourth manufacturing facility can provide other services for the foundry entity.

[0095] IC manufacturing plant 640 uses the mask (or multiple masks) manufactured by mask chamber 630 to manufacture IC device 660. Therefore, IC manufacturing plant 640 at least indirectly uses IC design layout 622 to manufacture IC device 660. In some embodiments, semiconductor wafer 642 is manufactured by IC manufacturing plant 640 using mask (or multiple masks) to form IC device 660. Semiconductor wafer 642 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0096] IC manufacturing system 600 is shown with design room 620, mask room 630, and IC fabrication plant 640 as separate components or entities. However, it should be understood that one or more of design room 620, mask room 630, and IC fabrication plant 640 are part of the same component or entity.

[0097] Fig.28 7 is a flow chart illustrating an exemplary method 700 for fabricating a semiconductor device according to various aspects of an embodiment of the present disclosure, the semiconductor device including the disclosed e-fuse memory cells (e.g., the e-fuse memory cells 201A-201F and 301) and a backside power rail (e.g., for providing a supply voltage V SS The method 700 may be the method 400 ( Fig.25 ) as part of operation 420. Thus, a semiconductor device can be manufactured based on at least a portion of the layout design disclosed herein.

[0098] At least some operations of method 700 may be used to form a semiconductor device with a non-planar transistor configuration. For example, the semiconductor device may include one or more FinFETs or GAA FETs. However, it should be understood that the transistors of the semiconductor device may each be configured as any of a variety of other types of transistors, such as, for example, complementary FETs (CFETs), while remaining within the scope of the disclosed embodiments. It should be noted that method 700 is merely an example and is not intended to limit the disclosed embodiments. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 700, and some other operations may only be briefly described herein. The following discussion of method 700 may involve Figures 1 to 24 One or more components of a

[0099] Briefly, the method 700 begins with operation 702 of providing a semiconductor substrate having a first portion and a second portion adjacent to the first portion. The method 700 proceeds to operation 704 of forming a first sub-transistor in the first portion and a second sub-transistor in the second portion on the front side. The method 700 proceeds to operation 706 of forming a first interconnect structure (the first interconnect structure includes a fuse resistor electrically coupled to the first sub-transistor) in the first portion and the second portion on the front side. The method 700 proceeds to operation 708 of forming a plurality of first via structures (the first via structure is coupled to at least a portion of each of the first sub-transistor and the second sub-transistor) on the back side of the semiconductor substrate. The method 700 proceeds to operation 710 of forming a second via structure coupled to the first interconnect structure and adjacent to the second sub-transistor in the second portion on the back side of the semiconductor substrate. The method 700 proceeds to operation 712 of forming a second interconnect structure coupled to the first via structure and the second via structure on the back side.

[0100] In various embodiments, first and second sub-transistors (e.g., sub-transistor t1 and sub-transistor t2, respectively) on a front side (e.g., front side 202A) of a semiconductor substrate (e.g., substrate 202) and a first interconnect structure (e.g., front side interconnect structure 300) form a plurality of disclosed e-fuse memory cells (e.g., e-fuse memory cells 201A-201G), and a second interconnect structure (e.g., back side interconnect structure 250) on a back side (e.g., back side 202B) of the semiconductor substrate includes a configuration for providing a supply voltage (V SS ) and is coupled to the power rails of the e-fuse memory cells on the front side through a plurality of via structures (eg, backside vias 240 and 244 and / or feedthrough vias 280 and 286).

[0101] Corresponding to operation 702, a semiconductor substrate (e.g., substrate 202) may include a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. The semiconductor substrate includes a first portion (e.g., a first region P1) and a second portion (e.g., a second region P2).

[0102] Corresponding to operation 704, a plurality of first sub-transistors (e.g., sub-transistors t1) and second sub-transistors (e.g., sub-transistors t2) are formed on a front side (e.g., front side 202A) of a semiconductor substrate (e.g., in the first region P1 and the second region P2) along a first direction (e.g., a first lateral direction or an X-axis). Using FinFET as an exemplary embodiment of a transistor, the transistor may be formed by at least some of the following process steps: forming a fin structure (e.g., active region 204 or 206) protruding from a semiconductor substrate; forming a dummy gate structure (not depicted herein) spanning a channel region of the fin structure; forming a gate spacer (not depicted herein) disposed along opposite sidewalls of the dummy gate structure; forming source / drain regions (e.g., source / drain regions 216 / 218 and 226 / 228) disposed on opposite sides of the dummy gate structure in the fin structure; removing the dummy gate structure; and forming an active (e.g., metal) gate structure (e.g., gate structure 220 or 224) to replace the dummy gate structure.

[0103] Corresponding to operation 706, a first interconnect structure (e.g., front-side interconnect structure 300) is formed on the front side of the semiconductor substrate over the first sub-transistor and the second sub-transistor. The first interconnect structure may include a plurality of middle-of-line (MEOL) interconnect structures (e.g., source / drain contacts 230 and 234; contact features 236 and 238; via 260; gate contact 262, etc.) and a plurality of back-end-of-line (BEOL) interconnect structures (e.g., front-side metallization layers (such as M0, M1, M2, ..., and M3). n ) and vias (such as V0, V1, V2… and V n-1 ), etc.), as described above. In the present embodiment, the front-side interconnect structure includes a fuse resistor (e.g., fuse resistor 356) electrically coupled to a first sub-transistor (e.g., sub-transistor t1) to form an electric fuse memory cell (e.g., electric fuse memory cells 201A-201G). In some embodiments, the MEOL and BEOL interconnect structures can each extend in a single direction. For example, the source / drain contacts 230 and 234 and the contact members 236 and 238 can all extend in a second lateral direction parallel to the gate structures 220, 222, and 224.

[0104] The first interconnect structure can be formed by at least some of the following steps: forming a dielectric layer over the transistor on the front side; patterning the dielectric layer to form openings corresponding to the locations of the various components of the first interconnect structure; and forming a conductive (e.g., metal) structure in the opening, thereby producing the first interconnect structure. Each of the first interconnect structures disposed on the front side may include one or more metal materials disposed in a dielectric material (e.g., an ILD layer, an IMD layer, etc.; not depicted herein), such as, for example, tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof.

[0105] Corresponding to operations 708 and 710 collectively, a plurality of via structures connected to a portion of the component formed on the front side of the semiconductor substrate are formed on the back side (e.g., back side 202B) of the semiconductor substrate, including a first via structure (e.g., back side vias 240 and 244) and a second via structure (e.g., feed-through via 280). In operation 708, the first via structure is coupled to at least a portion of each of the first sub-transistor (e.g., sub-transistor t1) and the second sub-transistor (e.g., sub-transistor t2). In operation 710, the second via structure is formed in the second portion (e.g., second region P2) and extends along a first lateral direction (e.g., X-axis). The second via structure is formed adjacent to the second sub-transistor (e.g., sub-transistor t2) along the second lateral direction (e.g., Y-axis). A third via structure (e.g., feed-through via 286) adjacent to the first sub-transistor (e.g., sub-transistor t1) may be formed in the first portion (e.g., first region P1) along the second lateral direction (e.g., Y-axis). The third via structure extends along the first lateral direction and is coupled to the second interconnect structure (eg, backside interconnect structure 250 ).

[0106] The first via structure, the second via structure, and the third via structure can be formed by at least some of the following processing steps: flipping the semiconductor substrate; optionally, thinning the semiconductor substrate from the back side down until the bottom surface of the source / drain region (e.g., source / drain regions 216 / 218 and 226 / 228) is exposed; forming a dielectric layer over the back side; patterning the dielectric layer to form openings corresponding to the locations of the backside vias and the feedthrough vias; and forming a conductive (e.g., metal) structure in the openings to produce the via structure on the back side. The resulting backside vias (e.g., backside vias 240 and 244) are each coupled to one of the source / drain regions of each transistor, and the resulting feedthrough vias (e.g., feedthrough vias 280 and 286) are each coupled to a contact feature (e.g., contact feature 236). Each of the feedthrough vias has a larger cross-sectional area than the backside vias and therefore has a lower resistance.

[0107] Corresponding to operation 712, on the back side of the semiconductor substrate, a second interconnect structure (e.g., backside interconnect structure 250) is formed. The second interconnect structure extends along the first direction and is coupled to the first via structure (e.g., backside vias 240 and 244) and the second via structure (e.g., feed-through vias 280 and 286). In the present embodiment, the second interconnect structure is used as a power rail for providing a supply voltage to the electrical fuse memory cell from the back side. The second interconnect structure is formed in a manner similar to the formation of the first interconnect structure and is connected to each of the via structures formed in operations 708 and 710. Each of the second interconnect structures disposed on the back side may include one or more metal materials, such as, for example, tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof.

[0108] In one aspect of an embodiment of the present disclosure, a memory device is disclosed. The memory device includes a substrate having a first side opposite to a second side. The memory device includes a memory cell having a transistor and a resistor operably coupled in series with each other, wherein the memory cell is arranged on the first side, and the transistor also includes a plurality of first sub-transistors arranged in a first region of the substrate. The memory device includes a plurality of second sub-transistors arranged in a second region of the substrate. The memory device also includes a first interconnect structure arranged on the second side. Each of the first sub-transistors is coupled to the first interconnect structure through a plurality of first through-hole structures. Each of the second sub-transistors is coupled to the first interconnect structure through a plurality of second through-hole structures and at least a third through-hole structure, wherein each of the first through-hole structure and the second through-hole structure has a first cross-sectional area, and the third through-hole structure has a second cross-sectional area different from the first cross-sectional area.

[0109] In another aspect of the disclosed embodiment, a memory device is disclosed. The memory device includes: a substrate, including a first region and a second region each extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction. The memory device includes a first active region formed in the first region and on the front side of the substrate, wherein the first active region extends longitudinally along the first direction. The memory device includes a first interconnect structure formed on the front side and coupled to one or more first portions of the first active region. The memory device includes a second interconnect structure formed on the back side of the substrate opposite to the front side. The memory device includes a plurality of first through-hole structures coupling one or more second portions of the first active region to the second interconnect structure. The memory device includes a second active region formed in the second region and on the first side of the substrate, wherein the second active region extends longitudinally along the first direction. The memory device includes a plurality of second through-hole structures coupling one or more portions of the second active region to the second interconnect structure. The memory device also includes at least one third through-hole structure coupling the first interconnect structure to the second interconnect structure in the second region. The first through-hole structure and the second through-hole structure each extend a first length along the first direction. The third through-hole structure extends a second length longer than the first length along the first direction.

[0110] In another aspect of the disclosed embodiment, a method for manufacturing a memory device is disclosed. The method includes providing a substrate having a first portion and a second portion adjacent to the first portion. The method includes forming a first sub-transistor in the first portion and a second sub-transistor in the second portion on the front side of the substrate and along a first direction. The method includes forming a first interconnect structure in the first portion and the second portion on the front side of the substrate, wherein the first interconnect structure includes a resistor electrically coupled to the first sub-transistor. The method includes forming a first through-hole structure electrically coupled to the source / drain region of each of the first sub-transistor and the second sub-transistor on the back side of the substrate opposite to the front side. The method includes forming a second through-hole structure extending in the first direction in the second portion on the back side of the substrate, wherein the second through-hole structure is electrically coupled to the first interconnect structure and is formed adjacent to the second sub-transistor in a second direction perpendicular to the first direction. The method includes forming a second interconnect structure extending in the first direction and electrically coupled to the first through-hole structure and the second through-hole structure on the back side of the substrate. The second interconnect structure includes a power rail configured to provide a supply voltage to the first sub-transistor.

[0111] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0112] Some embodiments of the present application provide a memory device, comprising: a substrate having a first side opposite to a second side; a memory cell comprising a transistor and a resistor coupled in series with each other, the memory cell being arranged on the first side, the transistor further comprising a plurality of first sub-transistors arranged in a first region of the substrate; a plurality of second sub-transistors arranged in a second region of the substrate; and a first interconnect structure arranged on the second side, wherein: each of the first sub-transistors is coupled to the first interconnect structure through a plurality of first through-hole structures, and each of the second sub-transistors is coupled to the first interconnect structure through a plurality of second through-hole structures and at least a third through-hole structure, each of the first through-hole structure and the second through-hole structure having a first cross-sectional area, and the third through-hole structure having a second cross-sectional area different from the first cross-sectional area.

[0113] In some embodiments, the first interconnect structure is configured to provide a supply voltage for the memory cell. In some embodiments, a conduction path is formed by applying a programming voltage on a first end of the resistor and applying a supply voltage on the first interconnect structure. In some embodiments, the conduction path extends from the first end of the resistor, at least through the resistor, the second end of the resistor, the first sub-transistor, and the second sub-transistor, and extends to the first interconnect structure. In some embodiments, the memory device also includes a second interconnect structure disposed on the first side, wherein the second interconnect structure includes a first portion coupled to the third through-hole structure and a second portion coupled to the second sub-transistor. In some embodiments, the resistor is disposed in a third portion of the second interconnect structure. In some embodiments, the first cross-sectional area is smaller than the second cross-sectional area. In some embodiments, at least a portion of the second region extends adjacent to the first region. In some embodiments, the substrate also includes a dummy region between the first region and the second region.

[0114] Some other embodiments of the present application provide a memory device, comprising: a substrate, comprising a first region and a second region, each of the first region and the second region extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction; a first active region formed in the first region and on a front side of the substrate, the first active region extending longitudinally along the first direction;

[0115] A first interconnect structure formed on the front side and coupled to one or more first portions of the first active region; a second interconnect structure formed on a back side of the substrate opposite to the front side; a plurality of first through-hole structures coupling one or more second portions of the first active region to the second interconnect structure; a second active region formed in the second region and on the first side of the substrate, the second active region extending longitudinally along the first direction; a plurality of second through-hole structures coupling one or more portions of the second active region to the second interconnect structure; and at least one third through-hole structure coupling the first interconnect structure to the second interconnect structure in the second region, wherein: each of the first through-hole structure and the second through-hole structure extends a first length along the first direction, and the third through-hole structure extends a second length along the first direction, the second length being longer than the first length.

[0116] In some embodiments, the third through-hole structure and the second active area are spaced apart along the second direction in a top view. In some embodiments, the first region extends a first height along the second direction, and the second region extends a second height along the second direction, the second height being the same as the first height. In some embodiments, the first region extends a first height along the second direction, and the second region extends a second height along the second direction, the second height being different from the first height. In some embodiments, the first active region extends a first height along the second direction, and the second active region extends a second height along the second direction, the second height being less than the first height. In some embodiments, the first active region extends a first height along the second direction, and the second active region extends a second height along the second direction, the second height being the same as the first height. In some embodiments, the memory device further comprises at least one fourth through-hole structure coupling the first interconnect structure to the second interconnect structure in the first region, wherein the third through-hole structure extends longitudinally along the first direction. In some embodiments, the first active region provides at least one transistor coupled to a fuse resistor disposed in the first interconnect structure. In some embodiments, the second active region provides a plurality of transistors commonly coupled to the one or more second portions of the first active region.

[0117] Some further embodiments of the present application provide a method for manufacturing a memory device, comprising: providing a substrate having a first portion and a second portion adjacent to the first portion; forming a first sub-transistor in the first portion and a second sub-transistor in the second portion on a front side of the substrate, wherein adjacent first sub-transistors and second sub-transistors are arranged along a first direction, respectively; forming a first interconnect structure in the first portion and the second portion on the front side of the substrate, wherein the first interconnect structure includes a fuse resistor electrically coupled to the first sub-transistor; forming a first through-hole structure coupled to at least a portion of each of the first sub-transistor and the second sub-transistor on a back side of the substrate opposite to the front side; forming a second through-hole structure extending along the first direction in the second portion on the back side of the substrate, wherein the second through-hole structure is coupled to the first interconnect structure and is formed adjacent to the second sub-transistor along a second direction perpendicular to the first direction; and forming a second interconnect structure extending along the first direction and coupled to the first through-hole structure and the second through-hole structure on the back side of the substrate, the second interconnect structure including a power rail configured to provide a supply voltage to the first sub-transistor.

[0118] In some embodiments, forming the second via structure includes forming a third via structure extending along the first direction in the first portion, and wherein the third via structure is coupled to the second interconnect structure and formed adjacent to the first sub-transistor along the second direction.

[0119] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A memory device, comprising: a substrate having a first side opposite to a second side; a memory cell including a transistor and a resistor coupled in series with each other, the memory cell being disposed on the first side, the transistor further comprising a plurality of first sub-transistors disposed in a first region of the substrate; A plurality of second sub-transistors are arranged in a second region of the substrate; as well as A first interconnect structure is disposed on the second side, wherein: Each of the first sub-transistors is coupled to the first interconnect structure through a plurality of first via structures, and Each of the second sub-transistors is coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, each of the first via structure and the second via structure having a first cross-sectional area, and the third via structure having a second cross-sectional area different from the first cross-sectional area.

2. The memory device according to claim 1, wherein: The first interconnect structure is configured to provide a supply voltage for the memory cell.

3. The memory device according to claim 1, wherein: A conductive path is formed by applying a programming voltage across a first end of the resistor and a supply voltage across the first interconnect structure.

4. The memory device according to claim 3, wherein: The conduction path extends from the first end of the resistor, through at least the resistor, the second end of the resistor, the first sub-transistor, and the second sub-transistor, and to the first interconnect structure.

5. The memory device of claim 1 , further comprising a second interconnect structure disposed on the first side, wherein: The second interconnect structure includes a first portion coupled to the third via structure and a second portion coupled to the second sub-transistor.

6. The memory device according to claim 5, wherein: The resistor is disposed in a third portion of the second interconnect structure.

7. The memory device according to claim 1, wherein: The first cross-sectional area is smaller than the second cross-sectional area.

8. The memory device according to claim 1, wherein: At least a portion of the second region extends adjacent to the first region.

9. A memory device comprising: a substrate including a first region and a second region, each of the first region and the second region extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction; a first active region formed in the first region and on the front side of the substrate, the first active region extending longitudinally along the first direction; a first interconnect structure formed on the front side and coupled to one or more first portions of the first active region; a second interconnect structure formed on a back side of the substrate opposite the front side; a plurality of first via structures coupling one or more second portions of the first active area to the second interconnect structure; a second active region formed in the second area and on the first side of the substrate, the second active region extending longitudinally along the first direction; a plurality of second via structures coupling one or more portions of the second active area to the second interconnect structure; as well as at least one third via structure coupling the first interconnect structure to the second interconnect structure in the second region, wherein: Each of the first via structure and the second via structure extends a first length along the first direction, and The third through hole structure extends along the first direction by a second length, and the second length is longer than the first length.

10. A method for manufacturing a memory device, comprising: providing a substrate having a first portion and a second portion adjacent to the first portion; forming a first sub-transistor in the first portion and a second sub-transistor in the second portion on the front side of the substrate, wherein adjacent first sub-transistors and second sub-transistors are respectively arranged along a first direction; forming a first interconnect structure in the first portion and the second portion on the front side of the substrate, wherein the first interconnect structure includes a fuse resistor electrically coupled to the first sub-transistor; forming a first via structure coupled to at least a portion of each of the first sub-transistor and the second sub-transistor on a back side of the substrate opposite the front side; forming a second via structure extending along the first direction in the second portion on the back side of the substrate, wherein the second via structure is coupled to the first interconnect structure and formed adjacent to the second sub-transistor along a second direction perpendicular to the first direction; and A second interconnect structure extending along the first direction and coupled to the first and second via structures is formed on the back side of the substrate, the second interconnect structure including a power rail configured to provide a supply voltage to the first sub-transistor.

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