Memory device and forming method thereof

Abstract

The embodiment of the invention discloses a memory device and a forming method thereof. A memory device includes a memory array including a plurality of memory cells. At least a first of the memory cells permanently assumes a first logic state based on the short circuit in a preset case. At least a second memory cell of the memory cells permanently assumes a second logic state opposite to the first logic state based on the open circuit in a predetermined case.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] Generally, there are two main types of data storage elements. The first type is a volatile memory device, in which the information stored in a particular storage element is lost the moment the memory device loses power. The second type is a non-volatile memory device, in which the information is retained even after power is removed. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a memory array comprising a plurality of memory cells; wherein at least a first memory cell among the memory cells permanently presents a first logic state based on a short circuit under a preset situation; and wherein at least a second memory cell among the memory cells permanently presents a second logic state opposite to the first logic state based on an open circuit under a preset situation.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory array comprising a plurality of one-time programmable (OTP) memory cells; wherein a first subset of the OTP memory cells is configured to permanently present a first logic state based on a short circuit; and wherein a second subset of the OTP memory cells is configured to permanently present a second logic state opposite to the first logic state based on an open circuit.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming a plurality of transistors along a main surface of a substrate; and forming a plurality of metal tracks above the plurality of transistors; wherein a first transistor of the transistors and at least a first metal track of the plurality of metal tracks together form a first memory cell, wherein the first metal track forms a short circuit coupled to the first transistor; and wherein a second transistor of the transistor and at least a third metal track and a fourth metal track of the plurality of metal tracks together form a second memory cell, wherein the third metal track and the fourth metal track form an open circuit coupled to the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device including a memory array is shown in accordance with some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 Schematic diagram of a portion of a memory array in which each memory cell is implemented as an e-fuse memory cell.

[0009] Figure 3 An example layout configured to form a primitive electrical fuse cell is shown in accordance with some embodiments.

[0010] Figure 4 An example layout configured to form a preset 0 e-fuse cell is shown in accordance with some embodiments.

[0011] Figure 5 An example layout configured to form a preset 1 electrical fuse cell is shown in accordance with some embodiments.

[0012] Figure 6 and Figure 7 According to some embodiments, Figure 3 A cross-sectional view of a semiconductor device formed by a layout.

[0013] Figure 8 , Fig. 9 and Fig.10 According to some embodiments, Figure 4 A cross-sectional view of a semiconductor device formed by a layout.

[0014] Fig.11 , Fig.12 and Fig.13 According to some embodiments, Figure 5 A cross-sectional view of a semiconductor device formed by a layout.

[0015] Fig.14 A flow chart of an example method for manufacturing a memory device including an original electrical fuse cell, a preset 0 electrical fuse cell, and a preset 1 electrical fuse cell according to some embodiments is shown.

[0016] Fig.15 According to some embodiments Figure 1 Schematic diagram of a portion of a memory array in which each memory cell is implemented as an anti-fuse memory cell.

[0017] Fig.16 An example schematic diagram of an original anti-fuse cell is shown in accordance with some embodiments.

[0018] Fig.17 An example schematic diagram of a preset 0 anti-fuse cell according to some embodiments is shown.

[0019] Fig.18An example schematic diagram of a preset 1 anti-fuse cell according to some embodiments is shown.

[0020] Fig.19 An example layout configured to form a plurality of antifuse cells is shown in accordance with some embodiments.

[0021] Fig. 20 A flow chart of an example method for fabricating a memory device including an original anti-fuse cell, a preset 0 anti-fuse cell, and a preset 1 anti-fuse cell is shown in accordance with some embodiments.

[0022] Fig.21 A flow chart of an example method for authenticating a memory device according to some embodiments is shown. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0024] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0025] One-time programmable (OTP) memory devices are among various types of non-volatile memory devices. Example implementations of OTP memory devices include metal fuses, gate oxide fuses, etc. Metal fuses use metal resistors as programming elements of corresponding OTP memory devices. Such metal fuses are sometimes referred to as efuse (electric fuse) memory devices, in which metal resistors can usually be programmed (e.g., once). The programming process usually includes burning the metal resistor from a short circuit to an open circuit. Gate oxide fuses use gate oxide (or other gate dielectric materials, such as high-k dielectric materials) as programming elements of corresponding OTP memory devices. Gate oxide fuses are sometimes referred to as anti-fuse memory devices, in which gate oxides can usually be programmed (e.g., once). The programming process usually includes breaking down the gate oxide from an open circuit to a short circuit.

[0026] OTP memory devices are often used in integrated circuits to adjust the circuits after the integrated circuits are manufactured. For example, OTP memory devices are used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is to tune analog circuits by adjusting the capacitance or resistance of analog circuits or enabling and disabling parts of the system. In yet another example, a recent trend is that a memory array including a plurality of OTP memory cells is used to verify peripheral circuits that are operably coupled to or integrated with a memory array. Such peripheral circuits include sense amplifiers that are typically configured to access (e.g., read) OTP memory cells. In the prior art, one or more OTP memory cells are preconfigured to present a specific logic state. Using the preconfigured logic state at a known position of the memory array (i.e., a known OTP memory cell), the peripheral circuit can be verified. To this end, each of these OTP memory cells is programmed to a preconfigured logic state through a series of the above-described programming processes.

[0027] As integrated circuit technology advances, more circuits can be implemented in an integrated circuit. In other words, the various device components of an integrated circuit are generally arranged in a more compact manner. The programming process of an OTP memory device (or cell) is generally associated with applying a high voltage to its programming element or conducting a high current through its programming element. Such strong (voltage / current) signals used in the programming process may inadvertently damage other device components (e.g., OTP memory cells that are not preconfigured to assume any logical state). In addition, the programming process generally consumes additional power, such as applying a given strong signal. Therefore, existing OTP memory devices are not completely satisfactory in some aspects.

[0028] The present disclosure provides various embodiments of a one-time programmable (OTP) memory device, which includes a plurality of memory cells, each of which presents a preconfigured logic state under preset conditions without any programming process. In one aspect of the present disclosure, as disclosed herein, the memory cells may each be an electric fuse memory cell. The electric fuse memory cell may be operably formed into a transistor and a fuse resistor connected in series with each other. In such an embodiment, an efuse memory cell presenting a logic 1 (hereinafter referred to as a "preset 1 electric fuse cell") may be formed based on an open circuit, and a preset memory cell presenting a logic 0 (hereinafter referred to as a "preset 0 electric fuse cell") may be formed based on a short circuit. For example, an open circuit may be formed by electrically decoupling various metal tracks of a preset 1 electric fuse cell, and a short circuit may be formed by electrically coupling various metal tracks in a preset 0 electric fuse cell. In another aspect of the present disclosure, the memory cells as disclosed herein may each be an anti-fuse memory cell. The anti-fuse memory cell may be operably formed into a programming transistor and a read resistor connected in series with each other. In such an embodiment, an anti-fuse memory cell presenting a logic 1 (hereinafter referred to as a "preset 1 anti-fuse cell") can be formed based on an open circuit, and a preset memory cell presenting a logic 0 (hereinafter referred to as a "preset 0 anti-fuse cell") can be formed based on a short circuit. For example, an open circuit can be formed based on using a programming transistor with a relatively high threshold voltage for the preset 1 anti-fuse cell, and a short circuit can be formed based on using a programming transistor with a relatively low threshold voltage for the preset 0 anti-fuse cell.

[0029] Figure 1 1 shows a block diagram of a memory device 100 according to various embodiments. Figure 1 In the illustrated embodiment, memory device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, and control logic circuit 110. Although not shown in FIG. Figure 1 , all components of the memory device 100 may be coupled to each other and to the control logic circuit 110. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in can be integrated together.For example, memory array 102 can include embedded I / O circuits (eg, 108).

[0030] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R 1 , R2 , R 3 …R M , each row extending in a first direction (eg, X direction), and a plurality of columns C 1 , C 2 , C 3 …C N , each column extends in a second direction (e.g., the Y direction). Each of the rows and columns may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through the corresponding conductive structures of the column and row. For example, each row may include one or more corresponding word lines (WL), and each column may include one or more corresponding bit lines (BL).

[0031] In some embodiments, each memory cell 103 is implemented as an electric fuse memory cell, which may include a fuse resistor and a WL transistor. The fuse resistor and the WL transistor are coupled in series with each other. In addition, the corresponding WL can be connected to the gate terminal of the WL transistor. The fuse resistor can have a first end connected to the corresponding BL and a second end connected to the first source / drain terminal of the WL transistor. The second source / drain terminal of the WL transistor can be coupled to a power supply voltage (e.g., ground). The details of the electric fuse memory cell will be referred to in detail. Figure 2 Further detailed discussion.

[0032] In some embodiments, each memory cell 103 is implemented as an anti-fuse memory cell, which may include a programming transistor and a reading transistor. The programming transistor and the reading transistor are coupled to each other in series. In addition, the corresponding programming WL may be connected to the gate terminal of the programming transistor, and the corresponding reading WL may be connected to the gate terminal of the reading transistor. The corresponding BL may be connected to the first source / drain terminal of the reading transistor, and the second source / drain terminal of the reading transistor is connected to the first source / drain terminal of the programming transistor. The second source / drain terminal of the programming transistor may be floating. Figure 3 The details of the anti-fuse memory cell are discussed in further detail.

[0033] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert a conductive structure (e.g., BL) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0034] Figure 2 Schematic diagram 200 shows a portion of a memory device 100 (eg, some memory cells 103) according to some embodiments, wherein each memory cell 103 is implemented as an e-fuse memory cell. Figure 2 In the example shown, an e-fuse memory cell 103 of the memory array 102 is shown. 00 , 103 01 , 103 02 , 103 03 , 103 10 , 103 11 , 103 12 , 103 13 , 103 20 , 103 21 , 103 22 , 103 23 , 103 30 , 103 31 , 103 32 and 103 33 , wherein the first subscript and the second subscript may represent their corresponding row and column, respectively. Although sixteen electrical fuse memory cells 103 are shown 00 Up to 103 33 , however, it should be understood that the memory array 102 may have any number of similar e-fuse memory cells while remaining within the scope of the present disclosure.

[0035] As shown, the electrical fuse memory cell 103 00 Up to 103 33 Each of the efuse memory cells 103 is composed of a fuse resistor and a WL transistor connected in series with each other, and is operably connected to one WL and one BL arranged in a corresponding row and a corresponding column, respectively. 00 As a representative example, the electric fuse memory cell 103 00 The circuit is composed of a fuse resistor 210 and a WL transistor 220 connected in series and arranged at BL 0 and WL 0 (Column C 0 and line R 0 One end of the fuse resistor 210 is connected to BL 0 , and the other end is connected to the first source / drain terminal of the WL transistor 220. The WL transistor 220 has a second source / drain terminal connected to ground and a second source / drain terminal connected to the WL 0 of the gate terminal.

[0036] In some embodiments, the WL transistor 220 may be formed along a major surface of the substrate (sometimes referred to as part of a "front end of line (FEOL) process / network"). Such a transistor may sometimes be referred to as a FEOL transistor. On the FEOL network, a number of metallization layers may be formed (sometimes referred to as part of a "back end of line (BEOL) process / network"). The fuse resistor 210 may be formed in or by the BEOL network. For example, the fuse resistor 210 may include a plurality of metal tracks disposed in one or more corresponding metallization layers. Depending on whether the electric fuse memory cell is preconfigured as a preset 0 electric fuse cell or a preset 1 electric fuse cell, some of the metal tracks are electrically coupled to each other or electrically isolated from each other. Therefore, these preset electric fuse cells may each permanently present a preconfigured logic state when formed (or manufactured). In other words, as disclosed herein, the preset electric fuse cell cannot be further programmed to present a desired logic state when manufactured, and such logic state cannot be changed.

[0037] For example, in Figure 2 In the electrical fuse memory cell 103 00 To 103 33 In the embodiment, the electrical fuse memory cell 103 21 and the electrical fuse memory cell 103 12 The first and second electric fuse memory cells 103 are pre-configured as a preset 0 electric fuse cell and a preset 1 electric fuse cell, respectively, while the other electric fuse memory cells remain as original electric fuse cells. The term original electric fuse cell as used herein may refer to an electric fuse memory cell that exhibits a short circuit (or logic 0) when manufactured and can be programmed to exhibit an open circuit (or logic 1). Unlike the original electric fuse memory cell, the electric fuse memory cell 103 21 may present a logic 0 when manufactured and cannot be programmed to a logic 1, and the e-fuse memory cell 103 12 It can present a logic 1 when manufactured, but cannot be programmed to a logic 0. The corresponding structures or configurations of the original electric fuse unit, the preset 0 electric fuse unit, and the preset 1 electric fuse unit will be respectively related to Figure 3 , Figure 4 and Figure 5 Further detailed discussion is conducted.

[0038] Despite Figure 2In the illustrative embodiment of the present invention, one preset 0 electrical fuse unit and one preset 1 electrical fuse unit are shown, but it should be understood that the array may include any number of preset 0 electrical fuse units and any number of preset 1 electrical fuse units. In addition, in some embodiments, the corresponding positions of the preset 0 electrical fuse unit and the preset 1 electrical fuse unit in the array may also be preconfigured. In the case where the positions of these preset units in the array are known, the corresponding functions of one or more peripheral circuits (e.g., sense amplifiers) operably coupled to the array may be verified. For example, the logic state of the preset unit and the position of such preset unit in the array may be preconfigured (e.g., known). If the sense amplifier operably coupled to the preset unit reads a logic state that is inconsistent with the preconfigured logic state, the sense amplifier may be determined to be faulty. In another example, assuming that both the logic state and the position of the preset unit are preconfigured, and the operably coupled sense amplifier has been determined to be operating normally, if the sense amplifier still reads an inconsistent logic state, one or more other peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be faulty.

[0039] First reference Figure 3 According to various embodiments, a method for forming a primitive electrical fuse unit (e.g. Figure 2 of 103 00 ). As described above, as disclosed herein, the original electrical fuse cell is formed by a WL transistor and a fuse resistor coupled in series, wherein the fuse resistor can be programmed to a desired logic state. In some embodiments, the WL transistor can be composed of a plurality of sub-transistors (e.g., 100 sub-transistors) that are coupled in parallel to each other; and the fuse resistor can be composed of at least one metal track disposed above the sub-transistors.

[0040] For example, according to some embodiments of the present disclosure, the original electrical fuse unit 103 00 Each sub-transistor of can have a channel structure composed of multiple nanostructures (e.g., nanosheets, nanowires, nanobridges). Although the current disclosure is intended to form the channel structure as a combination of discrete nanostructures, it should be understood that the original electrical fuse unit 103 00 The channel structure of the sub-transistor may be formed as an integral structure (eg, a semiconductor fin structure) while still being within the scope of the present disclosure.

[0041] like Figure 3As shown, layout 300 includes patterns 302 and 304, each of which is configured to form an active region (hereinafter, "active region 302" and "active region 304", respectively); and patterns 310, 315, 320, 325, 330, 335, 340, and 345, each of which is configured to form a gate structure (hereinafter, "gate structure 310", "gate structure 315", "gate structure 320", "gate structure 325", "gate structure 330", "gate structure 335", "gate structure 340", and "gate structure 345", respectively). In some embodiments, active regions 302 to 304 may each extend along a first lateral direction (e.g., X direction), and gate structures 310 to 345 may each extend along a different second lateral direction (e.g., Y direction). It should be understood that layout 300 may include any number of each active region and gate structure while remaining within the scope of the present disclosure.

[0042] In addition, Figure 3 In the exemplary embodiment of the present invention, each of the gate structures 310 to 345 passes through any one of the active regions 302 or 304. In other words, the gate structure 310 is aligned with but spaced apart from the corresponding gate structure (e.g., gate structure 315) along the Y direction; the gate structure 310 is aligned with but spaced apart from the corresponding gate structure (e.g., gate structure 325) along the Y direction; however, it should be understood that in some other embodiments, each of the gate structures 310 to 345 can extend continuously across both the active regions 302 and 304.

[0043] In some embodiments, each of the active regions 302 to 304 is formed by a stacked structure protruding from the main surface of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and separated vertically from each other. The portion of the semiconductor structure in the stacked structure covered by the gate structure is retained, while the other portion is replaced with a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of a corresponding transistor (or sub-transistor), the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of a transistor (or a sub-transistor), and the portion of the gate structure covering (e.g., spanning) the remaining portion of the semiconductor structure can be constructed as a gate structure or (terminal) of a transistor (or sub-transistor).

[0044] For example, in Figure 3, the portion of the active region 302 covered by the gate structure 310 may include a plurality of nanostructures separated vertically from each other that may be used as a channel of a first sub-transistor. The portion of the active region 302 disposed on the opposite side of the gate structure 310 is replaced with an epitaxial structure. Such an epitaxial structure may be used as a source / drain terminal of the first sub-transistor. The gate structure 310 may be used as a gate terminal of the first sub-transistor. Similarly, a second sub-transistor may be formed by the active region 302 and the gate structure 320. Therefore, it should be understood that the layout 300 may be used to manufacture a certain number of such sub-transistors. In some embodiments, such sub-transistors formed based on patterns 302 to 304 and 310 to 345 may be coupled in parallel to each other to be used together as the original electrical fuse unit 103. 00 ( Figure 2 ) of the WL transistor.

[0045] Layout 300 also includes patterns 350, 355, 360, 362, 364, 366, 368, 370, 372, 374, 376, and 378, each of which is configured to form a metal structure / track (hereinafter referred to as "metal track 350", "metal track 355", "metal track 360", "metal track 362", "metal track 364", "metal track 366", "metal track 368", "metal track 370", "metal track 372", "metal track 374", "metal track 376", and "metal track 378" respectively). In some embodiments, these metal tracks 350 to 378 are formed across multiple metallization layers disposed on a major surface of the substrate (e.g., a WL transistor or its sub-transistor is formed along the major surface). Such metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., where the M0 layer can be the layer closest to the major surface of the substrate. Each metallization layer includes a plurality of metal tracks embedded in one or more corresponding inter-layer dielectric (ILD) materials or inter-metal dielectric (IMD) materials.

[0046] In contrast to WL transistors (or sub-transistors thereof) which are generally referred to as being formed in a front-end-of-line (FEOL) network, the metallization layers are generally referred to as being formed in a back-end-of-line (BEOL) network. Although not shown for the sake of brevity, the layout 300 may include multiple patterns for forming respective middle-end-of-line (MEOL) metal structures. Such MEOL metal structures may electrically couple one or more of the FEOL components (e.g., a gate terminal, a drain terminal, a source terminal) to a corresponding one of the BEOL components (e.g., a metal track in any metallization layer). For example, the layout 300 may include patterns for forming respective MD structures, patterns for forming respective VG structures, and patterns for forming respective VD structures, each of the respective MD structures may be coupled to a source or drain terminal, each of the VG structures may couple a gate terminal to a metal track in the M0 layer, and each of the VD structures may couple the MD structure to a metal track in the M0 layer. For purposes of illustration, in Figure 6-Figure 7 Some such MEOL metal structures are shown in cross-sectional view in FIG.

[0047] Still reference Figure 3 In some embodiments, metal tracks 350 to 355 may be formed in the M0 layer and extend along a first lateral direction (e.g., X direction); metal tracks 360 to 368 may be formed in the M1 layer and extend along a second lateral direction (e.g., Y direction); and metal tracks 372 to 378 may be formed in the M2 layer and extend along the first lateral direction (e.g., X direction). Therefore, each of metal tracks 350 to 355 may sometimes be referred to as an M0 track; each of metal tracks 360 to 368 may sometimes be referred to as an M1 track; and each of metal tracks 372 to 378 may sometimes be referred to as an M2 track.

[0048] In some embodiments of the present disclosure, the M2 rails 370 to 378 may be used together as the original electrical fuse unit 103. 00 ( Figure 2) is a portion of a fuse resistor of the M2 track 370. Specifically, the M2 track 370 has a first end (e.g., a right end) coupled to one of the source / drain terminals of each sub-transistor formed below and a second end (e.g., a left end) coupled to the BL, which can be formed as one or more metal tracks spanning at least one metallization layer. In addition, at the right end (along the Y direction) of the M2 track 370, the M2 tracks 376 and 378 are spaced apart from the M2 track 370; and at the left end (along the Y direction) of the M2 track 370, the M2 tracks 372 and 374 are spaced apart from the M2 track 370. In some embodiments, the M2 tracks 384 and 388 can also be electrically coupled to the source / drain terminals of each sub-transistor formed below, and the M2 tracks 376 and 378 can also be electrically coupled to the BL. Furthermore, in some embodiments, the M2 rail 370 may be formed to have a narrower width (along the Y direction) than each of the M2 rails 372 to 378 , but the M2 rail 370 may be formed to have a longer length (along the X direction) than each of the M2 rails 372 to 378 .

[0049] Layout 300 also includes a pattern for forming via structures, each via structure being configured to electrically couple a first metal track in a lower metallization layer to a second metal track in an upper metallization layer. For example, each of M0 tracks 350 and 355 is electrically coupled to a plurality of sub-transistors formed thereunder, and is electrically coupled to a plurality of M1 tracks formed thereover through a plurality of via structures 382, ​​each of which is sometimes referred to as a V0 structure. Similarly, each of M2 tracks 372 to 378 is electrically coupled to a plurality of M1 tracks formed thereunder through a plurality of via structures 384, 386, 388, 390, 392, and 394, etc., each of which is sometimes referred to as a V1 structure.

[0050] Thus, according to some embodiments, the right end of the M2 track 370 and the M2 tracks 376 and 378 can be coupled to the underlying WL transistors through the V1 structures 390-394, the M1 tracks 366-368, the corresponding V0 structures 382, ​​and the M0 tracks 350-355; and the left end of the M2 track 370 together with the M2 tracks 372 and 374 can be coupled to the BL that can be formed in the next upper M3 layer through a plurality of via structures (not shown). In some other embodiments, the BL can be formed in any of a variety of other upper metallization layers, or on the back side of the substrate, while remaining within the scope of the present disclosure. In operation, a programming voltage can be applied to the left end of the M2 track 370 and the M2 tracks 372 and 374 through the BL. With the underlying WL transistor turned on, the metal track 370 can conduct a current flowing from the left end to the right end, which can burn out or burn out the metal track 370. After being programmed, a read voltage can similarly be applied to the left end of M2 track 370 and M2 tracks 372 and 374 through BL. With the WL transistor below conducting, metal track 370 can conduct current flowing from the left end to the right end. If metal track 370 has been blown (i.e., forming an open circuit), no such current can flow, and the original electrical fuse cell 103 00 The programmed logic state of can be determined as logic 1. If the metal track 370 is not blown (eg, remains short-circuited), such current can flow and the original electrical fuse unit 103 00 The programmed logic state can be determined as logic 0.

[0051] exist Figure 3 In the exemplary embodiment of , the left end of the M2 rail 370 is coupled to the M1 rails 360 to 364 through the V1 structures 384 to 388, but these M1 rails 360 to 364 may not be coupled to the underlying WL transistors. In other words, the V0 structure 382 is not formed between the M0 rails 350 / 355 and the M1 rails 360 / 362 / 364. The right end of the M2 rail 370 is coupled to the M1 rails 366 and 368, and these M1 rails 366-368 may be further coupled to the underlying WL transistors through at least a plurality of V0 structures 382 and the M0 rails 350-355. In addition, although in Figure 3 360 - 364 are shown decoupled from the WL transistors and two M1 rails (e.g., 366 and 368) are coupled to the WL transistors, but it should be understood that layout 300 may include any number of M1 rails (e.g., symmetrical numbers) formed on either end of M2 rail 370 while remaining within the scope of the present disclosure.

[0052] Next reference Figure 4According to various embodiments, a method for forming a preset 0 electrical fuse unit (eg Figure 2 of 103 21 ). As described above, as disclosed herein, the preset 0 electrical fuse cell is formed by a WL transistor and a fuse resistor coupled in series, wherein the fuse resistor is operably configured to be short-circuited (when manufactured), i.e., logic 0, and cannot be programmed to other logic states. In some embodiments, the WL transistor may be composed of a plurality of sub-transistors (e.g., 100 sub-transistors) coupled in parallel to each other; and the fuse resistor may be composed of at least one metal track disposed above the sub-transistors.

[0053] According to some embodiments of the present disclosure, similar to the original electrical fuse unit 103 00 Layout 300, preset 0 electrical fuse unit 103 21 Each sub-transistor of can have a channel structure composed of multiple nanostructures (e.g., nanosheets, nanowires, nanobridges). Although the current disclosure is intended to form the channel structure as a combination of discrete nanostructures, it should be understood that the preset 0 electrical fuse unit 103 21 The channel structure of the sub-transistor may be formed as an integral structure (eg, a semiconductor fin structure) while still being within the scope of the present disclosure.

[0054] In some embodiments, layout 400 has portions thereof configured to form WL transistors that are substantially similar to portions of layout 300 (e.g., active regions 302-304 and gate structures 310-345), and thus, the following description of layout 400 will focus on the differences. Figure 4 In the embodiment, the layout 400 includes patterns 402 and 404, each of which is configured to form an active region (hereinafter referred to as "active region 402" and "active region 404", respectively); and patterns 410, 415, 420, 425, 430, 435, 440 and 445, each of which is configured to form a gate structure (hereinafter referred to as "gate structure 410", "gate structure 415", "gate structure 420", "gate structure 425", "gate structure 430", "gate structure 435", "gate structure 440" and "gate structure 445", respectively). Preset 0 electrical fuse unit 103 21 Sub-transistors of the WL transistor may be formed by active regions 402 to 404 and gate structures 410 to 445 .

[0055] Layout 400 also includes patterns 450, 455, 460, 462, 464, 466, 468, 470, 472, and 474, each of which is configured to form metal structures / tracks (hereinafter referred to as "metal track 450", "metal track 455", "metal track 460", "metal track 462", "metal track 464", "metal track 466", "metal track 468", "metal track 470", "metal track 472", and "metal track 474", respectively). In some embodiments, these metal tracks 450 to 478 are formed across multiple metallization layers disposed on a major surface of a substrate (e.g., a WL transistor or its sub-transistor is formed along the major surface). Such metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., where the M0 layer may be the layer closest to the major surface of the substrate. Each metallization layer includes multiple metal tracks embedded in one or more corresponding inter-layer dielectric (ILD) materials or inter-metal dielectric (IMD) materials.

[0056] In contrast to WL transistors (or sub-transistors thereof) which are typically referred to as being formed in a front-end-of-line (FEOL) network, the metallization layers are typically referred to as being formed in a back-end-of-line (BEOL) network. Although not shown purely for the sake of brevity, the layout 400 may include multiple patterns to form respective middle-end-of-line (MEOL) metal structures. Such MEOL metal structures may electrically couple one or more of the FEOL components (e.g., a gate terminal, a drain terminal, a source terminal) to a corresponding one of the BEOL components (e.g., a metal track in any metallization layer). For example, the layout 400 may include patterns for forming respective MD structures, patterns for forming respective VG structures, and patterns for forming respective VD structures, each MD structure may be coupled to a source terminal or a drain terminal, each VG structure may couple a gate terminal to a metal track in the M0 layer, and each VD structure may couple an MD structure to a metal track in the M0 layer. For purposes of illustration, in Figure 8-Figure 10 Some such MEOL metal structures are shown in cross-sectional view in FIG.

[0057] Still reference Figure 4 In some embodiments, metal tracks 450 to 455 may be formed in the M0 layer and extend along a first lateral direction (e.g., X direction); metal tracks 460 to 468 may be formed in the M1 layer and extend along a second lateral direction (e.g., Y direction); and metal tracks 470 to 474 may be formed in the M2 layer and extend along the first lateral direction (e.g., X direction). Therefore, each of metal tracks 450 to 455 may sometimes be referred to as an M0 track; each of metal tracks 460 to 468 may sometimes be referred to as an M1 track; and each of metal tracks 470 to 474 may sometimes be referred to as an M2 track.

[0058] In some embodiments of the present disclosure, the M2 rails 470 to 474 may be used together as a preset 0 electrical fuse unit 103. 21 ( Figure 2 ) of the fuse resistor. On the side of the M2 track 470 (along the Y direction), the M2 tracks 472 and 474 are spaced apart from the M2 track 470. Each of the M2 tracks 472 and 474 may extend to the same length as the M2 track 470. 00 ), in some embodiments, metal track 470 is electrically isolated from the underlying components (e.g., the corresponding WL transistors). As shown, no via structure is formed between M2 track 470 and any underlying M1 track (e.g., 460 to 468). Instead, each of M2 tracks 472 and 474 can have its first end (e.g., the right end) electrically coupled to the source / drain terminal of each sub-transistor formed below, and the second end (e.g., the left end) of each of M2 tracks 472 and 474 is electrically coupled to the BL, which can be formed as one or more metal tracks spanning at least one metalization layer. In addition, in some embodiments, M2 track 470 can be formed to have a narrower width (along the Y direction) than each of M2 tracks 472 and 474.

[0059] Layout 400 also includes a pattern for forming via structures, each via structure being configured to electrically couple a first metal track in a lower metallization layer to a second metal track in an upper metallization layer. For example, each of M0 tracks 450 and 450 is electrically coupled to a plurality of sub-transistors formed thereunder, and is electrically coupled to a plurality of M1 tracks formed thereover through a plurality of via structures 482, each of which is sometimes referred to as a V0 structure. Similarly, each of M2 tracks 472 and 474 is electrically coupled to a plurality of M1 tracks formed thereunder through a plurality of via structures 484, 488, 490, and 494, etc., each of which is sometimes referred to as a V1 structure.

[0060] Thus, the right ends of the M2 tracks 472 and 474 can be coupled to the WL transistor below through the V1 structures 490-494, the M1 tracks 466-468, the corresponding V0 structures 482, and the M0 tracks 450-455; and the left ends of the M2 tracks 470 to 474 (or only 472 and 474) can be coupled to the BL that can be formed in the next upper M3 layer through multiple via structures (not shown). In some other embodiments, the BL can be formed in any of a variety of other upper metallization layers, or on the back side of the substrate, while remaining within the scope of the present disclosure. In operation, since the M2 tracks 472 and 474 are each formed to couple the BL to the WL transistor below, a short circuit is formed between the BL and the WL transistor. The M2 tracks 472 and 474 can sometimes be referred to as short tracks. In addition, the width of the M2 track 470 is substantially narrower than the width of each of the M2 tracks 472 and 474. Even if a voltage signal is applied to BL (which may be coupled to M2 rails 470 to 474), the wider M2 rails 472-474 cannot be programmed, ie cannot be changed from short circuit to open circuit. 21 It may present a logic 0 (equivalent to a short circuit across its fuse resistor) at the time of manufacture, and this logic 0 cannot be changed even by applying a programming voltage.

[0061] exist Figure 4 In the illustrative embodiment of , the left end of the M2 rail 470 is not coupled to any of the M1 rails 460 to 464, and these M1 rails 460 to 464 may not be coupled to the underlying WL transistors. In other words, the V0 structure 482 is not formed between the M0 rails 450 / 455 and the M1 rails 460 / 462 / 464. The right end of the M2 rail 470 is also not coupled to any of the M1 rails 466 to 468, but these M1 rails 466 to 468 may be coupled to the underlying WL transistors through at least a plurality of V0 structures 482 and the M0 rails 450-455. In addition, although in Figure 4 4 shows three M1 rails (e.g., 460-464) decoupled from the WL transistors and two M1 rails (e.g., 466 and 468) coupled to the WL transistors, but it should be understood that layout 400 may include any number of M1 rails (e.g., symmetrical numbers) formed on either end of M2 rail 470 while remaining within the scope of the present disclosure.

[0062] Then refer to Figure 5 According to various embodiments, a method for forming a preset 1 electrical fuse unit (eg Figure 2 of 103 12). As described above, as disclosed herein, the preset 1 electrical fuse cell is formed by a WL transistor and a fuse resistor coupled in series, wherein the fuse resistor is operably configured to be open (when manufactured), i.e., logic 1, and cannot be programmed to other logic states. In some embodiments, the WL transistor may be composed of a plurality of sub-transistors (e.g., 100 sub-transistors) coupled in parallel to each other; and the fuse resistor may be composed of at least one metal track disposed above the sub-transistors.

[0063] According to some embodiments of the present disclosure, similar to the original electrical fuse unit 103 00 The layout 300, preset 1 electrical fuse unit 103 12 Each sub-transistor may have a channel structure composed of multiple nanostructures (e.g., nanosheets, nanowires, nanobridges). Although the current disclosure is intended to form the channel structure as a combination of discrete nanostructures, it should be understood that the channel structure of the sub-transistor of the preset 1 electrical fuse unit 10312 can be formed as an integrated structure (e.g., a semiconductor fin structure) while still within the scope of the present disclosure.

[0064] In some embodiments, layout 500 has portions thereof configured to form a WL transistor that is substantially similar to portions of layout 300 (e.g., active regions 302-304 and gate structures 310-345), and thus, the following description of layout 500 will focus on the differences. Figure 5 , the layout 500 includes patterns 502 and 504, each of which is configured to form an active region (hereinafter referred to as "active region 502" and "active region 504", respectively); and patterns 510, 515, 520, 525, 530, 535, 540 and 545, each of which is configured to form a gate structure (hereinafter referred to as "gate structure 510", "gate structure 515", "gate structure 520", "gate structure 525", "gate structure 530", "gate structure 535", "gate structure 540" and "gate structure 545", respectively). Preset 1 electric fuse unit 1031 2 Sub-transistors of the WL transistor may be formed by active regions 502 to 504 and gate structures 510 to 545 .

[0065] Layout 500 also includes patterns 550, 555, 560, 562, 564, 566, 568, 570, 572, 574, 576, and 578, each of which is configured to form a metal structure / track (hereinafter referred to as "metal track 550", "metal track 555", "metal track 560", "metal track 562", "metal track 564", "metal track 566", "metal track 568", "metal track 570", "metal track 572", "metal track 574", "metal track 576", and "metal track 578" respectively). In some embodiments, these metal tracks 550 to 578 are formed across multiple metallization layers disposed on a major surface of the substrate (e.g., a WL transistor or its sub-transistor is formed along the major surface). Such metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., where the M0 layer may be the layer closest to the major surface of the substrate. Each metallization layer includes a plurality of metal tracks embedded in one or more corresponding inter-layer dielectric (ILD) materials or inter-metal dielectric (IMD) materials.

[0066] In contrast to WL transistors (or sub-transistors thereof) which are generally referred to as being formed in a front-end-of-line (FEOL) network, the metallization layers are generally referred to as being formed in a back-end-of-line (BEOL) network. Although not fully shown for the sake of brevity, the layout 500 may include multiple patterns to form respective middle-end-of-line (MEOL) metal structures. Such MEOL metal structures may electrically couple one or more of the FEOL components (e.g., a gate terminal, a drain terminal, a source terminal) to a corresponding one of the BEOL components (e.g., a metal track in any metallization layer). For example, the layout 500 may include patterns for forming respective MD structures, patterns for forming respective VG structures, and patterns for forming respective VD structures, each MD structure may be coupled to a source terminal or a drain terminal, each VG structure may couple a gate terminal to a metal track in the M0 layer, and each VD structure may couple an MD structure to a metal track in the M0 layer. For illustrative purposes, in Figure 11-13 Some such MEOL metal structures are shown in cross-sectional view in FIG.

[0067] Still reference Figure 5In some embodiments, metal tracks 550 to 555 may be formed in the M0 layer and extend along a first lateral direction (e.g., X direction); metal tracks 560 to 568 may be formed in the M1 layer and extend along a second lateral direction (e.g., Y direction); and metal tracks 572 to 578 may be formed in the M2 layer and extend along the first lateral direction (e.g., X direction). Therefore, each of metal tracks 550 to 555 may sometimes be referred to as an M0 track; each of metal tracks 560 to 568 may sometimes be referred to as an M1 track; and each of metal tracks 572 to 578 may sometimes be referred to as an M2 track.

[0068] In some embodiments of the present disclosure, the M2 rails 570 to 578 may be used together as the preset 1 electrical fuse unit 103. 12 ( Figure 2 ) of the fuse resistor. On the side of the right end of the M2 track 570 (along the Y direction), the M2 tracks 576 and 578 are spaced apart from the M2 track 570 and on the side of the left end of the M2 track 570, the M2 tracks 572 and 574 are spaced apart from the M2 track 570. 00 ), in some embodiments, metal track 570 is electrically isolated from underlying components (e.g., corresponding WL transistors). As shown, no via structure is formed between M2 track 570 and any underlying M1 track (e.g., 560 to 568). Instead, M2 tracks 576 and 578 can be electrically coupled to source / drain terminals of each sub-transistor formed underneath, and M2 tracks 572 and 574 can each be electrically coupled to a BL, which can be formed as one or more metal tracks spanning at least one metallization layer. In addition, in some embodiments, M2 track 570 can be formed to have a narrower width (along the Y direction) than each of M2 tracks 572-578, but M2 track 570 can be formed to have a longer length (along the X direction) than each of M2 tracks 572-778.

[0069] Layout 500 also includes a pattern for forming via structures, each of which is configured to electrically couple a first metal track in a lower metallization layer to a second metal track in an upper metallization layer. For example, each of M0 tracks 550 and 555 is electrically coupled to a plurality of sub-transistors ( Figure 5 572 to 578 are electrically coupled to a plurality of M1 tracks formed thereon through a plurality of via structures 582, each of which is sometimes referred to as a V0 structure. Similarly, each of the M2 tracks 572 to 578 is electrically coupled to a plurality of M1 tracks formed thereunder through a plurality of via structures 584, 588, 590, and 594, etc., each of which is sometimes referred to as a V1 structure.

[0070] Thus, the M2 rails 576 and 578 can be coupled to the underlying WL transistors through the V1 structures 590-594, the M1 rails 566-568, the corresponding V0 structures 582, and the M0 rails 550-555; and the M2 rails 570 to 574 (or only 572 and 574) can be coupled to the BL, which can be formed in the next upper M3 layer, through a plurality of via structures (not shown). In some other embodiments, the BL can be formed in any of a variety of other upper metallization layers, or on the back side of the substrate, while remaining within the scope of the present disclosure. In operation, each of the M2 rails 572 and 574 is formed to be coupled to the BL, and each of the M2 rails 576 and 578 is formed to be connected to the underlying WL transistor. Since each of the M2 rails 572 and 574 is electrically isolated from any of the M2 rails 576 or 578, an open circuit is formed between the BL and the WL transistor. The M2 rails 572 and 576 (or 574 and 578) may sometimes be referred to as open rails. In addition, the width of the M2 rail 570 is substantially narrower than the width of each of the M2 rails 572 to 578. Therefore, the preset 1 electrical fuse unit 103 12 It may present a logic 1 (equivalent to an open circuit across its fuse resistor) at the time of manufacture, and this logic 1 cannot be changed even by applying a programming voltage.

[0071] exist Figure 5 In the illustrative embodiment of , the left end of the M2 rail 570 is not coupled to any of the M1 rails 560 to 564, and these M1 rails 560 to 564 may not be coupled to the underlying WL transistors. In other words, the V0 structure 582 is not formed between the M0 rails 550 / 555 and the M1 rails 560 / 562 / 564. The right end of the M2 rail 570 is also not coupled to any of the M1 rails 566 to 568, but these M1 rails 566 to 568 may be coupled to the underlying WL transistors through at least a plurality of V0 structures 582 and the M0 rails 550-555. In addition, although in Figure 5 500 shows three M1 rails (e.g., 560-564) decoupled from the WL transistors and two M1 rails (e.g., 566 and 568) coupled to the WL transistors, but it should be understood that layout 500 can include any number of M1 rails (e.g., symmetrical numbers) formed on either end of M2 rail 570 while remaining within the scope of the present disclosure.

[0072] Figure 6 and Figure 7 Each shows how the Figure 3 The semiconductor device 600 is formed by the layout 300. Thus, the semiconductor device 600 may include at least one original electrical fuse unit 103. 00In some embodiments, Figure 6 The cross-sectional view is taken along the length direction of the active region 302, and Figure 7 The cross-sectional view is taken along the length direction of the M2 track 370. It should be understood that Figure 7 The cross-sectional view also includes Figure 6 The cross-sectional view of Figure 3 Some of the reference numerals will be reused in the following discussion of the semiconductor device 600 .

[0073] First reference Figure 6 , along the active region 302, a plurality of channels 610 and epitaxial structures 620 may be formed. Each of the channels 610 may be covered or wrapped by a corresponding one of the gate structures (e.g., 310, 320, 330, 340), and some of the epitaxial structures may be covered by a corresponding MD (e.g., 630). As described above, the original electrical fuse unit 103 00 At least a portion of the WL transistors of the embodiment of the present invention may be formed by the active region 302 and the gate structures 310 to 340. For example, a first subset of sub-transistors of the WL transistors are formed by the active region 302 and the gate structures 310 to 340, while a second subset of sub-transistors of the WL transistors are formed by the active region 304 and the gate structures 315, 325, 335, and 345 (in Figure 6 (not shown in the example cross-sectional view).

[0074] Furthermore, the sub-transistors may be coupled in parallel with each other. Thus, every other epitaxial structure 620 is coupled to one or more metal tracks formed thereon via a corresponding one of the MDs 630. For example, Figure 6 MD 630 is shown coupled to M0 track 350 via a plurality of VD structures 640. Figure 3 As discussed, the M0 track 350 has one (e.g., right) end coupled to the metal track, and the other (e.g., left) end isolated from the metal track. Therefore, the V0 structure 382 exists only between the right end of the M0 track 350 and the M1 tracks 366 to 368, respectively.

[0075] Next reference Figure 7 , M2 rail 370 is shown coupled to M1 rails 360 to 368 through a plurality of V1 structures 386 and 392, respectively. In other words, to form the original electrical fuse cell 103 00 , M2 track 370 (which is operable to function as at least a portion of its fuse resistor), each of the M1 tracks (e.g. Figure 3300) is coupled to the M2 rail 370 through a corresponding one of the V1 structures 386 / 392, regardless of whether the M1 rail is coupled to the underlying WL transistor. Thus, the original electrical fuse cell (or its fuse resistor, such as the M2 rail 370) is programmable.

[0076] Figure 8 , Fig. 9 and Fig.10 8 and 9 show cross-sectional views of a semiconductor device 800 according to some embodiments. Figure 4 Thus, the semiconductor device 800 may include at least one preset 0 electrical fuse unit 103. 21 In some embodiments, Figure 8 The cross-sectional view is taken along the length direction of the active region 402. Fig. 9 The cross-sectional view is taken along the length direction of the M2 track 470, and Fig.10 The cross-sectional view is taken along the length direction of the M2 track 472. It should be understood that Fig. 9 and Fig.10 Each of the cross-sectional views also includes Figure 8 The cross-sectional view of Figure 4 Some of the reference numerals will be reused in the following discussion of the semiconductor device 800 .

[0077] First reference Figure 8 , along the active region 402, a plurality of channels 810 and epitaxial structures 820 may be formed. Each of the channels 810 may be covered or wrapped by a corresponding one of the gate structures (e.g., 410, 420, 430, 440), and some of the epitaxial structures may be covered by a corresponding MD (e.g., 830). As described above, the preset 0 electrical fuse unit 103 21 At least a portion of the WL transistor of may be formed by active region 402 and gate structures 410 to 440. For example, a first subset of sub-transistors of the WL transistor is formed by active region 402 and gate structures 410 to 440, while a second subset of sub-transistors of the WL transistor is formed by active region 404 and gate structures 415, 425, 435, and 445 (in Figure 8 (not shown in the example cross-sectional view).

[0078] Furthermore, the sub-transistors may be coupled in parallel with each other. Thus, every other epitaxial structure 820 is coupled to one or more metal tracks formed thereon via a corresponding one of the MDs 830. For example, Figure 8 MD 830 is shown coupled to M0 track 450 via a plurality of VD structures 840. Figure 4As discussed, the M0 track 450 has one (eg, right) end coupled to the metal track, and the other (eg, left) end is isolated from the metal track. Therefore, the V0 structure 482 exists only between the right end of the M0 track 450 and the M1 tracks 466 to 468, respectively.

[0079] Next reference Fig. 9 , the M2 rail 470 is shown as being decoupled from any of the M1 rails 460 to 468. In other words, to form the preset 0 electrical fuse unit 103 21 , each of the M1 tracks (e.g. Figure 4 400) is decoupled from the M2 rail 470 (which is operative to function as at least a portion of its fuse resistor), regardless of whether the M1 rail is coupled to the underlying WL transistor. Thus, the preset 0 electrical fuse cell (or its fuse resistor, such as the M2 rail 470) is non-programmable. In contrast, Fig.10 As shown in the cross-sectional view of FIG. 4 , the fabricated M1 tracks are coupled to each other (eg, short-circuited) via another M2 track (eg, 472) and V1 structures 484 and 490. Therefore, by default, the fuse resistor of the preset 0 electrical fuse unit presents a logic 0 according to the short circuit.

[0080] Fig.11 , Fig.12 and Fig.13 Each shows a cross-sectional view of a semiconductor device 1100 according to some embodiments, which may be configured according to Figure 5 Thus, the semiconductor device 1100 may include at least one preset electrical fuse unit 103. 12 In some embodiments, Fig.11 The cross-sectional view is taken along the length direction of the active region 502. Fig.12 The cross-sectional view is taken along the length direction of the M2 track 570, and Fig.13 The cross-sectional view is taken along the length direction of the M2 track 572 / 576. It should be understood that Fig.12 and Fig.13 Each of the cross-sectional views also includes Fig.11 The cross-sectional view of Figure 5 Some of the reference numerals will be reused in the following discussion of the semiconductor device 1100 .

[0081] First reference Fig.11, a plurality of channels 1110 and epitaxial structures 1120 may be formed along the active region 502. Each of the channels 1110 may be covered or wrapped by a corresponding one of the gate structures (e.g., 510, 520, 530, 540), and some of the epitaxial structures may be covered by corresponding MDs (e.g., 1130). As described above, the preset 1 electrical fuse unit 103 12 At least a portion of the WL transistor of may be formed by active region 502 and gate structures 510 to 540. For example, a first subset of sub-transistors of the WL transistor is formed by active region 502 and gate structures 510 to 540, while a second subset of sub-transistors of the WL transistor is formed by active region 504 and gate structures 515, 525, 535, and 545 (in Fig.11 (not shown in the example cross-sectional view).

[0082] Furthermore, these sub-transistors can be coupled in parallel with each other. Thus, every other epitaxial structure 1120 is coupled to one or more metal tracks formed thereon through a corresponding one of the MDs 1130. For example, Fig.11 MD 1130 is shown coupled to M0 track 550 via a plurality of VD structures 1140. Figure 5 As discussed, the M0 track 550 has one (eg, right) end coupled to the metal track, and the other (eg, left) end is isolated from the metal track. Therefore, the V0 structure 582 exists only between the right end of the M0 track 550 and the M1 tracks 566 to 568, respectively.

[0083] Next reference Fig.12 , the M2 rail 570 is shown as being decoupled from any of the M1 rails 560 to 568. In other words, to form the preset 1 electrical fuse unit 103 12 , each of the M1 tracks (e.g. Figure 5 500) is decoupled from the M2 rail 570 (which is operable to function as at least a portion of its fuse resistor), regardless of whether the M1 rail is coupled to the underlying WL transistor. Thus, the preset 1 electrical fuse cell (or its fuse resistor, such as the M2 rail 570) is non-programmable. In contrast, Fig.13 As shown in the cross-sectional view of FIG. 1 , the manufactured M1 tracks are grouped into two subsets that are decoupled from each other (e.g., forming an open circuit). Specifically, a first subset of M1 tracks 560 to 564 is coupled to M2 track 572, and a second subset of M1 tracks 566 to 568 is coupled to M2 track 576, wherein M2 track 572 and M2 track 576 are physically separated and electrically isolated from each other. Therefore, in the default case, the fuse resistor of the preset 1 electrical fuse unit presents a logical 1 according to the open circuit.

[0084] Fig.141400 is a flowchart of an example method 1400 for forming a memory device including a memory array according to some embodiments. The memory array includes a plurality of original electrical fuse units, a plurality of preset 0 electrical fuse units, and a plurality of preset 1 electrical fuse units. In some embodiments, the method 1400 may be performed to respectively Figure 3 , Figure 4 and Figure 5 300, 400 and 500 shown in FIG. 5 to form a memory device, and thus, Figure 3-Figure 5 Some reference numbers (and Figure 6-Figure 13 ) may be reused in the following discussion of method 1400. It should be noted that method 1400 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 1400 may be used in the following discussion of method 1400. Fig.14 Additional operations are provided before, during, and after method 1400, and some other operations may be only briefly described herein.

[0085] According to various embodiments, method 1400 begins with operation 1402 of providing a substrate. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other basic semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0086] Method 1400 continues to operation 1404, in which, according to various embodiments, a stack comprising an alternating series of first and second nanostructures is formed. Such a stack may be formed based on one of the (active region) patterns discussed above. The stack may be formed in the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be 25% SiGe. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials have different etching characteristics (e.g., etching rates), respectively.

[0087] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next until the desired number and desired thickness of nanostructures are obtained. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) can be doped (in-situ doping) during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or germanium), depending on the type of transistor.

[0088] According to various embodiments, method 1400 continues to operation 1406, in which a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-mentioned (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and the stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, so that the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0089] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) above the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on the flattened a-Si and patterned. The hard mask can be formed by a nitride layer or an oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After forming the pseudo gate structure, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any appropriate combination of these materials) followed by directional etching (e.g., RIE).

[0090] Method 1400 proceeds to operation 1408, in which, according to various embodiments, internal spacers are formed by replacing the ends of each SiGe sacrificial nanostructure with a dielectric material. When forming a pseudo gate structure that covers certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacers are formed by filling these recesses of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbon nitride, silicon carbon nitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0091] According to various embodiments, method 1400 proceeds to operation 1410 to form a plurality of epitaxial structures. When forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form the doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and P-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0092] According to various embodiments, method 1400 proceeds to operation 1412, where the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with a corresponding active gate structure. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructure is removed while keeping the Si channel nanostructure substantially intact by applying a selective etch (e.g., hydrochloric acid (HCl)). After removing the SiGe sacrificial nanostructure, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls contacting the dielectric fin structure. Next, a plurality of active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls contacting the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). When forming the active gate structure, various WL transistors of the disclosed electric fuse memory cell can be formed, including the original electric fuse cell, the preset 0 electric fuse cell, and the preset 1 electric fuse cell.

[0093] According to various embodiments, method 1400 proceeds to operation 1414, where a plurality of front-side interconnect structures are formed. When forming the WL transistor, a plurality of intermediate-end interconnect structures (e.g., VG, VD, MD) are formed above the WL transistor. For example, a plurality of VGs may be formed to be respectively connected to the gate terminals of the WL transistor, and a plurality of MDs may be formed to be respectively connected to the source / drain terminals of the WL transistor (one or more). In addition, a plurality of back-end metal tracks (e.g., M0 tracks, M1 tracks, M2 tracks, etc.) may be formed above the intermediate-end interconnect structures.

[0094] The front-side interconnect structure is formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure may be formed by overlapping the front side of the substrate with the above-mentioned metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0095] In some embodiments, the corresponding fuse resistors of the disclosed original electrical fuse unit, preset 0 electrical fuse unit, and preset 1 electrical fuse unit can be formed by coupling or decoupling these back-end metal tracks, respectively. For example, operation 1414 can also include operation 1416 of coupling the M2 track (fuse resistor) to the M1 track, operation 1418 of decoupling the M2 track from the M1 track and forming a short track, and operation 1420 of decoupling the M2 track from the M1 track and forming an open track.

[0096] First, refer to operation 1416 (and combine Figure 3 , Figure 6 and Figure 7 ), M2 rail 370 as the original electrical fuse unit 103 00 At least a portion of the fuse resistor is coupled to the underlying M1 rails 360 to 368 through V1 structures 386 and 392. In addition, the M2 rail 370 is coupled (e.g., downwardly) to the WL transistor formed by the active regions 302 to 304 and the gate structures 310 to 345 through the M1 rails 366-368, the M0 rails 350-355, the VD 640, and the MD 630; and the M2 rail 370 is coupled (e.g., upwardly) to the BL formed thereon. In this way, the M2 rail 370 can be programmed (e.g., from short circuit to open circuit) through the BL and the activated WL transistor.

[0097] Next, refer to operation 1418 (and combine Figure 4 , Figure 8 , Fig. 9 and Fig.10 ), used as the original electrical fuse unit 103 21 The M2 rail 470 of at least a portion of the fuse resistor is decoupled from any of the underlying M1 rails 460 to 468. In addition, the M2 rails 472 and 474 are each coupled (e.g., downwardly) to the WL transistor formed by the active regions 402 to 404 and the gate structures 410 to 445 through the M1 rails 466-468, the M0 rails 450-455, the VD840 and the MD830; and each of the M2 rails 472 and 474 is coupled (e.g., upwardly) to the BL formed thereon. In this way, in the case where the M2 rail 470 is non-programmable (e.g., by not being connected to the underlying WL transistor), the M2 rails 472 and 474 are each formed as a short circuit to electrically connect the WL transistor to the BL, thereby presenting a logic 0 when manufactured.

[0098] Next, refer to operation 1420 (and combine Figure 5 , Fig.11 , Fig.12 and Fig.13 ), used as the original electrical fuse unit 103 12The M2 rail 570 of at least a portion of the fuse resistor is decoupled from any of the underlying M1 rails 560 to 568. In addition, the M2 rails 576 and 578 are each coupled (e.g., downwardly) to the WL transistor formed by the active regions 502 to 504 and the gate structures 510 to 545 through the M1 rails 566-568, the M0 rails 550-555, the VD1140, and the MD1130; and each of the M2 rails 572 and 574 is coupled (e.g., upwardly) to the BL formed thereon. In this way, in the case where the M2 rail 570 is non-programmable (e.g., by not being connected to the underlying WL transistor), the M2 rail pair 572 and 576 (and the M2 rail pair 574 and 578) are each formed as an open circuit to electrically disconnect the WL transistor from the BL, thereby presenting a logic 1 when manufactured.

[0099] Fig.15 Schematic diagram 1500 shows a portion of a memory device 100 (eg, some of the memory cells 103), wherein each memory cell 103 is implemented as an anti-fuse memory cell, according to some embodiments. Fig.15 In the example shown, an anti-fuse memory cell 103 of the memory array 102 is shown. 00 , 103 01 , 103 02 , 103 03 , 103 10 , 103 11 , 103 12 , 103 13 , 103 20 , 103 21 , 103 22 , 103 23 , 103 30 , 103 31 , 103 32 and 103 33 , wherein the first subscript and the second subscript may represent their corresponding row and column, respectively. Although sixteen anti-fuse memory cells 103 are shown 00 Up to 103 33 , however, it should be understood that the memory array 102 may have any number of similar anti-fuse memory cells while remaining within the scope of the present disclosure.

[0100] As shown, the anti-fuse memory cell 103 00 Up to 103 33 Each of the anti-fuse memory cells 103 is composed of a programming transistor and a reading transistor connected in series to each other, and is operatively connected to a programming WL, a reading WL, and a BL. The programming and reading WLs are arranged in corresponding rows, and the BLs are arranged in corresponding columns.00 As a representative example, the anti-fuse memory cell 103 00 It is composed of a programming transistor 1510 and a reading transistor 1520 connected in series and arranged at BL 0 and WLP / R 0 The cross (column C 0 and line R 0 ). The programming transistor 1510 has a first source / drain terminal that is floating and a second source / drain terminal that is connected to a first source / drain terminal of the reading transistor 1520. The reading transistor 1520 has a first source / drain terminal that is connected to the BL 0 The gate terminals of the programming transistor 1510 and the reading transistor 1520 are connected to the WLP 0 and WLR 0 .

[0101] In some embodiments, both programming transistor 1510 and read transistor 1520 may be formed along a major surface of a substrate (sometimes referred to as part of a "front end of line (FEOL) process / network"), which is sometimes referred to as a FEOL transistor. On the FEOL network, many metallization layers may be formed (sometimes referred to as part of a "back end of line (BEOL) process / network"). In some other embodiments, at least one of programming transistor 1510 and read transistor 1520 may be formed in a BEOL network, which is sometimes referred to as a BEOL transistor. Depending on whether the anti-fuse memory cell is preconfigured as a preset 0 anti-fuse cell or a preset 1 anti-fuse cell, its programming transistor and read transistor may have different threshold voltages, respectively. For example, the programming transistor of a preset 0 anti-fuse cell may have a substantially lower threshold voltage than its read transistor. Therefore, the programming transistor may be easily turned on, or remain activated most of the time (sometimes referred to as "always on"). Similarly, the programming transistor of the preset 1 anti-fuse cell can have a substantially higher threshold voltage than its reading transistor, which causes the programming transistor to rarely conduct, or remain deactivated (sometimes referred to as "always off") most of the time. Therefore, these preset anti-fuse cells can each permanently assume a pre-configured logic state when they are formed (or manufactured). In other words, as disclosed herein, the preset anti-fuse cells cannot be further programmed to assume the logic state desired at the time of manufacturing, and such logic state cannot be changed.

[0102] For example, in Fig.15 In the anti-fuse memory cell 103 00 To 103 33 In the embodiment, the anti-fuse storage memory cell 103 21 and anti-fuse memory cell 103 12The anti-fuse memory cells 103 are pre-configured as a preset 0 anti-fuse cell and a preset 1 anti-fuse cell, respectively, while the other anti-fuse memory cells remain as original anti-fuse cells. The term original anti-fuse cell as used herein may refer to an anti-fuse memory cell that exhibits an open circuit (or logic 1) as manufactured and can be programmed to exhibit a short circuit (or logic 0). Unlike the original anti-fuse memory cell, the anti-fuse memory cell 103 21 may present a logic 0 as manufactured and cannot be programmed to a logic 1, while the anti-fuse memory element 103 12 Can present a logic 1 as manufactured and cannot be programmed to a logic 0. Fig.16 , Fig.17 and Fig.18 The respective structures or configurations of the original anti-fuse cell, the preset 0 anti-fuse cell, and the preset 1 anti-fuse cell are discussed in further detail.

[0103] Despite Fig.15 In the illustrative embodiment of the present invention, one preset 0 anti-fuse unit and one preset 1 anti-fuse unit are shown, but it should be understood that the array may include any number of preset 0 anti-fuse units and any number of preset 1 anti-fuse units. In addition, in some embodiments, the corresponding positions of the preset 0 anti-fuse units and the preset 1 anti-fuse units in the array may also be pre-configured. In the case where the positions of these preset units in the array are known, the corresponding functions of one or more peripheral circuits (e.g., sense amplifiers) operably coupled to the array may be verified. For example, the logic state of the preset unit and the position of the preset unit in the array may be pre-configured (e.g., known). If the sense amplifier operably coupled to the preset unit reads a logic state that is inconsistent with the pre-configured logic state, the sense amplifier may be determined to be faulty. In another example, it is assumed that both the logic state and the position of the preset unit are pre-configured, and if the sense amplifier still reads an inconsistent logic state, and the operably coupled sense amplifier has been determined to be operating normally. If the sense amplifier still reads an inconsistent logic state, one or more other peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be faulty.

[0104] First reference Fig.16 , according to various embodiments, an original anti-fuse cell (e.g. Fig.15 of 103 00). Although each of the programming transistor 1520 and the reading transistor 1510 is implemented as an n-type metal oxide semiconductor field effect transistor (n-type MOSFET) or sometimes referred to as an NMOS transistor. However, it should be understood that each of the programming and reading transistors can be implemented as a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) while remaining within the scope of the present disclosure.

[0105] In some embodiments, the original anti-fuse unit 103 00 The programming transistor 1520 and the reading transistor 1510 may share similar threshold voltages. For example, the gate structure of the programming transistor 1520 may have a gate dielectric layer having a first thickness, and the gate structure of the reading transistor 1510 may have a gate dielectric layer having a second thickness, wherein the first thickness may be substantially similar to the second thickness. In another example, the gate structure of the programming transistor 1520 may have a gate dielectric layer having a first dielectric constant, and the gate structure of the reading transistor 1510 may have a gate dielectric layer having a second dielectric constant, wherein the first dielectric constant may be substantially similar to the second dielectric constant. In yet another example, the gate structure of the programming transistor 1520 may have a first combination of work function layers (resulting in a first flat band voltage), and the gate structure of the reading transistor 1510 may have a second combination of work function layers (resulting in a second flat band voltage), wherein the first flat band voltage may be substantially similar to the second flat band voltage.

[0106] refer to Fig.17 According to various embodiments, a preset 0 anti-fuse unit (eg Fig.15 of 103 21 ). Although each of the programming transistor 1520 and the reading transistor 1510 is implemented as an n-type metal oxide semiconductor field effect transistor (n-type MOSFET) or sometimes referred to as an NMOS transistor. However, it should be understood that each of the programming and reading transistors can be implemented as a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) while remaining within the scope of the present disclosure.

[0107] In some embodiments, the anti-fuse unit 103 is preset to 0. 21The programming transistor 1520 and the reading transistor 1510 may have different threshold voltages, respectively, wherein the programming transistor 1520 may have a threshold voltage substantially lower than that of the reading transistor 1510. For example, the gate structure of the programming transistor 1520 may have a gate dielectric layer of a first thickness, and the gate structure of the reading transistor 1510 may have a gate dielectric layer of a second thickness, wherein the first thickness may be substantially thinner than the second thickness. In another example, the gate structure of the programming transistor 1520 may have a gate dielectric layer having a first dielectric constant, and the gate structure of the reading transistor 1510 may have a gate dielectric layer having a second dielectric constant, wherein the first dielectric constant may be substantially higher than the second dielectric constant. In yet another example, the gate structure of the programming transistor 1520 may have a first combination of work function layers (resulting in a first flat band voltage), and the gate structure of the reading transistor 1510 may have a second combination of work function layers (resulting in a second flat band voltage), and the first flat band voltage may be substantially lower than the second flat band voltage.

[0108] refer to Fig.18 , showing a preset 1 anti-fuse unit (eg Fig.15 of 103 12 ). Although each of the programming transistor 1520 and the reading transistor 1510 is implemented as an n-type metal oxide semiconductor field effect transistor (n-type MOSFET) or sometimes referred to as an NMOS transistor. However, it should be understood that each of the programming and reading transistors can be implemented as a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) while remaining within the scope of the present disclosure.

[0109] In some embodiments, the anti-fuse unit 103 is preset 00 The programming transistor 1520 and the reading transistor 1510 may have different threshold voltages, respectively, wherein the programming transistor 1520 may have a threshold voltage substantially higher than that of the reading transistor 1510. For example, the gate structure of the programming transistor 1520 may have a gate dielectric layer of a first thickness, and the gate structure of the reading transistor 1510 may have a gate dielectric layer of a second thickness, wherein the first thickness may be substantially thicker than the second thickness. In another example, the gate structure of the programming transistor 1520 may have a gate dielectric layer having a first dielectric constant, and the gate structure of the reading transistor 1510 may have a gate dielectric layer having a second dielectric constant, wherein the first dielectric constant may be substantially lower than the second dielectric constant. In yet another example, the gate structure of the programming transistor 1520 may have a first combination of work function layers (resulting in a first flat band voltage), and the gate structure of the reading transistor 1510 may have a second combination of work function layers (resulting in a second flat band voltage), wherein the first flat band voltage may be substantially higher than the second flat band voltage.

[0110] In order to 00 Programming is done through the WLR 0 A sufficiently high voltage (e.g., a positive voltage corresponding to a logic high state) is provided to its gate terminal to turn on the read transistor 1510. Before, simultaneously with, or subsequently to turning on the read transistor 1510, a sufficiently high voltage (e.g., a breakdown voltage (VBD) sometimes referred to as a programming voltage) is applied to the WLP 0 , and a sufficiently low voltage (such as a positive voltage corresponding to a logic low state or a ground voltage) is applied to BL 0 When the read transistor 1510 is turned on, the low voltage (applied to BL 0 ) can be transferred to the source terminal of the programming transistor 1520. Therefore, VBD can exist simultaneously between one of the non-floating source / drain terminals (and connected to the read transistor 1510) and the gate terminal of the programming transistor 1520 to break down a portion of the gate dielectric layer of the programming transistor 1520 (e.g., the portion between its gate and the non-floating source / drain terminals).

[0111] After the gate dielectric layer (or a portion of the gate dielectric layer) is broken down, the portion of the gate dielectric layer that interconnects the gate terminal and the source / drain terminal behaves as a resistor. Specifically, before the programming process, even if the read transistor 1510 is turned on, there is no conduction path. After the programming process, when the read transistor 1510 is turned on, BL 0 and WLP 0 There is a conductive path between them (eg, through a resistor formed on the broken-down portion of the gate dielectric layer). Therefore, the original anti-fuse cell 103 00 It presents an open circuit (eg, logic 1) when manufactured, and can be programmed to have a short circuit (eg, logic 0).

[0112] In contrast, due to the preset 0 anti-fuse unit 103 21 The programming transistor 1520 has a substantially lower threshold voltage than its reading transistor 1510, so even in the WLP 2 When a low voltage signal or almost no voltage signal is applied to the programming transistor 1522, the programming transistor 1522 may also be activated. 21 This low threshold voltage forms across the WLP 2 A conduction path connected to the source / drain terminals of the read transistor 1510 is formed to the programming transistor 1520. Thus, when the read transistor 1510 is turned on, a conduction path from the WLP 2 To BL 1 Therefore, even if it is not programmed, the preset 0 anti-fuse unit 103 21Similarly, due to the preset 1 anti-fuse unit 103 12 The programming transistor 1520 has a substantially higher threshold voltage than its reading transistor 1510, so even in the WLP 1 When a high voltage signal is applied to the programming transistor 1520, the programming transistor 1520 may be hardly activated or not activated. 12 , such a high threshold voltage is equivalent to the WLP 1 The open circuit to the source / drain terminal of the read transistor 1510 connected to the programming transistor 1520. In addition, even in the WLP 1 Even if a strong programming voltage is applied to the circuit, the open circuit will hardly become a short circuit. 12 A logical 1 may be presented.

[0113] exist Fig.19 In the embodiment, a method for forming Fig.15 Example layout 1900 of multiple anti-fuse memory cells. For example, layout 1900 can form two anti-fuse memory cells arranged along the same column, for example, sharing the same BL and coupled to a corresponding WLP and a corresponding WLR. In one embodiment, both of these cells (formed by layout 1900) can be original anti-fuse cells. In another embodiment, both of these cells (formed by layout 1900) can be preset 0 anti-fuse cells. In yet another embodiment, both of these cells (formed by layout 1900) can be preset 1 anti-fuse cells. In yet another embodiment, one of the two cells (formed by layout 1900) can be an original anti-fuse cell, and the other can be a preset 1 or preset 0 anti-fuse cell.

[0114] As shown, layout 1900 includes patterns 1902, 1904, 1906, 1908, and 1910, wherein pattern 1902 is configured to form an active region (hereinafter referred to as "active region 1902"), and each of patterns 1904 to 1910 is configured to form a gate structure (hereinafter referred to as "gate structure 1904", "gate structure 1906", "gate structure 1908", and "gate structure 1910", respectively). Active region 1902 may extend along a first lateral direction (e.g., X direction), and gate structures 1904 to 1910 may each extend along a second lateral direction (e.g., Y direction). Using active region 1902 and gate structures 1904-1910, a first anti-fuse memory cell 1920 and a second anti-fuse memory cell 1930 may be formed. In some embodiments, a first anti-fuse memory cell 1920 may be formed from the active region 1902 and the gate structures 1904 - 1906 ; and a second anti-fuse memory cell 1930 may be formed from the active region 1902 and the gate structures 1908 - 1910 .

[0115] For example, the portion of the active region 1902 covered by the gate structure 1904 may include a plurality of nanostructures separated vertically from each other, which may be used as a channel of a programming transistor of the first anti-fuse memory cell 1920. The portion of the active region 1902 disposed on the opposite side of the gate structure 1904 is replaced with an epitaxial structure. Such an epitaxial structure may be used as a source / drain terminal of a programming transistor of the first anti-fuse memory cell 1920. The gate structure 1904 may be used as a gate terminal of a programming transistor of the first anti-fuse memory cell 1920. The portion of the active region 1902 covered by the gate structure 1906 may include a plurality of nanostructures separated vertically from each other, which may be used as a channel of a read transistor of the first anti-fuse memory cell 1920. The portion of the active region 1902 disposed on the opposite side of the gate structure 1906 is replaced with an epitaxial structure. Such an epitaxial structure may be used as a source / drain terminal of a read transistor of the first anti-fuse memory cell 1920. The gate structure 1906 can be used as a gate terminal of a read transistor of the first anti-fuse memory cell 1920. Similarly, the read transistor of the second anti-fuse memory cell 1930 can be formed by the active region 1902 and the gate structure 1908, and the programming transistor in the second anti-fuse memory cell 1930 can be formed by the active region 1902 and the gate structure 1910. In this way, the gate structures 1904 to 1910 can be respectively operatively used as a first programming word line (e.g., WLP 0 ), the first read word line (eg, WLR 0 ), the second read word line (eg WLR 1 ) and a second programming word line (eg, WLP 1 ),like Fig.19 shown.

[0116] Layout 1900 also includes patterns 1932, 1934, and 1936, each of which is configured to form a metal structure / track (hereinafter, "metal track 1932", "metal track 1934", and "metal track 1936", respectively). In some embodiments, these metal tracks 1932 to 1936 are formed in one of a plurality of metallization layers disposed above a major surface of the substrate (e.g., along which anti-fuse memory cells, such as 1920 and 1930, are formed). Such metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., where the M0 layer may be the layer closest to the major surface of the substrate. Each metallization layer includes a plurality of metal tracks embedded in one or more corresponding interlayer dielectric (ILD) materials or intermetal dielectric (IMD) materials.

[0117] Metal tracks 1932 to 1936 may all be formed in the M0 layer (and therefore each is referred to as an M0 track hereinafter). In some embodiments, M0 track 1932 may be operatively used as a bit line (e.g., BL 1936 ) connecting first anti-fuse memory cell 1920 to second anti-fuse memory cell 1930. 0 ). The read transistors of the first and second anti-fuse memory cells 1920 and 1930 share a via structure (formed by pattern 1938) coupled to BL 0 The M0 rail 1934 and the M0 rail 1936 can be coupled to the gate structure 1904 (WLP) through a via structure (formed by pattern 1940) and a via structure (formed by pattern 1942), respectively. 0 ) and gate structure 1910(WLP 1 ).

[0118] Fig. 20 A flowchart of an example method 2000 for forming a memory device including a memory array according to some embodiments is shown. The memory array includes a plurality of original anti-fuse cells, a plurality of preset 0 anti-fuse cells, and a plurality of preset 1 anti-fuse cells. In some embodiments, the method 2000 may be performed to Fig.19 1900 is used to form a memory device, and thus, may be reused in the following discussion of method 2000. Fig.19 Note that method 2000 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 2000 may be used in Fig. 20 Additional operations are provided before, during, and after method 2000, and some other operations may be only briefly described herein.

[0119] According to various embodiments, method 2000 starts from operation 2002, wherein a substrate is provided. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0120] Method 2000 continues to operation 2004, in which, according to various embodiments, a stack comprising an alternating series of first and second nanostructures is formed. Such a stack may be formed based on one of the (active region) patterns discussed above. The stack may be formed in the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be 25% SiGe. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials have different etching characteristics (e.g., etching rates), respectively.

[0121] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next layer until the desired number and desired thickness of nanostructures are obtained. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium and / or carbon-doped silicon (Si:C) can be doped (in-situ doping) during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants, depending on the type of transistor.

[0122] According to various embodiments, method 2000 continues to operation 2006, in which a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-mentioned (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and the stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, so that the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0123] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on the flattened a-Si and patterned. The hard mask can be formed by a nitride layer or an oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After the pseudo gate structure is formed, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any appropriate combination of these materials) followed by directional etching (e.g., RIE).

[0124] Method 2000 continues to operation 2008, where, according to various embodiments, internal spacers are formed by replacing the ends of each SiGe sacrificial nanostructure with a dielectric material. When forming a dummy gate structure that covers certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacers are formed by filling these recesses of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0125] According to various embodiments, method 2000 continues to operation 2010, in which a plurality of epitaxial structures are formed. When forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form a doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and p-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0126] According to various embodiments, method 2000 continues to operation 2012, where the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with corresponding active gate structures. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructure is removed while keeping the Si channel nanostructure substantially intact by applying selective etching (e.g., hydrochloric acid (HCl)). After removing the SiGe sacrificial nanostructure, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls that contact the dielectric fin structure. Next, multiple active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls that contact the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). When the active gate structure is formed, corresponding programming and reading transistors of the disclosed anti-fuse memory cells may be formed, the anti-fuse memory cells including the original anti-fuse cells, the preset 0 anti-fuse cells, and the preset 1 anti-fuse cells.

[0127] In some embodiments, the active gate structures of the programming transistors of the original anti-fuse unit, the preset 0 anti-fuse unit, and the preset 1 anti-fuse unit may have different compositions or other configurations, respectively, so that their programming transistors have a threshold voltage equal to, lower than, or higher than the threshold voltage of their corresponding read transistors. Some non-limiting examples of achieving different threshold voltages include different thicknesses of gate dielectric layers, different dielectric constants of gate dielectric layers, different combinations of work function metal layers, etc.

[0128] The method 2000 proceeds to operation 2014, in which a plurality of front-side interconnect structures are formed according to various embodiments. When forming the programming transistor and the read transistor, a plurality of intermediate-end interconnect structures (e.g., VG, VD, MD) are formed on the programming transistor and the read transistor. For example, a plurality of VGs may be formed to be connected to the gate terminals of the programming transistor and the read transistor, respectively, and a plurality of MDs may be formed to be connected to the source / drain terminals of the programming transistor and the read transistor, respectively. In addition, a plurality of back-end metal tracks (e.g., M0 tracks, M1 tracks, M2 tracks, etc.) may be formed on the intermediate-end interconnect structures, which may be operably configured as WLP, WLR, and BL to couple to the corresponding programming and read transistors.

[0129] The front-side interconnect structure is formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure may be formed by overlapping the front side of the substrate with the above-mentioned metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0130] Fig.21 A flowchart of an example method 2100 for verifying a memory device according to some embodiments is shown. The operations of the method 2100 may be performed to verify Figure 1 The memory device 100 includes a memory array (e.g., 102) and a plurality of peripheral circuits (e.g., 104, 106, and 108). In addition, the memory array 102 may include a plurality of preset OTP memory cells having preconfigured logic states and positions, thereby allowing the peripheral circuits to be verified. It should be noted that the method 2100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 2100 may be used in the following manner: Fig.21 Additional operations are provided before, during, and after method 2100, and some other operations may be only briefly described here.

[0131] The method 2100 begins with operation 2102, where a memory array including a plurality of OTP memory cells is provided. Using the memory array 102 as a representative example, the memory array 102 includes a plurality of OTP memory cells 103. For example, the OTP memory cells 103 can be formed to have a first logic state, and if programmable, the OTP memory cells 103 can be reverse programmed to an opposite second logic state. In one aspect of the present disclosure, the OTP memory cells 103 are each implemented as an electric fuse memory cell, for example, consisting of a fuse resistor and a WL transistor electrically connected in series with each other. In another aspect of the present disclosure, each of the OTP memory cells 103 is implemented as an anti-fuse memory cell, for example, consisting of at least a programming transistor and a reading transistor electrically connected in series with each other.

[0132] The method 2100 proceeds to operation 2104, where a first position of a first OTP memory cell in the memory array is identified. In some embodiments, the first OTP memory cell is configured to permanently assume a first logic state based on a short circuit. The first position of the first OTP memory cell may be selected by a user of the memory device. Continuing with the above example, such a first OTP memory cell may be a preset 0 electrical fuse cell, e.g. Figure 2 of 103 21 , or preset 0 anti-fuse unit, for example, Fig.15 of 103 21 . By default, the preset 0 electrical fuse cell can present a logic 0 through one or more short-circuit tracks as described above, and if the preset 0 electrical fuse cell is formed to present a logic 0, such logic 0 cannot be changed. By default, the preset 0 anti-fuse cell can present a logic 0 through a programming transistor with a low threshold voltage as described above, and if the preset 0 anti-fuse cell is formed to present a logic 0, such logic 0 cannot be changed.

[0133] The method 2100 proceeds to operation 2106, where a second location of a second OTP memory cell in the memory array is identified. In some embodiments, the second OTP memory cell is configured to permanently assume a second logic state based on an open circuit. Similarly, the second location of the second OTP memory cell can be selected by a user of the memory device. Continuing with the above example, such a second OTP memory cell can be a preset 1 electrical fuse cell, such as Figure 2 of 103 12 , or preset 1 anti-fuse unit, for example, Fig.15 of 103 12. By default, the preset 1 electric fuse cell can present a logic 1 through one or more open-circuit tracks as described above, and if the preset 1 electric fuse cell is formed to present a logic 1, such logic 1 cannot be changed. By default, the preset 1 anti-fuse cell can present a logic 1 through a programming transistor with a high threshold voltage as described above, and if the preset 1 anti-fuse cell is formed to present a logic 1, such logic 1 cannot be changed.

[0134] The method 2100 proceeds to operation 2108, in which the functionality of the peripheral circuit operably coupled to the memory array is verified based on at least one of the first logic state at the first position or the second logic state at the second position. In some embodiments, the first and second positions of the first and second OTP memory cells may be preconfigured. In addition, the respective numbers of the first and second OTP memory cells may also be preconfigured. Based on their positions in the memory array and their respective preset logic states, the respective functionality of one or more peripheral circuits operably coupled to the memory array (e.g., sense amplifiers of I / O circuits) may be verified. For example, the logic state of the preset cell and the position of such preset cell in the array may be preconfigured (e.g., known). If the sense amplifier operably coupled to the preset cell reads a logic state that is inconsistent with the preconfigured logic state, the sense amplifier may be determined to be faulty. In another example, assuming that both the logic state and the position of the preset cell are preconfigured, and the operably coupled sense amplifier has been determined to be operating normally, if the sense amplifier still reads an inconsistent logic state, one or more other peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be faulty.

[0135] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, and the memory array includes a plurality of memory cells. At least a first memory cell among the memory cells permanently presents a first logic state based on a short circuit under a preset condition. At least a second memory cell among the memory cells permanently presents a second logic state opposite to the first logic state based on an open circuit under a preset condition.

[0136] In some embodiments, each of the memory cells comprises an electrical fuse memory cell.

[0137] In some embodiments, the first memory cell includes a transistor formed along a major surface of the substrate.

[0138] In some embodiments, the first memory cell further includes: a first metal track disposed above the main surface and extending along a first lateral direction; a second metal track disposed above the main surface, extending along the first lateral direction, and spaced apart from the first metal track along a second lateral direction perpendicular to the first lateral direction; a third metal track disposed above the first metal track and the second metal track and extending along the second lateral direction; a fourth metal track disposed above the first metal track and the second metal track and extending along the second lateral direction; and a fifth metal track disposed above the first metal track and the second metal track, extending along the second lateral direction, and between the third metal track and the fourth metal track; wherein the third metal track and the fourth metal track each electrically couple the first metal track to the second metal track to form a short circuit; and wherein the fifth metal track is electrically isolated from each of the first metal track and the second metal track.

[0139] In some embodiments, the third metal track and the fourth metal track each have a first width along the first lateral direction, and the fifth metal track has a second width along the first lateral direction, and wherein the first width is greater than the second width.

[0140] In some embodiments, the second memory cell includes a transistor formed along a major surface of the substrate.

[0141] In some embodiments, the second memory cell further includes: a first metal track disposed above the main surface and extending along a first lateral direction; a second metal track disposed above the main surface, extending along the first lateral direction, and spaced apart from the first metal track along a second lateral direction perpendicular to the first lateral direction; a third metal track disposed above the first metal track and extending along the second lateral direction; a fourth metal track disposed above the second metal track and extending along the second lateral direction; a fifth metal track disposed above the first metal track, extending along the second lateral direction, and spaced apart from the third metal track along the first lateral direction; and a sixth metal track disposed above the second metal track and extending along the second lateral direction. direction and is spaced from the fourth metal track along the first lateral direction; and a seventh metal track is disposed above the first metal track and the second metal track, extends along the second lateral direction, and is interposed between the third metal track and the fifth metal track and between the fourth metal track and the sixth metal track; wherein the third metal track and the fifth metal track are each electrically coupled to the first metal track, and the fourth metal track and the sixth metal track are each electrically coupled to the second metal track, but the third metal track is electrically isolated from the fourth metal track, and the fifth metal track is electrically isolated from the sixth metal track, thereby forming an open circuit; and wherein the seventh metal track is electrically isolated from each of the first metal track and the second metal track.

[0142] In some embodiments, the third through sixth metal tracks each have a first width along the first lateral direction, and the seventh metal track has a second width along the first lateral direction, and wherein the first width is greater than the second width.

[0143] In some embodiments, the memory cells each comprise an anti-fuse memory cell.

[0144] In some embodiments, the first memory cell includes a read transistor and a program transistor connected in series to each other, wherein the read transistor has a first threshold voltage and the program transistor has a second threshold voltage, and wherein the second threshold voltage is lower than the first threshold voltage to form a short circuit.

[0145] In some embodiments, the second memory cell includes a read transistor and a program transistor connected in series to each other, wherein the read transistor has a first threshold voltage and the program transistor has a second threshold voltage, and wherein the second threshold voltage is higher than the first threshold voltage to form an open circuit.

[0146] In some embodiments, corresponding locations of the first memory cell and the second memory cell in the memory array are preconfigured.

[0147] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, the memory array including a plurality of one-time programmable (OTP) memory cells. A first subset of the OTP memory cells is configured to permanently present a first logic state based on a short circuit. A second subset of the OTP memory cells is configured to permanently present a second logic state opposite to the first logic state based on an open circuit.

[0148] In some embodiments, a first subset of OTP memory cells each includes: a transistor coupled as a short circuit; a first metal track disposed above the transistor and extending along a first lateral direction; a second metal track disposed above the transistor, extending along the first lateral direction, and spaced apart from the first metal track along a second lateral direction perpendicular to the first lateral direction; a third metal track disposed above the first metal track and the second metal track and extending along the second lateral direction; a fourth metal track disposed above the first metal track and the second metal track and extending along the second lateral direction; and a fifth metal track disposed above the first metal track and the second metal track, extending along the second lateral direction, and between the third metal track and the fourth metal track; wherein the third metal track and the fourth metal track each electrically couple the first metal track to the second metal track to form a short circuit; and wherein the fifth metal track is electrically isolated from each of the first metal track and the second metal track.

[0149] In some embodiments, the third metal track and the fourth metal track each have a first width along the first lateral direction, and the fifth metal track has a second width along the first lateral direction, and wherein the first width is greater than the second width.

[0150] In some embodiments, the second subset of OTP memory cells each includes: a transistor coupled to be open; a first metal track disposed above the main surface and extending along a first lateral direction; a second metal track disposed above the main surface, extending along the first lateral direction, and spaced apart from the first metal track along a second lateral direction perpendicular to the first lateral direction; a third metal track disposed above the first metal track and extending along the second lateral direction; a fourth metal track disposed above the second metal track and extending along the second lateral direction; a fifth metal track disposed above the first metal track, extending along the second lateral direction, and spaced apart from the third metal track along the first lateral direction; a sixth metal track disposed on the second metal track; The invention relates to a first metal track and a second metal track, wherein the first metal track and the second metal track are arranged above the first metal track and extend in the second lateral direction and are spaced apart from the fourth metal track in the first lateral direction; and a seventh metal track is arranged above the first metal track and the second metal track, extends in the second lateral direction, and is between the third metal track and the fifth metal track and between the fourth metal track and the sixth metal track; wherein the third metal track and the fifth metal track are each electrically coupled to the first metal track, and the fourth metal track and the sixth metal track are respectively electrically coupled to the second metal track, but the third metal track is electrically isolated from the fourth metal track, and the fifth metal track is electrically isolated from the sixth metal track, thereby forming an open circuit; and wherein the seventh metal track is electrically isolated from each of the first metal track and the second metal track.

[0151] In some embodiments, the third through sixth metal tracks each have a first width along the first lateral direction, and the seventh metal track has a second width along the first lateral direction, and wherein the first width is greater than the second width.

[0152] In some embodiments, corresponding locations of the first subset of memory cells and the second subset of memory cells and corresponding numbers of the first subset of memory cells and the second subset of memory cells in the memory array are preconfigured.

[0153] In another aspect of the present disclosure, a method is disclosed. The method includes forming a plurality of transistors along a major surface of a substrate. The method includes forming a plurality of metal tracks above the plurality of transistors. A first transistor of the transistors forms a first memory cell together with at least a first metal track of the plurality of metal tracks, wherein the first metal track forms a short circuit coupled to the first transistor. A second transistor of the transistor forms a second memory cell together with at least a third metal track and a fourth metal track of the plurality of metal tracks, wherein the third metal track and the fourth metal track form an open circuit coupled to the second transistor.

[0154] In some embodiments, the first memory cell permanently assumes a first logic state based on a short circuit under a preset condition, and the second memory cell permanently assumes a second logic state based on an open circuit under a preset condition.

[0155] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0156] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cells; wherein at least a first memory cell among the memory cells permanently presents a first logic state due to a short circuit under a preset condition; and Wherein, at least a second memory cell among the memory cells permanently presents a second logic state opposite to the first logic state based on an open circuit under a preset condition.

2. The memory device according to claim 1, wherein: Each of the memory cells comprises an electrical fuse memory cell.

3. The memory device according to claim 2, wherein: The first memory cell includes a transistor formed along a major surface of a substrate.

4. The memory device according to claim 3, wherein: The first memory unit further comprises: a first metal track disposed above the major surface and extending in a first lateral direction; a second metal track disposed above the major surface, extending along the first transverse direction, and spaced apart from the first metal track along a second transverse direction perpendicular to the first transverse direction; a third metal track disposed above the first metal track and the second metal track and extending along the second transverse direction; a fourth metal track disposed above the first metal track and the second metal track and extending along the second transverse direction; and a fifth metal track, disposed above the first metal track and the second metal track, extending along the second transverse direction, and between the third metal track and the fourth metal track; wherein the third metal track and the fourth metal track each electrically couple the first metal track to the second metal track to form the short circuit; and Wherein, the fifth metal track is electrically isolated from each of the first metal track and the second metal track.

5. The memory device according to claim 4, wherein: The third metal track and the fourth metal track each have a first width along the first lateral direction, and the fifth metal track has a second width along the first lateral direction, and wherein the first width is greater than the second width.

6. The memory device according to claim 2, wherein: The second memory cell includes a transistor formed along a major surface of a substrate.

7. The memory device according to claim 6, wherein: The second memory unit further comprises: a first metal track disposed above the major surface and extending in a first lateral direction; a second metal track disposed above the major surface, extending along the first transverse direction, and spaced apart from the first metal track along a second transverse direction perpendicular to the first transverse direction; a third metal track, disposed above the first metal track and extending along the second transverse direction; a fourth metal track, disposed above the second metal track and extending along the second transverse direction; a fifth metal track disposed above the first metal track, extending along the second transverse direction, and spaced apart from the third metal track along the first transverse direction; a sixth metal track disposed above the second metal track, extending along the second lateral direction, and spaced apart from the fourth metal track along the first lateral direction; and a seventh metal track, disposed above the first metal track and the second metal track, extending along the second transverse direction, and between the third metal track and the fifth metal track and between the fourth metal track and the sixth metal track; wherein the third metal track and the fifth metal track are each electrically coupled to the first metal track, and the fourth metal track and the sixth metal track are each electrically coupled to the second metal track, but the third metal track is electrically isolated from the fourth metal track, and the fifth metal track is electrically isolated from the sixth metal track, thereby forming an open circuit; and Wherein, the seventh metal track is electrically isolated from each of the first metal track and the second metal track.

8. A memory device comprising: a memory array comprising a plurality of one-time programmable memory cells; wherein the first subset of the one-time programmable memory cells is configured to permanently assume a first logic state based on a short circuit; and The second subset of the one-time programmable memory cells is configured to permanently present a second logic state opposite to the first logic state based on an open circuit.

9. The memory device according to claim 8, wherein: The first subset of the one-time programmable memory cells each comprises: a transistor coupled to the short circuit; a first metal track disposed above the transistor and extending along a first lateral direction; a second metal track disposed above the transistor, extending along the first lateral direction, and spaced apart from the first metal track along a second lateral direction perpendicular to the first lateral direction; a third metal track disposed above the first metal track and the second metal track and extending along the second transverse direction; a fourth metal track disposed above the first metal track and the second metal track and extending along the second transverse direction; and a fifth metal track, disposed above the first metal track and the second metal track, extending along the second transverse direction, and between the third metal track and the fourth metal track; wherein the third metal track and the fourth metal track each electrically couple the first metal track to the second metal track to form the short circuit; and Wherein, the fifth metal track is electrically isolated from each of the first metal track and the second metal track.

10. A method of forming a memory device, comprising: forming a plurality of transistors along a major surface of the substrate; as well as forming a plurality of metal tracks over the plurality of transistors; wherein a first transistor of the transistors together with at least a first metal track of the plurality of metal tracks forms a first memory cell, wherein the first metal track forms a short circuit coupled to the first transistor; and Wherein a second transistor of the transistors forms a second memory cell together with at least a third metal track and a fourth metal track of the plurality of metal tracks, wherein the third metal track and the fourth metal track form an open circuit coupled to the second transistor.

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