Display panel, manufacturing method and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device, and belongs to the technical field of display. The display panel comprises a substrate base plate; a transistor device layer; the at least one metal layer is arranged on the side, away from the substrate, of the transistor device layer and comprises a plurality of metal wires extending in the first direction; the first insulating layer is arranged on the surface of one side, far away from the substrate, of the at least one metal layer; the first electrode layer is arranged on the surface of the side, away from the substrate, of the first insulating layer, and the first electrode layer comprises a plurality of first electrode blocks; a pixel defining layer including a plurality of first defining dams extending in a first direction and a plurality of second defining dams extending in a second direction; wherein the orthographic projection of the metal wire on the substrate is located in the orthographic projection of the first limiting dam on the substrate; the thickness of at least one metal layer in the at least one metal layer is greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 [mu] m greater than that of the first insulating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] The production methods of organic functional thin film layers of organic light-emitting diodes (OLEDs) are divided into vacuum thermal deposition and solution-casting method. The solution-casting method is further divided into spin coating, ink-jet printing, screen printing and other methods.

[0003] The inkjet printing method uses a solvent to melt the OLED organic material, and then prints the material directly on the surface of the substrate to form a light-emitting functional layer. However, due to the constraints of the printing technology itself, the formed light-emitting functional layer will affect the film quality due to the coffee ring effect and cause uneven light emission.

[0004] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a display panel and a manufacturing method thereof, and a display device to improve the coffee ring effect.

[0006] In order to achieve the above-mentioned invention object, the present disclosure adopts the following technical solutions:

[0007] According to a first aspect of the present disclosure, there is provided a display panel, comprising:

[0008] substrate substrate;

[0009] A transistor device layer is provided on one side of the base substrate;

[0010] At least one metal layer, disposed on a side of the transistor device layer away from the substrate, comprising a plurality of metal traces extending along a first direction;

[0011] A first insulating layer is provided on a surface of the at least one metal layer away from the base substrate;

[0012] A first electrode layer is provided on a surface of the first insulating layer away from the base substrate, and the first electrode layer includes a plurality of first electrode blocks;

[0013] a pixel definition layer, comprising a plurality of first defining dams extending along the first direction and a plurality of second defining dams extending along the second direction, wherein the plurality of first defining dams and the plurality of second defining dams intersect each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks;

[0014] Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate;

[0015] At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

[0016] In an exemplary embodiment of the present disclosure, the metal routing has a first surface close to the substrate substrate and a second surface away from the substrate substrate, and a side wall connecting the first surface and the second surface, a first angle is formed between the side wall of the metal routing and the first surface of the metal routing, and the first angle of at least some of the multiple metal routings is 70°-90°.

[0017] In an exemplary embodiment of the present disclosure, the at least one metal layer comprises:

[0018] A first metal layer is provided on a side of the transistor device layer away from the substrate, and the plurality of metal traces are distributed in the first metal layer;

[0019] The first angle of the metal traces distributed in the first metal layer is 70°-90°.

[0020] In an exemplary embodiment of the present disclosure, the at least one metal layer comprises:

[0021] A first metal layer is provided on a side of the transistor device layer away from the substrate, and at least part of the plurality of metal traces are distributed in the first metal layer;

[0022] A second metal layer is provided on a side of the first metal layer away from the substrate, and at least part of the plurality of metal traces are distributed in the second metal layer;

[0023] The first angle of the metal routing lines distributed in the first metal layer is 70°-90° and / or the first angle of the metal routing lines distributed in the second metal layer is 70°-90°.

[0024] In an exemplary embodiment of the present disclosure, an orthographic projection of the metal traces distributed in the first metal layer on the substrate does not overlap with an orthographic projection of the metal traces distributed in the second metal layer on the substrate.

[0025] In an exemplary embodiment of the present disclosure, the thickness of at least one metal layer among the at least one metal layer is not less than 0.7 μm.

[0026] In an exemplary embodiment of the present disclosure, the single metal layer in the at least one metal layer comprises a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate;

[0027] The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

[0028] In an exemplary embodiment of the present disclosure, the single metal layer in the at least one metal layer further includes a third sub-metal layer, and the third sub-metal layer is disposed on a side of the first sub-metal layer close to the base substrate;

[0029] The thickness of the first sub-metal layer is greater than the thickness of the third sub-metal layer.

[0030] In an exemplary embodiment of the present disclosure, the thickness of the first insulating layer is not greater than 0.2 μm.

[0031] In an exemplary embodiment of the present disclosure, the plurality of metal traces include a target metal trace, and the shortest distance between an edge of an orthographic projection of the target metal trace on the substrate and an edge of an orthographic projection of a corresponding first defining dam on the substrate is no greater than 2 μm;

[0032] The first angle of the target metal wiring is 70°-90°, and the thickness of the target metal wiring is not less than 0.7 μm.

[0033] In an exemplary embodiment of the present disclosure, the substrate includes a display area and a virtual area located at the periphery of the display area;

[0034] The plurality of first electrode blocks include a plurality of normal electrodes located in the display area and a plurality of virtual electrodes located in the virtual area, the normal electrodes are electrically connected to the transistor device layer, and the virtual electrodes are electrically insulated from the transistor device layer;

[0035] The orthographic projection of the metal traces distributed in the second metal layer on the substrate is located in the virtual area.

[0036] In an exemplary embodiment of the present disclosure, no organic material layer is included between the at least one metal layer and the first electrode layer.

[0037] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0038] A light-emitting functional layer is provided on a side of the first electrode layer away from the base substrate, and at least a part of the light-emitting functional layer is located in the pixel opening;

[0039] A second electrode layer is provided on a surface of the pixel definition layer and the light-emitting functional layer which is away from the base substrate;

[0040] The second electrode layer is connected to the metal layer closest to the second electrode layer among the at least one metal layer through a first via hole in the second defining dam.

[0041] In an exemplary embodiment of the present disclosure, the metal layer closest to the second electrode layer among the at least one metal layer is a third metal layer;

[0042] The metal wiring distributed in the third metal layer has a connection block, and the connection block is located at the intersection of the first limiting dam and the second limiting dam;

[0043] The size of the connecting block in the second direction is larger than the size of other areas of the metal wiring in the second direction;

[0044] The orthographic projection of the connection block on the base substrate is located within the orthographic projection of the first via hole on the base substrate.

[0045] In an exemplary embodiment of the present disclosure, the thickness of the third metal layer is not less than 0.7 μm.

[0046] In an exemplary embodiment of the present disclosure, the third metal layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate substrate;

[0047] The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

[0048] In an exemplary embodiment of the present disclosure, the hardness of the first sub-metal layer is less than the hardness of the second sub-metal layer.

[0049] In an exemplary embodiment of the present disclosure, the number of metal layers in the at least one metal layer is multiple layers, wherein the metal layer located on the side of the third metal layer close to the base substrate and closest to the third metal layer is the fourth metal layer;

[0050] The metal routing lines distributed in the third metal layer are connected to the metal routing lines distributed in the fourth metal layer through via holes.

[0051] In an exemplary embodiment of the present disclosure, the display panel includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the red sub-pixel, the green sub-pixel and the blue sub-pixel are arranged in sequence along the first direction;

[0052] The connection block is located between the red sub-pixel and the green sub-pixel, or between the blue sub-pixel and the green sub-pixel.

[0053] In an exemplary embodiment of the present disclosure, the size of the second limiting dam located between the red sub-pixel and the green sub-pixel, and the size of the second limiting dam located between the blue sub-pixel and the green sub-pixel in the first direction are both larger than the size of the second limiting dam located between the red sub-pixel and the blue sub-pixel in the first direction.

[0054] In an exemplary embodiment of the present disclosure, the plurality of first defining dams include a plurality of first sub-defining dams and a plurality of second sub-defining dams, the first sub-defining dams and the second sub-defining dams both extend along a first direction, the second sub-defining dams are located on one side of the first sub-defining dams along a second direction, the first sub-defining dams and the second sub-defining dams both have a bottom end close to the substrate and a top end away from the substrate, and a distance between the bottom end and the top end of the first sub-defining dams is smaller than a distance between the bottom end and the top end of the second sub-defining dams;

[0055] The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the second sub-definition dam on the substrate.

[0056] According to a second aspect of the present disclosure, a method for manufacturing a display panel is provided, comprising:

[0057] providing a substrate base plate;

[0058] forming a transistor device layer on one side of the base substrate;

[0059] Forming at least one metal layer on a side of the transistor device layer away from the substrate, wherein the at least one metal layer includes a plurality of metal traces extending along a first direction;

[0060] Forming a first insulating layer on a surface of the at least one metal layer away from the base substrate;

[0061] forming a first electrode layer on a surface of the first insulating layer away from the base substrate, wherein the first electrode layer comprises a plurality of first electrode blocks;

[0062] forming a pixel definition layer, the pixel definition layer comprising a plurality of first definition dams extending along the first direction and a plurality of second definition dams extending along the second direction, the plurality of first definition dams and the plurality of second definition dams intersecting each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks;

[0063] Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate;

[0064] At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

[0065] According to a third aspect of the present disclosure, a display device is provided, comprising the display panel as described in the first aspect.

[0066] The display panel provided by the present disclosure includes a substrate, a transistor device layer, at least one metal layer, a first insulating layer, a first electrode layer and a pixel definition layer, wherein at least one metal layer includes a plurality of metal traces extending along a first direction, the pixel definition layer includes a first limiting dam extending along the first direction, the orthographic projection of the metal traces on the substrate is located within the orthographic projection of the first limiting dam on the substrate, and the thickness of at least one metal layer in the at least one metal layer is at least 0.5 μm greater than the thickness of the first insulating layer. In this way, the thicker metal traces help to form a larger slope angle, and with the thinner first insulating layer, the first limiting dam can also form a larger slope angle, thereby helping to slow down the ink climbing phenomenon, improve the coffee ring effect, and enhance the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0068] Figure 1 It is a schematic diagram of light intensity distribution of a display panel in the related art;

[0069] Figure 2 is a schematic diagram of a planar structure of a display panel in an exemplary embodiment of the present disclosure;

[0070] Figure 3 is an example layout of the first metal layer of the display panel in the exemplary embodiment of the present disclosure;

[0071] Figure 4 is an example layout of a pixel definition layer of a display panel in an exemplary embodiment of the present disclosure;

[0072] Figure 5yes Figure 2 Cross-section in the AA direction;

[0073] Figure 6 yes Figure 2 Cross-section in the BB direction;

[0074] Figure 7 is an example layout of the second metal layer of the display panel in the exemplary embodiment of the present disclosure;

[0075] Figure 8 This is an example layout of the superposition of the first metal layer and the second metal layer of the display panel in the exemplary embodiment of the present disclosure;

[0076] Fig. 9 is a schematic cross-sectional view of a first metal layer and a second metal layer of a display panel in an exemplary embodiment of the present disclosure;

[0077] Fig.10 is a schematic cross-sectional view of a first metal layer and a second metal layer of a display panel in another exemplary embodiment of the present disclosure;

[0078] Fig.11 is a schematic diagram of a planar structure of a display panel in another exemplary embodiment of the present disclosure;

[0079] Fig.12 yes Fig.11 Cross-section in CC direction;

[0080] Fig.13 is a schematic diagram of a planar structure of a display panel in another exemplary embodiment of the present disclosure;

[0081] Fig.14 yes Fig.13 Cross-section in the EE direction;

[0082] Fig.15 is a schematic diagram of light intensity distribution of a display panel in an exemplary embodiment of the present disclosure;

[0083] Fig.16 Schematic diagram of a single metal layer structure in an exemplary embodiment of the present disclosure.

[0084] The main components in the figure are described as follows:

[0085] 1-substrate; 2-pixel definition layer; 3-hole injection layer; 100-substrate substrate; 110-display area; 111-virtual area; 120-peripheral area; 01-metal routing; 011-connection block; 02-connection routing; 200-transistor device layer; 201-active layer; 202-first gate insulation layer; 203-first gate metal layer; 204-interlayer dielectric layer; 205-source and drain layer; 300-planarization layer; 401-first metal layer; 402-second metal layer; 403-third metal layer; 404-third Four metal layers; 405-first insulating layer; 406-second insulating layer; 01a-first sub-metal layer; 01b-second sub-metal layer; 01c-third sub-metal layer; 501-first electrode layer; 5011-normal electrode; 5012-virtual electrode; 502-light-emitting functional layer; 503-second electrode layer; 600-pixel definition layer; 601-first defining dam; 6011-first sub-defining dam; 6012-second sub-defining dam; 602-second defining dam; 6021-first via hole; 603-pixel opening. DETAILED DESCRIPTION

[0086] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0087] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0088] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0089] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0090] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0091] like Figure 1 As shown, in the related art, inkjet printing technology is applied to the production and preparation of OLED display panels due to its advantages of high production efficiency and low material cost. The display panel includes a substrate 1 and a pixel definition layer 2 arranged on one side of the substrate 1. Inkjet printing technology is to drop inkjet droplets into the pixel area defined by the pixel definition layer 2, and then perform a drying process to solidify the inkjet droplets to form a film layer such as a hole injection layer 3. However, although this method is simple to make, during the drying process of the inkjet droplets, the evaporation rate at the edge position is greater than the evaporation rate at the middle position, causing an outward capillary flow to be generated inside the inkjet droplets, carrying the suspended particles to the edge position, and depositing them into a ring at the edge position, resulting in the thickness at the edge position being greater than the thickness at the middle position, resulting in a coffee ring effect, thereby interfering with the microcavity effect, especially when the display panel also includes a light extraction layer 4, the light extraction layer 4 is usually located on the side of the cathode layer of the light-emitting device away from the substrate 1, and the light intensity distribution is uneven, affecting the display quality of the OLED display panel.

[0092] like Figures 2 to 6 As shown, the present disclosure provides a display panel, including a substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405 and a first electrode layer 501. The transistor device layer 200 is arranged on one side of the substrate 100; the at least one metal layer is arranged on the side of the transistor device layer 200 away from the substrate 100, including a plurality of metal traces 01 extending along a first direction Y; the first insulating layer 405 is arranged on the surface of the side of the at least one metal layer away from the substrate 100; the first electrode layer 501 is arranged on the surface of the side of the first insulating layer 405 away from the substrate 100, and the first electrode layer 501 includes a plurality of first electrode blocks; the pixel definition layer 600 includes a plurality of first defining dams 601 extending along the first direction Y and a plurality of second defining dams 602 extending along the second direction X, the plurality of first defining dams 601 and the plurality of second defining dams 602 mutually cross to define a plurality of pixel openings 603, and the pixel openings 603 expose each first electrode block one by one. The orthographic projection of the metal trace 01 on the substrate 100 is located within the orthographic projection of the first limiting dam 601 on the substrate 100 ; at least one of the at least one metal layer has a thickness greater than that of the first insulating layer 405 , and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer 405 .

[0093] The display panel provided by the present disclosure includes a base substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405, a first electrode layer 501 and a pixel definition layer 600, wherein the at least one metal layer includes a plurality of metal traces 01 extending along a first direction Y, the pixel definition layer 600 includes a first limiting dam 601 extending along the first direction Y, the orthographic projection of the metal traces 01 on the base substrate 100 is located within the orthographic projection of the first limiting dam 601 on the base substrate 100, and the thickness of at least one metal layer in the at least one metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. Thus, the thicker metal traces 01 help to form a larger slope angle, and when used with the thinner first insulating layer 405, the first limiting dam 601 can also form a larger slope angle, thereby helping to slow down the ink climbing phenomenon, improve the coffee ring effect, and enhance the display quality of the display panel.

[0094] The components of the display panel provided by the present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments:

[0095] like Figures 2 to 6 As shown, the embodiment of the present disclosure provides a display panel, which can be an OLED (Organic Light-Emitting Diode) display panel or a QLED (Quantum Dot Light Emitting Diodes) display panel. The display panel provided by the present disclosure includes a substrate 100, a transistor device layer 200, at least one metal layer, a first insulating layer 405, a first electrode layer 501 and a pixel definition layer 600.

[0096] The substrate 100 may be a substrate 100 of an inorganic material, or may be a substrate 100 of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate 100 may be polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. The substrate 100 may also be a flexible substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be polyimide (PI). The substrate 100 may also be a composite of multiple layers of materials. For example, in one embodiment of the present disclosure, the substrate 100 may include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence. In some embodiments of the present disclosure, the substrate 100 includes a display area 110 and a virtual area 111 located outside the display area 110. The display area 110 is used to display a picture.

[0097] like Figure 2 and Figure 5 As shown, the transistor device layer 200 is arranged on one side of the substrate 100. The transistor device layer 200 may include devices such as transistors and capacitors for forming pixel circuits. The pixel circuit is used to drive the light-emitting devices such as organic light-emitting diodes or quantum dot light-emitting diodes of the display panel to emit light. The pixel circuit can be a pixel circuit such as 7T1C, 7T2C, 6T1C or 6T2C, and its structure is not specifically limited here. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0098] In some embodiments of the present disclosure, the transistor device layer 200 may be composed of a multilayer film structure. Taking the transistor in the driving circuit as a top-gate thin film transistor as an example, the transistor device layer 200 includes an active layer 201, a first gate insulating layer 202, a first gate metal layer 203, an interlayer dielectric layer 204 and a source-drain layer 205.

[0099] The active layer 201 is arranged on one side of the substrate 100; the first gate insulating layer 202 is arranged on the side of the active layer 201 away from the substrate 100, and the first gate insulating layer 202 covers the active layer 201; the first gate metal layer 203 is arranged on the side of the first gate insulating layer 202 away from the substrate 100, and the first gate metal layer 203 is used to form the gate of the transistor. The interlayer dielectric layer 204 is arranged on the side of the first gate metal layer 203 away from the substrate 100, and the interlayer dielectric layer 204 covers the first gate metal layer 203; the source-drain layer 205 is arranged on the side of the interlayer dielectric layer 204 away from the substrate 100, and the source-drain layer 205 is used to form the source and drain of the transistor, and the source and drain are connected to the active layer 201.

[0100] In other embodiments, the transistor device layer 200 may further include a second gate insulating layer and a second gate metal layer. In such embodiments, the second gate insulating layer and the second gate metal layer are disposed between the first gate metal layer 203 and the source-drain layer 205. The first gate metal layer 203 is used to form a first plate of the capacitor and a gate of the transistor T; the second gate insulating layer is disposed on a side of the first gate metal layer 203 away from the substrate 100, and the second gate insulating layer covers the first gate metal layer 203; the second gate metal layer is disposed on a side of the first gate insulating layer 202 away from the substrate 100, and is disposed opposite to the first plate, and the second gate metal layer is used to form a second plate of the capacitor; the interlayer dielectric layer 204 is disposed on a side of the second gate metal layer away from the substrate 100, and the interlayer dielectric layer 204 covers the second gate metal layer.

[0101] In some embodiments of the present disclosure, the display panel further includes a planarization layer 300 disposed between the transistor device layer 200 and at least one metal layer. Specifically, the planarization layer 300 is disposed on a side of the source / drain layer 205 away from the base substrate 100 .

[0102] like Figures 2 to 6 As shown, at least one metal layer is disposed on a side of the transistor device layer 200 away from the substrate 100, including a plurality of metal traces 01 extending along a first direction Y. The at least one metal layer can be one, two, three or more metal layers. The multiple metal traces 01 can be distributed in one, two, three or more metal layers. Fig. 9 As shown, when the at least one metal layer includes multiple metal layers, a second insulating layer 406 is disposed between two adjacent metal layers.

[0103] The first insulating layer 405 is disposed on the surface of the side of the at least one metal layer away from the base substrate 100. The material of the first insulating layer 405 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride and other inorganic materials. The thickness of at least one metal layer in the at least one metal layer is greater than the thickness of the first insulating layer 405, and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. Specifically, it can be at least 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, etc.

[0104] For example, if the at least one metal layer includes one metal layer, the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405. For another example, if the at least one metal layer includes two metal layers, the thickness of at least one of the two metal layers is at least 0.5 μm greater than the thickness of the first insulating layer 405. Similarly, if the at least one metal layer includes three metal layers, the thickness of at least one of the three metal layers is at least 0.5 μm greater than the thickness of the first insulating layer 405.

[0105] The first electrode layer 501 is disposed on a surface of the first insulating layer 405 away from the substrate, so that the first insulating layer 405 with a relatively thin thickness is included between the first electrode layer 501 and at least one metal layer. The first electrode layer 501 includes a plurality of first electrode blocks. The first electrode blocks can be used as anodes of light-emitting devices such as organic light-emitting diodes or quantum dot light-emitting diodes.

[0106] like Fig.11 As shown, in some embodiments of the present disclosure, the plurality of first electrode blocks include a plurality of normal electrodes 5011 located in the display area 110 and a plurality of virtual electrodes 5012 located in the virtual area 111, the normal electrodes 5011 are electrically connected to the transistor device layer 200, and the virtual electrodes 5012 are electrically insulated from the transistor device layer 200. That is, the organic light emitting diode or quantum dot light emitting diode including the virtual electrodes 5012 does not emit light. The virtual electrodes 5012 located in the virtual area 111 can be used as a process reference area for forming the normal electrodes 5011 on the one hand, and on the other hand, can also help balance the display effect at the edge of the display area 110 of the display panel.

[0107] like Figure 2 , Figure 4 and Figure 5As shown, the pixel definition layer 600 includes a plurality of first defining dams 601 extending along a first direction Y and a plurality of second defining dams 602 extending along a second direction X. The plurality of first defining dams 601 and the plurality of second defining dams 602 intersect with each other to define a plurality of pixel openings 603. In a direction perpendicular to the base substrate 100, the pixel openings 603 correspond to the first electrode blocks one by one. The first direction Y and the second direction X have a certain angle. The first direction Y may be a column direction, and the second direction X may be a row direction, but is not limited thereto. The shape of the positive projection of the pixel opening 603 on the base substrate 100 may be a circular, elliptical, closed curved shape, and other shapes. The material of the pixel definition layer 600 may include materials such as fluorinated resin. The materials of the first defining dam 601 and the second defining dam 602 may be different.

[0108] In the present disclosure, the thickness relationship between at least one metal layer and the first insulating layer 405 is defined, and the at least one metal layer is maintained to have a thicker thickness, which helps to form a larger slope angle during etching, while the first insulating layer 405 has a thinner thickness. The insulating layer of this thickness not only plays an insulating effect, but also helps to maintain the larger slope angle formed by the aforementioned at least one metal layer, thereby providing a structural basis for the subsequent first limiting dam 601 to form a larger slope angle.

[0109] In some embodiments of the present disclosure, at least one of the at least one metal layer has a thickness of not less than 0.7 μm. The thickness of the first insulating layer 405 is not greater than 0.2 μm. Specifically, at least one of the at least one metal layer has a thickness of 0.7 μm-1 μm. The thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm or 0.2 μm.

[0110] In some embodiments of the present disclosure, the metal trace 01 has a first surface close to the substrate 100 and a second surface away from the substrate 100, and a side wall connecting the first surface and the second surface, and a first angle α is formed between the side wall of the metal trace 01 and the first surface of the metal trace 01, and the first angle α of at least some of the metal traces 01 among the multiple metal traces 01 is 70°-90°. It should be noted that the first angle α is the slope angle of the metal trace 01. The slope angle of at least some of the metal traces 01 among the multiple metal traces 01 is 70°-90°.

[0111] For example, the multiple metal traces 01 include a target metal trace, and the shortest distance D between the edge of the orthographic projection of the target metal trace on the substrate 100 and the edge of the orthographic projection of the corresponding first limiting dam 601 on the substrate 100 is not greater than 2 μm; the first angle α of the target metal trace is 70°-90°. That is, the metal trace 01 closest to the edge of the corresponding first limiting dam 601 is the target metal trace, the first angle α of the target metal trace is 70°-90°, and the thickness of the target metal trace is not less than 0.7 μm. In this way, it is ensured that among the multiple metal traces 01, at least one target metal trace can play a role in raising the first limiting dam 601 and forming a larger slope angle.

[0112] It should be noted that, in the actual manufacturing process, the window size of the mask plate for forming the target metal wiring and the mask plate for forming the pixel definition layer can be set to be substantially equal. At this time, the shortest distance D between the edge of the orthographic projection on the substrate 100 and the edge of the orthographic projection of the corresponding first limiting dam 601 on the substrate 100 is related to the exposure bias value (Photo bias) and the etching bias value (Etch bias) in the process. For example, D = |ZXY|, where X is the exposure bias value (Photo bias) of the target metal wiring, Y is the etching bias value (Etch bias) of the target metal wiring after exposure, and Z is the exposure bias value of the first limiting dam.

[0113] When forming the metal trace 01, a metal material layer may be first deposited, and then the metal material layer may be patterned to form a metal layer including the metal trace 01. When patterning the metal material layer, dry etching or wet etching may be used, which may be determined according to the material properties of the metal material.

[0114] The single metal layer in at least one metal layer can be made of a single metal or a composite metal. For example, in some embodiments, the single metal layer in at least one metal layer is made of a single metal such as molybdenum (Mo), titanium (Ti), or aluminum (Al). Among them, wet etching of the molybdenum metal film layer helps to form a larger slope angle, and dry etching of the titanium metal layer and the aluminum metal layer helps to form a larger slope angle. Therefore, when the metal layer is made of different metal materials, different etching processes can be used accordingly.

[0115] like Fig.14As shown, in other embodiments, the single metal layer in at least one metal layer includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5μm. The thickness of the first sub-metal layer 01a can be 0.5μm-0.8μm, and the thickness of the second sub-metal layer 01b can be 0.05μm-0.2μm. The material of the first sub-metal layer 01a can be selected from aluminum (Al) metal material. The thicker aluminum metal layer mainly plays a padding role so that the formed metal line has a larger slope angle. The second sub-metal layer 01b can be selected from molybdenum (Mo) or titanium (Ti) metal materials. In this type of embodiment, it is preferred to use a dry etching process to form the metal trace 01.

[0116] Furthermore, the single metal layer in the at least one metal layer further includes a third sub-metal layer 01c, and the third sub-metal layer 01c is disposed on a side of the first sub-metal layer 01a close to the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c can be 0.05 μm-0.2 μm. The third sub-metal layer 01c can be selected from molybdenum (Mo) or titanium (Ti) metal materials.

[0117] like Figure 6 , Fig.15 As shown, further, in the present disclosure, no organic material layer is included between at least one metal layer and the first electrode layer 501. In the prior art, the thickness of the organic material layer in the display panel is usually thick, and such organic material layer may level the height difference formed by the metal wiring 01, so that the slope angle formed by the metal wiring 01 cannot have an effective influence on the slope angle of the first limiting dam 601. In the present disclosure, no organic material layer is provided between at least one metal layer and the first electrode layer 501, but only a first insulating layer 405 (inorganic material layer) with a relatively thin thickness is provided. In this way, the metal wiring 01 can give full play to the cushioning effect of the first limiting dam 601, and the larger slope angle of the metal wiring 01 can be used to promote the first limiting dam 601 to also form a larger slope angle, reduce the ink climbing, and then improve the coffee ring effect, improve the light intensity distribution of the light-emitting device, and improve the display quality of the display panel.

[0118] like Figure 5 , Fig.15 and Fig.16As shown, the display panel also includes a light-emitting functional layer 502 and a second electrode layer 503. The light-emitting functional layer 502 is arranged on the side of the first electrode layer 501 away from the base substrate 100, and the light-emitting functional layer 502 is at least partially located in the pixel opening 603. The light-emitting functional layer 502 is a multi-layer structure. In the direction away from the base substrate 100, the light-emitting functional layer 502 includes a hole injection layer, a hole transport layer, a light-emitting material layer, and an electron transport layer. Visible light can be generated by allowing holes and electrons to recombine into excitons in the light-emitting material layer, and the excitons radiate photons. The specific light-emitting principle is not described in detail here. The light-emitting material layer can be an organic light-emitting material layer or a quantum dot light-emitting material layer. In some embodiments, the light-emitting functional layer 502 may also include an electron injection layer, which is arranged on the side of the electron transport layer away from the base substrate 100.

[0119] Part or all of the film layers in the light-emitting functional layer 502 may be formed by an inkjet printing process. Preferably, part of the film layers in the light-emitting functional layer 502 are formed by an inkjet printing process, and part of the film layers are formed by an evaporation process. For example, the hole injection layer, the hole transport layer and the light-emitting material layer are formed by an inkjet printing process, and the electron transport layer and the electron injection layer are formed by an evaporation process. Among them, the film layer formed by printing is located in the pixel opening 603, and the film layer formed by evaporation can cover the surface of the pixel definition layer 600 away from the base substrate 100.

[0120] The second electrode layer 503 is disposed on a surface of the pixel definition layer 600 and the light emitting function layer 502 away from the base substrate 100. The second electrode layer 503 can be formed by sputtering. The material of the second electrode layer 503 can be transparent materials such as indium zinc oxide (IZO).

[0121] The display panel also includes a light extraction layer 600, which is disposed on the side of the second electrode layer 503 away from the base substrate 100. The light extraction layer 600 can significantly improve the light emission mode of the display device, so that the light originally confined inside the device can be emitted from the display panel, showing a higher light extraction efficiency. The light extraction layer 600, in combination with the setting method of at least one metal layer in the present disclosure, can more effectively adjust the light intensity distribution of the light-emitting device and improve the phenomenon of uneven light intensity distribution of the light-emitting device.

[0122] The display panel further includes an encapsulation layer, which covers the surface of the second electrode layer 503 away from the base substrate 100, and can be used to prevent external water and oxygen from corroding the light-emitting device.

[0123] In some embodiments of the present disclosure, encapsulation can be achieved by thin-film encapsulation (TFE). Specifically, the encapsulation layer may include a first inorganic layer, an organic layer, and a second inorganic layer, wherein the first inorganic layer covers the surface of the second electrode layer 503 away from the substrate 100, the organic layer may be provided on the surface of the first inorganic layer away from the substrate 100, and the boundary of the organic layer is limited to the inner side of the boundary of the first inorganic layer, and the second inorganic layer covers the organic layer and the first inorganic layer not covered by the organic layer, and the second inorganic layer can be used to block the intrusion of water and oxygen, and the flexible organic layer can be used to achieve flattening. The materials of the first inorganic layer and the second inorganic layer are materials with water and oxygen blocking effects such as Si3N4, SiO2, SiC, TiO2, Al2O3, and can be formed into a 0.03μm-1μm thin film by chemical vapor deposition (CVD), sputtering, atomic force deposition (ALD), and the like.

[0124] like Figure 4 As shown, in some embodiments of the present disclosure, the plurality of first defining dams 601 include a plurality of first sub-defining dams 6011 and a plurality of second sub-defining dams 6012, the first sub-defining dams 6011 and the second sub-defining dams 6012 both extend along the first direction Y, the second sub-defining dam 6012 is located on one side of the first sub-defining dam 6011 along the second direction X, the first sub-defining dam 6011 and the second sub-defining dam 6012 both have a bottom end close to the substrate 100 and a top end away from the substrate 100, the distance between the bottom end and the top end of the first sub-defining dam 6011 is smaller than the distance between the bottom end and the top end of the second sub-defining dam 6012; the orthographic projection of the metal trace 01 on the substrate 100 is located within the orthographic projection of the second sub-defining dam 6012 on the substrate 100. The distance between the bottom end and the top end of the first sub-defining dam 6011 may be 0.2 μm-0.6 μm, and the distance between the bottom end and the top end of the second sub-defining dam 6012 may be 1.5 μm-2 μm. There are many ways to arrange the first sub-defining dam 6011 and the second sub-defining dam 6012, such as arranging a second sub-defining dam 6012 every m first sub-defining dams 6011, where m can be a positive integer, such as 2≤m≤10. The distance between the bottom and top of the second defining dam 602 can be 1.5μm-2μm.

[0125] like Fig.13As shown, in the present disclosure, the display panel includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, and the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B are arranged in sequence along a first direction Y. A plurality of red sub-pixels R are arranged along a second direction X, that is, the colors of the sub-pixels in the same row are the same. The top material of the first sub-defining dam 6011 may include a lyophilic material, such as a lyophilic photoresist, a lyophilic inorganic film, etc., to ensure that the sub-pixels of the same color in the same row between two adjacent second sub-defining dams 6012 can be connected. The top material of the second defining dam 602 may include a lyophobic material, such as a lyophobic photoresist, to avoid flow interference between sub-pixels of different colors.

[0126] In the present disclosure, the at least one metal layer may include one, two or more metal layers. The configuration of the at least one metal layer in the present disclosure will be described in detail below in conjunction with different embodiments.

[0127] like Figures 2 to 6 As shown, in one embodiment of the present disclosure, at least one metal layer includes a first metal layer 401, which is disposed on a side of the transistor device layer 200 away from the substrate 100, and a plurality of metal traces 01 are distributed in the first metal layer 401; the first angle α of the metal traces 01 distributed in the first metal layer 401 is 70°-90°. The thickness of the first metal layer 401 is 0.7 μm-1 μm. The shortest distance D between the edge of the orthographic projection of the metal trace 01 on the substrate 100 and the edge of the orthographic projection of the corresponding first limiting dam 601 on the substrate 100 is not greater than 2 μm.

[0128] like Fig.16As shown, the first metal layer 401 can be made of a single metal such as molybdenum (Mo), titanium (Ti), aluminum (Al), etc., or can be made of a composite metal. For example, the first metal layer 401 includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5μm. The thickness of the first sub-metal layer 01a can be 0.5μm-0.8μm, such as 0.5μm, 0.6μm, 0.65μm, 0.7μm, 0.75μm, etc. The thickness of the second sub-metal layer 01b can be 0.05μm-0.2μm, such as 0.05μm, 0.08μm, 0.1μm, 0.15μm, 0.18μm, etc. The material of the first sub-metal layer 01a can be selected from aluminum (Al) metal materials. Furthermore, the first metal layer 401 further includes a third sub-metal layer 01c, which is disposed on a side of the first sub-metal layer 01a close to the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c may be 0.05 μm-0.2 μm. The third sub-metal layer 01c may be selected from molybdenum (Mo) or titanium (Ti) metal materials.

[0129] In this type of embodiment, the metal trace 01 distributed in the first metal layer 401 can be used as a data line, a power line, etc., for transmitting a data signal or a power voltage VDD / VSS.

[0130] like Figure 5 , Figure 6 As shown, the first insulating layer 405 is disposed on a surface of the first metal layer 401 away from the substrate 100, and the thickness of the first insulating layer 405 is not greater than 0.2 μm. Specifically, the thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm or 0.2 μm. The material of the first insulating layer 405 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride and other inorganic materials.

[0131] like Figures 7 to 10 , Fig.16As shown, in another embodiment of the present disclosure, at least one metal layer includes two metal layers, namely a first metal layer 401 and a second metal layer 402. The first metal layer 401 is disposed on a side of the transistor device layer 200 away from the substrate 100, and at least part of the metal traces 01 among the plurality of metal traces 01 are distributed in the first metal layer 401; the second metal layer 402 is disposed on a side of the first metal layer 401 away from the substrate 100, and at least part of the metal traces 01 among the plurality of metal traces 01 are distributed in the second metal layer 402. The first angle α of the metal traces 01 distributed in the first metal layer 401 is 70°-90° or / and the first angle α of the metal traces 01 distributed in the second metal layer 402 is 70°-90°.

[0132] The thickness of the first metal layer 401 and / or the second metal layer 402 is 0.7 μm-1 μm. Preferably, the thickness of the first metal layer 401 and the second metal layer 402 are both 0.7 μm-1 μm. The plurality of metal traces 01 include a target metal trace, and the shortest distance D between the edge of the orthographic projection of the target metal trace on the substrate 100 and the edge of the orthographic projection of the corresponding first limiting dam 601 on the substrate 100 is not greater than 2 μm. The target metal trace can be distributed in the first metal layer 401 and / or the second metal layer 402.

[0133] The first metal layer 401 and the second metal layer 402 can be made of a single metal such as molybdenum (Mo), titanium (Ti), aluminum (Al), or a composite metal. For example, the first metal layer 401 and the second metal layer 402 both include a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5μm. The thickness of the first sub-metal layer 01a can be 0.5μm-0.8μm, such as 0.5μm, 0.6μm, 0.65μm, 0.7μm, 0.75μm, etc. The thickness of the second sub-metal layer 01b can be 0.05μm-0.2μm, such as 0.05μm, 0.08μm, 0.1μm, 0.15μm, 0.18μm, etc. The material of the first sub-metal layer 01a can be selected from aluminum (Al) metal materials. Further, the first metal layer 401 and the second metal layer 402 also include a third sub-metal layer 01c, and the third sub-metal layer 01c is arranged on the side of the first sub-metal layer 01a close to the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c can be 0.05μm-0.2μm. The third sub-metal layer 01c can be selected from molybdenum (Mo) or titanium (Ti) metal materials.

[0134] Preferably, if Fig.10As shown, the orthographic projection of the metal trace 01 distributed in the first metal layer 401 on the substrate 100 does not overlap with the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 to avoid parasitic capacitance between the two.

[0135] In this type of embodiment, the metal traces 01 distributed in the first metal layer 401 and the second metal layer 402 can be used as data lines, power lines, etc., for transmitting data signals or power supply voltages VDD / VSS. Furthermore, the metal traces 01 distributed in the second metal layer 402 can also be used as gate drive circuit (GOA) signal lines, such as STU, VGH, VGL, RST and other DC signal traces.

[0136] The first insulating layer 405 is disposed on a surface of the second metal layer 402 away from the substrate 100, and the thickness of the first insulating layer 405 is not greater than 0.2 μm. Specifically, the thickness of the first insulating layer 405 is 0.05-0.2 μm, such as 0.05 μm, 0.1 μm, 0.15 μm or 0.2 μm. The material of the first insulating layer 405 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride and other inorganic materials.

[0137] like Fig.11 and Fig.12 As shown, in this type of embodiment, the orthographic projection of the metal trace 01 distributed in the first metal layer 401 on the substrate 100 is located in the display area 110 and the virtual area 111, and the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 can be located in the display area 110 and the virtual area 111, or only in the virtual area 111, and the present disclosure does not make special limitations. Preferably, the orthographic projection of the metal trace 01 distributed in the second metal layer 402 on the substrate 100 is located in the virtual area 111. In this case, the metal trace 01 distributed in the second metal layer 402 is used as a gate drive circuit (GOA) signal line, such as STU, VGH, VGL, RST and other DC signal traces.

[0138] Further, in this type of embodiment, the second metal layer 402 may also include a connection line 02, which extends along the second direction X and can be in contact with and connected to the metal trace 01. The orthographic projection of the connection line 02 on the base substrate 100 is located in the virtual area 111, and can also be used as a gate drive circuit (GOA) signal line, which is not specifically limited in the present disclosure.

[0139] like Fig.13 and Fig.14As shown, in another embodiment of the present disclosure, the second electrode layer 503 is connected to the metal layer closest to the second electrode layer 503 among the at least one metal layer through a first via hole 6021 in the second limiting dam 602. The metal layer connected to the second electrode layer 503 via the via hole can be used as a cathode auxiliary electrode layer, connected in parallel with the second electrode layer 503, to reduce resistance and impedance.

[0140] Specifically, the metal layer closest to the second electrode layer 503 in at least one metal layer is the third metal layer 403; the metal trace 01 distributed in the third metal layer 403 has a connection block 011, and the connection block 011 is located at the intersection of the first limiting dam 601 and the second limiting dam 602; the size of the connection block 011 in the second direction X is larger than the size of other areas of the metal trace 01 in the second direction X; the orthographic projection of the connection block 011 on the substrate 100 is located within the orthographic projection of the first via hole 6021 on the substrate 100. The orthographic projection of the connection block 011 on the substrate 100 can be a square, a rectangle or other polygons. There is a gap between the edge of the orthographic projection of the first via hole 6021 on the substrate 100 and the edge of the orthographic projection of the connection block 011 on the substrate 100, and the gap is greater than 0.

[0141] Furthermore, the thickness of the third metal layer 403 is not less than 0.7 μm. The third metal layer 403 includes a first sub-metal layer 01a and a second sub-metal layer 01b stacked in a direction away from the base substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the second sub-metal layer 01b, and the thickness of the first sub-metal layer 01a is not less than 0.5 μm. The hardness of the first sub-metal layer 01a is less than the hardness of the second sub-metal layer 01b. When etching to form the connection block 011 in the third metal layer 403, the orthographic projection of the first sub-metal layer 01a in the connection block 011 on the base substrate 100 will be located within the orthographic projection of the second sub-metal layer 01b on the base substrate 100. The connection block 011 of this structure can separate the film layer in the light-emitting functional layer 502 formed by the evaporation process later, and provide a structural basis for realizing the connection between the second electrode layer 503 and the third metal layer 403. At this time, the second electrode layer 503 may be formed by a sputtering process, and the formed second electrode layer 503 will be connected to the side wall of the connection block 011 , etc., so as to realize the parallel connection of the second electrode layer 503 and the third metal layer 403 .

[0142] The third metal layer 403 may further include a third sub-metal layer 01c, which is disposed on a side of the first sub-metal layer 01a close to the substrate 100; the thickness of the first sub-metal layer 01a is greater than the thickness of the third sub-metal layer 01c. The thickness of the third sub-metal layer 01c may be 0.05 μm-0.2 μm. The material of the first sub-metal layer 01a may be selected from aluminum (Al) metal materials. The second sub-metal layer 01b and the third sub-metal layer 01c may be selected from molybdenum (Mo) or titanium (Ti) metal materials.

[0143] Furthermore, the number of metal layers in at least one metal layer is multiple layers, wherein the metal layer located on the side of the third metal layer 403 close to the substrate 100 and closest to the third metal layer 403 is the fourth metal layer 404; the metal traces 01 distributed in the third metal layer 403 are connected to the metal traces 01 distributed in the fourth metal layer 404 through holes to further reduce resistance. Preferably, the conductivity of the fourth metal layer 404 is greater than that of the third metal layer 403. For example, the fourth metal layer 404 can be made of metals Cu and Ag with strong conductivity. The third metal layer 403 can be Ti / Al / Ti.

[0144] In this type of embodiment, the connection block 011 is located between the red sub-pixel R and the green sub-pixel G, or between the blue sub-pixel B and the green sub-pixel G. The size of the second defining dam 602 located between the red sub-pixel R and the green sub-pixel G, and the second defining dam 602 located between the blue sub-pixel B and the green sub-pixel G in the first direction Y are both larger than the size of the second defining dam 602 located between the red sub-pixel R and the blue sub-pixel B in the first direction Y. For example, the size of the second defining dam 602 located between the red sub-pixel R and the green sub-pixel G, and the second defining dam 602 located between the blue sub-pixel B and the green sub-pixel G in the first direction Y is 1.2-1.5 times the size of the second defining dam 602 located between the red sub-pixel R and the blue sub-pixel B in the first direction Y.

[0145] like Figures 2 to 6 As shown, the present disclosure also provides a method for manufacturing a display panel, comprising:

[0146] Step S100, providing a base substrate 100;

[0147] Step S200 , forming a transistor device layer 200 on one side of the base substrate 100 ;

[0148] Step S300, forming at least one metal layer on a side of the transistor device layer 200 away from the base substrate 100, wherein the at least one metal layer includes a plurality of metal traces 01 extending along a first direction Y;

[0149] Step S400, forming a first insulating layer 405 on a surface of at least one metal layer away from the base substrate 100;

[0150] Step S500, forming a first electrode layer 501 on a surface of the first insulating layer 405 away from the base substrate, wherein the first electrode layer 501 includes a plurality of first electrode blocks;

[0151] Step S600, forming a pixel definition layer 600, the pixel definition layer 600 includes a plurality of first defining dams 601 extending along a first direction Y and a plurality of second defining dams 602 extending along a second direction X, the plurality of first defining dams 601 and the plurality of second defining dams 602 intersect each other to define a plurality of pixel openings 603, in a direction perpendicular to the base substrate 100, the pixel openings 603 correspond one to one with the first electrode blocks;

[0152] The orthographic projection of the metal trace 01 on the base substrate 100 is located within the orthographic projection of the first limiting dam 601 on the base substrate 100;

[0153] The thickness of at least one of the at least one metal layer is greater than the thickness of the first insulating layer 405 , and the thickness of the metal layer is at least 0.5 μm greater than the thickness of the first insulating layer 405 .

[0154] The present disclosure also provides a display device, including a display panel, which can be a display panel of any of the above embodiments, and its specific structure and beneficial effects can refer to the embodiments of the display panel above, which will not be repeated here. The display device of the present disclosure can be an electronic device such as a mobile phone, a tablet computer, a television, etc., which will not be listed one by one here.

[0155] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0156] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A display panel, characterized in that: include: substrate substrate; A transistor device layer is provided on one side of the base substrate; At least one metal layer, disposed on a side of the transistor device layer away from the substrate, comprising a plurality of metal traces extending along a first direction; A first insulating layer is provided on a surface of the at least one metal layer away from the base substrate; A first electrode layer is provided on a surface of the first insulating layer away from the base substrate, and the first electrode layer includes a plurality of first electrode blocks; a pixel definition layer, comprising a plurality of first defining dams extending along the first direction and a plurality of second defining dams extending along the second direction, wherein the plurality of first defining dams and the plurality of second defining dams intersect each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks; Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate; At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

2. The display panel according to claim 1, characterized in that: The metal routing has a first surface close to the substrate, a second surface away from the substrate, and a side wall connecting the first surface and the second surface. A first angle is formed between the side wall of the metal routing and the first surface of the metal routing. The first angle of at least some of the multiple metal routings is 70°-90°.

3. The display panel according to claim 1, characterized in that: The at least one metal layer comprises: A first metal layer is provided on a side of the transistor device layer away from the substrate, and the plurality of metal traces are distributed in the first metal layer; The first angle of the metal traces distributed in the first metal layer is 70°-90°.

4. The display panel according to claim 1, characterized in that: The at least one metal layer comprises: A first metal layer is provided on a side of the transistor device layer away from the substrate, and at least part of the plurality of metal traces are distributed in the first metal layer; A second metal layer is provided on a side of the first metal layer away from the substrate, and at least part of the plurality of metal traces are distributed in the second metal layer; The first angle of the metal routing lines distributed in the first metal layer is 70°-90° and / or the first angle of the metal routing lines distributed in the second metal layer is 70°-90°.

5. The display panel according to claim 4, characterized in that: The orthographic projection of the metal wiring distributed in the first metal layer on the substrate does not overlap with the orthographic projection of the metal wiring distributed in the second metal layer on the substrate.

6. The display panel according to claim 1, characterized in that: At least one of the at least one metal layer has a thickness of not less than 0.7 μm.

7. The display panel according to claim 1, characterized in that: The single metal layer in the at least one metal layer comprises a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate; The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

8. The display panel according to claim 7, characterized in that: The single metal layer in the at least one metal layer further includes a third sub-metal layer, and the third sub-metal layer is arranged on a side of the first sub-metal layer close to the base substrate; The thickness of the first sub-metal layer is greater than the thickness of the third sub-metal layer.

9. The display panel according to claim 1, characterized in that: The thickness of the first insulating layer is no more than 0.2 μm.

10. The display panel according to claim 2, characterized in that: The plurality of metal traces include a target metal trace, and the shortest distance between an edge of an orthographic projection of the target metal trace on the substrate and an edge of an orthographic projection of a corresponding first limiting dam on the substrate is no greater than 2 μm; The first angle of the target metal wiring is 70°-90°, and the thickness of the target metal wiring is not less than 0.7 μm.

11. The display panel according to claim 4, characterized in that: The base substrate comprises a display area and a virtual area located outside the display area; The plurality of first electrode blocks include a plurality of normal electrodes located in the display area and a plurality of virtual electrodes located in the virtual area, the normal electrodes are electrically connected to the transistor device layer, and the virtual electrodes are electrically insulated from the transistor device layer; The orthographic projection of the metal traces distributed in the second metal layer on the substrate is located in the virtual area.

12. The display panel according to claim 1, characterized in that: No organic material layer is included between the at least one metal layer and the first electrode layer.

13. The display panel according to claim 1, characterized in that: The display panel further includes: A light-emitting functional layer is provided on a side of the first electrode layer away from the base substrate, and at least a part of the light-emitting functional layer is located in the pixel opening; A second electrode layer is provided on a surface of the pixel definition layer and the light-emitting functional layer which is away from the base substrate; The second electrode layer is connected to the metal layer closest to the second electrode layer among the at least one metal layer through a first via hole in the second defining dam.

14. The display panel according to claim 13, characterized in that: The metal layer closest to the second electrode layer among the at least one metal layer is a third metal layer; The metal wiring distributed in the third metal layer has a connection block, and the connection block is located at the intersection of the first limiting dam and the second limiting dam; The size of the connecting block in the second direction is larger than the size of other areas of the metal wiring in the second direction; The orthographic projection of the connection block on the base substrate is located within the orthographic projection of the first via hole on the base substrate.

15. The display panel according to claim 14, characterized in that: The thickness of the third metal layer is not less than 0.7 μm.

16. The display panel according to claim 15, characterized in that: The third metal layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction away from the substrate; The thickness of the first sub-metal layer is greater than that of the second sub-metal layer, and the thickness of the first sub-metal layer is not less than 0.5 μm.

17. The display panel according to claim 7 or 16, characterized in that: The hardness of the first sub-metal layer is less than the hardness of the second sub-metal layer.

18. The display panel according to claim 14, characterized in that: The number of metal layers in the at least one metal layer is multiple layers, wherein the metal layer located on the side of the third metal layer close to the base substrate and closest to the third metal layer is the fourth metal layer; The metal routing lines distributed in the third metal layer are connected to the metal routing lines distributed in the fourth metal layer through via holes.

19. The display panel according to claim 14, characterized in that: The display panel comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the red sub-pixel, the green sub-pixel and the blue sub-pixel are arranged in sequence along the first direction; The connection block is located between the red sub-pixel and the green sub-pixel, or between the blue sub-pixel and the green sub-pixel.

20. The display panel according to claim 19, characterized in that: The second defining dam located between the red sub-pixel and the green sub-pixel and the second defining dam located between the blue sub-pixel and the green sub-pixel have sizes in the first direction that are greater than the size of the second defining dam located between the red sub-pixel and the blue sub-pixel in the first direction.

21. The display panel according to claim 1, characterized in that: The plurality of first defining dams include a plurality of first sub-defining dams and a plurality of second sub-defining dams, the first sub-defining dams and the second sub-defining dams both extend along a first direction, the second sub-defining dams are located at one side of the first sub-defining dams along a second direction, the first sub-defining dams and the second sub-defining dams both have a bottom end close to the substrate and a top end away from the substrate, and a distance between the bottom end and the top end of the first sub-defining dams is smaller than a distance between the bottom end and the top end of the second sub-defining dams; The orthographic projection of the metal trace on the substrate is located within the orthographic projection of the second sub-definition dam on the substrate.

22. A method for manufacturing a display panel, characterized in that: include: providing a substrate base plate; forming a transistor device layer on one side of the base substrate; Forming at least one metal layer on a side of the transistor device layer away from the substrate, wherein the at least one metal layer includes a plurality of metal traces extending along a first direction; Forming a first insulating layer on a surface of the at least one metal layer away from the base substrate; forming a first electrode layer on a surface of the first insulating layer away from the base substrate, wherein the first electrode layer comprises a plurality of first electrode blocks; forming a pixel definition layer, the pixel definition layer comprising a plurality of first definition dams extending along the first direction and a plurality of second definition dams extending along the second direction, the plurality of first definition dams and the plurality of second definition dams intersecting each other to define a plurality of pixel openings, and in a direction perpendicular to the substrate, the pixel openings correspond one-to-one to the first electrode blocks; Wherein, the orthographic projection of the metal trace on the substrate is located within the orthographic projection of the first limiting dam on the substrate; At least one of the at least one metal layer has a thickness greater than that of the first insulating layer, and the thickness of the metal layer is at least 0.5 μm greater than that of the first insulating layer.

23. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-21.

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