Liquid crystal display circuit, display panel and display equipment

Abstract

The invention discloses a liquid crystal display circuit, a display panel and display equipment, and relates to the technical field of display, the circuit comprises a pixel array, the pixel array comprises column pixel units taking columns as units and row pixel units taking rows as units; each data signal line provides a data signal for the corresponding column pixel unit, and the polarities of the data signals provided by the adjacent data signal lines are opposite; a plurality of first gate lines, wherein each first gate line provides a first gate driving voltage for the pixel points connected with the first data signals in the corresponding row of pixel units for charging; a plurality of second gate lines, wherein each second gate line provides a second gate driving voltage for the pixel points connected with the second data signals in the corresponding row of pixel units for charging; wherein the polarity of the first data signal is opposite to that of the second data signal, and the liquid crystal display circuit aims at improving the display quality of an LCD product applied to the liquid crystal display circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display circuit, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, LCD (Liquid Crystal Display) products are widely used in many fields such as mobile phones, cars, central control, smart home, smart office, watches, bracelets, etc. Users also have higher requirements for the display quality of LCD products.

[0003] Existing display technologies, such as TFT (Thin Film Transistor) arrays in liquid crystal display technology, usually use a unified gate voltage (Vgh is a high voltage, Vgl is a low voltage) to control the switching state of pixels. However, since the IV characteristics of TFT (i.e., the relationship between drain current and gate-source voltage) are significantly affected by the gate-source voltage (i.e., Vgs), pixels of different polarities will exhibit different leakage current characteristics under the same gate voltage. Specifically, when the polarity of a pixel is reversed, its Vgs value will change accordingly, causing the leakage current to change accordingly. This change in leakage current is the root cause of display quality problems such as afterimages, crosstalk, and flicker, which seriously affects the display quality of LCD products.

[0004] Therefore, how to improve the display quality of LCD products is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The main purpose of the present application is to provide a liquid crystal display circuit, a display panel and a display device, aiming to improve the display quality of LCD products.

[0006] To achieve the above object, the present application provides a liquid crystal display circuit, the liquid crystal display circuit comprising:

[0007] A pixel array, the pixel array comprising column pixel units in columns and row pixel units in rows;

[0008] A plurality of data signal lines, each of which provides a data signal to a corresponding column of pixel units, and the data signals provided by adjacent data signal lines have opposite polarities;

[0009] A plurality of first gate lines, each of which provides a first gate driving voltage to charge a pixel point in a corresponding row of pixel units that receives the first data signal;

[0010] A plurality of second gate lines, each of which provides a second gate driving voltage to charge a pixel point in a corresponding row of pixel units that receives the second data signal; wherein,

[0011] The first data signal and the second data signal have opposite polarities.

[0012] In one embodiment, the data signal provided by each of the data signal lines to the corresponding column pixel unit in the Nth frame has a polarity opposite to that of the data signal provided to the corresponding column pixel unit in the N+1th frame, where N is a natural number greater than zero.

[0013] In one embodiment, each of the data signal lines is electrically connected to a corresponding column of pixel units;

[0014] In each of the column pixel units, the polarity of each pixel point is the same as the polarity of the data signal provided by the corresponding data signal line.

[0015] In one embodiment, the pixel points connected to the first data signal constitute first polarity pixels, and the pixel points connected to the second data signal constitute second polarity pixels, and the first polarity pixels are opposite to the second polarity pixels;

[0016] In each of the row pixel units, a first gate line and a second gate line are relatively arranged on both sides of the pixel points arranged in rows, and the second polarity pixels are arranged between adjacent first polarity pixels. The first gate line is electrically connected to each of the first polarity pixels, and the second gate line is electrically connected to each of the second polarity pixels.

[0017] In one embodiment, in each of the row pixel units, when the first gate line provides the first gate driving voltage to each of the first polarity pixels for charging, the second gate line provides the second gate driving voltage to each of the second polarity pixels for charging.

[0018] In one embodiment, if the first polarity pixel is a positive polarity pixel, the gate line voltage of the first gate line input connected to the first polarity pixel in the off state at the Nth frame is a first level, and after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the positive charging of the pixel, the first level is switched to a second level until the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel is switched from positive polarity to negative polarity, then the second level is switched to the first level as the gate line voltage of the first gate line input connected to the first polarity pixel in the off state at the N+1th frame; or,

[0019] If the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line connected to the second polarity pixel in the off state at the Nth frame is the first level, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the positive charging of the pixel, the first level is switched to the second level until the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel is switched from positive polarity to negative polarity, then the second level is switched to the first level as the gate line voltage input to the first gate line connected to the second polarity pixel in the off state at the N+1th frame; wherein,

[0020] The first level is lower than the second level.

[0021] In one embodiment, if the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the Nth frame is a first level, and after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the pixel negative charging, the gate line voltage connected to the first polarity pixel when it switches from the on state to the off state at the Nth frame maintains the first level unchanged, and when the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel switches from negative polarity to positive polarity, the first level is used as the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the N+1th frame; or,

[0022] If the second polarity pixel is a negative polarity pixel, the gate line voltage input by the second gate line connected to the off state of the second polarity pixel in the Nth frame is a first level, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected by the second polarity pixel when it switches from the on state to the off state in the Nth frame maintains the first level unchanged, and when the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level is used as the gate line voltage input by the first gate line connected to the off state of the second polarity pixel in the N+1th frame.

[0023] In one embodiment, the first polarity pixel includes a first pixel electrode and a first thin film transistor, a first channel end of the first thin film transistor is electrically connected to the first pixel electrode, a gate end of the first thin film transistor is electrically connected to the first gate line, and a second channel end of the first thin film transistor constitutes a data line identification end of the first polarity pixel and is electrically connected to a corresponding data signal line;

[0024] The second polarity pixel comprises a second pixel electrode and a second thin film transistor, a first channel end of the second thin film transistor is electrically connected to the second pixel electrode, a gate end of the second thin film transistor is electrically connected to the second gate line, and a second channel end of the second thin film transistor constitutes a data line identification end of the second polarity pixel and is electrically connected to a corresponding data signal line; wherein,

[0025] The first pixel electrode is opposite to the second pixel electrode, and the first thin film transistor is the same as the second thin film transistor.

[0026] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the liquid crystal display circuit described in any one of the above items.

[0027] In addition, to achieve the above-mentioned purpose, the present application also provides a display device, which includes the above-mentioned display panel.

[0028] The present application provides a liquid crystal display circuit, a display panel and a display device, which solve the display quality problems such as afterimage, crosstalk, flicker, etc. caused by pixel polarity inversion in the prior art, and significantly improve the display quality of LCD products applied to liquid crystal display circuits. Specifically, the present application divides the pixel array into column pixel units on a column basis and into row pixel units on a row basis, and introduces an alternating polarity data signal line layout, that is, adjacent data signal lines provide data signals of opposite polarities to their corresponding row pixel units; next, a first gate line provided in the present application is used to provide a first gate driving voltage for charging the pixel points connected to the first data signal, and a second gate line provided in the present application is used to provide a second gate driving voltage for charging the pixel points connected to the second data signal opposite to the first data signal, thereby ensuring that all pixel points in each row of pixel units connected to the first data signal are charged by the first gate driving voltage provided by the first gate line, and all pixel points of the second data signal opposite to the first data signal are charged by the second gate driving voltage provided by the second gate line, thereby enabling the gate-source voltage difference (Vgs) of the pixel points in each row of pixel units under different polarity conditions to be maintained at a relatively stable level, thereby effectively suppressing the fluctuation of the leakage current caused by the polarity reversal, avoiding the occurrence of adverse display phenomena such as afterimages, crosstalk, and flickering, and significantly improving the display quality of LCD products. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 It is a schematic diagram of the IV characteristics of TFT involved in LCD display technology;

[0032] Figure 2 is a structural block diagram of the first embodiment of the liquid crystal display circuit of the present application;

[0033] Figure 3 is a driving waveform diagram involved in an embodiment of a liquid crystal display circuit of the present application;

[0034] Figure 4 is a circuit diagram of an embodiment of a liquid crystal display circuit of the present application;

[0035] Figure 5 It is a schematic diagram of the switching of the working states of positive and negative frame pixels involved in an embodiment of the liquid crystal display circuit of the present application.

[0036] Description of Figure Numbers:

[0037] 10. Pixel array; L1. Column pixel unit; H1. Row pixel unit; S1. Data signal line; Gna. First gate line; Gnb. Second gate line; T1. First thin film transistor; T2. Second thin film transistor; VgL. First level; VL. Second level.

[0038] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0042] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0043] The requirements for display quality of automotive display technology are higher than those of conventional display technology, and it is particularly sensitive to problems such as afterimage, crosstalk, and flicker. In conventional designs, the gate voltages of all pixels are Vgh and Vgl, respectively. However, due to the polarity inversion of pixels, using a uniform gate voltage for all pixels is not the best choice.

[0044] As is known to all, the IV characteristics of a TFT (Thin Film Transistor) are determined by the gate-source voltage Vgs, which can be understood as the voltage difference between the gate terminal voltage and the source terminal voltage of the TFT. Figure 1 As shown, Figure 1 is the IV curve of a TFT device, Figure 1 The Id in the vertical axis refers to the leakage current. Figure 1 The Vgs in the horizontal axis refers to the gate-source voltage. Figure 1 It can be seen that the leakage current Id of the TFT device will change with the gate-source voltage Vgs. For example, for a negative pixel, the gate-source voltage Vgs is at point a; while for a positive pixel, the gate-source voltage Vgs will move left to point b, resulting in a change in the leakage current. This change in leakage current will cause display quality problems such as afterimages, crosstalk, and flicker.

[0045] In order to solve the display quality problems such as afterimage, crosstalk, flicker, etc. caused by pixel polarity inversion in the above-mentioned existing LCD display technology, the present application provides a liquid crystal display circuit, a display panel and a display device.

[0046] The present application embodiment provides a liquid crystal display circuit, referring to Figure 2 As shown, Figure 2 This is a structural block diagram of the first embodiment of the liquid crystal display circuit of the present application. The liquid crystal display circuit includes:

[0047] A pixel array 10, wherein the pixel array 10 includes column pixel units L1 with columns as units, and row pixel units H1 with rows as units; a plurality of data signal lines S1, each of the data signal lines S1 provides a data signal to a corresponding column pixel unit L1, and the data signals provided by adjacent data signal lines S1 have opposite polarities; a plurality of first gate lines Gna, each of the first gate lines Gna provides a first gate driving voltage to charge a pixel point in a corresponding row pixel unit H1 that is connected to the first data signal; a plurality of second gate lines Gnb, each of the second gate lines Gnb provides a second gate driving voltage to charge a pixel point in a corresponding row pixel unit H1 that is connected to the second data signal; wherein the first data signal and the second data signal have opposite polarities.

[0048] In this example, refer to Figure 1 As shown, the pixel array 10 is composed of a large number of pixel points, which are arranged in the form of a two-dimensional grid to form rows and columns. Specifically, the present application divides the pixel array 10 into column pixel units L1 based on columns, so that each data signal line S1 provides a data signal to the corresponding column pixel unit L1, and the present application also sets the data signals provided by adjacent data signal lines S1 to have opposite polarities, which can effectively reduce the charge accumulation and DC offset problems of each pixel point in the pixel array 10, balance the charge distribution of the pixel points in the pixel array 10, reduce the afterimage or image retention phenomenon caused by displaying the same image for a long time, and thus extend the service life of the LCD product applied to the liquid crystal display circuit. Next, the present application introduces a first gate line Gna and a second gate line Gnb to respectively control pixel points connected to data signals of different polarities, that is, in each row of pixel units H1, each pixel point connected to the first data signal is connected to the first gate line Gna, and each pixel point connected to the second data signal opposite to the first data signal is connected to the second gate line Gnb, and then different gate voltages can be provided according to the polarity of each pixel point in the row of pixel units H1, that is, the first gate line Gna set in the present application is used to provide a first gate driving voltage for charging the pixel point connected to the first data signal, and the second gate line Gnb set in the present application is used to provide a second gate driving voltage for charging the pixel point connected to the second data signal opposite to the first data signal, so as to ensure that the gate-source voltage difference (Vgs) of the pixel points in each row of pixel units H1 under different polarity conditions can be maintained at a relatively stable level, thereby effectively suppressing the fluctuation of the leakage current caused by the polarity reversal, avoiding the occurrence of adverse display phenomena such as afterimages, crosstalk, and flickering, and significantly improving the display quality of LCD products.

[0049] It should be noted that, refer to Figure 1 The first gate line Gna-1 and the second gate line Gnb-1 correspond to the row pixel unit H1-1 respectively, the first gate line Gna-2 and the second gate line Gnb-2 correspond to the row pixel unit H1-2 respectively, the first gate line Gna-3 and the second gate line Gnb-3 correspond to the row pixel unit H1-3 respectively, the first gate line Gna-4 and the second gate line Gnb-4 correspond to the row pixel unit H1-4 respectively, the first gate line Gna-5 and the second gate line Gnb-5 correspond to the row pixel unit H1-5 respectively, and the first gate line Gna-6 and the second gate line Gnb-6 correspond to the row pixel unit H1-6 respectively.

[0050] The data signal line S1-1 corresponds to the column pixel unit L1-1, the data signal line S1-2 corresponds to the column pixel unit L1-2, the data signal line S1-3 corresponds to the column pixel unit L1-3, the data signal line S1-4 corresponds to the column pixel unit L1-4, the data signal line S1-5 corresponds to the column pixel unit L1-5, the data signal line S1-6 corresponds to the column pixel unit L1-6, and the polarity of each pixel point in the same column unit is the same as the data signal polarity provided by the corresponding data signal line S1.

[0051] The pixel array 10 provided in the present application may be a conventional column-inverted pixel or a column-inverted Z-arranged pixel. The above is only a feasible implementation of the present application, and the present application does not impose any limitation thereto.

[0052] In summary, the present application provides a liquid crystal display circuit, a display panel, and a display device, which solve the display quality problems such as afterimages, crosstalk, and flickering caused by pixel polarity inversion in the prior art, and significantly improve the display quality of LCD products applied to liquid crystal display circuits. Specifically, the present application divides the pixel array 10 into column pixel units L1 in columns and into row pixel units H1 in rows, and introduces an alternating polarity data signal line S1 layout, that is, adjacent data signal lines S1 provide data signals of opposite polarity to their respective corresponding row pixel units H1; next, the first gate line Gna set in the present application provides a first gate drive voltage for charging the pixel point connected to the first data signal, and the second gate line Gnb set in the present application provides a second gate drive voltage for charging the pixel point connected to the second data signal opposite to the first data signal, thereby ensuring All pixel points connected to the first data signal in each row of pixel units H1 are charged by the first gate drive voltage provided by the first gate line Gna, and all pixel points of the second data signal opposite to the first data signal are charged by the second gate drive voltage provided by the second gate line Gnb, so that the gate-source voltage difference (Vgs) of the pixel points in each row of pixel units H1 under different polarity conditions can be maintained at a relatively stable level, thereby effectively suppressing the fluctuation of leakage current caused by polarity reversal, avoiding the occurrence of adverse display phenomena such as afterimage, crosstalk, flicker, etc., and significantly improving the display quality of LCD products.

[0053] Furthermore, in some feasible embodiments, the data signal provided by each data signal line S1 to the corresponding column pixel unit L1 in the Nth frame has a polarity opposite to that of the data signal provided to the corresponding column pixel unit L1 in the N+1th frame, and N is a natural number greater than zero.

[0054] In this embodiment, each data signal line S1 provides a data signal with opposite polarity to its corresponding column pixel unit L1 between consecutive frames (such as the Nth frame and the N+1th frame, where N is a natural number greater than zero). In other words, the present application sets each data signal line S1 to output a data signal with opposite polarity between different frames, which can not only effectively balance the charge distribution of the pixel points between different frames, but also adjust the gate-source voltage value of the pixel points to a certain extent, so that the gate-source voltage difference of the positive polarity pixel and the negative polarity pixel during the working process of different frames is more similar, thereby improving the problem of different leakage currents and greatly improving the display quality of LCD products in vehicle displays and other application scenarios.

[0055] It should be noted that the positive polarity pixel can be understood as a pixel point in the pixel array 10 where the polarity of the data signal provided by the data signal line S1 is positive, and the negative polarity pixel can be understood as a pixel point in the pixel array 10 where the polarity of the data signal provided by the data signal line S1 is negative. Figure 2 , the present application sets the polarity of the data signal provided by the data signal line S1-1, the data signal line S1-3 and the data signal line S1-5 to be positive, that is, the pixel points in the column pixel unit L1-1, the column pixel unit L1-3 and the column pixel unit L1-5 set in the present application are all positive polarity pixels; in addition, the present application sets the polarity of the data signal provided by the data signal line S1-2, the data signal line S1-4 and the data signal line S1-6 to be negative, that is, the pixel points in the column pixel unit L1-2, the column pixel unit L1-4 and the column pixel unit L1-6 set in the present application are all negative polarity pixels.

[0056] Furthermore, in some other feasible embodiments, each of the data signal lines S1 is electrically connected to the corresponding column pixel unit L1; in each of the column pixel units L1, the polarity of each pixel point is the same as the polarity of the data signal provided by the corresponding data signal line S1.

[0057] In this embodiment, the present application sets each data signal line S1 to be electrically connected to the corresponding column pixel unit L1. In each column pixel unit L1, the polarity of each pixel point is the same as the polarity of the data signal provided by the corresponding data signal line S1, thereby ensuring that the polarity of each pixel point in each column pixel unit L1 is the same as the polarity of the data signal provided by the corresponding data signal line S1, ensuring the consistency of the polarity of the pixel point and the data signal, which helps to improve the display accuracy and stability of LCD products applied to liquid crystal display circuits, and reduce display errors that may be caused by inconsistent polarity of pixels in the same column pixel unit L1, thereby effectively improving the display quality.

[0058] Further, in some other feasible embodiments, referring to Figure 2 , the pixel points connected to the first data signal constitute first polarity pixels, and the pixel points connected to the second data signal constitute second polarity pixels, and the first polarity pixels are opposite to the second polarity pixels; in each of the row pixel units H1, a first gate line Gna and a second gate line Gnb are relatively arranged on both sides of the pixel points arranged in rows, and the second polarity pixels are arranged between adjacent first polarity pixels, the first gate line Gna is electrically connected to each of the first polarity pixels, and the second gate line Gnb is electrically connected to each of the second polarity pixels.

[0059] In this embodiment, the present application defines the pixel points connected to the first data signal as first polarity pixels, and the pixel points connected to the second data signal constitute second polarity pixels. The two have opposite polarities, that is, the first polarity pixels are opposite to the second polarity pixels, which effectively realizes the alternating arrangement of pixel polarities. Exemplarily, a first gate line Gna and a second gate line Gnb are provided in each row of pixel units H1, and the first gate line Gna and the second gate line Gnb are relatively provided on both sides of the pixel points arranged in rows, so that all first polarity pixels in the same row of pixels are directly electrically connected to the first gate line Gna, and all second polarity pixels are directly electrically connected to the second gate line Gnb, thereby ensuring independent control of pixels of different polarities, and realizing precise gate voltage control of pixels of opposite polarities (i.e., first polarity pixels and second polarity pixels), so that the gate-source voltage difference (Vgs) of the pixel points in each row of pixel units H1 under different polarity conditions can be maintained at a relatively stable level, thereby effectively suppressing the fluctuation of leakage current caused by polarity reversal, avoiding the occurrence of adverse display phenomena such as afterimage, crosstalk, flicker, etc., and significantly improving the display quality of LCD products. In addition, the present application also arranges second polarity pixels between adjacent first polarity pixels, so that pixels of opposite polarity are staggered with each other, which helps to balance the electric field distribution in the display screen and reduce display problems caused by uneven electric field, thereby effectively improving the display quality of LCD products applied to liquid crystal display circuits.

[0060] Further, in some feasible embodiments, referring to Figure 2 as well as Figure 3 , Figure 3 In each row pixel unit H1, when the first gate line Gna provides the first gate driving voltage to each first polarity pixel for charging, the second gate line Gnb provides the second gate driving voltage to each second polarity pixel for charging.

[0061] In this embodiment, in each row of pixel units H1, the present application cleverly implements a timing synchronous gate voltage control strategy. Specifically, when the first gate line Gna provides a first gate drive voltage to all first polarity pixels in the row of pixel units H1 for charging, the second gate line Gnb synchronously provides a second gate drive voltage to all second polarity pixels in the row of pixel units H1 for charging, ensuring that pixels with opposite polarities (i.e., first polarity pixels and second polarity pixels) are synchronously excited by corresponding gate drive voltages in the same time window, effectively avoiding display problems caused by the first gate drive voltage and the second gate drive voltage being out of sync, and eliminating the gate-source voltage difference between pixels of different polarities in the row of pixel units H1 through gate voltages of different magnitudes output by different gate lines, thereby significantly improving the display quality of LCD products applied to liquid crystal display circuits.

[0062] In a specific embodiment, Figure 3 Gna in represents the first gate line Gna, Figure 2 DO in the figure indicates that the polarity of the output data signal is positive. Figure 2 Gnb in the figure represents the second gate line Gnb, Figure 2 DE in FIG. 1 represents a data signal line S1 that outputs a data signal having a negative polarity. Exemplarily, taking the driving of the pixel array 10 in the Nth frame as an example, when the positive polarity pixels in the row pixel unit H1 are driven by the first gate driving voltage (Gna-Vgh) output by the first gate line Gna to perform pixel positive charging, the negative polarity pixels in the row pixel unit H1 are driven by the second gate driving voltage (Gnb-Vgh) output by the second gate line Gnb to perform pixel negative charging synchronously, so that the first gate driving voltage (Gna-Vgh) transmitted by the first gate line Gna to the positive polarity pixels in the row pixel unit H1 and the second gate driving voltage (Gnb-Vgh) transmitted by the second gate line Gnb to the negative polarity pixels in the row pixel unit H1 are in a synchronous state in terms of timing, and the first gate driving voltage (Gna-Vgh) output by the first gate line Gna and the second gate driving voltage (Gnb-Vgh) output by the second gate line Gnb are different in magnitude, thereby eliminating the gate-source voltage difference between pixels of different polarities in the row pixel unit H1, thereby significantly improving the display quality of LCD products applied to liquid crystal display circuits.

[0063] Further, in some other feasible embodiments, referring to Figures 2 to 3, if the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the Nth frame is the first level VgL, after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the positive charging of the pixel, the first level VgL is switched to the second level VL, until the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel is switched from positive polarity to negative polarity, then the second level VL is switched to the first level VgL as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the N+1th frame; or,

[0064] If the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off state at the Nth frame is the first level VgL, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the positive charging of the pixel, the first level VgL is switched to the second level VL, until the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel is switched from positive polarity to negative polarity, then the second level VL is switched to the first level VgL, as the gate line voltage input to the first gate line Gna connected to the second polarity pixel in the off state at the N+1th frame; wherein the first level VgL is lower than the second level VL.

[0065] In the present embodiment, the present application may regard the first polarity pixel or the second polarity pixel as a positive polarity pixel. Exemplarily, if the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the Nth frame is the first level VgL, and after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the positive charging of the pixel, the first level VgL is switched to the second level VL, until the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel is switched from positive polarity to negative polarity, then the second level VL is switched to the first level VgL, as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the N+1 frame; or, if the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off state at the Nth frame is the first level VgL, and the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the positive charging of the pixel After that, the first level VgL is switched to the second level VL, until the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel is switched from positive polarity to negative polarity, then the second level VL is switched to the first level VgL, which is the gate line voltage input by the first gate line Gna connected to the off state of the second polarity pixel in the N+1th frame. When the polarity of the data signal provided by the data signal line S1 is reversed in consecutive frames, the gate line voltage is dynamically adjusted according to the change of pixel polarity, ensuring that the pixel polarity of each pixel point in the row pixel unit H1 can achieve smooth transition between different frames, avoiding display problems caused by voltage mismatch, such as brightness flicker, color distortion, etc.; it also reduces the charge accumulation and afterimage phenomenon caused by displaying the same polarity image for a long time, improves the display stability and clarity, and thus significantly improves the display quality of LCD products.

[0066] It should be noted that both the first level VgL and the second level VL represent low-level signals, and the low-level voltage of the first level VgL is lower than the low-level voltage of the second level VL.

[0067] Further, in some feasible embodiments, referring to Figures 2 to 3, if the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the Nth frame is the first level VgL, after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the pixel negative charging, the gate line voltage connected to the first polarity pixel when it is switched from the on state to the off state in the Nth frame maintains the first level VgL unchanged, and when the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel is switched from negative polarity to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the N+1th frame; or Alternatively, if the second polarity pixel is a negative polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off state at the Nth frame is the first level VgL, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected to the second polarity pixel when it switches from the on state to the off state in the Nth frame maintains the first level VgL unchanged, and when the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the second polarity pixel in the off state at the N+1th frame.

[0068] In this embodiment, the present application may regard the first polarity pixel or the second polarity pixel as a negative polarity pixel. Exemplarily, if the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the Nth frame is the first level VgL, after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected to the first polarity pixel when it switches from the on state to the off state in the Nth frame maintains the first level VgL unchanged, and when the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel switches from negative polarity to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state at the N+1 frame; or, if the second polarity pixel is a negative polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off state at the Nth frame is the first level Vg L, after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected to the second polarity pixel when it switches from the on state to the off state in the N frame maintains the first level VgL unchanged, and when the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the off state of the second polarity pixel in the N+1 frame, so that the gate line voltage can be adjusted in time according to the change of the polarity of the data signal, so that the pixel polarity working state of each pixel point in the row pixel unit H1 can better adapt to the display requirements, effectively improve the problem of different leakage current caused by pixel polarity reversal, thereby reducing the occurrence of display quality problems such as afterimage, crosstalk, flicker, etc., and significantly improving the display quality of LCD products.

[0069] Further, in some feasible embodiments, referring to Figure 4 , Figure 41. It is a circuit schematic diagram involved in an embodiment of a liquid crystal display circuit of the present application, wherein the first polarity pixel includes a first pixel electrode and a first thin film transistor T1, wherein a first passage end of the first thin film transistor T1 is electrically connected to the first pixel electrode, a gate end of the first thin film transistor T1 is electrically connected to the first gate line Gna, and a second passage end of the first thin film transistor T1 constitutes a data line identification end of the first polarity pixel and is electrically connected to a corresponding data signal line S1; the second polarity pixel includes a second pixel electrode and a second thin film transistor T2, wherein a first passage end of the second thin film transistor T2 is electrically connected to the second pixel electrode, a gate end of the second thin film transistor T2 is electrically connected to the second gate line Gnb, and a second passage end of the second thin film transistor T2 constitutes a data line identification end of the second polarity pixel and is electrically connected to a corresponding data signal line S1; wherein the first pixel electrode is opposite to the second pixel electrode, and the first thin film transistor T1 is the same as the second thin film transistor T2.

[0070] It should be noted that Figure 4 The thin film transistor electrically connected to the first gate line Gna is the first thin film transistor T1. Figure 4 The thin film transistor electrically connected to the second gate line Gnb is the second thin film transistor T2.

[0071] In this embodiment, refer to Figure 4 , taking the first polarity pixel as a positive polarity pixel and the second polarity pixel as a negative polarity pixel as an example, the present application controls each positive polarity pixel in each row using the first gate line Gna, and each negative polarity pixel using the second gate line Gnb, and provides different gate voltages through two gate lines (i.e., the first gate line Gna and the second gate line Gnb) to satisfy that different polarity pixels correspond to different gate line voltages Vg, and the gate line voltage Vg is switched between the first level VgL and the second level VL. Exemplary, refer to Figure 3 as well as Figure 4In the Nth frame, the present application sets the first polarity pixel as a positive polarity pixel electrically connected to the first gate line Gna, and the second polarity pixel as a negative polarity pixel electrically connected to the second gate line Gnb, and before the first gate line Gna inputs the first gate driving voltage (Gna-Vgh) to the positive polarity pixel of the Nth frame, the present application sets the first gate line Gna in each row to provide the gate line voltage Vg to the positive polarity pixel as the first level VgL, and when the positive polarity pixel completes the pixel positive charging of the first pixel electrode under the driving of the first gate driving voltage (Gna-Vgh), the gate line voltage Vg provided by the first gate line Gna to the positive polarity pixel is the second level VL, until the first polarity pixel in each row is the positive polarity pixel electrically connected to the data signal line S1 When the data signal (i.e., DO) provided in the N+1 frame is switched from positive polarity (Vdh) to negative polarity (Vdl), that is, when the first polarity pixel in each row is switched from positive polarity pixel in the N frame to negative polarity pixel in the N+1 frame, the gate line voltage Vg provided by the first gate line Gna to the first polarity pixel of the N+1 frame when it is a negative polarity pixel is reduced from the second level VL to the first level VgL, and after the first gate line Gna is driven by the first gate driving voltage (Gna-Vgh) provided when the first polarity pixel of the N+1 frame is a negative polarity pixel to complete the negative charging of the pixel of the first pixel electrode, the gate line voltage Vg provided by the first gate line Gna to the first polarity pixel after the negative pixel is charged maintains the first level VgL unchanged.

[0072] In another embodiment, the present application sets the second polarity pixel as a negative polarity pixel electrically connected to the second gate line Gnb in the Nth frame, and the second gate drive voltage (Gnb-Vgh) provided by the second gate line Gnb is synchronized in timing with the first gate drive voltage (Gna-Vgh) provided by the first gate line Gna to the first polarity pixel. Specifically, before the second gate line Gnb inputs the second gate drive voltage (Gnb-Vgh) to the second polarity pixel which is a negative polarity pixel in the Nth frame, the present application also sets the first gate line Gna in each row to provide the gate line voltage Vg as the first level VgL to the second polarity pixel which is a negative polarity pixel in the Nth frame, when the first polarity pixel which is a positive polarity pixel in the Nth frame is connected to the first gate drive voltage (Gna-Vgh), the second polarity pixel which is a negative polarity pixel in the Nth frame is enabled to synchronously connect to the second gate drive voltage (Gnb-Vgh) to negatively charge the second pixel electrode. After completing the negative charging of the second pixel electrode, The gate line voltage Vg provided by the second gate line Gnb to the second polarity pixel maintains the first level VgL unchanged, and when the data signal provided by the data signal line S1 (i.e., DE) electrically connected to the negative polarity pixel in each row switches from negative polarity (Vdl) to positive polarity (Vdh) in the N+1 frame, that is, when the second polarity pixel in each row switches from a negative polarity pixel in the Nth frame to a positive polarity pixel in the N+1 frame, the gate line voltage Vg input to the second polarity pixel after the second gate line Gnb charges the negative pixel is the first level VgL as the gate line voltage connected to the second polarity pixel before the positive polarity pixel in the N+1 frame is turned on.

[0073] Furthermore, in yet another embodiment, Figure 5 Schematic diagram of the switching of the working state of the positive and negative frame pixels involved in an embodiment of the liquid crystal display circuit of the present application. Taking the first polarity pixel as an example, Figure 5 It is illustrated that when the first pixel electrode electrically connected to the first channel end of the first thin film transistor T1 switches from a positive polarity pixel to a negative polarity pixel, the gate line voltage Vg output by the first gate line Gna connected to the gate end of the first thin film transistor T1 switches between a first level VgL and a second level VL, and the switching point is defined as follows: the switching point at which the source voltage Vs of the first thin film transistor T1 increases occurs after the first pixel electrode completes positive charging, that is, Figure 3 At point m of Gna, the gate voltage Vg provided by the first gate line Gna needs to increase from the first level VgL to the second level VL, and the switching point at which the source voltage Vs of the first thin film transistor T1 decreases occurs when the data line switches from positive polarity to negative polarity at the end of a frame, that is, Figure 3At point n of Gna in the middle, the gate voltage Vg provided by the first gate line Gna needs to be reduced from VL to VgL. That is to say, in this application, the pixels of the same polarity in each row are controlled by the same gate line, and the pixels of the other polarity are controlled by another gate line. The two gate lines are given different voltages to meet the different gate line voltages Vg corresponding to pixels of different polarities, but the gate-source voltage Vgs is kept as consistent as possible, and the gate line voltage Vg is adjusted in time according to the change of the polarity of the data signal, so that the pixel polarity working state of each pixel point in the row pixel unit H1 can better adapt to the display requirements, effectively improve the problem of different leakage current caused by pixel polarity inversion, thereby reducing the occurrence of display quality problems such as afterimage, crosstalk, flicker, etc., and significantly improving the display quality of LCD products.

[0074] In summary, the present application connects positive and negative polarity pixels to different gate signal lines respectively, and provides different gate voltages according to the pixel polarity to ensure that the gate-source voltage difference Vgs is as similar as possible for the positive and negative polarities, thereby improving the problem of different leakage currents, thereby reducing the occurrence of display quality problems such as afterimages, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0075] In addition, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes any of the above-mentioned liquid crystal display circuits.

[0076] In addition, the present application also provides a display device. The present application also provides a display device, and the display device includes the above-mentioned display panel.

[0077] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0078] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, a magnetic disk, or an optical disk as described above, and includes a number of instructions for enabling a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0080] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A liquid crystal display circuit, characterized in that: The liquid crystal display circuit comprises: A pixel array, the pixel array comprising column pixel units in columns and row pixel units in rows; A plurality of data signal lines, each of which provides a data signal to a corresponding column of pixel units, the data signals provided by adjacent data signal lines have opposite polarities, and the data signal is a first data signal or a second data signal; A plurality of first gate lines, each of which provides a first gate driving voltage to charge a pixel point in a corresponding row of pixel units that receives the first data signal; A plurality of second gate lines, each of which provides a second gate driving voltage to charge a pixel point in a corresponding row of pixel units that receives the second data signal; wherein, The first data signal and the second data signal have opposite polarities.

2. The liquid crystal display circuit according to claim 1, characterized in that: The data signal provided by each of the data signal lines to the corresponding column pixel unit in the Nth frame has a polarity opposite to that of the data signal provided to the corresponding column pixel unit in the N+1th frame, where N is a natural number greater than zero.

3. The liquid crystal display circuit according to claim 1, characterized in that: Each of the data signal lines is electrically connected to a corresponding column of pixel units; In each of the column pixel units, the polarity of each pixel point is the same as the polarity of the data signal provided by the corresponding data signal line.

4. The liquid crystal display circuit according to claim 1, characterized in that: The pixel points connected to the first data signal constitute first polarity pixels, and the pixel points connected to the second data signal constitute second polarity pixels, and the first polarity pixels are opposite to the second polarity pixels; In each of the row pixel units, a first gate line and a second gate line are relatively arranged on both sides of the pixel points arranged in rows, and the second polarity pixels are arranged between adjacent first polarity pixels. The first gate line is electrically connected to each of the first polarity pixels, and the second gate line is electrically connected to each of the second polarity pixels.

5. The liquid crystal display circuit according to claim 4, characterized in that: In each of the row pixel units, when the first gate line provides the first gate driving voltage to each of the first polarity pixels for charging, the second gate line provides the second gate driving voltage to each of the second polarity pixels for charging.

6. The liquid crystal display circuit according to claim 4, characterized in that: If the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the Nth frame is a first level, and after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the positive charging of the pixel, the first level is switched to a second level until the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel is switched from positive polarity to negative polarity, then the second level is switched to the first level as the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the N+1th frame; or, If the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line connected to the second polarity pixel in the off state at the Nth frame is the first level, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the positive charging of the pixel, the first level is switched to the second level until the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel is switched from positive polarity to negative polarity, then the second level is switched to the first level as the gate line voltage input to the first gate line connected to the second polarity pixel in the off state at the N+1th frame; wherein, The first level is lower than the second level.

7. The liquid crystal display circuit according to claim 4, characterized in that: If the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the Nth frame is a first level, after the first polarity pixel is turned on under the driving of the first gate driving voltage to complete the pixel negative charging, the gate line voltage connected to the first polarity pixel when it is switched from the on state to the off state at the Nth frame maintains the first level unchanged, and when the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel is switched from negative polarity to positive polarity, the first level is used as the gate line voltage input to the first gate line connected to the first polarity pixel in the off state at the N+1th frame; or, If the second polarity pixel is a negative polarity pixel, the gate line voltage input by the second gate line connected to the off state of the second polarity pixel in the Nth frame is a first level, and after the second polarity pixel is turned on under the driving of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected by the second polarity pixel when it switches from the on state to the off state in the Nth frame maintains the first level unchanged, and when the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level is used as the gate line voltage input by the first gate line connected to the off state of the second polarity pixel in the N+1th frame.

8. The liquid crystal display circuit according to claim 4, characterized in that: The first polarity pixel comprises a first pixel electrode and a first thin film transistor, a first channel end of the first thin film transistor is electrically connected to the first pixel electrode, a gate end of the first thin film transistor is electrically connected to the first gate line, and a second channel end of the first thin film transistor constitutes a data line identification end of the first polarity pixel and is electrically connected to a corresponding data signal line; The second polarity pixel comprises a second pixel electrode and a second thin film transistor, a first channel end of the second thin film transistor is electrically connected to the second pixel electrode, a gate end of the second thin film transistor is electrically connected to the second gate line, and a second channel end of the second thin film transistor constitutes a data line identification end of the second polarity pixel and is electrically connected to a corresponding data signal line; wherein, The first pixel electrode is opposite to the second pixel electrode, and the first thin film transistor is the same as the second thin film transistor.

9. A display panel, characterized in that: The display panel comprises a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate comprises the liquid crystal display circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9.

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