Display device

Abstract

A display device is provided. The display device includes a substrate, a circuit layer, and an element layer. The substrate includes a display area and a non-display area. The display area includes an emission area, a non-emission area, and a light sensing area in a portion of the non-emission area. The element layer includes a light emitting element in the light emitting region and a light sensing element in the light sensing region. The circuit layer includes a light emitting pixel driver, a light sensing pixel driver, data lines, read-out lines extending parallel to the data lines, first dummy lines extending in a first direction, and second dummy lines extending in a second direction and respectively paired with the data lines. The first dummy line includes a first readout bypass line electrically connected to the first readout line. The second dummy line includes a first readout connection line electrically connected to the first readout bypass line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0076411 filed in the Korean Intellectual Property Office on June 14, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] An aspect of an embodiment of the present disclosure relates to a display device. Background Art

[0003] With the development of the information society, more and more demands are being placed on display devices for displaying images in various ways. For example, display devices are employed in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0004] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device including a micro-light-emitting element.

[0005] Organic light-emitting display devices use light-emitting elements to display images. Each of the light-emitting elements includes a light-emitting layer made of an organic light-emitting material. Organic light-emitting display devices use self-luminous elements to realize image display, and therefore, compared with other display devices, can have relatively excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area at the periphery of the display area. An emission area for emitting light having corresponding brightness and color may be arranged in the display area.

[0008] The display device may additionally combine various input functions as well as a function of displaying an image to be appropriately applied to various electronic devices.

[0009] For example, the display device may include a scanning function for detecting the curvature of an object in contact with the screen based on a difference in the amount of light reflected from the screen.

[0010] The display device may include a data transmission line electrically connecting the data line to the display driving circuit.

[0011] Furthermore, when a scanning function is incorporated, the display device may further include a light sensing element for detecting the amount of light and a scanning driving circuit for collecting a light sensing signal generated by the light sensing element through a readout line.

[0012] In addition, the display device may further include a readout transmission line for electrically connecting the readout line to the scan driving circuit.

[0013] As such, in the case of a display device that provides a scanning function in addition to a display function, since data transmission lines and readout transmission lines may be arranged in the non-display area, there may be a limitation in reducing the width of the non-display area.

[0014] One or more embodiments of the present disclosure are directed to a display device capable of reducing the width of a non-display area while providing a scanning function.

[0015] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a display area and a non-display area, the display area including an emission area, a non-emission area as a separation area between the emission areas, and a light sensing area in a portion of the non-emission area, the non-display area being around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and including a light emitting element and a light sensing element, the light emitting element is respectively in the emission area, and the light sensing element is respectively in the light sensing area. The circuit layer includes: a light emitting pixel driver, electrically connected to the light emitting element, respectively; a light sensing pixel driver, electrically connected to the light sensing element, respectively; a data line, electrically connected to the light emitting pixel driver; a readout line, electrically connected to the light sensing pixel driver, and extending parallel to the data line; a first dummy line, extending in a first direction crossing the data line, and including a first readout detour line, the first readout detour line being electrically connected to a first readout line among the readout lines; and a second dummy line, extending in a second direction parallel to the data line and crossing the first direction, and paired with the data line, respectively, the second dummy line including a first readout connection line electrically connected to the first readout detour line.

[0016] In an embodiment, the data line, the readout line, and the second dummy line may be located on at least one insulating layer covering the first dummy line.

[0017] In an embodiment, the display device may further include a scanning drive circuit configured to collect light sensing signals from the light sensing element through a light sensing pixel driver and a readout line. The circuit layer may further include a readout transmission line in the non-display area and electrically connected between the readout line and the scanning drive circuit. Among the readout transmission lines, a first readout transmission line configured to transmit a signal of a first readout line may be electrically connected to the first readout line through a first readout connection line and a first readout detour line.

[0018] In an embodiment, the detour area on one side of the display area may include: a central detour middle area; a first detour side area parallel to the detour middle area in a first direction and in contact with the non-display area; a second detour side area between the detour middle area and the first detour side area; and a third detour side area between the first detour side area and the second detour side area. The data line may include: a first data line in the first detour side area; a second data line and a third data line in the second detour side area; and a fourth data line in the third detour side area. The first dummy line may also include a first data detour line electrically connected to the first data line and a second data detour line electrically connected to the fourth data line. The second dummy line may also include: a first data connection line paired with the second data line and electrically connected to the first data detour line; and a second data connection line paired with the third data line and electrically connected to the second data detour line. The first readout connection line may be paired with the fourth data line.

[0019] In an embodiment, the display device may further include a display driving circuit, the display driving circuit being configured to transmit a data signal for a light-emitting pixel driver to a data line, and the circuit layer may further include a data transmission line, the data transmission line being in the non-display area and electrically connected between the data line and the display driving circuit. Among the data transmission lines: a first data transmission line configured to transmit a data signal of a first data line may be electrically connected to the first data line through a first data bypass line and a first data connection line, a second data transmission line configured to transmit a data signal of a second data line may be directly electrically connected to the second data line, a third data transmission line configured to transmit a data signal of a third data line may be directly electrically connected to the third data line, and a fourth data transmission line configured to transmit a data signal of a fourth data line may be electrically connected to the fourth data line through a second data bypass line and a second data connection line.

[0020] In an embodiment, the substrate may include a main area and a sub-area, the main area including a display area and a non-display area, and the sub-area protrudes from one side of the main area in the second direction. The display drive circuit may be in the sub-area of ​​the substrate, and the scan drive circuit may be on a display circuit board connected to the sub-area of ​​the substrate. The data transmission lines may be gathered in a portion of the non-display area adjacent to the second bypass side area, and the readout transmission lines may be gathered in another portion of the non-display area adjacent to the third bypass side area.

[0021] In an embodiment, the first readout line may be located in the second bypass side region, the readout line may also include a second readout line in the third bypass side region, and among the readout transmission lines, a second readout transmission line configured to transmit a signal of the second readout line may be directly electrically connected to the second readout line.

[0022] In an embodiment, the first readout bypass line may include multiple first readout bypass lines, the first data bypass line may include multiple first data bypass lines, the second data bypass line may include multiple second data bypass lines, and at least one of the first readout bypass lines may be located between the first data bypass lines in the second direction, or between the second data bypass lines in the second direction.

[0023] In an embodiment, each of the first detour side area, the second detour side area, and the third detour side area may include: an adjacent area that contacts the non-display area in the second direction; and a separated area that is a remaining area except the adjacent area. The first readout detour line may be located in the adjacent area of ​​each of the first detour side area, the second detour side area, and the third detour side area, and the first data detour line and the second data detour line may be located in the separated area of ​​each of the first detour side area, the second detour side area, and the third detour side area.

[0024] In an embodiment, the bypass area of ​​the display area may further include a fourth bypass side area between the first bypass side area and the third bypass side area, the data line may further include a fifth data line in the fourth bypass side area, and the readout line may further include a third readout line in the first bypass side area and a fourth readout line in the fourth bypass side area. The first dummy line may further include a second readout bypass line electrically connected to the third readout line, and the second dummy line may further include a second readout connection line paired with the fifth data line and electrically connected to the second readout bypass line. Among the readout transmission lines: a third readout transmission line configured to transmit a signal of a third readout line may be electrically connected to the third readout line through a second readout connection line and a second readout bypass line, and a fourth readout transmission line configured to transmit a signal of a fourth readout line may be directly electrically connected to the fourth readout line.

[0025] In an embodiment, the data lines may also include a sixth data line in the second bypass side area, the first dummy line may also include a third data bypass line electrically connected to the fifth data line, and the second dummy line may also include a third data connection line paired with the sixth data line and electrically connected to the third data bypass line.

[0026] In an embodiment, each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area may include: an adjacent area that contacts the non-display area in the second direction; and a separated area that is a remaining area except the adjacent area. The first readout detour line may be located in the adjacent area of ​​each of the second detour side area and the third detour side area, the second readout detour line may be located in the adjacent area of ​​each of the first detour side area and the fourth detour side area, and the first data detour line and the second data detour line may be located in the separated area of ​​each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area.

[0027] In an embodiment, the circuit layer may further include: a first power line and a second power line in the non-display area, and configured to transmit a first power and a second power for driving the light emitting element, respectively. The first dummy line may further include a first auxiliary line electrically connected to the second power line, and the second dummy line may further include a second auxiliary line electrically connected to the first auxiliary line and the second power line.

[0028] In an embodiment, each of the first bypass side area, the second bypass side area, the third bypass side area and the fourth bypass side area may also include a buffer area between the adjacent area and the separation area, and the first auxiliary line may be located in the buffer area of ​​each of the first bypass side area, the second bypass side area, the third bypass side area and the fourth bypass side area.

[0029] In an embodiment, the circuit layer may further include: a first power line and a second power line, in the non-display area, and configured to transmit the first power and the second power for driving the light-emitting element, respectively; and a first power line, electrically connected between the light-emitting pixel driver and the first power line. One of the light-emitting elements may be electrically connected between one of the light-emitting pixel drivers and the second power, and one of the light-sensing elements may be electrically connected between an element output node of one of the light-sensing pixel drivers and the second power. One of the light-emitting pixel drivers may include: a first transistor configured to generate a driving current for driving one of the light-emitting elements; a second transistor electrically connected between one of the data lines and a first electrode of the first transistor; a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor; a fourth transistor electrically connected between a first initialization power line configured to transmit a first initialization power and the gate electrode of the first transistor; a fifth transistor electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and one of the light-emitting elements; a seventh transistor electrically connected between a second initialization power line configured to transmit a second initialization power and one of the light-emitting elements; and an eighth transistor electrically connected between a bias power line configured to transmit a bias power and the first electrode of the first transistor. One of the light-sensing pixel drivers may include: a ninth transistor configured to be turned on according to a voltage level of an element output node; a tenth transistor electrically connected between a reset voltage line configured to transmit a reset voltage and the element output node; and an eleventh transistor electrically connected between one of the readout lines and the ninth transistor.

[0030] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a display area and a non-display area, the display area including an emission area, a non-emission area as a separation area between the emission areas, and a light sensing area in a portion of the non-emission area, the non-display area being around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and including a light emitting element and a light sensing element, the light emitting element being in the emission area, respectively, and the light sensing element being in the light sensing area, respectively. The detour area on one side of the display area includes: a central detour middle area; a first detour side area, parallel to the detour middle area in a first direction, and in contact with the non-display area; a second detour side area, between the detour middle area and the first detour side area; and a third detour side area, between the first detour side area and the second detour side area. The circuit layer includes: light-emitting pixel drivers, which are electrically connected to the light-emitting elements respectively; light-sensing pixel drivers, which are electrically connected to the light-sensing elements respectively; data lines, which are electrically connected to the light-emitting pixel drivers; readout lines, which are electrically connected to the light-sensing pixel drivers and extend parallel to the data lines; a first data bypass line, which extends in a first direction crossing the data lines and is electrically connected to a first data line among the data lines in a first bypass side region; a first readout bypass line, which extends in the first direction crossing the data lines and is electrically connected to a first readout line among the readout lines; a first data connection line, which extends in a second direction parallel to the data lines and crossing the first direction, the first data connection line is paired with a second data line among the data lines in a second bypass side region and is electrically connected to the first data bypass line; and a first readout connection line, which extends in the second direction and is electrically connected to the first readout bypass line.

[0031] In an embodiment, the data line may further include a third data line in the second detour side region and a fourth data line in the third detour side region. The first readout connection line may be paired with the fourth data line, and the circuit layer may further include: a second data detour line extending in the first direction and electrically connected to the fourth data line; and a second data connection line extending in the second direction, paired with the third data line, and electrically connected to the second data detour line.

[0032] In an embodiment, the display device may further include: a scanning drive circuit configured to collect light sensing signals from the light sensing element through a light sensing pixel driver and a readout line; and a display drive circuit configured to transmit a data signal for the light emitting pixel driver to a data line. The circuit layer may further include: a readout transmission line in a non-display area and electrically connected between the readout line and the scanning drive circuit; and a data transmission line in a non-display area and electrically connected between the data line and the display drive circuit. In the data transmission line: a first data transmission line configured to transmit a data signal of a first data line may be electrically connected to the first data line through a first data bypass line and a first data connection line, a second data transmission line configured to transmit a data signal of a second data line may be directly electrically connected to the second data line, a third data transmission line configured to transmit a data signal of a third data line may be directly electrically connected to the third data line, and a fourth data transmission line configured to transmit a data signal of a fourth data line may be electrically connected to the fourth data line through a second data bypass line and a second data connection line. Among the readout transmission lines, a first readout transmission line configured to transmit a signal of the first readout line may be electrically connected to the first readout line through a first readout connection line and a first readout bypass line.

[0033] In an embodiment, the readout line may further include a second readout line in the third detour side region, and among the readout transmission lines, a second readout transmission line configured to transmit a signal of the second readout line may be directly electrically connected to the second readout line.

[0034] In an embodiment, the first readout bypass line may include multiple first readout bypass lines, the first data bypass line may include multiple first data bypass lines, the second data bypass line may include multiple second data bypass lines, and at least one of the first readout bypass lines may be located between the first data bypass lines in the second direction, or between the second data bypass lines in the second direction.

[0035] In an embodiment, each of the first detour side area, the second detour side area, and the third detour side area may include: an adjacent area that contacts the non-display area in the second direction; and a separated area that is a remaining area except the adjacent area. The first readout detour line may be located in the adjacent area of ​​each of the first detour side area, the second detour side area, and the third detour side area, and the first data detour line and the second data detour line may be located in the separated area of ​​each of the first detour side area, the second detour side area, and the third detour side area.

[0036] In an embodiment, the detour area of ​​the display area may further include a fourth detour side area between the first detour side area and the third detour side area, the data line may further include a fifth data line in the fourth detour side area and a sixth data line in the second detour side area, and the readout line may further include a third readout line in the first detour side area and a fourth readout line in the fourth detour side area. The circuit layer may further include: a second readout detour line extending in the first direction and electrically connected to the third readout line; a second readout connection line extending in the second direction, paired with the fifth data line, and electrically connected to the second readout detour line; a third data detour line extending in the first direction and electrically connected to the fifth data line; and a third data connection line extending in the second direction, paired with the sixth data line, and electrically connected to the third data detour line. Among the readout transmission lines: a third readout transmission line configured to transmit a signal of the third readout line may be electrically connected to the third readout line through the second readout connection line and the second readout detour line, and a fourth readout transmission line configured to transmit a signal of the fourth readout line may be directly electrically connected to the fourth readout line.

[0037] In an embodiment, the fourth detour side area may include an adjacent area contacting the non-display area in the second direction and a separated area as a remaining area other than the adjacent area. The first readout detour line may be located in the adjacent area of ​​each of the second detour side area and the third detour side area, the second readout detour line may be located in the adjacent area of ​​each of the first detour side area and the fourth detour side area, and the first data detour line and the second data detour line may be located in the separated area of ​​each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area.

[0038] In an embodiment, the circuit layer may further include: a first power line and a second power line in the non-display area and configured to transmit the first power and the second power for driving the light emitting element, respectively; and a first auxiliary line extending in the first direction and electrically connected to the second power line. Each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area may further include a buffer area between the adjacent area and the separation area, and the first auxiliary line may be located in the buffer area of ​​each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area.

[0039] According to one or more embodiments of the present disclosure, a display device may include a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate may include a display area in which an emission area is arranged and a non-display area disposed around the display area (e.g., adjacent to the display area). The display area may include a non-emitting area as a separation area between the emission areas and a light sensing area disposed in a portion of the non-emitting area. The element layer may include light emitting elements disposed in the emission area and light sensing elements disposed in the light sensing area, respectively. The circuit layer may include: light emitting pixel drivers, electrically connected to the light emitting elements, respectively; light sensing pixel drivers, electrically connected to the light sensing elements, respectively; data lines, electrically connected to the light emitting pixel drivers; readout lines, electrically connected to the light sensing pixel drivers and extending parallel to or substantially parallel to the data lines; first dummy lines, extending in a first direction crossing the data lines; and second dummy lines, extending in a second direction parallel to or substantially parallel to the data lines and paired with the data lines, respectively. The first dummy line may include a first readout detour line electrically connected to a first readout line as one of the readout lines, and the second dummy line includes a first readout connection line electrically connected to the first readout detour line.

[0040] According to one or more embodiments of the present disclosure, the display device may further include a scanning drive circuit for collecting light sensing signals of the light sensing element through a light sensing pixel driver and a readout line. The circuit layer may further include a readout transmission line disposed in the non-display area and electrically connected between the readout line and the scanning drive circuit. Among the readout transmission lines, a first readout transmission line that transmits a signal of the first readout line may be electrically connected to the first readout line through a first readout connection line and a first readout detour line.

[0041] According to one or more embodiments of the present disclosure, the detour area on one side of the display area may include: a central detour middle area; a first detour side area parallel to the detour middle area in the first direction and in contact with the non-display area; a second detour side area disposed between the detour middle area and the first detour side area; and a third detour side area disposed between the first detour side area and the second detour side area. The data line may include: a first data line disposed in the first detour side area; a second data line and a third data line disposed in the second detour side area; and a fourth data line disposed in the third detour side area. The first dummy line may include a first data detour line electrically connected to the first data line and a second data detour line electrically connected to the fourth data line. The second dummy line may include: a first data connection line paired with the second data line and electrically connected to the first data detour line; and a second data connection line paired with the third data line and electrically connected to the second data detour line. The first readout connection line may be paired with the fourth data line.

[0042] According to one or more embodiments of the present disclosure, the display device may further include a display driving circuit, which is used to transmit the data signal of the light-emitting pixel driver to the data line. The circuit layer may also include a data transmission line arranged in the non-display area and electrically connected between the data line and the display driving circuit. Among the data transmission lines, the first data transmission line may be electrically connected to the first data line through the first data bypass line and the first data connection line. Among the data transmission lines, the second data transmission line and the third data transmission line may be directly electrically connected to the second data line and the third data line. Among the data transmission lines, the fourth data transmission line may be electrically connected to the first data line through the second data bypass line and the second data connection line.

[0043] According to one or more embodiments of the present disclosure, a first data line in a first bypass side area among the data lines may be electrically connected to a first data transmission line through a first data connection line and a first data bypass line in a second bypass side area. A fourth data line in a third bypass side area among the data lines may be electrically connected to a fourth data transmission line through a second data connection line and a second data bypass line in the second bypass side area. Therefore, the first data transmission line and the fourth data transmission line may extend to a second bypass side area relatively adjacent to the sub-area, without extending to the first bypass side area and the third bypass side area. Therefore, the extension length of each of the first data transmission line and the fourth data transmission line may be reduced, and therefore, the width of the non-display area may be reduced.

[0044] According to one or more embodiments of the present disclosure, the first readout line among the readout lines can be electrically connected to the first readout transmission line through the first readout connection line of the third detour side area and the first readout detour line. Therefore, the first readout transmission line can extend to the first readout connection line of the third detour side area without extending to the first readout line. Therefore, because the extension length of the first readout transmission line set in the non-display area can be reduced, the width of the non-display area can be further reduced.

[0045] According to one or more embodiments of the present disclosure, a display device may include a readout line and a readout transmission line electrically connected between a light sensing element and a scanning drive circuit to embed a scanning function, but the length of the first readout transmission line may be reduced by a first readout bypass line and a first readout connection line, thereby reducing the width of a non-display area.

[0046] According to one or more embodiments of the present disclosure, the ratio of a display area on a display surface can be increased, and thus, the display quality of a display device can be improved.

[0047] However, aspects and features of the present disclosure are not limited to the above-described aspects and features, and additional aspects and features will be set forth in part in the description that follows and in part may be apparent from the description, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0049] Figure 1 is a perspective view of an electronic device according to one or more embodiments;

[0050] Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in ;

[0051] Figure 3 It is shown Figure 2 A plan view of a display device;

[0052] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA';

[0053] Figure 5 It is shown Figure 3 an enlarged layout diagram of part B;

[0054] Figure 6 It is shown Figure 5 A diagram of the scanning function of the light sensing area shown in FIG.

[0055] Figure 7 yes Figure 4 The block diagram of the circuit layer;

[0056] Figure 8 yes Figure 7 An equivalent circuit diagram of a light emitting pixel driver and a light sensing pixel driver shown in;

[0057] Fig. 9 It is shown Figure 8 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light emitting element;

[0058] Fig.10 is a diagram showing a method according to one or more embodiments Figure 2 A plan view of the base;

[0059] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Fig.10 an enlarged layout diagram of a portion C;

[0060] Fig.12 It is along Fig.11 A cross-sectional view taken along line D-D'; and

[0061] Figures 13 to 15 is a diagram showing a method according to one or more embodiments Fig.10 An enlarged layout diagram of portion C. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0063] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0064] In the accompanying drawings, for the sake of clarity, the relative sizes, thicknesses and ratios of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatially relative terms such as "under ... ", "under ... ", "lower (lower)", "under ... ", "above ... ", "upper (upper)" etc. may be used herein to describe the relationship between an element or feature and another (other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as "under" or "under" or "below" other elements or features will then be oriented to "above" other elements or features. Therefore, the example terms "under ... " and "under ... " can cover two orientations of above ... and below ... ". The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatially relative descriptive words used herein should be interpreted accordingly.

[0065] As used herein, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "superimposed" or "superimposed" means that a first object may be above or below a second object or on the side of the second object, and / or vice versa. In addition, the term "superimposed" may include layers, stacks, facing or facing, extending above, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will appreciate and understand. The expression "non-superimposed" may include "away from" or "on the side of" or "offset from" and any other suitable equivalents that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" may mean that a first object may be directly or indirectly opposite to a second object. In the case where a third object is placed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0066] In the drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0067] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, first component, first region, first layer or first part.

[0068] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, the element or layer may be directly on, directly connected to, or directly bound to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to one or more intervening layers, regions, or elements therebetween. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0069] The terms used herein are for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when the terms "include", "comprise", "have" and their variations are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or components is explained, but the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups is not excluded. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. For example, the statement "A and / or B" means A, B or A and B. Statements such as "at least one (kind / person) in ... ", when after (before) a column of elements, modify the entire column of elements, rather than modifying the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0070] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent variation in measured or calculated values ​​that one of ordinary skill in the art will recognize. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "can" means "one or more embodiments of the present disclosure." As used herein, the term "using" and its variations can be considered synonymous with the term "utilizing" and its variations, respectively.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0072] Figure 1 is a perspective view of an electronic device according to one or more embodiments. Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in FIG.

[0073] Reference Figure 1The electronic device 10 according to the embodiment is a device having a function for displaying an image in a display area. The electronic device 10 may be a portable device. For example, the electronic device 10 may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0074] However, the present disclosure is not limited thereto, and the electronic device 10 may be a large device such as a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) device.

[0075] The electronic device 10 according to the embodiment may include a cover window 11 and a lower cover 12. The cover window 11 and the lower cover 12 may be provided to protect the display device 100 (eg, see Figure 2 ) shell.

[0076] Reference Figure 2 The electronic device 10 may further include a display device 100 , a bracket 13 , and a main circuit board 14 accommodated between the cover window 11 and the lower cover 12 .

[0077] The display device 100 may include a main area MA and a sub area SBA protruding from one side of the main area MA. The main area MA may include a display area DA displaying an image and a non-display area NDA around (eg, adjacent to) the display area DA.

[0078] The display device 100 may also include a display driving circuit 200 disposed in the sub-area SBA, a display circuit board 300 connected to (e.g., joined to or attached to) one side of the sub-area SBA, a touch driving circuit 400 and a scan driving circuit 500 on (e.g., mounted on) the display circuit board 300, and a cable 600 extending from one side of the display circuit board 300.

[0079] As used in this specification, the first direction DR1 may be a direction parallel or substantially parallel to the short side of the electronic device 10 in a plan view, or in other words, may be a horizontal direction of the electronic device 10. The second direction DR2 may be a direction parallel or substantially parallel to the long side of the electronic device 10 in a plan view, or in other words, may be a vertical direction of the electronic device 10. The third direction DR3 may be a thickness direction of the electronic device 10.

[0080] The electronic device 10 may have a shape similar to or the same as a rectangular shape in a plan view. For example, in a plan view, the electronic device 10 may have a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2. Corners where the short sides extending in the first direction DR1 and the long sides extending in the second direction DR2 meet each other may be right angles or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the electronic device 10 is not limited to a rectangular shape, and may be formed into other polygonal shapes, a circular shape, or an elliptical shape.

[0081] The cover window 11 may be disposed on the display device 100 to cover the top surface of the display device 100. The cover window 11 may serve to protect the top surface of the display device 100.

[0082] The cover window 11 may include a transparent light-transmitting portion and an opaque light-shielding portion.

[0083] The light transmitting portion may overlap the display area DA of the display device 100 in the third direction DR3 , and the light shielding portion may overlap the non-display area NDA of the display device 100 in the third direction DR3 .

[0084] The cover window 11 may include a top surface portion forming a top surface of the electronic device 10, a left surface portion forming a left side surface of the electronic device 10, and a right surface portion forming a right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and the right surface portion of the cover window 11 may extend from the right side of the top surface portion.

[0085] Each of the top surface portion, the left surface portion, and the right surface portion of the cover window 11 may include a light-transmitting portion and a light-shielding portion.

[0086] The light-transmitting portion of the cover window 11 may be provided in most part of each of the top surface portion, the left surface portion, and the right surface portion of the cover window 11 .

[0087] The shading portion of the cover window 11 can be set at the upper edge and lower edge of the top surface portion of the cover window 11, the upper edge, left edge and lower edge of the left surface portion of the cover window 11, and the upper edge, right edge and lower edge of the right surface portion of the cover window 11.

[0088] The display device 100 may be disposed under the cover window 11 .

[0089] In other words, the cover window 11 may be disposed on or above the display device 100 .

[0090] The display device 100 may include a main area MA serving as a display surface and a sub area SBA protruding from one side of the main area MA.

[0091] The main area MA may include a display area DA for displaying an image and a non-display area NDA which is a peripheral area of ​​the display area DA.

[0092] The display area DA may be disposed in most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0093] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be an edge area of ​​the main area MA.

[0094] The sub region SBA may protrude from one side of the main region MA in the second direction DR2.

[0095] The length of the subregion SBA in the first direction DR1 may be less than or equal to the length of the main region MA in the first direction DR1. The length of the subregion SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2, but the disclosure is not limited thereto.

[0096] Since a portion of the sub-area SBA may be transformed into a curve, another portion of the sub-area SBA may overlap the main area MA in the third direction DR3.

[0097] The display driving circuit 200 may be disposed in the sub-area SBA.

[0098] The display device 100 may include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from the left side of the top surface portion, and the right surface portion of the display device 100 may extend from the right side of the top surface portion.

[0099] Each of the top, left, and right surface portions of the display device 100 may include a display area DA and a non-display area NDA.

[0100] The display area DA may be provided in most part of each of the top surface portion, the left surface portion, and the right surface portion of the display device 100 .

[0101] The non-display area NDA may be disposed at the upper and lower edges of the top surface portion of the display device 100 , at the upper, left and lower edges of the left surface portion of the display device 100 , and at the upper, right and lower edges of the right surface portion of the display device 100 .

[0102] The display driving circuit 200 may be mounted in the sub-area SBA of the display device 100 , and the display circuit board 300 may be attached to the display driving circuit 200 .

[0103] One end of the display circuit board 300 may be attached to a pad (also referred to as a “pad” or “soldering pad”) disposed on a lower edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0104] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape or a substantially flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0105] The display driving circuit 200 may drive the light emitting pixel driver EPD (eg, see FIG. 1 ) of the display area DA based on the control signal and the power voltage supplied from the display circuit board 300. Figure 7 ) of the data signal Vdata (for example, see Figure 8 ) is transmitted to the data line DL.

[0106] The display driving circuit 200 may be provided as an integrated circuit (IC) and may be mounted in the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, the present disclosure is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0107] According to an embodiment, the touch driving circuit 400 and the scan driving circuit 500 may also be installed in the sub-area SBA of the display device 100 .

[0108] In another embodiment, if Figure 2 As shown in , the touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0109] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 (eg, see FIG. 1 ) of the display device 100. Figure 4 ).

[0110] The scanning driving circuit 500 can detect the light of the display area DA through the light sensing pixel driver DPD (for example, see Figure 7 ) and the readout line ROL (see, for example, Figure 7 ) is electrically connected to the light sensing element PD (for example, see Figure 8 ).

[0111] The bracket 13 may be disposed under the display device 100 .

[0112] The bracket 13 may include plastic, metal, or both. The bracket 13 may include a first camera hole CMH1, a battery hole BH, and a cable hole CAH, the camera 16 may be inserted into the first camera hole CMH1, the battery 18 may be disposed in the battery hole BH, and the cable 600 connected to the display circuit board 300 may pass through the cable hole CAH.

[0113] The main circuit board 14 and the battery 18 may be disposed under the bracket 13. The main circuit board 14 may be a printed circuit board or a flexible printed circuit board.

[0114] The main circuit board 14 may include a main processor 15, a camera 16, and a main connector 17. The main processor 15 may be formed as an integrated circuit.

[0115] The camera 16 may be disposed on both the top and bottom surfaces of the main circuit board 14. The main processor 15 may be disposed on the top surface of the main circuit board 14, and the main connector 17 may be disposed on the bottom surface of the main circuit board 14.

[0116] The main processor 15 may control all overall functions of the electronic device 10 .

[0117] For example, the main processor 15 may output digital video data to the display driving circuit 200 through the display circuit board 300, so that the display device 100 displays an image. In addition, the main processor 15 may receive touch data including the user's touch coordinates from the touch driving circuit 400, determine whether the user has touched or approached the display device 100 or the electronic device 10, and then perform an operation corresponding to the user's touch input or approach input. For example, the main processor 15 may perform an operation or execute an application indicated by an icon touched by the user.

[0118] In addition, the main processor 15 may receive scan data from the scan driving circuit 500 and perform an operation or execute an application based on whether the scan data is valid.

[0119] The main processor 15 may be an application processor formed of an integrated circuit, a central processing unit, or a system chip.

[0120] The camera 16 may process image frames of still images or videos obtained by an image sensor in a camera mode and output the image frames to the main processor 15 .

[0121] The cable 600 passing through the cable hole CAH of the bracket 13 may be connected to the main connector 17. Thus, the main circuit board 14 may be electrically connected to the display circuit board 300.

[0122] The battery 18 may be disposed so as not to overlap the main circuit board 14 in the third direction DR3. The battery 18 may overlap the battery hole BH of the bracket 13 in the third direction DR3.

[0123] In addition, the main circuit board 14 may also be equipped with a mobile communication module (e.g., a mobile communication circuit or a mobile communication device) capable of transmitting and receiving radio signals with at least one of a base station, an external terminal, and a server in a mobile communication network. The radio signals may include various suitable types of data according to the transmission and reception of voice signals, video call signals, or text / multimedia messages.

[0124] The lower cover 12 may be disposed below the main circuit board 14 and the battery 18. The lower cover 12 may be fixed by being fastened to the bracket 13. The lower cover 12 may form an upper side surface, a lower side surface, and a bottom surface of the electronic device 10. The lower cover 12 may include plastic, metal, or both plastic and metal.

[0125] The lower cover 12 may include a second camera hole CMH2 through which the bottom surface of the camera 16 is exposed. The position of the camera 16 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera 16 are not limited to Figure 2 The location shown in .

[0126] Hereinafter, the display device 100 according to one or more embodiments of the present disclosure will be described in more detail.

[0127] Figure 3 It is shown Figure 2 A plan view of a display device. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'. Figure 5 It is shown Figure 3 An enlarged layout diagram of portion B.

[0128] Figure 3 and Figure 4 The display device 100 is shown in which a portion of the sub-area SBA is in a bent state.

[0129] The display device 100 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro-light-emitting display including a micro-light-emitting diode or a nano-light-emitting diode (LED). For convenience, the display device 100 will be described in more detail below using an organic light-emitting display device as a representative example. However, the present disclosure is not limited thereto, and the embodiments described herein may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0130] The display device 100 may be formed to be flat or substantially flat, but the present disclosure is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, folded, or curled.

[0131] Reference Figure 3 , at least one surface of the display device 100 includes a main area MA, and light for displaying an image is emitted from the main area MA.

[0132] In a plan view, the display area DA may be formed in a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. Corners where the short sides extending in the first direction DR1 and the long sides extending in the second direction DR2 meet each other may be rounded to have a curvature (e.g., a predetermined curvature) or may be right angles. The planar shape of the display area DA is not limited to a rectangular shape and may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0133] The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0134] Reference Figure 4 , the display device 100 includes a sub-area SBA protruding from one side of the main area MA.

[0135] The sub-region SBA may be a region protruding to one side from the non-display region NDA of the main region MA in the second direction DR2.

[0136] Since a portion of the sub-area SBA turns into a curve, another portion of the sub-area SBA may be disposed on the rear surface of the display device 100 .

[0137] The display device 100 according to one or more embodiments includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0138] According to one or more embodiments, the display device 100 may further include an encapsulation layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140. In addition, the display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0139] The substrate 110 may include a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA in the second direction DR2 .

[0140] The main area MA of the substrate 110 may include a display area DA at most of the center of the main area MA and a non-display area NDA at the periphery of the display area DA.

[0141] The sub region SBA may protrude from one side of the main region MA in the second direction DR2.

[0142] Reference Figure 5 , the display area DA includes the emission areas EA, the non-emission areas NEA as separation areas between the emission areas EA, and the light sensing areas ODA disposed in portions of the non-emission areas NEA.

[0143] Each of the emission areas EA may be a unit that emits light in a wavelength band corresponding to one color among two or more different colors having brightness corresponding to an image signal.

[0144] Each of the emission areas EA may have a rhombus planar shape or a rectangular planar shape. However, the present disclosure is not limited thereto, and the planar shape of the emission area EA is not limited to Figure 5 In other words, the emission area EA may have a polygonal shape (such as a diamond shape or a hexagonal shape) other than a rectangular shape, a circular shape, or an elliptical shape in a plan view.

[0145] The emission area EA may include a first emission area EA1 for emitting light of a first color having a desired wavelength band (e.g., a predetermined wavelength band), a second emission area EA2 for emitting light of a second color, and a third emission area EA3 for emitting light of a third color, the second color having a wavelength band lower than the wavelength band of the first color, and the third color having a wavelength band lower than the wavelength band of the second color.

[0146] For example, the first color may be red having a wavelength band of about 600 nm to about 750 nm, the second color may be green having a wavelength band of about 480 nm to about 560 nm, and the third color may be blue having a wavelength band of about 370 nm to about 460 nm. However, the present disclosure is not limited thereto, and the wavelength bands of the first color, the second color, and the third color may be modified differently as needed or desired.

[0147] Because the emission area EA includes a first emission area EA1, a second emission area EA2, and a third emission area EA3, each of the plurality of unit pixels UPX may be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2, and one or more third emission areas EA3 that are adjacent to each other in the emission area EA.

[0148] Each of the unit pixels UPX may be a unit for displaying various suitable colors including white. In other words, various suitable colors of light displayed by the unit pixel UPX may be implemented as a mixture of light emitted from two or more emission areas EA included in each unit pixel UPX.

[0149] In the case where the first color of the first emission area EA1, the second color of the second emission area EA2, and the third color of the third emission area EA3 are red, green, and blue, respectively, the third emission area EA3 may have a size larger than that of the first emission area EA1 (e.g., a width larger than the width of the first emission area EA1), and the second emission area EA2 may have a size smaller than that of the first emission area EA1 (e.g., a width smaller than the width of the first emission area EA1). However, the present disclosure is not limited thereto, and the width of the emission area EA is not limited to Figure 5 Width shown in .

[0150] In addition, the first emission regions EA1 and the third emission regions EA3 may be alternately arranged along the second direction DR2. The second emission regions EA2 may be arranged side by side with each other along the second direction DR2 and may be disposed between the first emission regions EA1 and the third emission regions EA3 along the first direction DR1.

[0151] In this case, each of the unit pixels UPX may include one first emission area EA1 and one third emission area EA3 adjacent to each other in the second direction DR2 and two second emission areas EA2 adjacent to them in the first direction DR1. However, the present disclosure is not limited thereto, and the arrangement pattern of the emission areas EA and the components of the unit pixels UPX are not limited to Figure 5 The arrangement pattern of the emission area EA and the components of the unit pixel UPX shown in FIG.

[0152] According to one or more embodiments, the display area DA includes the light sensing area ODA disposed in a portion of the non-emission area NEA.

[0153] For example, the light sensing area ODA may be disposed between the second emission areas EA2 having a relatively small width in the second direction DR2. One or more emission areas EA may be disposed between the light sensing areas ODA in each of the first direction DR1 and the second direction DR2.

[0154] like Figure 4 According to one or more embodiments, the element layer 130 includes light emitting elements LE (eg, see Figure 8 ) and light sensing elements PD respectively arranged in the light sensing areas ODA.

[0155] According to one or more embodiments, Figure 7 As shown in the figure, the circuit layer 120 may include light-emitting pixel drivers EPD respectively electrically connected to the light-emitting elements LE of the element layer 130, light-sensing pixel drivers DPD respectively electrically connected to the light-sensing elements PD of the element layer 130, data lines DL electrically connected to the light-emitting pixel drivers EPD, and read-out lines ROL electrically connected to the light-sensing pixel drivers DPD.

[0156] The encapsulation layer 140 may cover the element layer 130, and may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0157] The touch sensor layer 150 may be disposed on the encapsulation layer 140 and may correspond to the main area MA. The touch sensor layer 150 may include a touch electrode for sensing a touch of a user or an object.

[0158] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , the circuit layer 120 , and / or interfaces thereof to prevent or substantially prevent degradation of visibility of an image due to external light reflection.

[0159] Since a portion of the sub-area SBA is transformed into a bent shape, the display driving circuit 200 mounted in the sub-area SBA and the display circuit board 300 connected to one side of the sub-area SBA may be disposed under the substrate 110 .

[0160] The display driving circuit 200 may be electrically connected to the data lines DL of the circuit layer 120. The display driving circuit 200 may transmit data signals for the light emitting pixel driver EPD to the data lines DL based on control signals and power voltages supplied from the display circuit board 300.

[0161] The display driving circuit 200 may be provided as an integrated circuit (IC) and may be mounted in the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, the present disclosure is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0162] One end of the display circuit board 300 may be attached to a pad disposed on one edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0163] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape or a substantially flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0164] The display circuit board 300 may be connected to a signal pad SPD (eg, see Fig.10 ).

[0165] The touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0166] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 of the display device 100 .

[0167] The touch drive circuit 400 may apply a touch drive signal to the drive line of the touch sensor layer 150, and may receive a touch sensing signal from the sensing line. In addition, the touch drive circuit 400 may detect the amount of charge change of the capacitor based on the touch sensing signal, thereby determining whether the user has touched or approached. The user's touch may refer to an object (such as a pen or a user's finger) that is in direct contact with the top surface of the cover window 11 disposed on the touch sensor layer 150. The user's approach may refer to an object (such as a pen or a user's finger) that hovers above the top surface of the cover window 11 at a suitable distance (e.g., a predetermined distance). The touch drive circuit 400 may output touch data including the user's touch coordinates to the main processor 15.

[0168] The scan driving circuit 500 may be electrically connected to the readout line ROL of the circuit layer 120 .

[0169] The scanning driving circuit 500 can collect light sensing signals of the light sensing elements PD disposed in the light sensing area ODA of the main area MA through the light sensing pixel driver DPD and the readout line ROL. In addition, based on the collected light sensing signals, the scanning driving circuit 500 can output scanning data about the shape of the object in contact with the screen (e.g., the cover window 11) to the main processor 15 by detecting the difference in the amount of light reflected by the object in contact with the screen (e.g., the cover window 11).

[0170] Figure 6 It is shown Figure 5 The scanning function of the light sensing area is shown in the diagram.

[0171] Reference Figure 6 , the display device 100 according to one or more embodiments may include the light sensing element PD disposed in the light sensing area ODA, and thus may provide a scanning function to detect the shape of an object in contact with the screen.

[0172] The fingerprint of the user's finger FG in contact with the cover window 11 includes ridges RID and valleys VAL between the ridges RID. The ridges RID in the fingerprint are in contact with the cover window 11. However, the valleys VAL in the fingerprint are spaced apart from the cover window 11. In other words, the top surface of the cover window 11 facing the valleys VAL is in contact with the air.

[0173] The light emitted from the emission area EA may be reflected by the user's finger FG in contact with the cover window 11 and may be detected by the light sensing element PD of the light sensing area ODA. However, because the refractive index of the finger FG is different from that of air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0174] Therefore, based on the difference in the amount of light incident on the light sensing element PD, the ridges RID and valleys VAL of the fingerprint can be derived, so that the pattern of the fingerprint of the finger FG can be detected.

[0175] Figure 7 yes Figure 4 Block diagram of the circuit layer.

[0176] Reference Figure 7 According to one or more embodiments, the circuit layer 120 of the display device 100 may include light-emitting pixel drivers EPD corresponding to the emission areas EA of the display area DA, light-sensing pixel drivers DPD corresponding to the light-sensing areas ODA of the display area DA, data lines DL electrically connected to the light-emitting pixel drivers EPD, and readout lines ROL electrically connected to the light-sensing pixel drivers DPD.

[0177] The display device 100 according to one or more embodiments may include a data signal Vdata (eg, see Figure 8 ) is transmitted to the display driving circuit (e.g., data driver) 200 of the data line DL and the scanning driving circuit (e.g., readout IC) 500 of the light sensing pixel driver DPD through the readout line ROL.

[0178] The display device 100 according to one or more embodiments may further include a gate driving circuit (e.g., a gate driver) 101 that supplies one or more gate signals to the light emitting pixel driver EPD and the light sensing pixel driver DPD, and a gate driver circuit (e.g., a gate driver) 102 that supplies an emission control signal EC (e.g., see FIG. 1 ) to the light emitting pixel driver EPD. Figure 8 ) of the emission control circuit (e.g., emission driver) 102, a power supply unit (e.g., power supply, power supply circuit or power supply device) 700 that supplies various suitable power and voltages to the light-emitting pixel driver EPD and the light-sensing pixel driver DPD, and a timing controller 800 that controls the driving timing.

[0179] The timing controller 800 receives an image signal supplied from the outside of the display device 100. The timing controller 800 may output the image data DATA and the data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101 and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate the scan control signal SCS and the emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through the scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through the emission control driving line.

[0180] The display driving circuit 200 may convert the image data DATA into analog data voltages, and may output the analog data voltages to the data lines DL.

[0181] The gate driving circuit 101 may generate a gate signal in response to the scan control signal SCS, and may sequentially output the gate signal to the gate lines GL. Figure 8 As shown in the figure, the gate line GL may include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, a gate control line GCL for transmitting a gate control signal GC, a bias control line GBL for transmitting a bias control signal GB, and a reset control line GRL for transmitting a reset control signal GR.

[0182] The emission control circuit 102 may generate an emission control signal EC (eg, see Figure 8 ) are sequentially output to the emission control line ECL. The emission control signal EC of the emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. In some embodiments, the emission control circuit 102 may not be separately provided from the gate driving circuit 101, and may be combined with the gate driving circuit 101.

[0183] The power supply unit 700 may supply various suitable kinds of power for driving the light emitting pixel driver EPD and the light sensing pixel driver DPD.

[0184] For example, Figure 8 As shown in FIG. 7 , the power supply unit 700 may supply first power ELVDD and second power ELVSS for driving the light emitting element LE and first initialization power VINT and second initialization power VAINT for initializing the light emitting pixel driver EPD.

[0185] In addition, the power supply unit 700 may also supply a reset voltage VRST (eg, see Figure 8 ).

[0186] The scan driving circuit 500 may be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD.

[0187] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD. The scan driving circuit 500 may detect the shape of the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0188] The scan driving circuit 500 may generate scan data according to the magnitude of the photocurrent detected by the photo sensing element PD, and may transmit the scan data to the main processor 15. The main processor 15 may compare the scan data with reference data, and may execute an application based on whether the scan data matches the user's fingerprint.

[0189] Figure 8 yes Figure 7 The equivalent circuit diagram of the light-emitting pixel driver and the light-sensing pixel driver is shown in FIG.

[0190] Reference Figure 8 , one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0191] In other words, the anode electrode 131 (see, for example, Fig. 9 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (for example, see Fig. 9 ) may be applied with the second power ELVSS, and the second power ELVSS may have a voltage level lower than that of the first power ELVDD.

[0192] Figure 8 The capacitor Cel connected in parallel with the light emitting element LE in FIG. 1 may refer to (eg, may represent) a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 of the light emitting element LE.

[0193] The circuit layer 120 may further include a first power line VDL for transmitting the first power ELVDD, a first initialization power line VIL for transmitting the first initialization power VINT, a second initialization power line VAIL for transmitting the second initialization power VAINT, and a bias power line VBL for transmitting the bias power VBS.

[0194] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0195] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 generating a driving current for driving the light emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1 , and at least one first capacitor PC1 .

[0196] The first transistor T1 is connected in series with the light emitting element LE between the first power ELVDD and the second power ELVSS.

[0197] In other words, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0198] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0199] The gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1. In other words, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0200] Therefore, the potential of the gate electrode of the first transistor T1 may be maintained or substantially maintained by the first power ELVDD of the first power line VDL.

[0201] In addition, when the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference corresponding to the data signal Vdata and the first power ELVDD may be generated between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1.

[0202] In this case, when a voltage difference (e.g., a gate-source voltage difference) between a gate electrode of the first transistor T1 and a first electrode of the first transistor T1 becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on to generate a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0203] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line ELVSS. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current for the light emitting element LE.

[0204] Therefore, the light emitting element LE can emit light having desired brightness corresponding to the data signal Vdata.

[0205] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0206] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of the gate control line GCL.

[0207] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the first initialization power line VIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0208] The third transistor T3 and the fourth transistor T4 may be configured as N-type MOSFETs (eg, NMOS transistors).

[0209] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0210] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0211] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0212] The seventh transistor T7 may be electrically connected between the anode electrode 131 of the light emitting element LE and the second initialization power line VAIL. The seventh transistor T7 may be turned on by a bias control signal GB of a bias control line GBL.

[0213] The eighth transistor T8 may be connected between the first electrode of the first transistor T1 and the bias power line VBL.

[0214] The eighth transistor T8 may be turned on by a bias control signal GB of a bias control line GBL.

[0215] Among the first to eighth transistors T1 to T8 , except for the third transistor T3 and the fourth transistor T4 , the first transistor T1 , the second transistor T2 , and the fifth to eighth transistors T5 to T8 may be set as P-type MOSFETs (eg, PMOS transistors).

[0216] One of the light sensing elements PD of the element layer 130 may be electrically connected between an element output node NOP of one of the light sensing pixel drivers DPD of the circuit layer 120 and the second power ELVSS.

[0217] The circuit layer 120 may also include a reset control line GRL for transmitting a reset control signal GR to start resetting the light sensing pixel driver DPD, a reset voltage line VRL for transmitting a reset voltage VRST to reset the light sensing pixel driver DPD, and a readout line ROL that electrically connects the light sensing pixel driver DPD to the scan driving circuit 500.

[0218] Each of the light-sensing pixel drivers DPD may include at least one transistor T9 , T10 , and T11 .

[0219] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electric signal by generating a photocurrent corresponding to the amount of incident light, and may output a light sensing signal.

[0220] The light sensing element PD may be a photodiode including a sensing anode electrode, a sensing cathode electrode, and a photoelectric conversion layer disposed between the sensing anode electrode and the sensing cathode electrode.

[0221] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a pn type or pin type inorganic material. As another example, the light sensing element PD may be an organic photodiode including an electron donating material for generating donor ions and an electron accepting material for generating acceptor ions.

[0222] When light is incident on the light sensing element PD, the photoelectric conversion layer may react to the incident light to generate photocharges, and the photocharges generated in the photoelectric conversion layer may move, thereby generating a photocurrent between the sensing anode electrode and the sensing cathode electrode.

[0223] As an example, the photoelectric charge generated in the photoelectric conversion layer by the light incident on the photo sensing element PD can be accumulated in the sensing anode electrode. In addition, the potential of the element output node NOP electrically connected to the sensing anode electrode can be increased by the photocharge accumulated in the sensing anode electrode. When the readout line ROL is connected to the element output node NOP through the turned-on ninth transistor T9 and the eleventh transistor T11, the sensing voltage can be accumulated at the node N3 between the readout line ROL and the eleventh transistor T11 in proportion to the voltage of the element output node NOP where the charge is accumulated.

[0224] The ninth transistor T9 may include a gate electrode electrically connected to the element output node NOP, and the ninth transistor T9 may be electrically connected between the second initialization power line VAIL and the eleventh transistor T11 .

[0225] The ninth transistor T9 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge input to the element output node NOP of the gate electrode thereof.

[0226] In other words, when the potential of the element output node NOP increases by the photocharge accumulated in the light sensing element PD, and the voltage difference between the second initialization power VAINT and the potential of the element output node NOP becomes equal to or greater than the threshold voltage of the ninth transistor T9, the ninth transistor T9 may be turned on. In this case, a light sensing signal corresponding to the voltage difference between the second initialization power VAINT and the potential of the element output node NOP may be generated by the turned-on ninth transistor T9.

[0227] although Figure 8 The first electrode of the ninth transistor T9 is shown to be connected to the second initialization power line VAIL, but the present disclosure is not limited thereto. For example, the first electrode of the ninth transistor T9 may be connected to one of the first power line VDL and the first initialization power line VIL instead of the second initialization power line VAIL.

[0228] The tenth transistor T10 may be electrically connected between the element output node NOP and the reset voltage line VRL and may be turned on by the reset control signal GR of the reset control line GRL. When the tenth transistor T10 is turned on by the reset control signal GR, the potential of the element output node NOP may be reset to the reset voltage VRST of the reset voltage line VRL.

[0229] The eleventh transistor T11 may be electrically connected between the second electrode of the ninth transistor T9 and the readout line ROL, and may be turned on by the scan write signal GW of the scan write line GWL. Therefore, the source-drain current (e.g., the photosensitive signal) of the ninth transistor T9 may be transmitted to the readout line ROL through the eleventh transistor T11 turned on by the scan write signal GW.

[0230] The ninth transistor T9 and the eleventh transistor T11 may be provided as P-type MOSFETs (eg, PMOS transistors), and the tenth transistor T10 may be provided as N-type MOSFETs (eg, NMOS transistors).

[0231] Fig. 9 It is shown Figure 8 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light emitting element.

[0232] Reference Fig. 9 According to one or more embodiments, the circuit layer 120 of the display device 100 may include: a buffer layer 121, covering the first light shielding layer LB1 on the substrate 110; first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6, which are arranged on the buffer layer 121; a first gate insulating layer 122, covering the first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6; first gate conductive layers G1, G2 and G6, which are arranged on the first gate insulating layer 122; a second gate insulating layer 123, covering the first gate conductive layers G1, G2 and G6; second gate conductive layers CPE and LB2, which are arranged on the second gate insulating layer 123; a first interlayer insulating layer 124, covering the second gate conductive layers CPE and LB2; second semiconductor layers CH4, S4 and D4, which are arranged on the first interlayer insulating layer 124 on; a third gate insulating layer 125, covering the second semiconductor layers CH4, S4 and D4; a third gate conductive layer G4, arranged on the third gate insulating layer 125; a second interlayer insulating layer 126, covering the third gate conductive layer G4; the first source / drain conductive layers ANCE1, DCE1, GCNE and VIL, arranged on the second interlayer insulating layer 126; a first planarizing layer 127, covering the first source / drain conductive layers ANCE1, DCE1, GCNE and VIL; the second source / drain conductive layers ANCE2 and DCE2, arranged on the first planarizing layer 127; a second planarizing layer 128, covering the second source / drain conductive layers ANCE2 and DCE2; the third source / drain conductive layers ANCE3 and DL, arranged on the second planarizing layer 128; and a third planarizing layer 129, covering the third source / drain conductive layers ANCE3 and DL.

[0233] The circuit layer 120 of the display device 100 according to one or more embodiments may further include a third planarization layer 129 covering the third source / drain conductive layers ANCE3 and DL.

[0234] The element layer 130 of the display device 100 according to one or more embodiments may be disposed on the third planarization layer 129 of the circuit layer 120 .

[0235] The element layer 130 may include anode electrodes 131 respectively arranged in the emission area EA, a pixel defining layer 132 corresponding to the non-emission area NEA and covering the edge of the anode electrode 131, a light-emitting layer 133 respectively arranged on the anode electrode 131, and a cathode electrode 134 arranged on the light-emitting layer 133 and the pixel defining layer 132.

[0236] The first transistor T1 may include a channel portion CH1 formed of a first semiconductor layer on the buffer layer 121 , a source portion S1 and a drain portion D1 , and a gate electrode G1 disposed on the first gate insulating layer 122 and overlapping the channel portion CH1 .

[0237] A channel portion CH1 of the first transistor T1 may overlap the first light shielding layer LB1 on the substrate 110 .

[0238] The second transistor T2 may include a channel portion CH2 formed of the first semiconductor layer on the buffer layer 121 , a source portion S2 , and a drain portion D2 , and a gate electrode G2 disposed on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0239] The sixth transistor T6 may include a channel portion CH6 formed of the first semiconductor layer on the buffer layer 121 , a source portion S6 and a drain portion D6 , and a gate electrode G6 disposed on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0240] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through the first data link electrode DCE1 and the second data link electrode DCE2 .

[0241] The first data link electrode DCE1 may be disposed on the second interlayer insulating layer 126 and may be electrically connected to the source portion S2 of the second transistor T2 through a first data connection hole DCH1 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0242] The second data link electrode DCE2 may be disposed on the first planarization layer 127 , and may be electrically connected to the first data link electrode DCE1 through a second data connection hole DCH2 penetrating the first planarization layer 127 .

[0243] The data line DL may be disposed on the second planarization layer 128 , and may be electrically connected to the second data link electrode DCE2 through a third data connection hole DCH3 penetrating the second planarization layer 128 .

[0244] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1 .

[0245] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6 .

[0246] The drain portion D6 of the sixth transistor T6 may be electrically connected to the anode electrode 131 through the first, second, and third anode connection electrodes ANCE1, ANCE2, and ANCE3.

[0247] The first anode connection electrode ANCE1 may be disposed on the second interlayer insulating layer 126 and may be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode connection hole ANCH1 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0248] The second anode connection electrode ANCE2 may be disposed on the first planarization layer 127 , and may be electrically connected to the first anode connection electrode ANCE1 through a second anode connection hole ANCH2 penetrating the first planarization layer 127 .

[0249] The third anode connection electrode ANCE3 may be disposed on the second planarization layer 128 , and may be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3 penetrating the second planarization layer 128 .

[0250] The anode electrode 131 may be disposed on the third planarization layer 129 , and may be electrically connected to the third anode connection electrode ANCE3 through a fourth anode connection hole ANCH4 penetrating the third planarization layer 129 .

[0251] The first capacitor PC1 may be provided by an overlapped region between the capacitor electrode CPE provided on the second gate insulating layer 123 and the gate electrode G1 of the first transistor T1 .

[0252] The fourth transistor T4 may include a channel portion CH4 formed of the second semiconductor layer on the first interlayer insulating layer 124 , a source portion S4 and a drain portion D4 , and a gate electrode G4 disposed on the third gate insulating layer 125 and overlapping the channel portion CH4 .

[0253] A channel portion CH4 of the fourth transistor T4 may overlap the second light blocking layer LB2 on the second gate insulating layer 123 .

[0254] The source portion S4 of the fourth transistor T4 may be electrically connected to the first initialization power line VIL on the second interlayer insulating layer 126 through a hole VICH penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0255] The drain portion D4 of the fourth transistor T4 may be electrically connected to the gate electrode G1 of the first transistor T1 through the gate connection electrode GCNE on the second interlayer insulating layer 126 .

[0256] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate connection hole GCH1 penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0257] The gate connection electrode GCNE may be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate connection hole GCH2 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , and the second gate insulating layer 123 .

[0258] Because the third transistor T3 and the tenth transistor T10 are structurally identical or substantially identical (or similar) to the fourth transistor T4, and the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are structurally identical or substantially identical (or similar) to the second transistor T2 and the sixth transistor T6, their redundant descriptions may not be repeated.

[0259] In addition, according to one or more embodiments, the circuit layer 120 of the display device 100 may also include wiring electrically connected between some of the data lines DL and the display driving circuit 200 and arranged in the display area DA, and wiring electrically connected between some of the read-out lines ROL and the scan driving circuit 500 and arranged in the display area DA to reduce the width of the non-display area NDA.

[0260] Fig.10 is a diagram showing a method according to one or more embodiments Figure 2 A plan view of the base.

[0261] Reference Fig.10, the substrate 110 of the display device 100 according to one or more embodiments may include a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0262] The main area MA may include a display area DA disposed at most of the center of the main area MA and a non-display area NDA disposed at an edge of the main area MA to surround the display area DA (eg, around a periphery of the display area DA).

[0263] The display area DA may include a detour area DEA disposed at one side adjacent to the sub area SBA and a general area GA disposed in a remaining area of ​​the display area DA except the detour area DEA.

[0264] The bypass area DEA may include a bypass middle area MDDA set at the center on the first direction DR1, a first bypass side area SDA1 parallel to or substantially parallel to the bypass middle area MDDA on the first direction DR1 and in contact with the non-display area NDA, a second bypass side area SDA2 set between the bypass middle area MDDA and the first bypass side area SDA1, and a third bypass side area SDA3 set between the first bypass side area SDA1 and the second bypass side area SDA2.

[0265] The first detour side area SDA1 may be disposed closer to a bending corner of the substrate 110 than the detour middle area MDDA, the second detour side area SDA2, and the third detour side area SDA3.

[0266] The first detour side area SDA1, the third detour side area SDA3 and the second detour side area SDA2 may be disposed between one side of the detour middle area MDDA in the first direction DR1 and the non-display area NDA and between the other side of the detour middle area MDDA in the first direction DR1 and the non-display area NDA.

[0267] The general area GA may include a general middle area GMA connected to the bypass middle area MDDA of the bypass area DEA in the second direction DR2, a first general side area GSA1 connected to the first bypass side area SDA1 in the second direction DR2, a second general side area GSA2 connected to the second bypass side area SDA2 in the second direction DR2, and a third general side area GSA3 connected to the third bypass side area SDA3 in the second direction DR2.

[0268] The non-display area NDA may include a gate driving circuit area GDRA in which the gate driving circuit 101 and the emission control circuit 102 are disposed.

[0269] The gate driving circuit area GDRA may be disposed in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0270] The subregion SBA may include a bent region BA transformed into a bent shape, a first subregion SB1 disposed between one side of the bent region BA and the main region MA, and a second subregion SB2 connected to the other side (eg, opposite side) of the bent region BA.

[0271] When the bending area BA is transformed into a bent shape, the second sub-area SB2 is disposed under the substrate 110 and overlaps the main area MA.

[0272] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0273] A signal pad SPD bonded to the display circuit board 300 may be disposed at one edge of the second sub-region SB2 .

[0274] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Fig.10 An enlarged layout diagram of portion C.

[0275] Reference Fig.11 According to one or more embodiments, the circuit layer 120 of the display device 100 may include light emitting pixel drivers EPD electrically connected to the light emitting elements LE of the element layer 130, light sensing pixel drivers DPD electrically connected to the light sensing elements PD of the element layer 130, data lines DL electrically connected to the light emitting pixel drivers EPD to transmit data signals Vdata, readout lines ROL parallel to or substantially parallel to the data lines DL and electrically connected to the light sensing pixel drivers DPD to transmit light sensing signals, first dummy lines DML1 extending in a first direction DR1 crossing the data lines DL, and second dummy lines DML2 extending in a second direction DR2 parallel to or substantially parallel to the data lines DL and paired with the data lines DL, respectively.

[0276] The data line DL, the readout line ROL, and the second dummy line DML2 may extend in the second direction DR2.

[0277] According to one or more embodiments, the first dummy line DML1 may include a first readout bypass line RODTL1 electrically connected to a first readout line ROL1 among the readout lines ROL. The second dummy line DML2 may include a first readout connection line ROCNL1 electrically connected to the first readout bypass line RODTL1.

[0278] According to one or more embodiments, the circuit layer 120 may further include a readout transmission line ROTRL disposed in the non-display area NDA.

[0279] The readout transfer line ROTRL may be electrically connected between the scan driving circuit 500 and the readout line ROL.

[0280] Among the readout transmission lines ROTRL, a first readout transmission line ROTRL1 for transmitting a signal of the first readout line ROL1 may be electrically connected to the first readout line ROL1 through a first readout connection line ROCNL1 and a first readout bypass line RODTL1.

[0281] In other words, according to one or more embodiments, the first readout transmission line ROTRL1 can be electrically connected to the first readout line ROL1 by detouring to the first readout connection line ROCNL1 and the first readout bypass line RODTL1 set in the bypass area DEA of the display area DA, rather than being directly electrically connected to the first readout line ROL1.

[0282] Therefore, the first readout transmission line ROTRL1 can extend to the first readout connection line ROCNL1 of the third detour side area SDA3 instead of the first readout line ROL1 of the second detour side area SDA2, thereby having a relatively small extension length. Therefore, the width of the non-display area NDA can be reduced.

[0283] The third detour side area SDA3 may be adjacent to a portion of the non-display area NDA where the readout transmission lines ROTRL are gathered.

[0284] In other words, the readout transmission line ROTRL may extend to at least a portion of the third detour side area SDA3 and the first detour side area SDA1 adjacent thereto.

[0285] According to one or more embodiments, the readout line ROL may further include a second readout line ROL2 disposed in the third detour side area SDA3.

[0286] Among the readout transmission lines ROTRL, the second readout transmission line ROTRL2 for transmitting a signal of the second readout line ROL2 may be directly electrically connected to the second readout line ROL2.

[0287] In other words, the readout transmission line ROTRL may extend to the third detour side area SDA3. In addition, the second readout transmission line ROL2 of the third detour side area SDA3 may be directly electrically connected to the second readout transmission line ROTRL2.

[0288] On the other hand, the first readout line ROL1 set in the second bypass side area SDA2 can be electrically connected to the first readout transmission line ROTRL1 through the first readout connection line ROCNL1 and the first readout bypass line RODTL1 set in the bypass area DEA, rather than being directly electrically connected to the first readout transmission line ROTRL1 extending to the third bypass side area SDA3.

[0289] In this way, the read transmission line ROTRL can be gathered in a portion of the non-display area NDA adjacent to the third bypass side area SDA3. As a result, the total extension length of the read transmission line ROTRL can be reduced, and the area for arranging the read transmission line ROTRL can be reduced, thereby reducing the width of the non-display area NDA.

[0290] According to an embodiment, some of the readout transmission lines ROTRL may extend to at least a portion of the first detour side area SDA1 adjacent to the third detour side area SDA3 .

[0291] In other words, the second readout line ROL2 may be provided in the third detour side area SDA3 and in at least a portion of the first detour side area SDA1 adjacent to the third detour side area SDA3.

[0292] According to one or more embodiments, the data lines DL may include a first data line DL1 disposed in the first detour side area SDA1 , second and third data lines DL2 and DL3 disposed in the second detour side area SDA2 , and a fourth data line DL4 disposed in the third detour side area SDA3 .

[0293] The first dummy line DML1 may further include a first data bypass line DTDTL1 electrically connected to the first data line DL1 of the first detour side area SDA1 and a second data bypass line DTDTL2 electrically connected to the fourth data line DL4 of the third detour side area SDA3 .

[0294] The second dummy line DML2 may further include a first data link line DTCNL1 paired with the second data line DL2 of the second detour side area SDA2 and electrically connected to the first data detour line DTDTL1 and a second data link line DTCNL2 paired with the third data line DL3 of the second detour side area SDA2 and electrically connected to the second data detour line DTDTL2.

[0295] Among the detour lines for electrically connecting the first readout line ROL1 to the first readout transfer line ROTRL1 , the first readout connection line ROCNL1 in the second direction DR2 may be paired with the fourth data line DL4 of the third detour side area SDA3 .

[0296] According to one or more embodiments, the circuit layer 120 may further include a data transmission line DTTRL disposed in the non-display area NDA.

[0297] The data transmission line DTTRL may be electrically connected between the display driving circuit 200 and the data line DL.

[0298] The data transmission line DTTRL may extend to the second detour side area SDA2 and the detour middle area MDDA. In other words, the data transmission line DTTRL may be spaced apart from the first detour side area SDA1 adjacent to the bending corner of the substrate 110 and the third detour side area SDA3 to which the readout transmission line ROTRL extends.

[0299] According to one or more embodiments, the second data line DL2 and the third data line DL3 disposed in the second detour side area SDA2 may be directly electrically connected to the data transmission line DTTRL, respectively.

[0300] On the other hand, the first data line DL1 of the first detour side area SDA1 and the fourth data line DL4 of the third detour side area SDA3 may be electrically connected to the data transmission line DTTRL through detour lines disposed in the detour area DEA, respectively, rather than being directly electrically connected to the data transmission line DTTRL.

[0301] In other words, among the data transmission lines DTTRL, the first data transmission line DTTRL1 for transmitting the data signal of the first data line DL1 of the first detour side area SDA1 can be electrically connected to the first data line DL1 through the first data connection line DTCNL1 of the second detour side area SDA2 and the first data detour line DTDTL1.

[0302] Among the data transmission lines DTTRL, the second data transmission line DTTRL2 for transmitting the data signal of the second data line DL2 of the second detour side area SDA2 may be directly electrically connected to the second data line DL2.

[0303] Among the data transmission lines DTTRL, a third data transmission line DTTRL3 for transmitting a data signal of the third data line DL3 of the second detour side area SDA2 may be directly electrically connected to the third data line DL3.

[0304] Among the data transmission lines DTTRL, a fourth data transmission line DTTRL4 for transmitting a data signal of the fourth data line DL4 of the third detour side area SDA3 may be electrically connected to the fourth data line DL4 through the second data link line DTCNL2 and the second data detour line DTDTL2 of the second detour side area SDA2.

[0305] As such, the data transmission lines DTTRL may be gathered in a portion of the non-display area NDA adjacent to the second detour side area SDA2 .

[0306] In contrast, the readout transmission lines ROTRL may be gathered in a portion of the non-display area NDA adjacent to the third detour side area SDA3.

[0307] In other words, the gathering area of ​​the data transmission line DTTRL and the gathering area of ​​the readout transmission line ROTRL may be spaced apart from each other in the first direction DR1. Therefore, the readout transmission line ROTRL may be disposed in the same layer as the layer of the data transmission line DTTRL. Therefore, the layout of the data transmission line DTTRL and the readout transmission line ROTRL may be more easily designed.

[0308] In addition, the total extension length of the data transmission line DTTRL may be reduced, and the area for arranging the data transmission line DTTRL may be reduced, so that the width of the non-display area NDA may be reduced.

[0309] Furthermore, since the data transmission line DTTRL may not extend to the first detour side area SDA1 adjacent to the bending corner of the substrate 110 , the width of a portion of the non-display area NDA adjacent to the bending corner of the substrate 110 may be reduced.

[0310] The data lines DL may further include a seventh data line DL7 disposed in the detour middle area MDDA.

[0311] Because the data transmission line DTTRL extends to the second detour side area SDA2 and the detour middle area MDDA, among the data transmission lines DTTRL, the seventh data transmission line DTTRL7 for transmitting the data signal of the seventh data line DL7 of the detour middle area MDDA can be directly electrically connected to the seventh data line DL7.

[0312] According to one or more embodiments, the first readout detour line RODTL1 , the first data detour line DTDTL1 , and the second data detour line DTDTL2 may be limitedly (eg, selectively) disposed in a portion of the detour area DEA.

[0313] Therefore, because the end of each of the first read-out bypass line RODTL1, the first data bypass line DTDTL1 and the second data bypass line DTDTL2 can be arranged with regularity (e.g., predetermined regularity), the visibility of the first read-out bypass line RODTL1, the first data bypass line DTDTL1 and the second data bypass line DTDTL2 can be increased.

[0314] To prevent or reduce such visibility, the first dummy line DML1 may further include a first auxiliary line ASL1 disposed in a portion of the display area DA where the first, first, and second data bypass lines RODTL1, DTDTL1, and DTDTL2 are not disposed.

[0315] For example, some of the first auxiliary lines ASL1 may extend from both ends (eg, opposite ends) of each of the first readout bypass line RODTL1 , the first data bypass line DTDTL1 , and the second data bypass line DTDTL2 to the non-display area NDA.

[0316] In addition, other ones of the first auxiliary lines ASL1 may be arranged in the general area GA.

[0317] Similarly, the first readout link line ROCNL1 , the first data link line DTCNL1 , and the second data link line DTCNL2 may be limitedly (eg, selectively) disposed in a portion of the detour area DEA.

[0318] Therefore, since the end of each of the first readout link line ROCNL1, the first data link line DTCNL1 and the second data link line DTCNL2 can be arranged with regularity (e.g., predetermined regularity), the visibility of the first readout link line ROCNL1, the first data link line DTCNL1 and the second data link line DTCNL2 can be increased.

[0319] To prevent or reduce such visibility, the second dummy line DML2 may further include a second auxiliary line ASL2 disposed in a portion of the display area DA where the first readout link line ROCNL1 , the first data link line DTCNL1 , and the second data link line DTCNL2 are not disposed.

[0320] For example, some of the second auxiliary lines ASL2 may be paired with the first and seventh data lines DL1 and DL7 that are not paired with the first, second, and third data link lines ROCNL1, DTCNL1, and DTCNL2 among the data lines DL.

[0321] In addition, other ones of the second auxiliary lines ASL2 may extend from an end portion of each of the first readout link line ROCNL1 , the first data link line DTCNL1 , and the second data link line DTCNL2 to the non-display area NDA.

[0322] The second power ELVSS may be applied to the first and second auxiliary lines ASL1 and ASL2 .

[0323] According to one or more embodiments, the circuit layer 120 may further include a first power line VDSPL and a second power line VSSPL that transmit a first power ELVDD and a second power ELVSS for driving the light emitting element LE, respectively.

[0324] The first power line VDSPL and the second power line VSSPL may be disposed in the non-display area NDA and may extend to the sub-area SBA.

[0325] The first power line VDSPL may be electrically connected to a first power pad for transmitting the first power ELVDD among the signal pads SPD disposed in the second sub-region SB2 .

[0326] The second power line VSSPL may be electrically connected to a second power pad for transmitting the second power ELVSS among the signal pads SPD disposed in the second sub-region SB2 .

[0327] The first auxiliary line ASL1 may be electrically connected to the second power line VSSPL.

[0328] The second auxiliary line ASL2 may be electrically connected to the first auxiliary line ASL1 and the second power line VSSPL.

[0329] According to one or more embodiments, the circuit layer 120 may further include a second power auxiliary line VSAL disposed in the same layer as the data line DL and the second dummy line DML2 and electrically connected to the second power line VSSPL.

[0330] Fig.12 It is along Fig.11 A cross-sectional view taken along line D-D'.

[0331] Reference Fig.12 The data line DL, the readout line ROL, and the second dummy line DML2 may be disposed on at least one insulating layer (eg, a planarization layer) 127 , 128 covering the first dummy line DML1 .

[0332] In other words, the data lines DL including the first data line DL1 to the fourth data line DL4 and the seventh data line DL7, the readout lines ROL including the first readout lines ROL1 and the second readout lines ROL2, the second dummy line DML2 including the first readout link line ROCNL1, the first data link line DTCNL1, the second data link line DTCNL2 and the second auxiliary line ASL2 can be set in the third source / drain conductive layer on the second planarization layer 128.

[0333] The first dummy line DML1 including the first readout bypass line RODTL1 , the first data bypass line DTDTL1 , the second data bypass line DTDTL2 , and the first auxiliary line ASL1 may be disposed in a conductive layer below (eg, under) the second planarization layer 128 .

[0334] For example, a first dummy line DML1 including a first readout routing line RODTL1 , a first data routing line DTDTL1 , a second data routing line DTDTL2 , and a first auxiliary line ASL1 may be disposed in the first source / drain conductive layer on the second interlayer insulating layer 126 and may be covered by the first planarization layer 127 .

[0335] The second data bypass line DTDTL2 may be electrically connected to the second data link line DTCNL2 through the first bypass connection hole DECH1. The second data bypass line DTDTL2 may be electrically connected to the fourth data line DL4 through the second bypass connection hole DECH2.

[0336] The first and second detour connection holes DECH1 and DECH2 may penetrate the second planarization layer 128 and the first planarization layer 127 .

[0337] like Fig.11 As shown in FIG. 1 , according to embodiment C_1, at least one first readout bypass line RODTL1 may be arranged between the first data bypass lines DTDTL1 in the second direction DR2 or between the second data bypass lines DTDTL2 in the second direction DR2.

[0338] In other words, the first readout routing line RODTL1 may be adjacent to the first data routing line DTDTL1 or the second data routing line DTDTL2 .

[0339] As a result, the signal of the first readout bypass line RODTL1 may be easily distorted.

[0340] In other words, the signal of the first readout routing line RODTL1 may be distorted due to coupling interference with the data signal of the first data routing line DTDTL1 or the data signal of the second data routing line DTDTL2 .

[0341] Refer to below Figures 13 to 15 The embodiments described in more detail may help prevent or reduce distortion of the first readout detour line RODTL1 .

[0342] Figures 13 to 15 is a diagram showing a method according to one or more embodiments Fig.10 An enlarged layout diagram of portion C.

[0343] Reference Fig.13, except that each of the first detour side area SDA1, the second detour side area SDA2, and the third detour side area SDA3 includes an adjacent area ADJA contacting the non-display area NDA in the second direction DR2 and a separation area DSTA as a remaining area except the adjacent area ADJA, the display device 100 according to embodiment C_2 may be the same as that described above with reference to Fig.11 and Fig.12 The display device of the described embodiment C_1 is the same or substantially the same. The first readout bypass line RODTL1 can be set in an adjacent area ADJA of each of the first bypass side area SDA1, the second bypass side area SDA2, and the third bypass side area SDA3. The first data bypass line DTDTL1 and the second data bypass line DTDTL2 are set in a separated area DSTA of each of the first bypass side area SDA1, the second bypass side area SDA2, and the third bypass side area SDA3. Therefore, the redundant description may not be repeated, and the differences may be described in more detail below.

[0344] In each of the first detour side area SDA1 , the second detour side area SDA2 , and the third detour side area SDA3 , the separation area DSTA may be provided between the adjacent area ADJA and the general area GA.

[0345] As such, the first readout bypass line RODTL1 may be disposed in an adjacent area ADJA of each of the first bypass side area SDA1, the second bypass side area SDA2, and the third bypass side area SDA3. The first data bypass line DTDTL1 and the second data bypass line DTDTL2 may be disposed in a separate area DSTA of each of the first bypass side area SDA1, the second bypass side area SDA2, and the third bypass side area SDA3. Therefore, the first readout bypass line RODTL1 may not be adjacent to the first data bypass line DTDTL1 or the second data bypass line DTDTL2.

[0346] In other words, since the first readout bypass line RODTL1 can be spaced apart from the first data bypass line DTDTL1 and the second data bypass line DTDTL2, the influence of the data signal of the first data bypass line DTDTL1 or the data signal of the second data bypass line DTDTL2 on the signal of the first readout bypass line RODTL1 can be reduced. Therefore, the distortion of the signal of the first readout bypass line RODTL1 can be reduced.

[0347] Reference Fig.14 In addition to the detour area DEA of the display area DA further including a fourth detour side area SDA4 disposed between the first detour side area SDA1 and the third detour side area SDA3, the display device 100 according to the embodiment C_3 may be the same as that described above with reference to Fig.13The display device of the described embodiment C_2 is the same or substantially the same. Therefore, a redundant description may not be repeated, and the differences may be described in more detail below.

[0348] according to Fig.14 In the embodiment C_3 shown in FIG. 1 , the data line DL may further include a fifth data line DL5 disposed in the fourth detour side area SDA4 .

[0349] The readout lines ROL may further include a third readout line ROL3 disposed in the first detour side area SDA1 and a fourth readout line ROL4 disposed in the fourth detour side area SDA4.

[0350] The first dummy line DML1 may further include a second readout bypass line RODTL2 electrically connected to the third readout line ROL3 .

[0351] The second dummy line DML2 may further include a second readout link line ROCNL2 paired with the fifth data line DL5 of the fourth detour side area SDA4 and electrically connected to the second readout detour line RODTL2 .

[0352] Among the readout transmission lines ROTRL, the third readout transmission line ROTRL3 for transmitting a signal of the third readout line ROL3 may be electrically connected to the third readout line ROL3 of the first detour side area SDA1 through the second readout connection line ROCNL2 and the second readout detour line RODTL2 of the fourth detour side area SDA4.

[0353] Among the readout transmission lines ROTRL, a fourth readout transmission line ROTRL4 for transmitting a signal of the fourth readout line ROL4 may be directly electrically connected to the fourth readout line ROL4 of the fourth detour side area SDA4.

[0354] according to Fig.14 In the embodiment C_3 shown in FIG. 1 , the data line DL may further include a sixth data line DL6 disposed in the second detour side area SDA2 .

[0355] The first dummy line DML1 may further include a third data bypass line DTDTL3 electrically connected to the fifth data line DL5 .

[0356] The second dummy line DML2 may further include a third data link line DTCNL3 paired with the sixth data line DL6 and electrically connected to the third data bypass line DTDTL3 .

[0357] Among the data transmission lines DTTRL, a fifth data transmission line DTTRL5 for transmitting a data signal of the fifth data line DL5 may be electrically connected to the fifth data line DL5 of the fourth detour side area SDA4 through the third data link line DTCNL3 and the third data detour line DTDTL3 of the second detour side area SDA2.

[0358] Among the data transmission lines DTTRL, a sixth data transmission line DTTRL6 for transmitting a data signal of the sixth data line DL6 may be directly electrically connected to the sixth data line DL6 of the second detour side area SDA2.

[0359] according to Fig.14 In embodiment C_3 shown in, the first readout bypass line RODTL1 connecting the first readout line ROL1 of the second bypass side area SDA2 to the first readout connection line ROCNL1 of the third bypass side area SDA3 can be set in the adjacent area ADJA of each of the second bypass side area SDA2 and the third bypass side area SDA3.

[0360] A second readout detour line RODTL2 connecting the third readout line ROL3 of the first detour side area SDA1 to the second readout connection line ROCNL2 of the fourth detour side area SDA4 may be disposed in an adjacent area ADJA of each of the first detour side area SDA1 and the fourth detour side area SDA4.

[0361] The first and second data detour lines DTDTL1 and DTDTL2 may be disposed in the separation area DSTA of each of the first, second, third, and fourth detour side areas SDA1, SDA2, SDA3, and SDA4.

[0362] In addition, the third data detour line DTDTL3 may also be disposed in the separation area DSTA of each of the first detour side area SDA1 , the second detour side area SDA2 , the third detour side area SDA3 , and the fourth detour side area SDA4 .

[0363] So, according to Fig.14 In the embodiment C_3 shown in FIG. 1 , the readout transmission lines ROTRL may be gathered in a portion of the non-display area NDA adjacent to the third detour side area SDA3 and the fourth detour side area SDA4 .

[0364] In other words, the read-out transmission line ROTRL may not extend into the first bypass side area SDA1 adjacent to the curved corner of the substrate 110, and may not extend into the second bypass side area SDA2 and the bypass middle area MDDA where the data transmission line DTTRL extends, and therefore, the width of the portion of the non-display area NDA adjacent to the curved corner of the substrate 110 may be further reduced.

[0365] Reference Fig.15 , in addition to each of the first detour side area SDA1, the second detour side area SDA2, the third detour side area SDA3, and the fourth detour side area SDA4 further including a buffer area ABSA disposed between the adjacent area ADJA and the separation area DSTA, the display device 100 according to the embodiment C_4 may be the same as that described above with reference to Fig.14 The display device of the described embodiment C_3 is the same or substantially the same. Therefore, a redundant description may not be repeated, and the differences may be described in more detail below.

[0366] according to Fig.15 In the embodiment C_4 shown in FIG. 1 , the first auxiliary line ASL1 to which the second power ELVSS is applied may be disposed in the buffer area ABSA of each of the first to fourth detour side areas SDA1 , SDA2 , SDA3 , and SDA4 .

[0367] In this way, due to the arrangement of the buffer area ABSA, the first readout bypass line RODTL1 and the second readout bypass line RODTL2 can be further separated from the first data bypass line DTDTL1, the second data bypass line DTDTL2, and the third data bypass line DTDTL3. Therefore, the influence of the data signal of the first data bypass line DTDTL1, the data signal of the second data bypass line DTDTL2, and the data signal of the third data bypass line DTDTL3 on the signal of the first readout bypass line RODTL1 and the signal of the second readout bypass line RODTL2 can be reduced.

[0368] In addition, the signal of the first sensing bypass line RODTL1 and the signal of the second sensing bypass line RODTL2 may be more stably maintained by the second power ELVSS of the first auxiliary line ASL1.

[0369] Therefore, the signal distortion of the first readout bypass line RODTL1 and the signal distortion of the second readout bypass line RODTL2 can be greatly reduced.

[0370] The foregoing is an explanation of some embodiments of the present disclosure and is not to be construed as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those of ordinary skill in the art that, unless otherwise specifically noted, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the foregoing is an explanation of various example embodiments and is not to be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, the display device include: A substrate including a display area and a non-display area, the display area including an emission area, a non-emission area as a separation area between the emission areas, and a light sensing area in a portion of the non-emission area, the non-display area being around the display area; a circuit layer on the substrate; as well as The element layer is on the circuit layer and includes a light emitting element and a light sensing element. The light emitting element is respectively in the emission region, and the light sensing element is respectively in the light sensing region. Wherein, the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements respectively; Light sensing pixel drivers, electrically connected to the light sensing elements respectively; A data line electrically connected to the light-emitting pixel driver; a readout line electrically connected to the light sensing pixel driver and extending parallel to the data line; a first dummy line extending in a first direction crossing the data line and including a first sense bypass line electrically connected to a first sense line among the sense lines; and Second dummy lines extend in a second direction parallel to the data lines and crossing the first direction and are paired with the data lines, respectively, and include first readout connection lines electrically connected to the first readout detour lines.

2. The display device according to claim 1, in, The data line, the readout line, and the second dummy line are located on at least one insulating layer covering the first dummy line.

3. The display device according to claim 2, further comprising a scan driving circuit configured to collect light sensing signals from the light sensing element through the light sensing pixel driver and the readout line, in, The circuit layer further includes a readout transmission line, the readout transmission line being in the non-display area and electrically connected between the readout line and the scan drive circuit, and Among the readout transmission lines, a first readout transmission line configured to transmit a signal of the first readout line is electrically connected to the first readout line through the first readout connection line and the first readout bypass line.

4. The display device according to claim 3, in, The detour area on one side of the display area includes: a central detour middle area; a first detour side area, which is parallel to the detour middle area in the first direction and contacts the non-display area; a second detour side area, which is between the detour middle area and the first detour side area; and a third detour side area, which is between the first detour side area and the second detour side area. The data lines include: a first data line in the first detour side region; a second data line and a third data line in the second detour side region; and a fourth data line in the third detour side region. The first dummy line further includes a first data bypass line electrically connected to the first data line and a second data bypass line electrically connected to the fourth data line. The second dummy line further includes: a first data connection line, paired with the second data line and electrically connected to the first data bypass line; and a second data connection line, paired with the third data line and electrically connected to the second data bypass line, and Wherein, the first readout connection line is paired with the fourth data line.

5. The display device according to claim 4, further comprising a display driving circuit, wherein the display driving circuit is configured to transmit a data signal for the light-emitting pixel driver to the data line, in, The circuit layer further includes a data transmission line, the data transmission line is in the non-display area and is electrically connected between the data line and the display driving circuit, and Wherein, in the data transmission line: a first data transmission line configured to transmit a data signal of the first data line is electrically connected to the first data line through the first data bypass line and the first data connection line, A second data transmission line configured to transmit a data signal of the second data line is directly electrically connected to the second data line, A third data transmission line configured to transmit a data signal of the third data line is directly electrically connected to the third data line, and A fourth data transmission line configured to transmit a data signal of the fourth data line is electrically connected to the fourth data line through the second data bypass line and the second data connection line.

6. The display device according to claim 5, in, The substrate includes a main area and a sub-area, the main area includes the display area and the non-display area, and the sub-area protrudes from one side of the main area in the second direction. Wherein, the display driving circuit is in the sub-region of the substrate, Wherein, the scan driving circuit is on a display circuit board connected to the sub-area of ​​the substrate, wherein the data transmission lines are gathered in a portion of the non-display area adjacent to the second detour side area, and Wherein, the readout transmission lines are gathered in another portion of the non-display area adjacent to the third detour side area.

7. The display device according to claim 6, in, The first readout line is located in the second detour side area, wherein the readout line further comprises a second readout line in the third detour side region, and Among the readout transmission lines, a second readout transmission line configured to transmit a signal of the second readout line is directly electrically connected to the second readout line.

8. The display device according to claim 7, in, The first readout detour line includes a plurality of first readout detour lines, Wherein, the first data bypass line includes a plurality of first data bypass lines, Wherein, the second data bypass line includes a plurality of second data bypass lines, and At least one of the first readout bypass lines is located between the first data bypass lines in the second direction, or is located between the second data bypass lines in the second direction.

9. The display device according to claim 7, in, Each of the first detour side area, the second detour side area, and the third detour side area includes: an adjacent area that contacts the non-display area in the second direction; and a separation area that is a remaining area except the adjacent area, wherein the first readout detour line is located in the adjacent area of ​​each of the first detour side area, the second detour side area, and the third detour side area, and Wherein, the first data bypass line and the second data bypass line are located in the separate area of ​​each of the first bypass side area, the second bypass side area, and the third bypass side area.

10. The display device according to claim 7, in, The detour area of ​​the display area further includes a fourth detour side area between the first detour side area and the third detour side area, The data lines further include a fifth data line in the fourth detour side region, The readout lines further include a third readout line in the first detour side region and a fourth readout line in the fourth detour side region, The first dummy line further includes a second readout bypass line electrically connected to the third readout line. The second dummy line further includes a second readout connection line paired with the fifth data line and electrically connected to the second readout detour line. Wherein, in the readout transmission line: a third readout transmission line configured to transmit a signal of the third readout line is electrically connected to the third readout line through the second readout connection line and the second readout bypass line, and A fourth readout transmission line configured to transmit a signal of the fourth readout line is directly electrically connected to the fourth readout line.

11. The display device according to claim 10, in, The data lines further include a sixth data line in the second detour side region, Wherein, the first dummy line further includes a third data bypass line electrically connected to the fifth data line, and The second dummy line further includes a third data connection line paired with the sixth data line and electrically connected to the third data bypass line.

12. The display device according to claim 10, in, Each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area includes: an adjacent area that contacts the non-display area in the second direction; and a separation area that is a remaining area except the adjacent area, wherein the first readout detour line is located in the adjacent area of ​​each of the second detour side area and the third detour side area, wherein the second readout detour line is located in the adjacent area of ​​each of the first detour side area and the fourth detour side area, and The first data bypass line and the second data bypass line are located in the separate area of ​​each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area.

13. The display device according to claim 12, in, The circuit layer further includes: a first power line and a second power line, which are located in the non-display area and are configured to transmit a first power and a second power for driving the light emitting element, respectively. Wherein, the first dummy line further includes a first auxiliary line electrically connected to the second power line, and Wherein, the second dummy line further includes a second auxiliary line electrically connected to the first auxiliary line and the second power line.

14. The display device according to claim 13, in, Each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area further includes a buffer area between the adjacent area and the separation area, and Wherein, the first auxiliary line is located in the buffer area of ​​each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area.

15. The display device according to claim 7, in, The circuit layer further includes: a first power line and a second power line, which are in the non-display area and are configured to transmit a first power and a second power for driving the light-emitting element, respectively; and a first power line, which is electrically connected between the light-emitting pixel driver and the first power line, wherein one of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power; wherein one of the light sensing elements is electrically connected between an element output node of one of the light sensing pixel drivers in the light sensing pixel driver and the second power; wherein the one of the light-emitting pixel drivers comprises: a first transistor configured to generate a driving current for driving the one of the light-emitting elements; a second transistor electrically connected between a data line in the data lines and a first electrode of the first transistor; a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor; a fourth transistor electrically connected between a first initialization power line configured to transmit a first initialization power and the gate electrode of the first transistor; a fifth transistor electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the one of the light-emitting elements; a seventh transistor electrically connected between a second initialization power line configured to transmit a second initialization power and the one of the light-emitting elements; and an eighth transistor electrically connected between a bias power line configured to transmit a bias power and the first electrode of the first transistor, and Among them, the one light sensing pixel driver in the light sensing pixel driver includes: a ninth transistor, configured to be turned on according to the voltage level of the element output node; a tenth transistor, electrically connected between a reset voltage line configured to transmit a reset voltage and the element output node; and an eleventh transistor, electrically connected between one of the readout lines and the ninth transistor.

16. A display device, the display device include: A substrate including a display area and a non-display area, the display area including an emission area, a non-emission area as a separation area between the emission areas, and a light sensing area in a portion of the non-emission area, the non-display area being around the display area; a circuit layer on the substrate; as well as The element layer is on the circuit layer and includes a light emitting element and a light sensing element. The light emitting element is respectively in the emission region, and the light sensing element is respectively in the light sensing region. The detour area on one side of the display area includes: a central detour middle area; a first detour side area, which is parallel to the detour middle area in a first direction and contacts the non-display area; a second detour side area, which is between the detour middle area and the first detour side area; and a third detour side area, which is between the first detour side area and the second detour side area, and Wherein, the circuit layer includes: a light-emitting pixel driver, electrically connected to the light-emitting elements respectively; a light-sensing pixel driver, electrically connected to the light-sensing elements respectively; a data line, electrically connected to the light-emitting pixel driver; a readout line, electrically connected to the light-sensing pixel driver and extending parallel to the data line; a first data bypass line, extending in the first direction crossing the data line and electrically connected to a first data line among the data lines in the first bypass side area; a first readout bypass line, extending in the first direction crossing the data line and electrically connected to a first readout line among the readout lines; a first data connection line, extending in a second direction parallel to the data line and crossing the first direction, the first data connection line is paired with a second data line among the data lines in the second bypass side area and electrically connected to the first data bypass line; and a first readout connection line, extending in the second direction and electrically connected to the first readout bypass line.

17. The display device according to claim 16, in, The data lines further include a third data line in the second detour side region and a fourth data line in the third detour side region, wherein the first readout connection line is paired with the fourth data line, and Wherein, the circuit layer further includes: a second data bypass line extending in the first direction and electrically connected to the fourth data line; and a second data connection line extending in the second direction, paired with the third data line, and electrically connected to the second data bypass line.

18. The display device according to claim 17, wherein the display device further comprises: include: a scanning driving circuit configured to collect light sensing signals from the light sensing element through the light sensing pixel driver and the readout line; as well as A display driving circuit is configured to transmit a data signal for the light-emitting pixel driver to the data line, The circuit layer further comprises: a readout transmission line in the non-display area and electrically connected between the readout line and the scan drive circuit; and a data transmission line in the non-display area and electrically connected between the data line and the display drive circuit. Wherein, in the data transmission lines: a first data transmission line configured to transmit a data signal of the first data line is electrically connected to the first data line through the first data bypass line and the first data connection line, a second data transmission line configured to transmit a data signal of the second data line is directly electrically connected to the second data line, a third data transmission line configured to transmit a data signal of the third data line is directly electrically connected to the third data line, and a fourth data transmission line configured to transmit a data signal of the fourth data line is electrically connected to the fourth data line through the second data bypass line and the second data connection line, and Among the readout transmission lines, a first readout transmission line configured to transmit a signal of the first readout line is electrically connected to the first readout line through the first readout connection line and the first readout bypass line.

19. The display device according to claim 18, in, The sense lines further include a second sense line in the third detour side region, and Among the readout transmission lines, a second readout transmission line configured to transmit a signal of the second readout line is directly electrically connected to the second readout line.

20. The display device according to claim 19, in, The first readout detour line includes a plurality of first readout detour lines, Wherein, the first data bypass line includes a plurality of first data bypass lines, Wherein, the second data bypass line includes a plurality of second data bypass lines, and At least one of the first readout bypass lines is located between the first data bypass lines in the second direction, or is located between the second data bypass lines in the second direction.

21. The display device according to claim 19, in, Each of the first detour side area, the second detour side area, and the third detour side area includes: an adjacent area contacting the non-display area in the second direction; and a separation region, being the remaining region other than the adjacent region, wherein the first readout detour line is located in the adjacent area of ​​each of the first detour side area, the second detour side area, and the third detour side area, and Wherein, the first data bypass line and the second data bypass line are located in the separate area of ​​each of the first bypass side area, the second bypass side area, and the third bypass side area.

22. The display device according to claim 21, in, The detour area of ​​the display area further includes a fourth detour side area between the first detour side area and the third detour side area, The data lines further include a fifth data line in the fourth detour side region and a sixth data line in the second detour side region. The readout lines further include a third readout line in the first detour side region and a fourth readout line in the fourth detour side region, Wherein, the circuit layer further includes: a second readout bypass line extending in the first direction and electrically connected to the third readout line; a second readout connection line extending in the second direction, paired with the fifth data line, and electrically connected to the second readout bypass line; a third data bypass line extending in the first direction and electrically connected to the fifth data line; and a third data connection line extending in the second direction, paired with the sixth data line, and electrically connected to the third data bypass line, and Among them, among the readout transmission lines: the third readout transmission line configured to transmit the signal of the third readout line is electrically connected to the third readout line through the second readout connecting line and the second readout bypass line, and the fourth readout transmission line configured to transmit the signal of the fourth readout line is directly electrically connected to the fourth readout line.

23. The display device according to claim 22, in, The fourth detour side area includes an adjacent area contacting the non-display area in the second direction and a separation area which is a remaining area except the adjacent area, wherein the first readout detour line is located in the adjacent area of ​​each of the second detour side area and the third detour side area, wherein the second readout detour line is located in the adjacent area of ​​each of the first detour side area and the fourth detour side area, and The first data bypass line and the second data bypass line are located in the separate area of ​​each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area.

24. The display device according to claim 23, in, The circuit layer further includes: a first power line and a second power line in the non-display area and configured to transmit a first power and a second power for driving the light emitting element, respectively; and a first auxiliary line extending in the first direction and electrically connected to the second power line, wherein each of the first detour side area, the second detour side area, the third detour side area and the fourth detour side area further includes a buffer area between the adjacent area and the separation area, and Wherein, the first auxiliary line is located in the buffer area of ​​each of the first detour side area, the second detour side area, the third detour side area, and the fourth detour side area.

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