Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a data signal line, a data auxiliary line, a display area and a non-display area, the display area comprises a first display area and a second display area, the non-display area comprises a fan-out area, and the fan-out area comprises a plurality of fan-out wires; the data signal lines located in the first display area are directly and electrically connected with the fan-out wires, and the data signal lines located in the second display area are electrically connected with the fan-out wires through the data auxiliary lines. The display panel further comprises a substrate and a first coupling adjustment structure located between a film layer where the substrate is located and a film layer where the data auxiliary lines are located. In the thickness direction of the display panel, the first coupling adjustment structure is overlapped with the data auxiliary line and is connected with the fixed potential signal line, so that a stable capacitance structure can be formed between the data auxiliary line and the first coupling adjustment structure, and the stable capacitance structure can ensure that the signal potential in the data auxiliary line is relatively stable; interference of other changing signals on signals in the data auxiliary line can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. However, there are still some technical problems in the display panels in the prior art that need to be solved. For example, there will be coupling interference in the signals on some signal lines, thereby affecting the display effect of the display panel. Summary of the invention

[0003] An embodiment of the present invention provides a display panel and a display device, wherein a first coupling adjustment structure electrically connected to a fixed potential signal line is arranged between a film layer where a data auxiliary line is located and a film layer where a substrate is located, and a stable capacitor structure is formed with the first coupling adjustment structure and the data auxiliary line to avoid interference of other signals with signals in the data auxiliary line, thereby ensuring display stability.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a plurality of signal lines;

[0005] The signal lines include data signal lines, and a plurality of the data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect;

[0006] The display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least on one side of the first display area along the second direction; the first display area and the second display area both comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located on one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out wirings;

[0007] The signal line further includes a data auxiliary line, at least a portion of one of the data auxiliary lines is located in the display area, and the data signal line located in the second display area is electrically connected to the fan-out wiring through the data auxiliary line;

[0008] The display panel also includes a substrate and a first coupling adjustment structure located between the film layer where the substrate is located and the film layer where the data auxiliary line is located; along the thickness direction of the display panel, the first coupling adjustment structure overlaps with the data auxiliary line, and the first coupling adjustment structure is electrically connected to the fixed potential signal line.

[0009] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the first aspect.

[0010] In the technical solution provided by the embodiment of the present invention, the display panel includes a plurality of signal lines, the signal lines include data signal lines and data auxiliary lines, the data signal lines located in the first display area are directly electrically connected to the fan-out wiring, the data signal lines located in the second display area are electrically connected to the fan-out wiring through the data auxiliary lines, and at least part of the data auxiliary lines are located in the display area, so that the data signal lines in the second display area can be avoided from being directly electrically connected to the fan-out wiring, and the area of ​​the fan-out area can be avoided from being increased due to the setting of the fan-out wiring, thereby increasing the area ratio of the display area and the screen ratio of the display panel. Further, the display panel also includes a first coupling adjustment structure located between the film layer where the data auxiliary lines are located and the film layer where the substrate is located, the first coupling adjustment structure is electrically connected to the fixed potential signal line and overlaps with the data auxiliary line along the thickness direction of the display panel, so that a stable capacitor structure can be formed between the data auxiliary line and the first coupling adjustment structure, and the stable capacitor structure can ensure that the signal potential in the data auxiliary line is relatively stable, and can reduce the interference of other changing signals on the signal in the data auxiliary line. On the other hand, a stable capacitor structure can be formed between the data auxiliary line and the first coupling adjustment structure, so that the lateral capacitance formed between the data auxiliary line and other signal lines is small, which can also reduce the interference of other changing signals on the signals in the data auxiliary line, ensure the stability of the data signal potential of the signals in the data auxiliary line, and ensure the stability of the display effect of the second display area and the entire display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 3 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a multi-channel distribution unit provided by an embodiment of the present invention

[0016] Figure 5 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 6is a circuit connection diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 7 The embodiment of the present invention provides a Figure 6 A timing diagram of an embodiment of signals of a pixel circuit shown in FIG.

[0019] Figure 8 is a circuit connection diagram of another pixel circuit provided by an embodiment of the present invention;

[0020] Fig. 9 The embodiment of the present invention provides a Figure 8 A timing diagram of an embodiment of signals of a pixel circuit shown in FIG.

[0021] Fig.10 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0022] Fig.11 yes Fig.10 A schematic structural diagram of the zeroth metal layer in the display panel;

[0023] Fig.12 yes Fig.10 The structural schematic of the first semiconductor layer in the display panel;

[0024] Fig.13 yes Fig.10 The structural intention of the first metal layer in the display panel;

[0025] Fig.14 yes Fig.10 The structural intention of the second metal layer in the display panel;

[0026] Fig.15 yes Fig.10 The structural intention of the third metal layer in the display panel;

[0027] Fig.16 yes Fig.10 A schematic diagram of the laminated structure of some film layers in the display panel;

[0028] Fig.17 yes Fig.10 The structural intention of the fifth metal layer in the display panel;

[0029] Fig.18 yes Fig.10 The structural intention of the anode layer in the display panel;

[0030] Fig.19 yes Fig.10 A schematic diagram of the laminated structure of some film layers in the display panel;

[0031] Fig. 20 yes Fig.10 A schematic diagram of the stacked structure of all film layers in the display panel;

[0032] Fig.21 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0033] Fig. 22 yes Fig.21 A schematic structural diagram of a zero-metal layer in the display panel;

[0034] Fig.23 yes Fig.21 A structural schematic of a first semiconductor layer in the display panel;

[0035] Fig.24 yes Fig.21 A structural intention of a first metal layer in the display panel;

[0036] Fig.25 yes Fig.21 A structural intention of a second metal layer in the display panel;

[0037] Fig.26 yes Fig.21 A structural schematic of a second semiconductor layer in the display panel;

[0038] Fig. 27 yes Fig.21 The structural intention of a fourth metal layer in the display panel;

[0039] Fig.28 yes Fig.21 A structural intention of a third metal layer in the display panel;

[0040] Fig.29 yes Fig.21 A schematic diagram of a laminated structure of a partial film layer in the display panel;

[0041] Fig.30 yes Fig.21 The structural intention of a fifth metal layer in the display panel;

[0042] Fig.31 yes Fig.21 The structural intention of an anode layer in the display panel;

[0043] Fig.32 yes Fig.21 A schematic diagram of a laminated structure of a partial film layer in the display panel;

[0044] Fig.33 yes Fig.21 A schematic diagram of a laminated structure of all film layers in the display panel;

[0045] Fig.34 yes Fig.21 A schematic structural diagram of another zero-metal layer in the display panel;

[0046] Fig.35 yes Fig.21 Another structural intention of the first semiconductor layer in the display panel;

[0047] Fig.36 yes Fig.21 The structural intention of another first metal layer in the display panel;

[0048] Fig.37 yes Fig.21 The structural intention of another second metal layer in the display panel;

[0049] Fig.38 yes Fig.21 Another structural intention of the second semiconductor layer in the display panel;

[0050] Fig.39 yes Fig.21 The structural intention of another fourth metal layer in the display panel;

[0051] Fig.40 yes Fig.21 The structural intention of another third metal layer in the display panel;

[0052] Fig.41 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel;

[0053] Fig.42 yes Fig.21 The structural intention of another fifth metal layer in the display panel;

[0054] Fig.43 yes Fig.21 Another structural intention of the anode layer in the display panel;

[0055] Fig.44 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel;

[0056] Fig.45 yes Fig.21 A schematic diagram of another laminated structure of all film layers in the display panel;

[0057] Fig.46 yes Fig.21A schematic structural diagram of another zero-metal layer in the display panel;

[0058] Fig.47 yes Fig.21 A structural schematic diagram of another first semiconductor layer in the display panel;

[0059] Fig.48 yes Fig.21 A structural intention of another first metal layer in the display panel;

[0060] Fig.49 yes Fig.21 A structural intention of another second metal layer in the display panel;

[0061] Fig.50 yes Fig.21 A structural schematic diagram of another second semiconductor layer in the display panel;

[0062] Fig.51 yes Fig.21 A structural intention of a fourth metal layer in the display panel;

[0063] Fig.52 yes Fig.21 A structural intention of a third metal layer in the display panel;

[0064] Fig.53 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel;

[0065] Fig.54 yes Fig.21 A structural intention of a fifth metal layer in the display panel;

[0066] Fig.55 yes Fig.21 A structural intention of another anode layer in the display panel;

[0067] Fig.56 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel;

[0068] Fig.57 yes Fig.21 A schematic diagram of another laminated structure of all film layers in the display panel;

[0069] Fig.58 is a schematic diagram of stacking of some film layers in another display panel provided by an embodiment of the present invention;

[0070] Fig.59 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a system, product or device comprising a series of units is not necessarily limited to those steps or units clearly listed, but may include other units that are not clearly listed or inherent to these products or devices.

[0073] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Figure 3 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, combined with Figure 1 , Figure 2 and Figure 3As shown, the display panel provided by the embodiment of the present invention includes a plurality of signal lines; the signal lines include data signal lines DATA, the plurality of data signal lines DATA extend along a first direction (the X direction shown in the figure) and are arranged along a second direction (the Y direction shown in the figure); the first direction and the second direction intersect; the display panel also includes a display area AA and a non-display area NAA at least partially surrounding the display area AA, the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 is located on at least one side of the first display area AA1 along the second direction; the first display area AA1 and the second display area AA2 each include a plurality of data signal lines DATA; the non-display area NAA includes a first display area AA1 and a second display area AA2 ... the display area AA1 along the first direction A fan-out area NAA1 on one side, the fan-out area NAA1 includes multiple fan-out traces FANOUT; the signal line also includes a data auxiliary line FIAA, at least a part of a data auxiliary line FIAA is located in the display area AA, and the data signal line DATA located in the second display area AA2 is electrically connected to the fan-out trace FANOUT through the data auxiliary line FIAA; the display panel also includes a substrate 10 and a first coupling adjustment structure 11 located between the film layer where the substrate is located and the film layer where the data auxiliary line FANOUT is located; along the thickness direction of the display panel (the Z direction as shown in the figure), the first coupling adjustment structure 11 overlaps with the data auxiliary line FIAA, and the first coupling adjustment structure 11 is electrically connected to the fixed potential signal line.

[0074] Specifically, refer to Figure 1 and Figure 2 As shown, the display panel includes signal lines, and the signal lines include a data signal box DATA and other signal lines required to ensure the normal operation of the display panel, such as a power signal line, a scan signal line, and a touch signal line. Figure 1 As shown, the display panel may also include a pixel circuit 20 and a light-emitting element 30, the signal line is electrically connected to the pixel circuit 20, and is configured to provide a voltage signal and / or a current signal to the pixel circuit 20; the pixel circuit 20 is electrically connected to the light-emitting element 30, and is configured to drive the light-emitting element 30 to emit light under the action of the voltage signal and / or the current signal. Further, the pixel circuit 20 has various configuration modes, and the pixel circuit may be "2T1C", "7T1C" or "8T1C", where "T" represents a transistor and "C" represents a storage capacitor. The embodiment of the present invention defines the specific composition mode of the pixel circuit, for example, the "3T1C", "6T1C" pixel circuit, etc. are also within the scope of the technical solution protected by the embodiment of the present invention. The light-emitting element 30 may be at least one of a light-emitting diode, an organic light-emitting diode, and a micro light-emitting diode, and the embodiment of the present invention does not limit the specific form of the light-emitting element 30.

[0075] Continue to refer Figure 1 and Figure 2As shown, the display panel provided by the embodiment of the present invention includes a display area AA and a non-display area NAA, and the above-mentioned data signal line DATA, pixel circuit 20 and light emitting element 30 can be arranged in the display area AA. The display area AA further includes a first display area AA1 and a second display area AA2. Figure 2 In the example, the second display area AA2 is located on both sides of the first display area AA1 along the second direction Y, but it is not limited thereto. Figure 2 In the orientation shown, the second display area AA2 is located between the first display area AA1 and the non-display areas NA on the left and right sides. Along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The non-display area NAA includes a fan-out area NAA1, which is located on one side of the display area AA along the first direction X. Taking the lower side as an example in the figure, the fan-out area NAA1 can be arranged with multiple fan-out lines FANOUT, and the fan-out lines FANOUT are electrically connected to the data signal lines DATA, thereby connecting the data signal lines DATA to the display controller to ensure stable transmission of data signals. Continue to refer to Figure 2 , multiple data signal lines DATA are set in the first display area AA1 and the second display area AA2. The data signal line DATA in the first display area AA1 can be directly electrically connected to the fan-out line FANOUT. The data signal line DATA in the second display area AA2 is electrically connected to the fan-out line FANOUT through the data auxiliary line FIAA in the display area AA. The data auxiliary line FIAA can be understood as a connecting bridge between the data signal line DATA and the fan-out line FANOUT in the second display area AA2, and at least part of a data auxiliary line FIAA is located in the display area AA. In this way, the fan-out line FANOUT can be centrally set in the fan-out area NAA1 below the first display area AA1, thereby reducing the occupied space of the fan-out line FANOUT and the setting area of ​​the fan-out area NAA1, effectively reducing the proportion of the non-display area NAA, increasing the proportion of the display area AA of the display panel, increasing the display effect of the display panel, and realizing a narrow frame.

[0076] Furthermore, since the signal transmitted in the data auxiliary line FIAA is a data signal, when the potential in the data auxiliary line FIAA is set to float, the signal in the data auxiliary line FIAA will be disturbed by other jump signals and change, and the signal change in the data auxiliary line FIAA will cause the signal change in the data signal line DATA in the second display area AA2 connected thereto, thereby affecting the display brightness of the light-emitting element electrically connected to the data signal line DATA in the second display area AA2, resulting in display abnormality. Based on this, the display panel in the embodiment of the present invention also includes a first coupling adjustment structure 11, and along the thickness direction of the display panel, the first coupling adjustment structure 11 is located in the film layer below the data auxiliary line FIAA and overlaps with the data auxiliary line FIAA, so that a capacitor structure is formed between the first coupling adjustment structure 11 and the data auxiliary line FIAA. Since the first coupling adjustment structure 11 is electrically connected to the fixed potential signal line, in which a fixed potential signal is transmitted, in the capacitor structure formed between the first coupling adjustment structure 11 and the data auxiliary line FIAA, the potentials of the two capacitor plates, that is, the first coupling adjustment structure 11 and the data auxiliary line FIAA can be kept stable, ensuring that the data signal on the data auxiliary line FIAA will not be disturbed by other jump signals and change even when the potential is floating, or ensuring that the data signal on the data auxiliary line FIAA is less disturbed by other jump signals when the potential is floating, ensuring good signal stability in the data auxiliary line FIAA, and further ensuring the stability of the signal in the data signal line DATA in the second display area AA2 connected thereto, thereby ensuring the normal display effect of the display panel.

[0077] In summary, the display panel provided by the embodiment of the present invention, by setting the data signal line located in the second display area to be electrically connected to the fan-out line through the data auxiliary line, can avoid the data signal line in the second display area being directly electrically connected to the fan-out line, can avoid increasing the area of ​​the fan-out area due to the setting of the fan-out line, improve the area ratio of the display area, and improve the screen ratio of the display panel. Furthermore, the first coupling adjustment structure overlaps with the projection of the data auxiliary line on the plane where the substrate is located, that is, the first coupling adjustment structure and the data auxiliary line form a capacitor structure, and the first coupling adjustment structure is electrically connected to the fixed potential signal line, so that the signals in the first coupling adjustment structure and the data auxiliary line can be kept stable, and the interference of other jump-changing signals on the signals in the data auxiliary line can be reduced, thereby ensuring the stability of the display effect of the second display area and the entire display area.

[0078] Based on the above embodiments, Figure 4 is a schematic diagram of the structure of a multiplex distribution unit provided by an embodiment of the present invention, such as Figure 4As shown, the display panel also includes a plurality of multi-way distribution units DEMUX and at least two switch control lines SW arranged in the non-display area; the multi-way distribution unit DEMUX includes at least two multi-way distribution switches K, and the multi-way distribution switch K includes an input end, an output end and a control end; in the same multi-way distribution unit DEMUX, the input ends of at least two multi-way distribution switches K are connected, the output ends of at least two multi-way distribution switches K are respectively electrically connected to different data signal lines DATA, the control ends of at least two multi-way distribution switches K are respectively electrically connected to different switch control lines SW, and the data signal line DATA located in the second display area AA2 is electrically connected to the output end of the multi-way distribution switch K through the data auxiliary line FIAA.

[0079] like Figure 4 As shown, the display panel also includes a plurality of multiplexer units DEMUX located in the non-display area NAA. The multiplexer unit DEMUX can be understood as a combined logic circuit, which includes at least two multiplexer switches K. In the same multiplexer unit DEMUX, the input ends of at least two multiplexer switches K are connected and electrically connected to the same signal output terminal, and the output ends of at least two multiplexer switches K are electrically connected to different data signal lines DATA, respectively. That is, the same multiplexer unit DEMUX can distribute the input signal transmitted by the same signal output terminal to any one of the multiple data signal lines DATA in a time-sharing manner, so that the number of signal output terminals can be reduced under the premise of realizing the normal output of the data signal, and the difficulty of arranging the new output terminal in the display panel can be reduced.

[0080] Specifically, Figure 4Take the multiplexer unit DEMUX including two multiplexers K1 and K2 as an example for explanation. Correspondingly, the display panel includes two switch control lines SW1 and SW2, the control end of the multiplexer switch K1 is electrically connected to the switch control line SW1, the control end of the multiplexer switch K2 is electrically connected to the switch control line SW2, and the enable signal of the multiplexer switch is transmitted in time-sharing in the switch control lines SW1 and SW2. When the enable signal is transmitted in the switch control line SW1, the multiplexer switch K1 is turned on, and the multiplexer switch K1 is used to transmit the data signal input from the input end to the data signal line connected thereto through the data auxiliary line FIAA; at this time, the switch control line SW2 transmits a non-enable signal, the multiplexer switch K2 is turned off, and the data auxiliary line FIAA connected to the multiplexer switch K2 is in a state of potential floating, and the data auxiliary line FIAA connected to the multiplexer switch K2 is easily interfered by other jumping signals. Similarly, when the enable signal is transmitted in the switch control line SW2, the multi-way distribution switch K2 is turned on, and the multi-way distribution switch K2 is used to transmit the data signal input at the input end to the data signal line connected thereto through the data auxiliary line FIAA; at this time, the non-enable signal is transmitted in the switch control line SW1, the multi-way distribution switch K1 is closed, and the data auxiliary line FIAA connected to the multi-way distribution switch K1 is in a state of potential floating, and the data auxiliary line FIAA connected to the multi-way distribution switch K1 is easily interfered by other jumping signals. Therefore, the embodiment of the present invention adds a first coupling adjustment structure 11, and sets a capacitor structure between the first coupling adjustment structure 11 and the data auxiliary line FIAA, and transmits a fixed potential signal therein, so as to ensure that the potentials in the first coupling adjustment structure 11 and the data auxiliary line FIAA can be kept stable, and ensure that the data signal on the data auxiliary line FIAA will not be interfered by other jumping signals and change even when the potential is floating, so as to ensure that the signal stability in the data auxiliary line FIAA is good.

[0081] It should be noted that Figure 4 The multiplexing unit DEMUX shown may include a multiplexing unit DEMUX connected to the data auxiliary line FIAA and a multiplexing unit DEMUX connected to the data signal line DATA. The distribution of the multiplexing unit DEMUX connected to the data auxiliary line FIAA and the multiplexing unit DEMUX connected to the data signal line DATA is not limited in the embodiment of the present invention.

[0082] Based on the above embodiments, Figure 5 is a schematic cross-sectional view of another display panel provided by an embodiment of the present invention. Figure 2 and Figure 5As shown, the data auxiliary line FIAA includes a first wiring branch FIAA1 and a second wiring branch FIAA2 connected, the first wiring branch FIAA1 extends along the second direction and is electrically connected to the data signal line DATA of the second display area AA1, and the second wiring branch FIAA2 extends along the first direction and is electrically connected to the fan-out wiring FANOUT; the first coupling adjustment structure 11 includes a first coupling branch 111 and / or a second coupling branch 112; the first coupling branch 111 is located at the film layer where the substrate 10 is located and the first wiring branch F IAA1 is located between the film layers and extends along the second direction; along the thickness direction of the display panel, the first coupling division 111 overlaps with the first routing division FIAA1, and the first coupling division 111 is electrically connected to the fixed potential signal line; the second coupling division 112 is located between the film layer where the substrate 10 is located and the film layer where the second routing division FIAA2 is located and extends along the first direction; along the thickness direction of the display panel, the second coupling structure 112 overlaps with the second routing division FIAA2, and the second coupling division 112 is electrically connected to the fixed potential signal line.

[0083] Specifically, the data auxiliary line FIAA includes a first wiring section FIAA1 and a second wiring section FIAA2 connected, the first wiring section FIAA1 extends along the second direction and is electrically connected to the data signal line DATA of the second display area AA1, and the second wiring section FIAA2 extends along the first direction and is electrically connected to the fan-out wiring FANOUT. The first wiring section FIAA1 and the second wiring section FIAA2 can be arranged in the same layer or in different layers. Figure 5 Only the first routing division FIAA1 and the second routing division FIAA2 are set in different layers and electrically connected through vias as an example for explanation. The first coupling adjustment structure 11 may include a first coupling division 111 coupled with the first routing division FIAA1 to form a capacitor structure, and the first coupling division 111 is electrically connected to the fixed potential signal line, so that a stable capacitor structure is formed between the first coupling division 111 and the first routing division FIAA1, and the potentials in the first coupling division 111 and the first routing division FIAA1 can be kept stable, ensuring that the data signal on the first routing division FIAA1 will not be disturbed by other jump signals and change even when the potential is floating, ensuring that the signal stability in the first routing division FIAA1 is good.

[0084] Furthermore, the first coupling adjustment structure 11 may also include a second coupling division 112 coupled with the second routing division FIAA2 to form a capacitor structure, and the second coupling division 112 is electrically connected to the fixed potential signal line, so that a stable capacitor structure is formed between the second coupling division 112 and the second routing division FIAA2, and the potentials in the second coupling division 112 and the second routing division FIAA2 can be kept stable, ensuring that the data signal on the second routing division FIAA2 will not be disturbed by other jump signals and change even when the potential is floating, thereby ensuring good signal stability in the second routing division FIAA2.

[0085] In summary, the first coupling adjustment structure 11 can be set to include at least one of the first coupling sub-section 111 and the second coupling sub-section 112. In actual processes, the first coupling adjustment structure 11 can be set to include the first coupling sub-section 111 and / or the second coupling sub-section 112 according to actual needs and wiring space. By setting the first coupling adjustment structure 11 to include the first coupling sub-section 111 and / or the second coupling sub-section 112, at least part of the data auxiliary line FIAA forms a stable capacitor structure with the first coupling adjustment structure 11, ensuring that the signal potential in the data auxiliary line FIAA is stable and free from interference from other jump signals.

[0086] It should be noted that when the first coupling adjustment structure 11 includes the first coupling sub-section 111 and the second coupling sub-section 112, the first coupling sub-section 111 and the second coupling sub-section 112 can be arranged in the same layer or in different layers, and the embodiment of the present invention does not limit this. In addition, when the first coupling sub-section 111 and the second coupling sub-section 112 are arranged in the same layer, the first coupling sub-section 111 and the second coupling sub-section 112 can be connected to form an integrated structure to ensure that the performance of the capacitor structure between the first coupling adjustment structure 11 and the data auxiliary line FIAA is stable.

[0087] Based on the above embodiments, Figure 6 is a circuit connection diagram of a pixel circuit provided by an embodiment of the present invention, Figure 7 The embodiment of the present invention provides a Figure 6 A timing diagram of signals of an embodiment of a pixel circuit shown in FIG. Figure 8 is a circuit connection diagram of another pixel circuit provided by an embodiment of the present invention, Fig. 9 The embodiment of the present invention provides a Figure 8 The timing diagram of the signal of the pixel circuit shown in the embodiment, combined with Figure 1 , Figure 6-Figure 9As shown, the display panel also includes a pixel circuit 20, the pixel circuit 20 includes at least one first type transistor, the first type transistor includes a first active layer POLY; the first coupling section 111 includes a first sub-coupling section 1111, and the film layer where the first sub-coupling section 1111 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located.

[0088] Specifically, refer to Figure 6 As shown, the pixel circuit may include a first light emission control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emission control transistor T6, an anode reset transistor T7 and a storage capacitor Cst. Figure 6 Taking the pixel circuit shown in FIG. 1 as an example, its working process can be roughly as follows: the scanning signal line (shown as S1 in the figure) connected to the control end of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and when the initialization reset transistor T5 is turned on, the reset signal in the reset signal line (shown as VREF1 in the figure) connected to the input end of the initialization reset transistor T5 is written to the gate of the driving transistor T3 to reset the first node N1. The storage capacitor Cst is set to ensure that the potential of the first node N1 is stable. The scanning signal line (shown as S2 in the figure) connected to the control end of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and when the threshold compensation transistor T4 is turned on, the threshold voltage compensation is performed on the driving transistor T3. The scanning signal line (shown as S2 in the figure) connected to the control end of the data write transistor T2 can control the on and off of the data write transistor T2, and when the data write transistor T2 is turned on, the data signal on the data signal line DATA is written to the first pole of the driving transistor T3. At the same time, the scanning signal line (shown as S2 in the figure) connected to the control end of the anode reset transistor T7 can control the on and off of the anode reset transistor T7, and reset the anode of the light-emitting element 30 connected to the pixel circuit when the anode reset transistor T7 is turned on, that is, the reset signal on the reset signal line (shown as VFER2 in the figure) is written to the anode of the light-emitting element 30. The light-emitting control signal line EMIT connected to the control end of the first light-emitting control transistor T1 and the control end of the second light-emitting control transistor T6 can control the on and off of the control end of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, and write the power signal transmitted by the power signal line PVDD to the light-emitting element 3 when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, thereby realizing the display and light emission of the light-emitting element 30. Specifically, refer to Figure 7As shown, a frame time Y of the display panel at least includes an initialization writing stage Y1, a data writing stage Y2 and a light emitting stage Y3. In the initialization stage Y1, the initialization reset transistor T5 is turned on under the control of the scan signal S1, and the initialization signal VREF1 is written into the first node N1 electrically connected to the gate of the driving transistor T3 to initialize the gate of the driving transistor T3. In the data writing stage Y2, the data writing transistor T2 and the threshold compensation transistor T4 are turned on under the control of the scan signal S2, so that the data signal Vdata is sequentially written into the gate of the driving transistor T3 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4. At the same time, in the data writing stage Y2, the anode reset transistor T7 is turned on under the control of the scan signal S2, and the reset signal Vref2 is written into the anode of the light emitting element 30 to initialize the anode of the light emitting element 30. In the light emitting stage Y3, the first light emitting transistor T1 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal Emit, so that the driving transistor T3 generates a driving current that can be transmitted to the anode of the light emitting element 30, thereby driving the light emitting element 30 to emit light.

[0089] For further reference, Figure 8 As shown, the pixel circuit may include a first light emission control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emission control transistor T6, an anode reset transistor T7, a bias transistor T8 and a storage capacitor Cst. The working process of the pixel circuit is similar to the above process and will not be repeated here. Figure 8 In the pixel circuit, the scanning signal line (shown as SP in the figure) connected to the control end of the bias transistor T8 can control the on and off of the bias transistor T8, and when the bias transistor T8 is turned on, the bias signal transmitted by the reset signal line (shown as DVH in the figure) is written into the bias transistor T8, and the bias adjustment of the second node N2 is performed.

[0090] Specifically, refer to Fig. 9 As shown, further, in a driving cycle Y of the pixel circuit, it includes a data writing stage Y1, a light emitting stage Y2 and a light emitting holding stage Y3, wherein the data writing stage Y1 includes a non-enable level stage of the light emitting control signal Emit, the light emitting stage Y2 includes an enable level stage of the light emitting control signal Emit, and in the light emitting holding stage Y3, the light emitting control signal Emit includes a plurality of non-enable level stages and at least one enable level stage ( Fig. 9In the example of an enable level stage, the level of the bias voltage signal line DVH in the data writing stage Y1 and the light emitting stage Y2 can be the same as or different from the level of the bias voltage signal line DVH in the light emitting holding stage Y3. Fig. 9 ). Further, the data writing phase Y1 includes a first bias adjustment phase Y11, in which the signal transmitted by the scanning signal line SP includes at least one low level period, and during this period, the signal transmitted by the scanning signal line S2N includes at least one high level period. In other words, in the first bias adjustment phase Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on, and the bias signal of the bias voltage signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and then transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4, that is, in the first bias adjustment phase Y11, the bias signal can perform bias adjustment on the first node N1, the second node N2 and the third node N3. The data writing stage Y1 also includes an initialization and second bias adjustment stage Y12, in which the signal transmitted by the scanning signal line S2N includes at least one high level period, and the signal transmitted by the scanning signal line S2N also includes at least one high level period. In other words, in the initialization and second bias adjustment stage Y12, the initialization transistor T5 is turned on, and the later threshold compensation transistor T4 is also turned on. The initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5, and the initialization signal line VREF1 can also adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4. The data writing stage Y1 also includes a data signal writing stage Y13, in which the signal transmitted by the scanning signal line S2N includes a high level period, and the signal transmitted by the scanning signal line SP* includes at least one low level period. In other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. The data writing phase Y1 also includes a third bias adjustment phase Y14. In the third bias adjustment phase Y14, the signal transmitted by the scanning signal line SP includes at least one low level period. During this period, the bias of the second phase N2 can be further adjusted by the bias transistor T8.

[0091] Based on the above embodiments, the types of transistors in the pixel circuit may be diverse. The pixel circuit may include a first type transistor, and the first type transistor includes a first active layer POLY. For example, the first type transistor may be a low temperature polysilicon (LTPS) transistor. The low temperature polysilicon transistor has the advantages of high switching speed, high carrier mobility, and low power. For example, Figure 6 and Figure 8 As shown, Figure 6 The transistors in are all first type transistors, that is, the first light emission control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emission control transistor T6 and the anode reset transistor T7 are all low temperature polysilicon transistors, Figure 8 Some of the transistors in are first type transistors, wherein the first light emission control transistor T1, the data writing transistor T2, the driving transistor T3, the second light emission control transistor T6, the anode reset transistor T7 and the bias transistor T8 are all first type transistors, Figure 8 The threshold compensation transistor T4 and the initialization reset transistor T5 may be second type transistors. The second type transistors may be oxide (Indium Gallium Zinc Oxide, IGZO) transistors. Oxide transistors have advantages such as small leakage current.

[0092] Furthermore, the first coupling section 111 includes a first sub-coupling section 1111, and the film layer where the first sub-coupling section 1111 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, that is, the first sub-coupling section 1111 is located in the film layer on the side of the display panel closer to the substrate 10. In the thickness direction of the display panel, the distance between the film layer where the first sub-coupling section 1111 is located and the first wiring section FIAA1 is relatively large. In this way, while ensuring that a coupling capacitor can be formed between the first sub-coupling section 1111 and the first wiring section FIAA1, it has little effect on the transmission signal in the first wiring section FIAA1, and will not affect the size of the data signal when the data signal is normally transmitted in the first wiring section FIAA1.

[0093] On the basis of the above embodiment, the display panel also includes a shading structure 12, and the film layer where the shading structure 12 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located; the shading structure 12 includes a plurality of shading sections 121, and along the thickness direction of the display panel, the shading section 121 overlaps with the channel region in the first active layer; the first sub-coupling section 1111 is arranged on the same layer as the shading structure 12.

[0094] Specifically, the display panel is formed by overlapping multiple film layers. Fig.10 is a schematic diagram of a film structure of a display panel provided by an embodiment of the present invention, with reference to Fig.10 As shown, the film structure of the pixel circuit from the bottom to the light-emitting side of the display panel can be a substrate 10, a first buffer layer 201, a zero metal layer 202 (M0), a second buffer layer 203, a first semiconductor layer 204, a first insulating layer 205, a first metal layer 206 (M1), an interlayer insulating layer 207, a second metal layer 208 (MC), a second insulating layer 209, a third metal layer 210 (M2), a first planarization layer 211, a fifth metal layer 212 (M3), a second planarization layer 213 and an anode layer 214 (RE). Specifically, Fig.11 yes Fig.10 A schematic diagram of the structure of the zeroth metal layer in the display panel, Fig.12 yes Fig.10 The structural schematic of the first semiconductor layer in the display panel, Fig.13 yes Fig.10 The structural intention of the first metal layer in the display panel, Fig.14 yes Fig.10 The structural intention of the second metal layer in the display panel, Fig.15 yes Fig.10 The structural intention of the third metal layer in the display panel, Fig.16 yes Fig.10 The schematic diagram of the laminated structure of some film layers in the display panel, specifically the schematic diagram of the laminated structure from the zeroth metal layer to the third metal layer, Fig.17 yes Fig.10 The structural intention of the fifth metal layer in the display panel, Fig.18 yes Fig.10 The structural intention of the anode layer in the display panel, Fig.19 yes Fig.10 The schematic diagram of the laminated structure of some film layers in the display panel, specifically the schematic diagram of the laminated structure from the fifth metal layer to the anode layer, Fig. 20 yes Fig.10 The schematic diagram of the stacked structure of all film layers in the display panel is specifically a schematic diagram of the stacked structure from the zeroth metal layer to the anode layer. Figure 10-Figure 20 As shown, Figure 10-Figure 20The film layer structure described above may correspond to the case where the pixel circuit includes a first type transistor. Among them, the first active layer POLY may be located in the first semiconductor layer 204; the film layer where the light shielding structure 12 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, and it may be located in the zero metal layer 202; the film layer where the first sub-coupling structure 1111 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, and it may be located in the zero metal layer 202; the gate of the first type transistor may be located in the first metal layer 206, the two capacitor plates of the storage capacitor may be located in the first metal layer 206 and the second metal layer 208 respectively, the first wiring division FIAA1 may be located in the third metal layer 209, and the second wiring division FIAA2 may be located in the fifth metal layer 210.

[0095] Furthermore, Fig.21 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention, referring to Fig.11 As shown, the film structure of the pixel circuit from the bottom to the light-emitting side of the display panel may be a substrate 10, a first buffer layer 201, a zero metal layer 202, a second buffer layer 203, a first semiconductor layer 204, a first insulating layer 205, a first metal layer 206, an interlayer insulating layer 207, a second metal layer 208, a second insulating layer 209, a second semiconductor layer 215 (IGZO), a third insulating layer 216, a fourth metal layer 217 (MG), a fifth insulating layer 218, a third metal layer 210 (M3), a first planarization layer 211, a fifth metal layer 212 (M3), a second planarization layer 213 and an anode layer 214. Specifically, Fig. 22 yes Fig.21 A schematic diagram of the structure of a zero-metal layer in the display panel, Fig.23 yes Fig.21 A schematic structural diagram of a first semiconductor layer in the display panel, Fig.24 yes Fig.21 The structural intention of a first metal layer in the display panel, Fig.25 yes Fig.21 The structural intention of a second metal layer in the display panel, Fig.26 yes Fig.21 A schematic structural diagram of a second semiconductor layer in the display panel, Fig. 27 yes Fig.21 The structural intention of a fourth metal layer in the display panel, Fig.28 yes Fig.21 The structural intention of a third metal layer in the display panel, Fig.29 yes Fig.21 A schematic diagram of a laminated structure of a portion of the film layers in the display panel, specifically a schematic diagram of the laminated structure from the zeroth metal layer to the third metal layer, Fig.30yes Fig.21 The structural intention of a fifth metal layer in the display panel, Fig.31 yes Fig.21 The structural schematic of an anode layer in the display panel, Fig.32 yes Fig.21 A schematic diagram of a laminated structure of a portion of the film layers in the display panel, specifically a schematic diagram of the laminated structure from the fifth metal layer to the anode layer, Fig.33 yes Fig.21 A schematic diagram of a stacked structure of all film layers in the display panel, specifically a schematic diagram of the stacked structure from the zeroth metal layer to the anode layer. Fig.34 yes Fig.21 A schematic diagram of the structure of another zeroth metal layer in the display panel, Fig.35 yes Fig.21 Another structural schematic of the first semiconductor layer in the display panel, Fig.36 yes Fig.21 Another structural intention of the first metal layer in the display panel, Fig.37 yes Fig.21 The structural intention of another second metal layer in the display panel, Fig.38 yes Fig.21 Another structural schematic of the second semiconductor layer in the display panel, Fig.39 yes Fig.21 The structural intention of another fourth metal layer in the display panel, Fig.40 yes Fig.21 Another structural intention of the third metal layer in the display panel, Fig.41 yes Fig.21 A schematic diagram of the laminated structure of another part of the film layers in the display panel, specifically a schematic diagram of the laminated structure from the zeroth metal layer to the third metal layer, Fig.42 yes Fig.21 The structural intention of another fifth metal layer in the display panel, Fig.43 yes Fig.21 Another structural intention of the anode layer in the display panel, Fig.44 yes Fig.21 A schematic diagram of the laminated structure of another part of the film layers in the display panel, specifically a schematic diagram of the laminated structure from the fifth metal layer to the anode layer, Fig.45 yes Fig.21 Another schematic diagram of the stacked structure of all film layers in the display panel is specifically a schematic diagram of the stacked structure from the zeroth metal layer to the anode layer. Fig.46 yes Fig.21 A schematic diagram of the structure of another zero-metal layer in the display panel, Fig.47 yes Fig.21 Another structural intention of the first semiconductor layer in the display panel is: Fig.48yes Fig.21 Another structural intention of the first metal layer in the display panel is: Fig.49 yes Fig.21 A structural intention of another second metal layer in the display panel is: Fig.50 yes Fig.21 Another structural schematic of the second semiconductor layer in the display panel is as follows: Fig.51 yes Fig.21 A structural intention of a fourth metal layer in the display panel is as follows: Fig.52 yes Fig.21 A structural intention of another third metal layer in the display panel is: Fig.53 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel, specifically a schematic diagram of a laminated structure from the zeroth metal layer to the third metal layer, Fig.54 yes Fig.21 A structural intention of a fifth metal layer in the display panel is as follows: Fig.55 yes Fig.21 Another structural intention of the anode layer in the display panel is: Fig.56 yes Fig.21 A schematic diagram of a laminated structure of another partial film layer in the display panel, specifically a schematic diagram of the laminated structure from the fifth metal layer to the anode layer, Fig.57 yes Fig.21 A schematic diagram of a stacked structure of all film layers in the display panel, specifically a schematic diagram of a stacked structure from the zeroth metal layer to the anode layer. Figure 21-Figure 57 As shown, Figure 21-Figure 57 The film layer structure described above may correspond to the case where the pixel circuit includes a first type transistor and a second type transistor. Among them, the first active layer POLY may be located in the first semiconductor layer 204; the film layer where the light shielding structure 12 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, and it may be located in the zero metal layer 202; the film layer where the first sub-coupling structure 1111 is located is located between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, and it may be located in the zero metal layer 202; the gate of the first type transistor may be located in the first metal layer 206, the two capacitor plates of the storage capacitor may be located in the first metal layer 206 and the second metal layer 208 respectively, the active layer of the second type transistor may be located in the second semiconductor layer 213, the top gate of the second type transistor may be located in the fourth metal layer 215, the first wiring division FIAA1 may be located in the third metal layer 209, and the second wiring division FIAA2 may be located in the fifth metal layer 210. The film layer structure of a specific pixel circuit can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and any of the above film layers can include at least one sublayer, which is not specifically limited in the embodiment of the present invention.

[0096] Specifically, since the channel region of the first active layer POLY will generate light leakage under the irradiation of external ambient light and thus affect the conduction performance of the first type of transistor, a light shielding structure 12 can be set between the substrate 10 and the first active layer POLY, and the light shielding structure 12 includes a plurality of light shielding sections 121, and the light shielding sections 121 are arranged to overlap with the channel region in the first active layer along the thickness direction of the display panel, so that the channel region of the first active layer POLY can be shielded by the light shielding sections 121, ensuring that the channel region of the first active layer POLY is protected from interference from external ambient light. It should be noted that the light shielding structure 12 can only shield the channel region of some transistors in the aforementioned pixel circuit, or can shield the channel region of all transistors in the aforementioned pixel circuit, and the embodiment of the present application does not limit this.

[0097] Furthermore, the first sub-coupling division 1111 is arranged in the same layer as the shading structure 12, for example, both are located in the zero metal layer 202. In this way, on the one hand, a coupling capacitor can be formed between the first sub-coupling division 1111 and the first wiring division FIAA1 to ensure that the first wiring division FIAA1 is not interfered by other jump signals when the potential is floating. On the other hand, the setting of the first sub-coupling division 1111 will not increase the film layer structure in the display panel, which is conducive to realizing the thin setting of the display panel. On the other hand, the first sub-coupling division 1111 is arranged in the same layer as the shading structure 12 and can be prepared in the same mask process. The setting of the first sub-coupling division 1111 does not increase the process difficulty of the display panel, thereby ensuring the simplicity of the process of the display panel.

[0098] In addition, the film layer where the first sub-coupling sub-section 1111 is located is located between the film layer where the substrate 10 is located and the film layer POLY where the first active layer is located, that is, the first sub-coupling sub-section 1111 is located in the zero metal layer M0. In the display panel, the zero metal layer M0 is the metal layer located at the bottom, and various signal lines, such as scanning signal lines, data signal lines or power signal lines, are usually not formed in this metal layer. Therefore, the routing space in the zero metal layer M0 is relatively sufficient, and the layout design is relatively simple, and the first sub-coupling sub-section 1111 and other signal lines will not be short-circuited due to insufficient routing space. Moreover, in the present application, the first sub-coupling sub-section 1111 and the first routing sub-section FIAA1 are overlapped, which can avoid the coupling capacitors on the first routing sub-section FIAA1 and other jump signal lines from affecting the transmission of the signal on the first routing sub-section FIAA1, which means that there will also be capacitance between the first sub-coupling sub-section 1111 and the first routing sub-section FIAA1. Although a capacitor needs to be formed between the first sub-coupling division 1111 and the first routing division FIAA1 to play a shielding role, this capacitor should not be too large to avoid adverse effects of excessive capacitance on the signal on the first routing division FIAA1. Therefore, the first sub-coupling division 1111 can be set on the lowest zero metal layer M0, so that the distance between the first sub-coupling division 1111 and the first routing division FIAA1 is larger, so that the capacitance formed between the first sub-coupling division 1111 and the first routing division FIAA1 is smaller, so as to avoid adverse effects of excessive capacitance on the signal on the first routing division FIAA1.

[0099] Based on the above embodiments, continue to refer to Figure 6-Figure 57 As shown, the display panel also includes a pixel circuit, which includes a driving transistor T3 and at least one switching transistor; the shading structure 12 includes a first shading portion 121a and a second shading portion 121b, and along the thickness direction of the display panel, the first shading portion 121a overlaps with the channel region of the first active layer in the driving transistor T3, and the second shading portion 121b overlaps with the channel region of the first active layer of at least part of the switching transistor; the first sub-coupling structure 1111 connects at least two second shading portions 121b arranged along the second direction.

[0100] Specific, combined Figure 6 and Figure 8 As shown, the pixel circuit includes a driving transistor and a switching transistor. The driving transistor can be understood as a transistor that converts a driving voltage signal into a driving current signal. Figure 6 and Figure 8 In the pixel circuit shown in FIG. 1 , the driving transistor is T3. All transistors except the driving transistor in the pixel circuit can be understood as switching transistors. Figure 6For example, the first light emission control transistor T1, the data writing transistor T2, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emission control transistor T6 and the anode reset transistor T7 are all switch transistors. Figure 8 For example, the first light emission control transistor T1, the data writing transistor T2, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emission control transistor T6, the anode reset transistor T7 and the bias adjustment transistor T8 are all switching transistors.

[0101] For further reference, Fig.11 , Fig.12 , Fig.16 , Fig. 22 , Fig.23 , Fig.29 , Fig.34 , Fig.35 , Fig.41 , Fig.46 , Fig.47 as well as Fig.53 As shown, the light shielding structure 12 includes a first light shielding sub-portion 121a and a second light shielding sub-portion 121b. Along the thickness direction of the display panel, the first light shielding sub-portion 121a overlaps with the channel region of the first active layer of the driving transistor T3, and the second light shielding sub-portion 121b overlaps with the channel region of the first active layer of at least part of the switching transistor. The corresponding conditions of the second light shielding sub-portion 121b and the channel region of the first active layer of the switching transistor are diverse. Among them, Fig.11 , Fig.12 as well as Fig.16 The pixel circuit shown in the figure is described by taking the overlap of the second light shielding structure 121b and the channel region of the first active layer of the initialization reset transistor T5 as an example; Fig. 22 , Fig.23 as well as Fig.29 The pixel circuit shown is described by taking the overlap of the second light shielding structure 121b with the anode reset transistor T7 and the channel region of the first active layer of the bias adjustment transistor T8 as an example; Fig.34 , Fig.35 as well as Fig.41 The pixel circuit shown is described by taking the overlap of the second light shielding structure 121b with the anode reset transistor T7 and the channel region of the first active layer of the bias adjustment transistor T8 as an example; Fig.46 , Fig.47 as well as Fig.53 The pixel circuit shown is described by taking the overlap of the second light shielding structure 121b with the channel region of the first active layer of the anode reset transistor T7 and the bias adjustment transistor T8 as an example. In actual design, the correspondence between the second light shielding sub-section 121b and the channel region of the first active layer of the switch transistor can be set according to requirements. Fig.11 , Fig. 22, Fig.34 as well as Fig.46 As shown, the first sub-coupling structure 1111 connects at least two second light shielding sub-sections 121b arranged along the second direction. Fig.11 , Fig. 22 , Fig.34 as well as Fig.46 The first sub-coupling structure 1111 is connected to a row of multiple second light-shielding sub-sections 121b arranged along the second direction as an example for description. Since the first sub-coupling structure 1111 is electrically connected to the fixed potential signal line, the first sub-coupling structure 1111 is connected to at least two second light-shielding sub-sections 121b arranged along the second direction, so that at least two second light-shielding sub-sections 121b arranged along the second direction are also electrically connected to the fixed potential signal line, and the potential in the second light-shielding sub-section 121b and the entire light-shielding structure is stable, and will not interfere with the potential in the first active layer shielded by it, thereby ensuring the normal operation of the entire pixel circuit.

[0102] The above embodiment is described based on the case where the first coupling section includes the first sub-coupling section. Furthermore, the first coupling section may also include sub-coupling sections in other configurations, which will be described in detail below.

[0103] Specifically, refer to Figure 11-Figure 57 As shown, the display panel also includes a pixel circuit, the pixel circuit includes at least one first type transistor, the first type transistor includes a first active layer POLY; the first coupling division includes a second sub-coupling division 1112, and the film layer where the second sub-coupling division 1112 is located is located between the film layer where the first active layer POLY is located and the film layer where the first routing division FIAA1 is located.

[0104] As mentioned above, the first type of transistor can be a low-temperature polysilicon transistor, and the first active layer includes silicon, for example, low-temperature polysilicon. Further, the first coupling subsection includes a second sub-coupling subsection 1112 located between the film layer where the first active layer is located and the film layer where the first wiring subsection FIAA1 is located, and the second sub-coupling subsection 1112 is electrically connected to the fixed potential and overlaps with the first wiring subsection FIAA1 along the thickness direction of the display panel. A stable coupling capacitor is formed between the second sub-coupling subsection 1112 and the first wiring subsection FIAA1 to ensure that the first wiring subsection FIAA1 is not interfered by the jump signal when the potential is floating, or the interference is small, to ensure the stability of the signal in the first wiring subsection FIAA1, and then to ensure the signal in the data signal line connected thereto, and to ensure the stability of the overall display effect of the display panel.

[0105] In addition, reference Fig.16 , Fig.29 , Fig.41 and Fig.53The orthographic projection of the second coupling sub-section 1112 on the substrate is located between the orthographic projection of the first routing section FIAA1 on the substrate and the orthographic projection of at least one scanning signal line on the substrate. In this way, the second coupling sub-section 1112 can also prevent coupling between the scanning signal lines of the first routing section FIAA1.

[0106] For further reference, Figure 11 to Figure 33 As shown, the pixel circuit also includes a storage capacitor Cst, and the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2 arranged opposite to each other, and the second electrode plate Cst2 is located on the side of the first electrode plate Cst1 away from the first active layer POLY; the display panel also includes a first semiconductor layer 204, a first metal layer 206, a second metal layer 208 and a third metal layer 210 arranged in a stacked manner, the first active layer POLY is located in the first semiconductor layer 204, the first electrode plate Cst1 is located in the first metal layer 206, and the second electrode plate Cst2 is located in the second metal layer 208; the first routing division FIAA1 is located in the third metal layer 210; the second sub-coupling division 1112 is located in the second metal layer 208.

[0107] As mentioned above, the active layer of the first type transistor can be located in the first semiconductor layer 204, the gate of the first type transistor and the first plate Cst1 of the storage capacitor Cst can be located in the first metal layer 206, that is, the M1 metal layer; the second plate Cst2 of the storage capacitor Cst can be located in the second metal layer 208, that is, the MC metal layer; the first wiring division FIAA1 can be located in the third metal layer 210, that is, the M2 metal layer. Further, refer to Fig.14 , Fig.16 , Fig.25 and Fig.29 As shown, the second sub-coupling sub-portion 1112 is arranged in the second metal layer 208. The arrangement of the second sub-coupling sub-portion 1112 does not add an additional film layer of the display panel, which is conducive to the thinning arrangement of the display panel. In addition, the second sub-coupling sub-portion 1112 is arranged in the second metal layer 208, which may correspond to a pixel circuit including only the first type of transistor, such as Fig.14 and Fig.16 As shown; the corresponding pixel circuit may also include a first type transistor and a second type transistor at the same time, such as Fig.25 and Fig.29As shown; the second sub-coupling sub-portion 1112 is arranged in the second metal layer 208, and the types of applicable pixel circuits are various, and the application range is wide. Further, the second sub-coupling sub-portion 1112 is arranged in the second metal layer 208, and the distance between it and the third metal layer 210 where the first wiring sub-portion FIAA1 is located in the thickness direction of the display panel is small, so that the coupling effect between the second sub-coupling sub-portion 1112 and the first wiring sub-portion FIAA1 is obvious, and the formed coupling capacitor has strong stability, which is beneficial to the first wiring sub-portion FIAA1 from being interfered by the jump signal when the potential is floating, or the interference degree is small, so as to ensure the stability of the signal in the first wiring sub-portion FIAA1.

[0108] For further reference, Figure 34-Figure 57 As shown, the pixel circuit further includes at least one second type transistor, the second type transistor includes a second active layer IGZO and a top gate, the top gate is located on the side of the second active layer IGZO away from the first active layer POLY; the pixel circuit further includes a storage capacitor Cst, the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2 arranged opposite to each other, the second electrode plate Cst2 is located on the side of the first electrode plate Cst1 away from the first active layer POLY; the display panel further includes a first semiconductor layer 204, a first metal layer 206, a first semiconductor layer 207, a first semiconductor layer 208, a first semiconductor layer 209, a first semiconductor layer 210, a first semiconductor layer 211, a first semiconductor layer 212, a first semiconductor layer 213, a first semiconductor layer 214, a first semiconductor layer 215, a first semiconductor layer 216, a first semiconductor layer 217, a first semiconductor layer 218, a first semiconductor layer 219, a first semiconductor layer 220, a first semiconductor layer 221, a first semiconductor layer 222, a first semiconductor layer 223, a first semiconductor layer 224, a first semiconductor layer 225, a first semiconductor layer 226, a first semiconductor layer 227, a first semiconductor layer 228, a first semiconductor layer 229, a first semiconductor layer 230, a first semiconductor layer 231, a first semiconductor layer 232, a first semiconductor layer 233, a first semiconductor layer 234, a first semiconductor layer 235, a first semiconductor layer 236, a first semiconductor layer 237, a first semiconductor layer 238, a first semiconductor layer 239, a first semiconductor layer 240, a first semiconductor layer 241, a first semiconductor layer 242, a first semiconductor layer 243, a first semiconductor layer 244, a first semiconductor layer 245, a first semiconductor layer 246, two metal layers 208, a second semiconductor layer 215, a fourth metal layer 217 and a third metal layer 210; the first active layer POLY is located in the first semiconductor layer 204, the first electrode Cst1 is located in the first metal layer 206, the second electrode Cst2 is located in the second metal layer 208, the second active layer IGZO is located in the second semiconductor layer 215, the top gate is located in the fourth metal layer 217, and the first routing division FIAA1 is located in the third metal layer 210; the second sub-coupling division 1112 is located in the second metal layer 208 and / or the fourth metal layer 217.

[0109] As mentioned above, the active layer of the first type transistor can be located in the first semiconductor layer 204, the gate of the first type transistor and the first plate Cst1 of the storage capacitor Cst can be located in the first metal layer 206, that is, the M1 metal layer; the second plate Cst2 of the storage capacitor Cst can be located in the second metal layer 208, that is, the MC metal layer; the active layer of the second type transistor can be located in the second semiconductor layer 215, and the top gate of the second type transistor can be located in the fourth metal layer 217, that is, the MG metal layer; the first wiring division FIAA1 can be located in the third metal layer 210, that is, the M2 metal layer. Further, refer to Fig.39 , Fig.41 , Fig.49 and Fig.53As shown, the second sub-coupling section 1112 is located in the second metal layer 208 and / or the fourth metal layer 217. The second sub-coupling section 1112 does not add an additional film layer to the display panel, which is beneficial to the thinning of the display panel. Fig.39 and Fig.41 Take the second coupling sub-section 1112 located in the fourth metal layer 217 as an example for explanation. Fig.49 and Fig.53 The second sub-coupling division 1112 is located in the second metal layer 208 as an example for explanation. Further, the second sub-coupling division 1112 is located in the second metal layer 208 and / or the fourth metal layer 217, and is relatively close to the third metal layer 210 where the first wiring division FIAA1 is located in the thickness direction of the display panel, so that the coupling effect between the second sub-coupling division 1112 and the first wiring division FIAA1 is obvious, and the formed coupling capacitor has strong stability, which is beneficial to the first wiring division FIAA1 from being interfered by the jump signal when the potential is floating, or the interference degree is small, so as to ensure the stability of the signal in the first wiring division FIAA1.

[0110] Based on the above embodiments, continue to refer to Figure 6 , Figure 8 and 11- Fig.57 As shown, the pixel circuit includes a voltage regulating transistor; the signal line also includes a voltage regulating signal line, which is electrically connected to the first electrode of the voltage regulating transistor; the voltage regulating signal line includes a first voltage regulating section, which extends along the second direction, and at least part of the first voltage regulating section is located between the film layer where the first active layer POLY is located and the film layer where the first routing section FIAA1 is located; the second sub-coupling section 1112 is multiplexed as at least part of the first voltage regulating section.

[0111] Specifically, refer to Figure 6 and Figure 8 The pixel circuit includes a voltage regulating transistor, and the signal line also includes a voltage regulating signal line, the voltage regulating signal line is electrically connected to the first electrode (that is, the input end) of the voltage regulating transistor, so that the voltage regulating signal is input through the voltage regulating transistor to the position where the voltage regulation is required in the pixel circuit, such as the gate of the driving transistor, the first electrode and / or the second electrode of the driving transistor, the anode of the light emitting element, etc. Specifically, the voltage regulating transistor may include Figure 6 The initialization reset transistor T5 and the anode reset transistor T7 shown include Figure 8The initialization reset transistor T5, the anode reset transistor T7 and the bias adjustment transistor T8 are shown; that is to say, the voltage adjustment transistor includes one or more of the initialization reset transistor T5, the anode reset transistor T7 and the bias adjustment transistor T8. The voltage adjustment signal line is a signal line for transmitting a fixed potential signal, which outputs a fixed potential signal to the first pole (that is, the input end) of the voltage adjustment transistor, such as an initialization reset signal, a bias adjustment signal and an anode reset signal. Correspondingly, the voltage adjustment signal line may include an initialization reset signal line, an anode reset signal line and a bias adjustment signal line. In addition, the voltage adjustment signal line may include a first voltage adjustment section extending along the second direction and located between the film layer where the first active layer POLY is located and the film layer where the first routing section FIAA1 is located, so that the second sub-coupling section 1112 can be multiplexed as at least part of the first voltage adjustment section to ensure a simple structure setting in the display panel.

[0112] Based on the above embodiments, continue to refer to Figure 6 , Figure 8 and 11- Fig.57 As shown, the voltage regulating transistor includes an initialization reset transistor T5 and an anode reset transistor T7; the voltage regulating signal line includes an initialization reset signal line VREF1 and an anode reset signal line VREF2; the pixel circuit also includes a driving transistor T3, and the display panel also includes a light emitting element 30; the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3; the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the light emitting element 30; the initialization reset signal line VREF1 includes a first initialization reset line VREF1 1, a plurality of first initialization reset lines VREF11 are arranged along a first direction and extend along a second direction, the first voltage regulation division includes the first initialization reset line VREF11; the second sub-coupling division 1112 is multiplexed as the first initialization reset line VREF11; and / or, the anode reset signal line VREF2 includes a first anode reset line VREF21, a plurality of first anode reset lines VREF21 are arranged along a first direction and extend along a second direction, the first voltage regulation division includes the first anode reset line VREF21; the second sub-coupling division 1112 is multiplexed as the first anode reset line VREF21.

[0113] As mentioned above, the voltage regulating transistor includes an initialization reset transistor T5 and an anode reset transistor T7. The initialization reset transistor T5 is used to transmit the initialization reset signal provided by the initialization reset signal line VREF1 to the gate of the driving transistor T3 when it is turned on, so as to reset the first node N1. The anode reset transistor T7 is used to transmit the anode reset signal provided by the anode reset signal line VREF2 to the anode of the light-emitting element when it is turned on, so as to reset the anode of the light-emitting element, so as to prevent the residual display signal of the previous needle from affecting the display effect of the current frame.

[0114] Further, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, a plurality of first initialization reset lines VREF11 are arranged along the first direction and extend along the second direction, the first initialization reset line VREF11 is electrically connected to a plurality of initialization reset transistors T5 arranged in the same row, and is used to provide an initialization reset signal to the plurality of initialization reset transistors T5 arranged in the same row. Since the initialization reset signal is a fixed potential signal, the second sub-coupling section 1112 also extends along the second direction, so the reference Fig.14 and Fig.16 As shown, the second sub-coupling division 1112 can be set to be multiplexed as the first initialization reset line VREF11, so that the second sub-coupling division 1112 and the first initialization reset line VREF11 have the same structure, which can form a stable capacitor structure with the first wiring division FIAA1 to ensure that the potential of the first wiring division FIAA1 is not interfered by other jump signals when it is floating, and can also provide an initialization reset signal for the initialization reset transistor T5, so as to realize a simple and efficient wiring scheme in the display panel. And / or, the anode reset signal line VREF2 includes a first anode reset line VREF21, and a plurality of first anode reset lines VREF21 are arranged along the first direction and extend along the second direction. The first anode reset line VREF21 is electrically connected to a plurality of anode reset transistors T7 arranged in the same row, and is used to provide an anode reset signal for the plurality of anode reset transistors T7 arranged in the same row. Since the anode reset signal is a fixed potential signal, the second sub-coupling division 1112 also extends along the second direction, so the reference Fig.25 and Fig.29 As shown, Fig.39 and Fig.41 As shown, Fig.51 and Fig.53 As shown, the second sub-coupling division 1112 can be set to be multiplexed as the first anode reset line VREF21. In this way, the second sub-coupling division 1112 and the first anode reset line VREF21 have the same structure, which can form a stable capacitor structure with the first wiring division FIAA1 to ensure that the potential of the first wiring division FIAA1 is not interfered by other jump signals when it is floating, and can also provide an anode reset signal for the anode reset transistor T7, thereby realizing a simple and efficient wiring solution in the display panel.

[0115] For further information, please refer to Fig.14 and Fig.16 As shown, the second sub-coupling section 1112 is multiplexed into a first initialization reset line VREF11 and a first anode reset line VREF21; along the first direction, the first initialization reset line VREF11 and the first anode reset line VREF21 are alternately arranged.

[0116] Specifically, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, and the anode reset signal line VREF2 includes a first anode reset line VREF21. Among the two second sub-coupling divisions 1112 adjacently arranged along the first direction, one of the second sub-coupling divisions 1112 is multiplexed as the first initialization reset line VREF11, and the other second sub-coupling division 1112 is multiplexed as the first anode reset line VREF21. In this way, the first initialization reset line VREF11 and the first anode reset line VREF21 are evenly distributed in the entire display area, ensuring that the initialization reset signal and the anode reset signal can be well transmitted in the entire display area.

[0117] Based on the above embodiments, continue to refer to Figure 6 , Figure 8 and 11- Fig.57 As shown, the voltage regulation signal line includes a second voltage regulation section, the second voltage regulation section extends along the first direction, and the second voltage regulation section and the first voltage regulation section are arranged in different layers and are electrically connected.

[0118] As mentioned above, the voltage regulation signal line includes a first voltage regulation section extending along the second direction. Further, the voltage regulation signal line may also include a second voltage regulation section extending along the first direction, and the second voltage regulation section is arranged in a different layer from the first voltage regulation section and is electrically connected, so that the first voltage regulation section and the second voltage regulation section form a grid-shaped voltage regulation signal line, so that the voltage regulation signal line is evenly distributed in the entire display area, and the voltage regulation transistors at different positions can be connected to the voltage regulation signal line to ensure a good voltage regulation effect. Further, the second voltage regulation section is arranged in a different layer from the first voltage regulation section and is electrically connected, and the second voltage regulation section is arranged in parallel with the first voltage regulation section, which is conducive to reducing the resistance of the voltage regulation signal line, reducing the signal attenuation caused by impedance during the transmission of the voltage regulation signal, and ensuring the accuracy of the voltage regulation signal.

[0119] For further reference, Fig.15 and Fig.17As shown, the initialization reset signal line VREF1 includes a second initialization reset line VREF12, and a plurality of second initialization reset lines VREF12 extend along the first direction and are arranged along the second direction. The second voltage adjustment section may include the second initialization reset line VREF12, so that the second initialization reset line VREF12 extending along the first direction and the first initialization reset line VREF11 extending along the second direction form an initialization reset signal line VREF1 with a grid structure, ensuring that the initialization reset signal line VREF1 is evenly distributed in the entire display area, and can reduce the resistance in the initialization reset signal line VREF1, thereby ensuring that the initialization reset signal has a high accuracy.

[0120] For further information, please refer to Fig.17 , Fig.30 , Fig.42 as well as Fig.54 As shown, the anode reset signal line VREF2 includes a second anode reset line VREF22, and a plurality of second anode reset lines VREF22 extend along the first direction and are arranged along the second direction. The second voltage adjustment section may include the second anode reset line VREF22, so that the second anode reset line VREF22 extending along the first direction and the first anode reset line VREF21 extending along the second direction form a grid-structured anode reset signal line VREF2, ensuring that the anode reset signal line VREF2 is evenly distributed in the entire display area, and can reduce the resistance in the anode reset signal line VREF2, thereby ensuring that the anode reset signal is highly accurate.

[0121] For further information, please refer to Fig.30 , Fig.42 as well as Fig.54 As shown, the bias adjustment signal line DVH includes a second bias adjustment line DVH2, and a plurality of second bias adjustment lines DVH2 extend along the first direction and are arranged along the second direction. The second voltage adjustment section may include the second bias adjustment line DVH2, so that the second bias adjustment line DVH2 extending along the first direction and the first bias adjustment line DVH1 extending along the second direction form a grid structure of bias adjustment signal lines DVH, thereby ensuring that the bias adjustment signal lines DVH are evenly distributed in the entire display area, and can reduce the resistance in the bias adjustment signal lines DVH, thereby ensuring high accuracy of the bias adjustment signal.

[0122] Further, when the second voltage adjustment subsection includes at least two of the second initialization reset line VREF12, the second anode reset signal line VREF22, and the second bias adjustment line DVH2, the two different signal lines may be alternately arranged in the second direction. Fig.17As shown, the second voltage regulation subsection includes a second initialization reset line VREF12 and a second anode reset signal line VREF22. At this time, the second initialization reset line VREF12 and the second anode reset signal line VREF22 are alternately arranged in the second direction to ensure that the second initialization reset line VREF12 and the second anode reset signal line VREF22 are evenly distributed in the entire display area. Fig.30 , Fig.42 and Fig.54 As shown, when the second voltage regulation section includes both the second anode reset signal line VREF22 and the second bias adjustment line DVH2, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 are alternately arranged in the second direction to ensure that the second anode reset signal line VREF22 and the second bias adjustment line DVH2 are evenly distributed in the entire display area. When the second voltage regulation section includes both the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2, the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 can be arranged in the second direction, and it has a variety of feasible arrangements, such as the second initialization reset line VREF12-the second anode reset signal line VREF22-the second bias adjustment line DVH-the second initialization reset line VREF12-the second anode reset signal line VREF22-the second bias adjustment line DVH, or the second initialization reset line VREF12-the second bias The first embodiment of the present invention is to provide a reset adjustment line DVH-second anode reset signal line VREF22-second initialization reset line VREF12-second bias adjustment line DVH-second anode reset signal line VREF22, or a second anode reset signal line VREF22-second bias adjustment line DVH-second initialization reset line VREF12-second anode reset signal line VREF22-second bias adjustment line DVH-second initialization reset line VREF12. The embodiment of the present invention does not limit the arrangement of the three, and it only needs to ensure that the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 can be distributed more evenly in the display area.

[0123] Based on the above embodiments, continue to refer to Fig.30 , Fig.42 as well as Fig.54As shown, the signal lines also include a plurality of first power signal lines PVDD, which extend along the first direction and are arranged along the second direction; a second voltage adjustment division, a second routing division FIAA2 and two data signal lines DATA are arranged between two adjacent first power signal lines PVDD; the second voltage adjustment division and the second routing division FIAA2 are arranged between two adjacent data signal lines DATA, or the two data signal lines DATA are arranged between the second voltage adjustment division and the second routing division FIAA2.

[0124] like Fig.30 , Fig.42 as well as Fig.54 , the signal line also includes a plurality of first power signal lines PVDD, and the first power signal line PVDD serves as a positive power signal line for providing a positive power signal to the pixel circuit. In order to ensure that the loss of the positive power signal during transmission is relatively small, the line width of the first power signal line PVDD is generally relatively large, as shown in the figure. Furthermore, the first power signal line PVDD, the data signal line DATA, the second routing division FIAA2 and the second voltage adjustment division are all signal lines extending along the first direction, and can be arranged in the same layer, for example, in the metal layer closest to the anode side. In addition, two adjacent first power signal lines PVDD are provided with a second voltage adjustment division, a second routing division FIAA2 and two data signal lines DATA, wherein the second voltage adjustment division can be one of the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 mentioned above. As shown Fig.30 , Fig.42 as well as Fig.54 As shown, there are two data signal lines DATA, a second routing portion FIAA2 and a second anode reset signal line VREF22 arranged between two adjacent first power signal lines PVDD; there are two data signal lines DATA, a second routing portion FIAA2 and a second bias adjustment line DVH2 arranged between two adjacent first power signal lines PVDD.

[0125] Furthermore, the settings of the data signal line DATA, the second routing division FIAA2 and the second voltage adjustment division match the settings of different transistors in the pixel circuit. The second voltage adjustment division and the second routing division FIAA2 may be set between two adjacent data signal lines DATA, or the two data signal lines DATA may be set between the second voltage adjustment division and the second routing division FIAA2. The relative position relationship between the data signal line DATA and the second routing division FIAA2 is diverse and can match different pixel circuit settings. Furthermore, the second voltage adjustment division and the second routing division FIAA2 are set between two adjacent data signal lines DATA, and the second voltage adjustment division (one of the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2) can be used as a shielding signal line between two adjacent data signal lines DATA, and a shielding signal line between the second routing division FIAA2 and the data signal line DATA, to reduce interference between different data signals.

[0126] Based on the above embodiments, continue to refer to Figure 8 and 22- Fig.57 As shown, the voltage regulating transistor includes an initialization reset transistor, an anode reset transistor and a bias regulating transistor; the voltage regulating signal line includes an initialization reset signal line, an anode reset signal line and a bias regulating signal line; the pixel circuit also includes a driving transistor, and the display panel also includes a light-emitting element; the initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light-emitting element; the bias regulating transistor is electrically connected between the bias regulating signal line and the first electrode and / or the second electrode of the driving transistor; the initialization reset signal line includes a first initialization reset signal line. line, a plurality of first initialization reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulation division includes the first initialization reset line; the anode reset signal line includes the first anode reset line, a plurality of first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulation division includes the first anode reset line; the bias regulation signal line includes the first bias regulation line, a plurality of first bias regulation lines are arranged along the first direction and extend along the second direction, and the first voltage regulation division includes the first bias regulation line; the second sub-coupling division is multiplexed as at least one of the first initialization reset line, the first anode reset line and the first bias regulation line.

[0127] Specifically, the voltage regulating transistor includes an initialization reset transistor T5, an anode reset transistor T7 and a bias regulating transistor T8. The initialization reset transistor T5 is used to transmit the initialization reset signal provided by the initialization reset signal line VREF1 to the gate of the driving transistor T3 when it is turned on, so as to reset the first node N1. The anode reset transistor T7 is used to transmit the anode reset signal provided by the anode reset signal line VREF2 to the anode of the light-emitting element when it is turned on, so as to reset the anode of the light-emitting element, so as to avoid the display signal residual from the previous needle affecting the display effect of the current frame. The bias regulating transistor T8 is used to transmit the bias regulating signal provided by the bias regulating signal line DVH to the second node N2 and / or the third node N3 when it is turned on, so as to bias the second node N2 and / or the third node N3.

[0128] Further, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, a plurality of first initialization reset lines VREF11 are arranged along the first direction and extend along the second direction, the first initialization reset line VREF11 is electrically connected to a plurality of initialization reset transistors T5 arranged in the same row, and is used to provide an initialization reset signal to the plurality of initialization reset transistors T5 arranged in the same row. Since the initialization reset signal is a fixed potential signal, the second sub-coupling section 1112 also extends along the second direction, so the reference Fig.14 and Fig.16 As shown, the second sub-coupling division 1112 can be set to be multiplexed as the first initialization reset line VREF11. In this way, the second sub-coupling division 1112 and the first initialization reset line VREF11 have the same structure, which can form a stable capacitor structure with the first wiring division FIAA1 to ensure that the potential of the first wiring division FIAA1 is not interfered by other jump signals when it is floating, and can also provide an initialization reset signal for the initialization reset transistor T5, thereby realizing a simple and efficient wiring solution in the display panel.

[0129] The anode reset signal line VREF2 includes a first anode reset line VREF21, and a plurality of first anode reset lines VREF21 are arranged along the first direction and extend along the second direction. The first anode reset line VREF21 is electrically connected to a plurality of anode reset transistors T7 arranged in the same row, and is used to provide an anode reset signal to the plurality of anode reset transistors T7 arranged in the same row. Since the anode reset signal is a fixed potential signal, the second sub-coupling section 1112 also extends along the second direction, so the reference Fig.25 and Fig.29 As shown, Fig.39 and Fig.41 As shown, Fig.51 and Fig.53As shown, the second sub-coupling division 1112 can be set to be multiplexed as the first anode reset line VREF21. In this way, the second sub-coupling division 1112 and the first anode reset line VREF21 have the same structure, which can form a stable capacitor structure with the first wiring division FIAA1 to ensure that the potential of the first wiring division FIAA1 is not interfered by other jump signals when it is floating, and can also provide an anode reset signal for the anode reset transistor T7, thereby realizing a simple and efficient wiring solution in the display panel.

[0130] The bias adjustment signal line DVH includes a first bias adjustment line DVH1, and a plurality of first bias adjustment lines DVH1 are arranged along the first direction and extend along the second direction. The first bias adjustment line DVH1 is electrically connected to a plurality of bias adjustment transistors T8 arranged in the same row, and is used to provide a bias adjustment signal for the plurality of bias adjustment transistors T8 arranged in the same row. Since the bias adjustment signal is a fixed potential signal, the second sub-coupling sub-section 1112 also extends along the second direction, so the second sub-coupling sub-section 1112 can be set to be multiplexed as the first bias adjustment line DVH1. In this way, the second sub-coupling sub-section 1112 and the first bias adjustment line DVH1 have the same structure, which can form a stable capacitor structure with the first wiring sub-section FIAA1 to ensure that the first wiring sub-section FIAA1 is not interfered by other jump signals when the potential is floating, and can also provide an anode reset signal for the bias adjustment transistor T8, thereby realizing a simple and efficient wiring scheme in the display panel.

[0131] Therefore, the second sub-coupling division 1112 can be set to multiplex as at least one of the first initialization reset line VREF11, the first anode reset line VREF21 and the first bias adjustment line DVH1, so as to ensure that the second sub-coupling division 1112 and the first wiring division FIAA1 form a stable capacitor structure and ensure that the potential of the first wiring division FIAA1 is not interfered by other jump signals when it is floating. It can also provide a voltage adjustment signal for at least one of the initialization reset transistor T5, the anode reset transistor T7 and the bias adjustment transistor T8, so as to realize a simple and efficient wiring scheme in the display panel.

[0132] In summary, the above embodiment describes in detail the setting method of the first coupling structure. By setting a longitudinal (thickness direction of the display panel) coupling capacitor between the first coupling section and the first routing section, it can be ensured that the first routing section has a relatively stable potential when the potential is floating.

[0133] Based on the above embodiments, continue to refer to Figure 22-Figure 57As shown, the display panel further includes a plurality of pixel circuits, the pixel circuit further includes at least one second type transistor; the pixel circuit includes a driving transistor T3 and an initial reset transistor T5, the signal line includes an initialization reset signal line VREF1, and the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3; the second type transistor includes an initialization reset transistor T5; the plurality of initialization reset transistors include a first initialization reset transistor T51, a second initialization reset transistor T52, and a third initialization reset transistor T53 that are adjacently arranged along a second direction; the distance between the active layer of the first initialization reset transistor T51 and the active layer of the second initialization reset transistor T52 is a first distance, and the distance between the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53 is a second distance ; The first distance is smaller than the second distance; The signal line further comprises a plurality of first scanning signal lines SIN, The first scanning signal lines SIN extend along the second direction and are arranged along the first direction, and along the thickness direction of the display panel, The first scanning signal lines SIN overlap with the active layers of the first initialization reset transistor T51, the second initialization reset transistor T52 and the third initialization reset transistor T53; The display panel further comprises a second coupling adjustment structure 13, The second coupling adjustment structure 13 connects the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53; The second coupling adjustment structure 13 is electrically connected to the fixed potential signal line, and the orthographic projection of the second coupling adjustment structure 13 on the plane where the substrate is located is located between the orthographic projection of the first routing portion FIAA1 on the plane where the substrate is located and the orthographic projection of the first scanning signal line SIN on the plane where the substrate is located.

[0134] Specifically, as mentioned above, the pixel circuit includes a second type transistor, which may be an oxide semiconductor transistor having a small leakage current characteristic. Further, the second type transistor may include an initialization reset transistor T5, which is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3. Since the initialization reset transistor T5 is a second type transistor, its small leakage current characteristic can ensure that the gate of the driving transistor T3, that is, the potential of the first node N1, is stable.

[0135] For further reference, Fig.26 , Fig.38 as well as Fig.50As shown, the multiple initialization reset transistors include a first initialization reset transistor T51, a second initialization reset transistor T52, and a third initialization reset transistor T53 that are adjacently arranged along the second direction; the distance between the active layer of the first initialization reset transistor T51 and the active layer of the second initialization reset transistor T52 is a first distance, and the distance between the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53 is a second distance; the first distance is smaller than the second distance, that is, the distance between the active layer of the first initialization reset transistor T51 and the second initialization reset transistor T52 is smaller than the distance between the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53, and the second initialization reset transistor T52 and the third initialization reset transistor T53 are two initialization reset transistors T5 with active layers farther apart along the second direction. Further, refer to Fig.26 , Fig. 27 , Fig.29 , Fig.38 , Fig.39 , Fig.41 , Fig.50 , Fig.51 and Fig.53As shown, the signal line also includes a plurality of first scanning signal lines SIN, the first scanning signal lines SIN extend along the second direction and are arranged along the first direction, and along the thickness direction of the display panel, the first scanning signal line SIN overlaps with the active layer of the first initialization reset transistor T51, the active layer of the second initialization reset transistor T52, and the active layer of the third initialization reset transistor T53, and the first scanning signal line S1N transmits a scanning signal for controlling the first initialization reset transistor T51, the second initialization reset transistor T52, and the third initialization reset transistor T53 to be turned on or off, and the scanning signal is a jump signal, so the first scanning signal line S1N will pull down or pull up the rated potential of the signal in the first wiring division FIAA1 when the potential in the first wiring division FIAA1 is floating, resulting in abnormal display. Therefore, the above embodiment illustrates that by setting a first coupling section 111 overlapping with the first wiring section FIAA1 and electrically connected to the fixed potential signal line, the first coupling section 111 overlaps with the first wiring section FIAA1 to form a longitudinal (thickness direction of the display panel) coupling capacitor to ensure the stability of the signal in the first wiring section FIAA1. On this basis, the display panel provided by the embodiment of the present invention may also include a second coupling adjustment structure 13, the second coupling adjustment structure 13 connects the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53; the second coupling adjustment structure 13 is electrically connected to the fixed potential signal line, and the orthographic projection of the second coupling adjustment structure 13 on the plane where the substrate 10 is located is located between the orthographic projection of the first wiring section FIAA1 on the plane where the substrate 10 is located and the orthographic projection of the first scanning signal line S1N on the plane where the substrate is located, so that the second coupling adjustment structure 13 can form a lateral coupling capacitor with the first wiring section FIAA1 and the first scanning signal line S1N respectively. The lateral coupling capacitor formed between the second coupling adjustment structure 13 and the first wiring branch FIAA1 can ensure that the first wiring branch FIAA1 maintains a relatively stable potential when the potential is floating. The lateral coupling capacitor formed between the second coupling adjustment structure 13 and the first scanning signal line S1N can disperse a portion of the signal in the first scanning signal line SIN, reduce the coupling capacitance between the first scanning signal line SIN and the first wiring branch FIAA1, reduce the interference of the jump signal in the first scanning signal line SIN on the signal in the first wiring branch FIAA1, and ensure that the signal of the first wiring branch FIAA1 is relatively stable when the potential is floating.

[0136] Furthermore, the second coupling adjustment structure 13 can be arranged in the same layer as the active layer of the initialization reset transistor T5, that is, the second coupling adjustment structure 13 can be arranged in the second semiconductor layer 215, so that the second coupling adjustment structure 13 will not increase the film layer structure of the display panel, ensuring that the structure of the display panel is relatively simple.

[0137] Furthermore, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, and multiple first initialization reset lines are arranged along the first direction and extend along the second direction; the second coupling adjustment structure 13 is electrically connected to the first initialization reset line VREF11; along the thickness direction of the display panel, the second coupling adjustment structure 13 overlaps with the first initialization reset line VREF11.

[0138] Continue to refer Fig.26 , Fig. 27 , Fig.29 , Fig.38 , Fig.39 , Fig.41 , Fig.50 , Fig.51 and Fig.53 As shown, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, and the second coupling adjustment structure 13 overlaps and is electrically connected with the first initialization reset line VREF11, ensuring that a fixed positioning signal can be transmitted in the second coupling adjustment structure 13, and a relatively stable side coupling capacitor is formed with the first wiring division FIAA1 and the first scanning signal line S1N. In addition, the second coupling adjustment structure 13 overlaps and is electrically connected with the first initialization reset line VREF11, that is, the second coupling adjustment structure 13 is arranged in parallel with the first initialization reset line VREF11, which can also reduce the resistance on the first initialization reset line VREF11, reduce the loss of the initialization reset signal during the transmission process, and ensure the accuracy of the initialization signal.

[0139] The above embodiment describes in detail the configuration of the second coupling structure. By configuring a lateral (substrate plane) coupling capacitor between the second coupling section and the first routing section, it is possible to ensure that the first routing section has a relatively stable potential when the potential is floating.

[0140] Based on the above embodiments, continue to refer to Figure 6 , Figure 8 , Fig.11 -As shown in Figure 57, the signal line also includes a plurality of second scanning signal lines, which extend along the second direction and are arranged along the first direction; along the thickness direction of the display panel, the first wiring portion FIAA1 does not overlap with the second scanning signal lines; the display panel also includes a third coupling adjustment structure 14; along the thickness direction of the display panel, the third coupling adjustment structure 14 overlaps with the second scanning signal lines, and the third coupling adjustment structure 14 is electrically connected to the fixed potential signal line.

[0141] Specifically, the second scanning signal line is a signal line overlapping the active layer of the anode reset transistor T7. Figure 6 , Figure 11-Figure 20 The pixel circuit shown includes a first type transistor as an example, the second scanning signal line is S1; Figure 8 , Figure 22-Figure 57 The pixel circuit shown includes a first type transistor and a second type transistor as an example, and the second scan signal line is SP. Since the first wiring branch FIAA1 does not overlap with the second scan signal line along the thickness direction of the display panel, there will be lateral coupling interference between the first wiring branch FIAA1 and the second scan signal line, and the jumping signal on the second scan signal line will affect the potential in the first wiring branch FIAA1 when the potential of the first wiring branch FIAA1 is floating. Therefore, the embodiment of the present invention adds a third coupling adjustment structure 14, sets the third coupling adjustment structure 14 to be electrically connected to the fixed potential signal line, and in the thickness direction of the display panel, the third coupling adjustment structure 14 overlaps with the second scan signal line, so that a longitudinal coupling capacitor is formed between the third coupling adjustment structure 14 and the second scan signal line, which can disperse a part of the signal in the second scan signal line, reduce the coupling capacitance between the second scan signal line and the first wiring branch FIAA1, reduce the interference of the jumping signal in the second scan signal line on the signal in the first wiring branch FIAA1, and ensure that the signal of the first wiring branch FIAA1 is relatively stable when the potential is floating.

[0142] Based on the above embodiment, the display panel also includes a pixel circuit, the pixel circuit includes at least one first type transistor, the first type transistor includes a first active layer; the third coupling adjustment structure includes a third coupling division, and the film layer where the third coupling division is located is located between the film layer where the substrate is located and the film layer where the first active layer is located.

[0143] As mentioned above, the pixel circuit includes at least one first type transistor, the first type transistor is a low temperature polysilicon transistor, and the first active layer includes silicon, such as low temperature polysilicon. The third coupling adjustment structure includes a third coupling sub-section, and the film layer where the third coupling sub-section is located is located between the film layer where the substrate is located and the film layer where the first active layer is located. For example, the third coupling sub-section is arranged in the same layer as the shading structure, and both are located in the zero metal layer M0. In this way, the arrangement of the third coupling sub-section will not increase the film layer structure of the display panel, which is conducive to realizing a thin display panel structure.

[0144] Based on the above embodiments, continue to refer to Figure 22-Figure 57 As shown, the display panel also includes a pixel circuit, the pixel circuit includes at least one first type transistor, the first type transistor includes a first active layer; the third coupling adjustment structure 14 includes a fourth coupling division 141, and the film layer where the fourth coupling division 141 is located is located between the film layer where the second scanning signal line is located and the film layer where the first routing division FIAA1 is located.

[0145] As mentioned above, the pixel circuit includes at least one first type transistor, the first type transistor is a low temperature polysilicon transistor, and the first active layer includes silicon, such as low temperature polysilicon. The third coupling adjustment structure 14 includes a fourth coupling sub-section 141, and the film layer where the fourth coupling sub-section 141 is located is located between the film layer where the second scanning signal line is located and the film layer where the first wiring sub-section FIAA1 is located, so that the distance between the fourth coupling sub-section 141 and the film layer where the second scanning signal line is located is small, and a coupling capacitor structure with a relatively stable coupling effect can be formed between the fourth coupling sub-section 141 and the second scanning signal line, which fully disperses the signal in the second scanning signal line and reduces the interference of the jump signal in the second scanning signal line on the signal in the first wiring sub-section FIAA1.

[0146] Specific, combined Fig. 27 , Fig.29 , Fig.39 , Fig.41 , Fig.49 and Fig.53 As shown, the fourth coupling sub-portion 141 may be located in the second metal layer 208, that is, the MC metal layer, and / or located in the fourth metal layer 217, that is, the MG metal layer. Fig. 27 , Fig.29 , Fig.39 , Fig.41 , Fig.49 and Fig.53 The fourth coupling sub-portion 141 is located in the fourth metal layer 217 as an example for description. The fourth coupling sub-portion 141 is arranged in the second metal layer 208 and / or the fourth metal layer 217. In addition to ensuring that a coupling capacitor structure with a relatively stable coupling effect can be formed between the fourth coupling sub-portion 141 and the second scanning signal line, the arrangement of the fourth coupling sub-portion 141 does not increase the film layer of the display panel, which is conducive to realizing a thin design of the display panel.

[0147] As mentioned above, the second sub-coupling sub-section 1112 can be multiplexed into at least one of the first initialization reset line VREF11, the first anode reset line VREF21, and the first bias adjustment line DVH1. Further, the fourth coupling sub-section 141 can be multiplexed into at least one of the first initialization reset line VREF11, the first anode reset line VREF21, and the first bias adjustment line DVH1, and the second sub-coupling sub-section 1112 and the fourth coupling sub-section 141 are multiplexed into different signal lines. Specifically, as Fig.25 , Fig. 27 and Fig.29 As shown, the second sub-coupling section 1112 is multiplexed as the first anode reset line VREF21, and the fourth coupling section 141 can be multiplexed as the first bias adjustment line DVH1; Fig.39 and Fig.41As shown, the second sub-coupling section 1112 is multiplexed as the first anode reset line VREF21, and the fourth coupling section 141 can be multiplexed as the first bias adjustment line DVH1; Fig.49 , Fig.51 and Fig.53 As shown, the second sub-coupling section 1112 is multiplexed as the first bias adjustment line DVH1 , and the fourth coupling section 141 can be multiplexed as the first anode reset line VREF21 .

[0148] To sum up, the above embodiment illustrates the setting method of the third coupling adjustment structure. By setting the third coupling adjustment structure to form a coupling capacitor with the second scanning signal line, the signal in the second scanning signal line can be dispersed, thereby reducing the interference of the jump signal in the second scanning signal line on the signal in the first routing section.

[0149] Based on the above embodiments, continue to refer to Figure 6 , Figure 11-Figure 20 As shown, the display panel also includes a pixel circuit, which includes a driving transistor T3 and a threshold compensation transistor T4, and the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4 are electrically connected to the first connection structure 15; the display panel also includes a first shielding structure 16, and the first shielding structure 16 is electrically connected to the fixed potential signal line; along the thickness direction of the display panel, the first shielding structure 16 covers at least part of the first connection structure 15.

[0150] refer to Figure 6 , Fig.15 , Fig.16 and Fig.17 As shown, the pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, and the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4 are electrically connected to the first connection structure 15, or the first connection structure connects the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4. That is to say, the potential at the first connection structure 15 is equivalent to the potential of the N1 node. In order to ensure the normal operation of the driving transistor T3, it is necessary to ensure that the potential at the position of the first connection structure 15 remains stable. Therefore, in the embodiment of the present invention, a first shielding structure 16 is provided, and the first shielding structure 16 is electrically connected to the fixed potential signal line; along the thickness direction of the display panel, the first shielding structure 16 covers at least part of the first connection structure 15. That is, a coupling capacitor is formed between the first shielding structure 16 and the first connection structure 15, and at the same time, since the first shielding structure 16 is electrically connected to the fixed potential signal line, the potential of the first shielding structure 16 is stable, and the coupling capacitor structure formed between the first shielding structure 16 and the first connection structure 15 is stable, so the potential of the first connection structure 15 can be guaranteed to be stable, and the normal operation of the driving transistor T3 can be ensured.

[0151] Based on the above embodiments, continue to refer to Figure 6 , Figure 11-Figure 20 As shown, the pixel circuit also includes a voltage regulating transistor; the signal line also includes a voltage regulating signal line, which is electrically connected to the first electrode of the voltage regulating transistor; the voltage regulating signal line includes a second voltage regulating section, which extends along the first direction; and the first shielding structure is electrically connected to at least part of the second voltage regulating section.

[0152] As mentioned above, the pixel circuit includes a voltage regulating transistor, and the signal line also includes a voltage regulating signal line, and the voltage regulating signal line is electrically connected to the first electrode (that is, the input end) of the voltage regulating transistor, so that the voltage regulating signal is input through the voltage regulating transistor to the position in the pixel circuit where voltage regulation is required, such as the gate of the driving transistor and the anode of the light-emitting element. Furthermore, the voltage regulating signal line may include a second voltage regulating section extending along the first direction, and the first shielding structure 16 is electrically connected to at least part of the second voltage regulating section, so that a fixed voltage regulating signal is transmitted in the first shielding structure 16, and there is no need to add a separate fixed potential signal to the first shielding structure 16. The implementation method of electrically connecting the first shielding structure 16 to the fixed potential signal line is simple. Fig.17 As shown, the first shielding structure 16 can be an initialization reset signal line VREF1 or an anode reset signal line VREF2.

[0153] Specifically, the voltage regulating transistor includes an initialization reset transistor T5 and an anode reset transistor T7; the voltage regulating signal line includes an initialization reset signal line VREF1 and an anode reset signal line VREF2; the display panel also includes a light-emitting element 30; the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3; the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the light-emitting element 30; the initialization reset signal line VREF1 includes a second initialization reset line VREF12, a plurality of second initialization reset lines VREF12 extend along the first direction and are arranged along the second direction, and the first shielding structure 16 is electrically connected to the second initialization reset line VREF12; and / or, the anode reset signal line VREF2 includes a second anode reset line VREF22, a plurality of second anode reset lines VREF22 extend along the first direction and are arranged along the second direction, and the first shielding structure 16 is electrically connected to the second anode reset line VREF22.

[0154] As mentioned above, the voltage regulating transistor includes an initialization reset transistor T5, the voltage regulating signal line includes an initialization reset signal line VREF1, the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3, and is used to initialize the gate of the driving transistor T3. Further, the voltage regulating transistor also includes an anode reset transistor T7, the voltage regulating signal line also includes an anode reset signal line VREF2, the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the anode of the light emitting element 30, and is used to reset the anode of the light emitting element 30.

[0155] Further, the initialization reset signal line VREF1 includes a first initialization reset line VREF11 extending along the second direction and a second initialization reset line VREF12 extending along the first direction, and the first initialization reset line VREF11 and the second initialization reset line VREF12 are electrically connected to form a grid-like initialization reset signal line VREF1, which ensures that the initialization reset signal line VREF1 is evenly distributed in the entire display area on the one hand, and reduces the resistance of the initialization reset signal line VREF1 on the other hand. Similarly, the anode reset signal line VREF2 includes a first anode reset line VREF21 extending along the second direction and a second anode reset line VREF22 extending along the first direction, and the first anode reset line VREF21 and the second anode reset line VREF22 are electrically connected to form a grid-like anode reset signal line VREF2, which ensures that the anode reset signal line VREF2 is evenly distributed in the entire display area on the one hand, and reduces the resistance of the anode reset signal line VREF2 on the other hand.

[0156] For further reference, Fig.15 , Fig.16 and Fig.17 As shown, the second initialization reset line VREF12 includes a first reset sub-portion VREF12a and a second reset sub-portion VREF12b arranged in different layers, and the first reset sub-portion VREF12a connects two second reset sub-portions VREF12b arranged adjacent to each other along the first direction, thus obtaining a second initialization reset line VREF12 extending along the first direction. Fig.17 As shown, the first shielding structure 16 and the second initialization reset line VREF12 are electrically connected to each other, which can be the first shielding structure 16 and the first reset sub-portion VREF12a. This ensures that the first shielding structure 16 is electrically connected to the fixed potential signal line, thereby achieving shielding protection for the first connection structure 16. Fig.15 , Fig.16 and Fig.17As shown, the second anode reset line VREF22 includes a third reset sub-portion VREF22a and a fourth reset sub-portion VREF22b arranged in different layers, and the third reset sub-portion VREF22a connects two fourth reset sub-portions VREF22b arranged adjacent to each other along the first direction, thereby obtaining a second anode reset line VREF22 extending along the first direction. Fig.17 As shown, the electrical connection between the first shielding structure 16 and the second anode reset line VREF22 may be the electrical connection between the first shielding structure 16 and the third reset sub-portion VREF22a, thereby ensuring that the first shielding structure 16 is electrically connected to the fixed potential signal line, thereby achieving shielding protection for the first connection structure 16.

[0157] For further reference, Fig.17 As shown, the first shielding structure 16 and the second initialization reset line VREF12 can be set on the same layer, and / or the first shielding structure 16 and the second anode reset line VREF22 can be set on the same layer, ensuring that the setting of the first shielding structure 16 does not increase the film layer in the display panel, ensuring the structure of the display panel is simple.

[0158] For further information, please refer to Fig.17 As shown, the initialization reset signal line VREF1 includes a second initialization reset line VREF12, and the anode reset signal line VREF2 includes a second anode reset line VREF22; along the second direction, the second initialization reset line VREF12 and the second anode reset line VREF22 are alternately arranged. Further, the first shielding structure electrically connected to the second initialization reset line VREF12 and the first shielding structure electrically connected to the second anode reset line VREF22 are alternately arranged in the second direction.

[0159] Based on the above embodiments, continue to refer to Figure 6 , Figure 11-Figure 20 As shown, the display panel also includes a pixel circuit, the pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4 are electrically connected to the first connection structure 15; the data auxiliary line FIAA includes a second routing branch FIAA2, the second routing branch FIAA2 extends along the first direction and is electrically connected to the fan-out routing; the display panel also includes a second shielding structure 17, the second shielding structure 17 is electrically connected to the fixed potential signal line; at least a part of the second shielding structure 17 is located between the orthographic projection of the data signal line DATA on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located; and / or, at least a part of the second shielding structure 17 is located between the orthographic projection of the second routing branch FIAA2 on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located.

[0160] As mentioned above, the pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, and the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4 are electrically connected to the first connection structure 15, or the first connection structure connects the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4. In order to ensure that the driving transistor T3 works normally, it is necessary to ensure that the potential at the position of the first connection structure 15 remains stable, and it is necessary to shield the interference caused by the jumping signal to the position of the first connection structure 15. Therefore, in the embodiment of the present invention, a second shielding structure 17 is provided, and the second shielding structure 17 is electrically connected to the fixed potential signal line, and the orthographic projection of at least part of the second shielding structure 17 on the plane where the substrate is located is located between the orthographic projection of the data signal line DATA on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located, that is, the second shielding structure 17 can shield the interference of the jumping signal in the data signal line DATA on the position of the first connection structure 15, and ensure the stability of the potential at the position of the first connection structure 15. And / or, the orthographic projection of at least part of the second shielding structure 17 on the plane where the substrate is located is located between the orthographic projection of the second routing division FIAA2 on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located, that is, the second shielding structure 17 can shield the interference of the jumping signal in the second routing division FIAA2 on the position of the first connection structure 15, thereby ensuring the stability of the potential at the position of the first connection structure 15.

[0161] For further information, please refer to Fig.14 , Fig.15 , Fig.16 and Fig. 20 As shown, the second shielding structure 17 may include a first sub-shielding structure 171 and a second sub-shielding structure 172. The orthographic projection of the first sub-shielding structure 171 on the plane where the substrate is located is located between the orthographic projection of the data signal line DATA on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located, and is used to shield the interference of the jump signal in the data signal line DATA on the position of the first connection structure 15; the orthographic projection of the second sub-shielding structure 172 on the plane where the substrate is located is located between the orthographic projection of the second routing division FIAA2 on the plane where the substrate is located and the orthographic projection of the first connection structure 15 on the plane where the substrate is located, and is used to shield the interference of the jump signal in the second routing division FIAA2 on the position of the first connection structure 15.

[0162] refer to Fig.14 As shown, the first sub-shielding structure 171 and the second sub-shielding structure 172 can be arranged in the same layer, for example, both are located in the second metal layer 208, that is, both are located in the MC metal layer. In this way, the second shielding structure 17 is arranged differently to increase the film layer in the display panel, which is conducive to realizing a thin display panel design.

[0163] Based on the above embodiments, continue to refer to Figure 22-Figure 33 As shown, the display panel also includes a pixel circuit, the pixel circuit includes a driving transistor T3 and a data writing transistor T2, the second electrode of the data writing transistor T2 and the first electrode of the driving transistor T3 are electrically connected to the second connection structure 18; the signal line also includes a plurality of light-emitting control signal lines EMIT, the plurality of light-emitting control signal lines EMIT are arranged along the first direction and extend along the second direction; the display panel also includes a third shielding structure 19, the third shielding structure 19 is electrically connected to the fixed potential signal line; the film layer where the third shielding structure 19 is located is located between the film layer where the second connection structure 18 is located and the film layer where the light-emitting control signal line EMIT is located, and the orthographic projection of the third shielding structure 19 on the plane where the substrate is located overlaps with the orthographic projection of the second connection structure 18 on the plane where the substrate is located and the orthographic projection of the light-emitting control signal line EMIT on the plane where the substrate is located.

[0164] As mentioned above, the pixel circuit includes a driving transistor T3, a data writing transistor T2 and a bias adjusting transistor T8, and the second electrode of the data writing transistor T2, the first electrode of the driving transistor T3 and the first electrode of the bias adjusting transistor T8 are electrically connected to the second connection structure 18, that is, the second connection structure 18 connects the second electrode of the writing transistor T2, the first electrode of the driving transistor T3 and the first electrode of the bias adjusting transistor T8. In other words, the potential of the second connection structure 18 is equivalent to the potential of the N2 node. Furthermore, the signal line also includes a plurality of light-emitting control signal lines EMIT, and along the thickness direction of the display panel, the light-emitting control signal line EMIT overlaps with the second connection structure 18, so the jumping signal in the light-emitting control signal line EMIT will interfere with the potential at the position of the second connection structure 18, affecting the normal operation of the driving transistor. Therefore, in the embodiment of the present invention, a third shielding structure 19 is additionally provided, and the third shielding structure 19 is electrically connected to the fixed potential signal line. The film layer where the third shielding structure 19 is located is located between the film layer where the second connection structure 18 is located and the film layer where the light-emitting control signal line EMIT is located, and the orthographic projection of the third shielding structure 19 on the plane where the substrate is located overlaps with the orthographic projection of the second connection structure 18 on the plane where the substrate is located and the orthographic projection of the light-emitting control signal line EMIT on the plane where the substrate is located. In this way, the third shielding structure 19 can shield the jumping signal in the light-emitting control signal line EMIT, avoid the interference of the jumping signal in the light-emitting control signal line EMIT on the potential at the position of the second connection structure 18, ensure the stability of the potential at the position of the second connection structure 18, and further ensure the normal operation of the driving transistor and the entire pixel circuit.

[0165] For further reference, Fig.24 , Fig. 27 as well as Fig.28As shown, the light emitting control signal line EMIT can be located in the first metal layer 206, that is, in the M1 metal layer; the third shielding structure 19 can be located in the fourth metal layer 217, that is, in the MG metal layer; the second connection structure 18 can be located in the third metal layer 210, that is, in the M2 metal layer. The provision of the third shielding structure 19 does not increase the film layer in the display panel, which is conducive to realizing a thin design of the display panel.

[0166] Based on the above embodiments, Fig.58 FIG. 1 is a schematic diagram of stacking some film layers in another display panel provided by an embodiment of the present invention, such as Figure 2 and Fig.58 As shown, the display panel also includes a virtual auxiliary line L0, which is arranged in the same layer as the data auxiliary line FIAA and there is a break D between the virtual auxiliary line L0 and the data auxiliary line FIAA; the display panel also includes a light-emitting element 30, and along the thickness direction of the display panel, the light-emitting element 30 covers the break D.

[0167] Furthermore, the display area AA may further include a virtual auxiliary line L0, and the virtual auxiliary line L0 includes a first virtual auxiliary line L01 and a second virtual auxiliary line L02. Figure 2 and Fig.58 As shown, the first virtual auxiliary line L01 and the second virtual auxiliary line L02 are both insulated from the data auxiliary line FIAA. The setting of the virtual auxiliary line L0 can compensate for the length of the data auxiliary line FIAA. For example, the first virtual auxiliary line L01 can be used to compensate the first routing section FIAA1, and the second virtual auxiliary line L02 is used to supplement the first routing section FIAA2. That is, by setting the virtual auxiliary line L0, the data auxiliary line FIAA setting area is wired evenly on the whole, ensuring that the density of routing settings in different areas is balanced, thereby avoiding different light reflectances in different areas of the display panel due to unbalanced routing settings, and avoiding the uneven display effect of the display panel.

[0168] Furthermore, the virtual auxiliary line L0 can be electrically connected to the fixed potential end. On the one hand, it can avoid interference with the display caused by coupling other signals due to the floating potential of the virtual auxiliary line L0. On the other hand, connecting in parallel with the fixed potential end can reduce the resistance on the fixed signal end or the fixed potential signal line, thereby ensuring that the fixed potential signal has a small loss during the transmission process.

[0169] For further information, please refer to Fig.58As shown, due to the insulation setting of the virtual auxiliary line L0 and the data auxiliary line FIAA, there is a break between the virtual auxiliary line L0 and the data auxiliary line FIA, specifically, there is a break D between the first virtual auxiliary line L01 and the first wiring segment FIAA1, and there is a break D between the second virtual auxiliary line L02 and the second connecting line segment L2. Further, in the thickness direction of the display panel, the light-emitting element 30 covers the break D, specifically, the anode RE of the light-emitting element covers the break D, which can be understood as the projection of at least one anode RE in the display panel at the substrate can cover the projection of the break D at the substrate, that is, it can ensure that the set break D is blocked, and the density of the wiring setting in different areas is balanced, thereby avoiding the different light reflectances in different areas of the display panel due to the uneven wiring setting, and avoiding the uneven display effect of the display panel.

[0170] On this basis, along the thickness direction of the display panel, the first coupling adjustment structure overlaps with the break. That is, along the thickness direction of the display panel, the first coupling adjustment structure covers the break, or in other words, there is no break in the first coupling adjustment structure, and the first coupling adjustment structure is a continuous structure, for example, a structure that is continuous in the first direction, and / or a structure that is continuous in the second direction. By setting the first coupling adjustment structure as a continuous structure, it is possible to ensure that the coupling effect between the first coupling structure and the data auxiliary line is good, and it is possible to ensure that when the potential of the data auxiliary line is floating, the potential in the data auxiliary line can be fully coupled with the data auxiliary line to ensure stability.

[0171] Based on the above embodiments, continue to refer to Fig.18 , Fig.31 , Fig.43 and Fig.55 As shown, the display panel also includes a light-emitting element 30; the light-emitting element includes a first color light-emitting element 301, a second color light-emitting element 302 and a third color light-emitting element 303, the first color light-emitting element 301, the second color light-emitting element 302 and the third color light-emitting element 303 are one of a red light-emitting element, a blue light-emitting element and a green light-emitting element and are different from each other; a plurality of first color light-emitting elements 301 and a second color light-emitting element 302 constitute a first virtual quadrilateral S1, the first color light-emitting element 301 is at a first vertex of the first virtual quadrilateral S1, the second color light-emitting element 302 is at a second vertex of the first virtual quadrilateral S1, and the third color light-emitting element 303 is inside the first virtual quadrilateral S1; a plurality of third color light-emitting elements 303 constitute a second virtual quadrilateral S2, a plurality of third color light-emitting elements 303 are respectively at the vertices of the second virtual quadrilateral S2, and the first color light-emitting element 301 or the second color light-emitting element 302 is inside the second virtual quadrilateral S2.

[0172] For details, see Fig.18 , Fig.31 , Fig.43 and Fig.55 , a plurality of first color light emitting elements 301 and second color light emitting elements 302 form a first virtual quadrilateral S1, two first color light emitting elements 301 are located at the diagonal corners of the first virtual quadrilateral S1, and two second color light emitting elements 302 are located at the other two diagonal corners of the first virtual quadrilateral S1. And the third color light emitting element 303 is placed inside the first virtual quadrilateral S1.

[0173] Furthermore, a plurality of third color light emitting elements 303 may also form a second virtual quadrilateral S2, in which the first color light emitting element 301 may be located inside, or the second color light emitting element 302 may be located inside. Furthermore, the first color, the second color, and the third color correspond to one of red, blue, and green, respectively. By arranging the light emitting elements as described above, a better rendering effect of the light emitting elements can be ensured, further ensuring the color display effect of the display panel.

[0174] Based on the same application concept, an embodiment of the present application further provides a display device, which includes any display panel provided in the above-mentioned embodiments. Fig.59 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Fig.59 As shown, the display device 1 includes a display panel 100. Therefore, the display device also has the beneficial effects of the display panel in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel, which will not be repeated below.

[0175] The display device 1 provided in the embodiment of the present application can be Fig.59 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0176] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, It is characterized in that Includes multiple signal lines; The signal lines include data signal lines, and a plurality of the data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect; The display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least on one side of the first display area along the second direction; the first display area and the second display area both comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located on one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out wirings; The signal line further includes a data auxiliary line, at least a portion of one of the data auxiliary lines is located in the display area, and the data signal line located in the second display area is electrically connected to the fan-out wiring through the data auxiliary line; The display panel also includes a substrate and a first coupling adjustment structure located between the film layer where the substrate is located and the film layer where the data auxiliary line is located; along the thickness direction of the display panel, the first coupling adjustment structure overlaps with the data auxiliary line, and the first coupling adjustment structure is electrically connected to the fixed potential signal line.

2. The display panel according to claim 1, It is characterized in that The data auxiliary line includes a first routing section and a second routing section connected, the first routing section extends along the second direction and is electrically connected to the data signal line of the second display area, and the second routing section extends along the first direction and is electrically connected to the fan-out routing line; The first coupling adjustment structure includes a first coupling sub-section and / or a second coupling sub-section; The first coupling sub-portion is located between the film layer where the substrate is located and the film layer where the first routing sub-portion is located and extends along the second direction; along the thickness direction of the display panel, the first coupling sub-portion overlaps with the first routing sub-portion, and the first coupling sub-portion is electrically connected to the fixed potential signal line; The second coupling section is located between the film layer where the substrate is located and the film layer where the second routing section is located and extends along the first direction; along the thickness direction of the display panel, the second coupling structure overlaps with the second routing section, and the second coupling section is electrically connected to the fixed potential signal line.

3. The display panel according to claim 2, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit including at least one first type transistor, the first type transistor including a first active layer; The first coupling section includes a first sub-coupling section, and the film layer where the first sub-coupling section is located is located between the film layer where the substrate is located and the film layer where the first active layer is located.

4. The display panel according to claim 3, It is characterized in that The display panel further includes a light shielding structure, wherein the film layer where the light shielding structure is located is located between the film layer where the substrate is located and the film layer where the first active layer is located; The light shielding structure comprises a plurality of light shielding sub-parts, and along the thickness direction of the display panel, the light shielding sub-parts overlap with the channel region in the first active layer; The first sub-coupling section is arranged on the same layer as the light shielding structure.

5. The display panel according to claim 4, It is characterized in that The display panel further comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor and at least one switching transistor; The shading structure includes a first shading portion and a second shading portion. Along the thickness direction of the display panel, the first shading portion overlaps with the channel region of the first active layer in the driving transistor, and the second shading portion overlaps with the channel region of the first active layer of at least part of the switching transistor; the first sub-coupling structure connects at least two of the second shading portions arranged along the second direction.

6. The display panel according to claim 2, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit including at least one first type transistor, the first type transistor including a first active layer; The first coupling section includes a second sub-coupling section, and the film layer where the second sub-coupling section is located is located between the film layer where the first active layer is located and the film layer where the first routing section is located.

7. The display panel according to claim 6, It is characterized in that The pixel circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are arranged opposite to each other, and the second electrode plate is located on a side of the first electrode plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer and a third metal layer which are stacked, wherein the first active layer is located in the first semiconductor layer, the first electrode plate is located in the first metal layer, and the second electrode plate is located in the second metal layer; and the first wiring section is located in the third metal layer; The second sub-coupling section is located in the second metal layer.

8. The display panel according to claim 6, It is characterized in that The pixel circuit further includes at least one second type transistor, the second type transistor including a second active layer and a top gate, the top gate being located on a side of the second active layer away from the first active layer; The pixel circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are arranged opposite to each other, and the second electrode plate is located on a side of the first electrode plate away from the first active layer; The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a fourth metal layer and a third metal layer which are stacked; The first active layer is located in the first semiconductor layer, the first electrode is located in the first metal layer, the second electrode is located in the second metal layer, the second active layer is located in the second semiconductor layer, the top gate is located in the fourth metal layer, and the first wiring section is located in the third metal layer; The second sub-coupling portion is located in the second metal layer and / or the fourth metal layer.

9. The display panel according to claim 6, It is characterized in that The pixel circuit includes a voltage regulating transistor; The signal line further comprises a voltage regulating signal line, wherein the voltage regulating signal line is electrically connected to the first electrode of the voltage regulating transistor; The voltage regulation signal line includes a first voltage regulation sub-portion, the first voltage regulation sub-portion extends along the second direction, and at least a portion of the first voltage regulation sub-portion is located between the film layer where the first active layer is located and the film layer where the first routing sub-portion is located; The second sub-coupling section is multiplexed as at least a portion of the first voltage regulating section.

10. The display panel according to claim 9, It is characterized in that The voltage regulating transistor includes an initialization reset transistor and an anode reset transistor; The voltage regulation signal line includes an initialization reset signal line and an anode reset signal line; The pixel circuit further includes a driving transistor, and the display panel further includes a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; The initialization reset signal line includes a first initialization reset line, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction, the first voltage adjustment subsection includes the first initialization reset line; the second sub-coupling subsection is multiplexed as the first initialization reset line; and / or, The anode reset signal line includes a first anode reset line, a plurality of the first anode reset lines are arranged along the first direction and extend along the second direction, the first voltage adjustment section includes the first anode reset line; and the second sub-coupling section is multiplexed as the first anode reset line.

11. The display panel according to claim 10, It is characterized in that The second sub-coupling section is multiplexed into the first initialization reset line and the first anode reset line; Along the first direction, the first initialization reset lines and the first anode reset lines are arranged alternately.

12. The display panel according to claim 9, It is characterized in that The voltage regulating transistor includes an initialization reset transistor, an anode reset transistor and a bias regulating transistor; The voltage adjustment signal line includes an initialization reset signal line, an anode reset signal line and a bias adjustment signal line; The pixel circuit further includes a driving transistor, and the display panel further includes a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; the bias adjustment transistor is electrically connected between the bias adjustment signal line and the first electrode and / or the second electrode of the driving transistor; The initialization reset signal line includes a first initialization reset line, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment subsection includes the first initialization reset line; The anode reset signal line includes a first anode reset line, a plurality of the first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment subsection includes the first anode reset line; The bias adjustment signal line includes a first bias adjustment line, a plurality of the first bias adjustment lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment subsection includes the first bias adjustment line; The second sub-coupling section is multiplexed as at least one of the first initialization reset line, the first anode reset line, and the first bias adjustment line.

13. The display panel according to claim 2, It is characterized in that The display panel further includes a plurality of pixel circuits, and the pixel circuit further includes at least one second type transistor; The pixel circuit includes a driving transistor and an initial reset transistor, the signal line includes an initial reset signal line, and the initial reset transistor is electrically connected between the initial reset signal line and the gate of the driving transistor; the second type transistor includes the initial reset transistor; The plurality of initialization reset transistors include a first initialization reset transistor, a second initialization reset transistor and a third initialization reset transistor which are adjacently arranged along the second direction; The distance between the active layer of the first initialization reset transistor and the active layer of the second initialization reset transistor is a first distance, and the distance between the active layer of the second initialization reset transistor and the active layer of the third initialization reset transistor is a second distance; the first distance is smaller than the second distance; The signal lines further include a plurality of first scanning signal lines, the first scanning signal lines extending along the second direction and arranged along the first direction, and along the thickness direction of the display panel, the first scanning signal lines overlap with the active layer of the first initialization reset transistor, the active layer of the second initialization reset transistor, and the active layer of the third initialization reset transistor; The display panel also includes a second coupling adjustment structure, which connects the active layer of the second initialization reset transistor and the active layer of the third initialization reset transistor; the second coupling adjustment structure is electrically connected to the fixed potential signal line, and the orthographic projection of the second coupling adjustment structure on the plane where the substrate is located is located between the orthographic projection of the first routing branch on the plane where the substrate is located and the orthographic projection of the first scanning signal line on the plane where the substrate is located.

14. The display panel according to claim 13, It is characterized in that The second coupling structure is arranged at the same layer as the active layer of the initialization reset transistor.

15. The display panel according to claim 13, It is characterized in that The initialization reset signal line includes a first initialization reset line, and a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction; The second coupling adjustment structure is electrically connected to the first initialization reset line; along the thickness direction of the display panel, the second coupling adjustment structure overlaps with the first initialization reset line.

16. The display panel according to claim 2, It is characterized in that The signal lines further include a plurality of second scanning signal lines, which extend along the second direction and are arranged along the first direction; Along the thickness direction of the display panel, the first wiring section does not overlap with the second scanning signal line; The display panel further includes a third coupling adjustment structure; Along the thickness direction of the display panel, the third coupling adjustment structure overlaps with the second scanning signal line, and the third coupling adjustment structure is electrically connected to the fixed potential signal line.

17. The display panel according to claim 16, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit including at least one first type transistor, the first type transistor including a first active layer; The third coupling adjustment structure includes a third coupling sub-section, and the film layer where the third coupling sub-section is located is located between the film layer where the substrate is located and the film layer where the first active layer is located.

18. The display panel according to claim 16, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit including at least one first type transistor, the first type transistor including a first active layer; The third coupling adjustment structure includes a fourth coupling sub-portion, and the film layer where the fourth coupling sub-portion is located is located between the film layer where the second scanning signal line is located and the film layer where the first routing sub-portion is located.

19. The display panel according to claim 1, It is characterized in that The display panel further includes a pixel circuit, wherein the pixel circuit includes a driving transistor and a threshold compensation transistor, wherein a gate electrode of the driving transistor and a first electrode of the threshold compensation transistor are electrically connected to a first connection structure; The display panel further includes a first shielding structure, which is electrically connected to the fixed potential signal line; along the thickness direction of the display panel, the first shielding structure covers at least a portion of the first connection structure.

20. The display panel according to claim 19, It is characterized in that The pixel circuit also includes a voltage regulating transistor; The signal line further comprises a voltage regulating signal line, wherein the voltage regulating signal line is electrically connected to the first electrode of the voltage regulating transistor; The voltage regulation signal line includes a second voltage regulation sub-portion, and the second voltage regulation sub-portion extends along the first direction; The first shielding structure is electrically connected to at least a portion of the second voltage regulation subdivision.

21. The display panel according to claim 20, It is characterized in that The voltage regulating transistor includes an initialization reset transistor and an anode reset transistor; The voltage regulation signal line includes an initialization reset signal line and an anode reset signal line; The display panel further includes a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; The initialization reset signal line includes a second initialization reset line, a plurality of the second initialization reset lines extend along the first direction and are arranged along the second direction, and the first shielding structure is electrically connected to the second initialization reset line; and / or, The anode reset signal line includes a second anode reset line. A plurality of the second anode reset lines extend along the first direction and are arranged along the second direction. The first shielding structure is electrically connected to the second anode reset line.

22. The display panel according to claim 1, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit including a driving transistor and a threshold compensation transistor, the gate of the driving transistor and a first electrode of the threshold compensation transistor being electrically connected to a first connection structure; The data auxiliary line includes a second routing section, the second routing section extends along the first direction and is electrically connected to the fan-out routing; The display panel further comprises a second shielding structure, wherein the second shielding structure is electrically connected to the fixed potential signal line; The orthographic projection of at least part of the second shielding structure on the plane where the substrate is located is located between the orthographic projection of the data signal line on the plane where the substrate is located and the orthographic projection of the first connecting structure on the plane where the substrate is located; And / or, the orthographic projection of at least part of the second shielding structure on the plane where the substrate is located is located between the orthographic projection of the second routing section on the plane where the substrate is located and the orthographic projection of the first connecting structure on the plane where the substrate is located.

23. The display panel according to claim 1, It is characterized in that The display panel further includes a pixel circuit, the pixel circuit includes a driving transistor and a data writing transistor, the second electrode of the data writing transistor and the first electrode of the driving transistor are electrically connected to the second connection structure; The signal lines further include a plurality of light-emitting control signal lines, which are arranged along the first direction and extend along the second direction; The display panel further comprises a third shielding structure, wherein the third shielding structure is electrically connected to the fixed potential signal line; The film layer where the third shielding structure is located is located between the film layer where the second connecting structure is located and the film layer where the light-emitting control signal line is located, and the orthographic projection of the third shielding structure on the plane where the substrate is located overlaps with the orthographic projection of the second connecting structure on the plane where the substrate is located and the orthographic projection of the light-emitting control signal line on the plane where the substrate is located.

24. The display panel according to claim 9, It is characterized in that The voltage regulation signal line includes a second voltage regulation section, the second voltage regulation section extends along the first direction, and the second voltage regulation section is arranged in a different layer from the first voltage regulation section and is electrically connected.

25. The display panel according to claim 24, It is characterized in that The signal lines further include a plurality of first power signal lines, the plurality of first power signal lines extending along the first direction and arranged along the second direction; One second voltage adjustment sub-portion, one second routing sub-portion and two data signal lines are arranged between two adjacent first power signal lines; The second voltage regulating section and the second routing section are arranged between two adjacent data signal lines, or two data signal lines are arranged between the second voltage regulating section and the second routing section.

26. The display panel according to claim 1, It is characterized in that The display panel further includes a virtual auxiliary line, wherein the virtual auxiliary line and the data auxiliary line are arranged in the same layer and there is a break between the virtual auxiliary line and the data auxiliary line; The display panel further includes a light emitting element, and along a thickness direction of the display panel, the light emitting element covers the fracture.

27. The display panel according to claim 26, It is characterized in that Along the thickness direction of the display panel, the first coupling adjustment structure overlaps with the break.

28. The display panel according to claim 1, It is characterized in that The display panel further comprises a plurality of multiplexing units and at least two switch control lines arranged in the non-display area; The multi-way distribution unit includes at least two multi-way distribution switches, and the multi-way distribution switch includes an input end, an output end and a control end; in the same multi-way distribution unit, the input ends of at least two of the multi-way distribution switches are connected, the output ends of at least two of the multi-way distribution switches are respectively electrically connected to different data signal lines, the control ends of at least two of the multi-way distribution switches are respectively electrically connected to different switch control lines, and the data signal line located in the second display area is electrically connected to the output end of the multi-way distribution switch through the data auxiliary line.

29. The display panel according to claim 1, It is characterized in that The display panel further includes a light emitting element; The light-emitting elements include a first color light-emitting element, a second color light-emitting element and a third color light-emitting element, wherein the first color light-emitting element, the second color light-emitting element and the third color light-emitting element are one of a red light-emitting element, a blue light-emitting element and a green light-emitting element and are different from each other; A plurality of the first color light emitting elements and the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements are located at first vertices of the first virtual quadrilateral, the second color light emitting elements are located at second vertices of the first virtual quadrilateral, and the third color light emitting elements are located inside the first virtual quadrilateral; The plurality of third color light emitting elements form a second virtual quadrilateral, the plurality of third color light emitting elements are respectively located at the vertices of the second virtual quadrilateral, and the first color light emitting element or the second color light emitting element is located inside the second virtual quadrilateral.

30. A display device, It is characterized in that A display panel comprising any one of claims 1-29.

Images