Method for manufacturing capacitor, capacitor and memory
Through the passivation treatment of the first conductive layer and the ammonia gas inlet of the dielectric layer, the challenge of selecting the material of the capacitor dielectric layer in DRAM is solved, the dielectric constant and storage capacity are improved, and the high capacitance value and Low leakage demand.
Patent Information
- Application Number
- CN202310719409.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-16
- Publication Date
- 2024-12-17
AI Technical Summary
The shrinkage of capacitors in dynamic random memory (DRAM) poses challenges to the selection of dielectric layer material with high capacitance values and low leakage, and the prior art is difficult to meet these needs simultaneously.
Passivation gas is used to passivate the first conductive layer, and ammonia gas is in situ during the deposition of the dielectric layer to form a high-quality dielectric layer, which increases the dielectric constant and reduces the surface roughness and protrusion number. .
The storage capacity of the capacitor and the quality of the dielectric layer are improved, so that the dielectric constant of the dielectric layer is greater than 80, and the performance of the capacitor is enhanced.
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Figure CN119156126A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to but are not limited to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a capacitor, a capacitor, and a memory. Background Art
[0002] With the miniaturization of dynamic random access memory (DRAM), the capacitor of dynamic random access memory is challenged: it is necessary to meet the requirements of high capacitance and low leakage at the same time, so the material selection of the dielectric layer is particularly important. Summary of the invention
[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0004] The embodiments of the present application provide a method for manufacturing a capacitor, a capacitor and a memory. The method of the present application can improve the quality of the dielectric layer of the capacitor.
[0005] The present application provides a method for manufacturing a capacitor, comprising:
[0006] depositing a first conductive layer on the substrate;
[0007] Performing a passivation treatment on the first conductive layer using a passivation gas;
[0008] Depositing a dielectric layer on a side of the passivated first conductive layer away from the substrate, and introducing ammonia gas in situ during the deposition of the dielectric layer; and
[0009] A second conductive layer is deposited on a side of the dielectric layer facing away from the substrate.
[0010] In an embodiment of the present application, the passivation gas is selected from nitrogen, nitric oxide, nitrous oxide or nitrogen dioxide.
[0011] In an embodiment of the present application, introducing ammonia gas in-situ during the deposition of the dielectric layer includes: after the dielectric layer reaches a set thickness, introducing ammonia gas in-situ while continuing to deposit the dielectric layer.
[0012] In an embodiment of the present application, the set thickness accounts for 80%-90% of the total thickness of the dielectric layer.
[0013] In the embodiments of the present application, the process conditions for in-situ introduction of ammonia gas include: a flow rate of ammonia gas is 20-200 sccm; and the introduction time of ammonia gas is 1-5 s.
[0014] In an embodiment of the present application, passivating the first conductive layer using a passivation gas includes: forming a plasma from the passivation gas, and passivating the first conductive layer using the plasma.
[0015] In an embodiment of the present application, the method further includes: performing annealing after forming the second conductive layer.
[0016] In an embodiment of the present application, the method further includes: performing annealing after forming the dielectric layer and before depositing the second conductive layer.
[0017] The present application also provides a capacitor, comprising:
[0018] a first conductive layer, the first conductive layer comprising a passivation layer;
[0019] a dielectric layer located on one side of the first conductive layer, the thickness of the dielectric layer being less than 10 nm and the dielectric constant of the dielectric layer being greater than 80; and
[0020] a second conductive layer located on a side of the dielectric layer away from the first conductive layer;
[0021] Wherein, the passivation layer is located on a side of the first conductive layer close to the dielectric layer.
[0022] In an embodiment of the present application, the material of the dielectric layer is strontium titanate.
[0023] The present application also provides a memory, comprising a transistor and the capacitor as described above, wherein the capacitor is connected to a source or a drain of the transistor.
[0024] In an embodiment of the present application, the memory includes a storage unit disposed on a substrate, the storage unit includes one transistor and one capacitor, wherein:
[0025] The transistor comprises a semiconductor column and a gate electrode, wherein the semiconductor column extends in a direction perpendicular to the substrate, the semiconductor column comprises a first electrode region close to the substrate and a second electrode region far from the substrate, and a channel region between the first electrode region and the second electrode region; one of the first electrode region and the second electrode region is a source electrode region, and the other is a drain electrode region; the gate electrode surrounds the channel region; and
[0026] The capacitor is disposed on the second electrode region of the semiconductor column in a direction perpendicular to the substrate and is connected to the second electrode region of the semiconductor column.
[0027] In an embodiment of the present application, the memory is a 3D memory, comprising a plurality of storage units distributed in different layers, stacked in a direction perpendicular to the substrate and periodically distributed; each of the storage units comprises one of the transistors and one of the capacitors; wherein,
[0028] The transistor comprises a semiconductor layer and a gate electrode, wherein the semiconductor layer extends in a direction parallel to the substrate and comprises a first electrode region, a second electrode region and a channel region located between the first electrode region and the second electrode region; one of the first electrode region and the second electrode region is a source electrode region, and the other is a drain electrode region; and the gate electrode surrounds the channel region;
[0029] The capacitor extends in a direction parallel to the substrate.
[0030] The method for manufacturing a capacitor in an embodiment of the present application performs a passivation treatment on the first conductive layer by using a passivation gas, so that the surface of the first conductive layer is passivated, thereby forming a nitrogen-rich passivation layer on the surface of the first conductive layer, making the first conductive layer more resistant to oxidation, and making the surface of the first conductive layer smoother, so that the quality of the subsequently deposited dielectric layer is better, and the dielectric layer at the interface between the first conductive layer and the dielectric layer has a higher k value, for example, a k value greater than 80. During the deposition process of the dielectric layer, ammonia gas is introduced in situ to inhibit the generation of oxygen vacancies in the dielectric layer, reduce the surface roughness and protrusion number of the dielectric layer, thereby improving the quality of the dielectric layer, and further improving the storage capacity of the capacitor.
[0031] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0033] Figure 1 A process flow chart of a method for manufacturing a capacitor provided for an exemplary embodiment of the present application;
[0034] Figure 2 A schematic diagram of a longitudinal cross-sectional structure of a method for manufacturing a capacitor provided by an exemplary embodiment of the present application after forming a first conductive layer;
[0035] Figure 3 A schematic diagram of a longitudinal cross-sectional structure after pattern etching of a first conductive layer in a method for manufacturing a capacitor provided by an exemplary embodiment of the present application;
[0036] Figure 4 A schematic diagram of a longitudinal cross-sectional structure of a first conductive layer after passivation treatment in a method for manufacturing a capacitor provided by an exemplary embodiment of the present application;
[0037] Figure 5 A schematic diagram of a longitudinal cross-sectional structure of a method for manufacturing a capacitor provided by an exemplary embodiment of the present application after a dielectric layer is formed;
[0038] Figure 6 A schematic diagram of the longitudinal cross-sectional structure of a capacitor obtained by a method for manufacturing a capacitor provided in an exemplary embodiment of the present application.
[0039] Figure 7 A schematic diagram of a longitudinal cross-sectional structure of another method for manufacturing a capacitor provided by an exemplary embodiment of the present application after forming a first conductive layer;
[0040] Figure 8 A schematic diagram of a longitudinal cross-sectional structure of passivating a first conductive layer in another method for manufacturing a capacitor provided by an exemplary embodiment of the present application;
[0041] Fig. 9 A schematic diagram of a longitudinal cross-sectional structure of another method for manufacturing a capacitor provided by an exemplary embodiment of the present application, in which a dielectric layer is deposited on a first conductive layer that has been passivated and ammonia gas is introduced;
[0042] Fig.10 A schematic diagram of the longitudinal cross-sectional structure of another method for manufacturing a capacitor provided by an exemplary embodiment of the present application after a second conductive layer is formed on a dielectric layer.
[0043] Fig.11 A schematic diagram of a memory including a transistor and a capacitor obtained by a method for manufacturing a capacitor according to an exemplary embodiment of the present application.
[0044] Fig.12 A schematic diagram of a memory including a transistor and a capacitor obtained by a method for manufacturing a capacitor according to another exemplary embodiment of the present application.
[0045] The meanings of the symbols in the accompanying drawings are:
[0046] 1-storage cell; 3-substrate; 6-base plate; 10-transistor; 11-semiconductor column; 12-gate electrode; 13-semiconductor layer; 20-capacitor; 21-first conductive layer; 21'-passivation layer; 22-second conductive layer; 23-dielectric layer; 111-first electrode region; 112-channel region; 113-second electrode region. Figure 7-10 For along Fig.12 Cross-sectional view taken along the a-a' direction. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.
[0048] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.
[0049] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values shown in the drawings.
[0050] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.
[0051] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0052] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.
[0053] The present application provides a method for manufacturing a capacitor, comprising:
[0054] depositing a first conductive layer on the substrate;
[0055] Performing a passivation treatment on the first conductive layer using a passivation gas;
[0056] Depositing a dielectric layer on a side of the passivated first conductive layer away from the substrate, and introducing ammonia gas in situ during the deposition of the dielectric layer; and
[0057] A second conductive layer is deposited on a side of the dielectric layer facing away from the substrate.
[0058] The method for manufacturing a capacitor in an embodiment of the present application performs a passivation treatment on the first conductive layer by using a passivation gas, so that the surface of the first conductive layer is passivated, thereby forming a nitrogen-rich passivation layer on the surface of the first conductive layer, making the first conductive layer more resistant to oxidation, and making the surface of the first conductive layer smoother, so that the quality of the subsequently deposited dielectric layer is better, and the dielectric layer at the interface between the first conductive layer and the dielectric layer has a higher k value, for example, a k value greater than 80. During the deposition process of the dielectric layer, ammonia gas is introduced in situ to inhibit the generation of oxygen vacancies in the dielectric layer, reduce the surface roughness and protrusion number of the dielectric layer, thereby improving the quality of the dielectric layer, and further improving the storage capacity of the capacitor.
[0059] Figure 1 A process flow chart of a method for manufacturing a capacitor provided for an exemplary embodiment of the present application.
[0060] like Figure 1 As shown, in an exemplary embodiment of the present application, a method for manufacturing a capacitor includes:
[0061] depositing a first conductive layer on the substrate;
[0062] Performing a passivation treatment on the first conductive layer using a passivation gas;
[0063] Depositing a dielectric layer on a side of the passivated first conductive layer away from the substrate, and introducing ammonia gas in situ during the deposition of the dielectric layer; and
[0064] A second conductive layer is deposited on a side of the dielectric layer facing away from the substrate.
[0065] In an embodiment of the present application, the passivation gas is selected from nitrogen, nitric oxide, nitrous oxide or nitrogen dioxide.
[0066] In an embodiment of the present application, introducing ammonia gas in-situ during the deposition of the dielectric layer includes: after the dielectric layer reaches a set thickness, introducing ammonia gas in-situ while continuing to deposit the dielectric layer.
[0067] In an embodiment of the present application, the set thickness accounts for 80%-90% of the total thickness of the dielectric layer. During the deposition process of the dielectric layer, ammonia is introduced in situ to suppress the generation of oxygen vacancies in the dielectric layer, reduce the surface roughness and protrusion number of the dielectric layer, thereby improving the quality of the dielectric layer, and further improving the storage capacity of the capacitor.
[0068] In the embodiments of the present application, the process conditions for in-situ introduction of ammonia gas include: a flow rate of ammonia gas is 20-200 sccm; and the introduction time of ammonia gas is 1-5 s.
[0069] In an embodiment of the present application, passivating the first conductive layer using a passivation gas includes: forming a plasma from the passivation gas, and passivating the first conductive layer using the plasma.
[0070] In an embodiment of the present application, the method further includes: performing annealing after forming the second conductive layer.
[0071] In an embodiment of the present application, the method further includes: performing annealing after forming the dielectric layer and before depositing the second conductive layer.
[0072] In an embodiment of the present application, after forming the second conductive layer, the process conditions for annealing include: an annealing temperature of 500-600° C., an annealing time of 30s-120s, and an annealing atmosphere of vacuum, nitrogen or argon.
[0073] In an embodiment of the present application, after forming the dielectric layer and before depositing the second conductive layer, the annealing process conditions include: annealing temperature of 500-600°C, annealing time of 30s-120s, and annealing atmosphere of vacuum, nitrogen or argon environment.
[0074] In an embodiment of the present application, the material of the dielectric layer includes a main material and a doping material, and the main material is strontium titanate.
[0075] In an embodiment of the present application, the doping material is selected from one or more of Si, Hf, Y, Al, Zr and Gd.
[0076] In an embodiment of the present application, the material of the first conductive layer or the second conductive layer is metal, alloy, or metal oxide. For example, the material of the first conductive layer and the second conductive layer is independently selected from one or more of Ru, Ti, Ta, TiN, and TaN.
[0077] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor after forming a first conductive layer provided by an exemplary embodiment of the present application. Figure 3A schematic diagram of the longitudinal cross-sectional structure of a first conductive layer after patterning in a method for manufacturing a capacitor provided by an exemplary embodiment of the present application. Figure 4 A schematic diagram of the longitudinal cross-sectional structure of passivating a first conductive layer in a method for manufacturing a capacitor provided by an exemplary embodiment of the present application. Figure 5 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor provided by an exemplary embodiment of the present application, in which a dielectric layer is deposited on a first conductive layer that has been passivated and ammonia gas is introduced. Figure 6 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor after forming a second conductive layer on a dielectric layer provided by an exemplary embodiment of the present application.
[0078] like Figures 2 to 6 As shown, in an exemplary embodiment of the present application, a method for manufacturing a capacitor may include:
[0079] S10: Provide a substrate 3, for example, a silicon-based substrate, and Figure 2 The first conductive layer 21 is deposited on the upper surface of the substrate 3 as shown in FIG. Figure 2 Intermediate products shown;
[0080] S10′: pattern-etching the first conductive layer 21 to form a groove penetrating the first conductive layer 21 in the first conductive layer 21, wherein the groove exposes the substrate 3, and the following is obtained: Figure 3 The intermediate product shown; illustratively, the groove may extend in a direction perpendicular to the substrate 3;
[0081] S20: Passivating the first conductive layer 21 with a passivating gas to form a passivation layer 21' on the surface of the first conductive layer 21. The passivation layer 21' may be a nitrogen-rich film layer. For example, if the first conductive layer 21 is formed of Ti, the passivation layer 21' may be a nitrogen-rich TiN layer, such as Figure 4 As shown;
[0082] S30: depositing a dielectric layer 23 on the first conductive layer 21 after passivation treatment, and introducing ammonia gas in situ during the deposition of the dielectric layer 23, and annealing to obtain Figure 5The intermediate product shown; illustratively, a dielectric layer 23 covering the surface of the first conductive layer 21 and the groove can be deposited on the substrate 3; wherein, the dielectric layer 23 of a set thickness (for example, 80% to 90% of the total thickness of the dielectric layer 23 to be deposited) can be deposited by an atomic layer deposition (ALD) process in the absence of ammonia, and then the dielectric layer 23 is deposited by the ALD process and ammonia is introduced in situ at the same time; the introduction of ammonia in situ during the deposition of the dielectric layer 23 can inhibit the generation of oxygen vacancies in the dielectric layer, reduce the surface roughness and the number of protrusions of the dielectric layer, and thus improve the quality of the dielectric layer;
[0083] S40: depositing a second conductive layer 22 on the dielectric layer 23 and annealing to obtain a dielectric layer 23; Figure 6 Capacitor 20 is shown.
[0084] like Figure 6 As shown, the first conductive layer 21 can extend in a direction perpendicular to the substrate 3; the dielectric layer 23 can extend in a direction perpendicular to the substrate 3; the second conductive layer 22 can extend in a direction perpendicular to the substrate 3, and the cross-sectional profile of the second conductive layer 22 on a horizontal plane parallel to the substrate 3 can be a closed ring.
[0085] Figure 7 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor after forming a first conductive layer provided by an exemplary embodiment of the present application. Figure 8 A schematic diagram of the longitudinal cross-sectional structure of passivating a first conductive layer in a method for manufacturing a capacitor provided by an exemplary embodiment of the present application. Fig. 9 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor provided by an exemplary embodiment of the present application, in which a dielectric layer is deposited on a first conductive layer that has been passivated and ammonia gas is introduced. Fig.10 A schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a capacitor after forming a second conductive layer on a dielectric layer provided by an exemplary embodiment of the present application.
[0086] like Figures 7 to 10 As shown, in another exemplary embodiment of the present application, a method for manufacturing a capacitor may include:
[0087] S10: providing a substrate 3, for example, a substrate of a silicon-based nanowire structure, the substrate 3 may have a sidewall extending in a horizontal direction and two end faces connected to the sidewall; depositing a first conductive layer 21 on the substrate 3 to obtain Figure 7 The intermediate product shown; illustratively, the first conductive layer 21 can be deposited on two opposite sides of the sidewall of the substrate 3, for example, Figure 7The first conductive layer 21 is deposited on both the upper and lower surfaces of the substrate 3 shown in the figure; alternatively, the first conductive layer 21 can be deposited on the entire side wall of the substrate 3 to obtain the first conductive layer 21 having a ring-shaped longitudinal section; in addition, the first conductive layer 21 can also cover at least one end surface of the substrate 3;
[0088] S20: Passivation treatment is performed on the first conductive layer 21 using a passivation gas to form a passivation layer 21' on the surface of the first conductive layer. The passivation layer 21' may be a nitrogen-rich film layer. For example, if the first conductive layer 21 is formed of Ti, the passivation layer 21' may be a nitrogen-rich TiN layer, such as Figure 8 As shown;
[0089] S30: depositing a dielectric layer 23 on the side of the first conductive layer 21 which has been passivated and is away from the substrate 3, and introducing ammonia gas in situ during the deposition of the dielectric layer 23 to suppress the generation of oxygen vacancies in the dielectric layer, and annealing to obtain the following: Fig. 9 The intermediate product shown; illustratively, the dielectric layer 23 of a set thickness (for example, 80% to 90% of the total thickness of the dielectric layer 23 to be deposited) can be first deposited by the ALD process in the absence of ammonia, and then the dielectric layer 23 can be deposited by the ALD process while introducing ammonia in situ;
[0090] S40: depositing a second conductive layer 22 on the side of the dielectric layer 23 away from the substrate 3, and annealing to obtain Fig.10 Capacitor 20 is shown.
[0091] like Fig.10 As shown, the first conductive layer 21 may extend in a horizontal direction parallel to the substrate 3; the dielectric layer 23 may extend in a horizontal direction; the second conductive layer 22 may extend in a horizontal direction, and the cross-sectional profiles of the first conductive layer 21, the second conductive layer 22 and the dielectric layer 23 in a longitudinal section perpendicular to the substrate 3 may be a closed ring. In an embodiment of the present application, in S10, the passivation gas is selected from nitrogen, nitric oxide, nitrous oxide or nitrogen dioxide.
[0092] In an embodiment of the present application, in S20, passivating the first conductive layer 2 using a passivation gas includes: forming a plasma from the passivation gas, and passivating the first conductive layer using the plasma;
[0093] In the embodiment of the present application, in S30, the process conditions for introducing ammonia gas in situ include: the flow rate of ammonia gas is 20-200 sccm; and the introduction time of ammonia gas is 1-5 s.
[0094] In an embodiment of the present application, the process conditions of the annealing in step S30 may include: an annealing temperature of 500-600° C., an annealing time of 30 s-120 s, and an annealing atmosphere of vacuum, nitrogen or argon.
[0095] In an embodiment of the present application, the process conditions of annealing in step S40 may include: an annealing temperature of 500-600° C., an annealing time of 30 s-120 s, and an annealing atmosphere of vacuum, nitrogen or argon.
[0096] In an embodiment of the present application, the material of the dielectric layer includes a main material and a doping material, and the main material is strontium titanate.
[0097] In an embodiment of the present application, the doping material is selected from any one or more of Si, Hf, Y, Al, Zr and Gd.
[0098] In an embodiment of the present application, the material of the first conductive layer or the second conductive layer is metal, alloy, or metal oxide. For example, the material of the first conductive layer and the second conductive layer is independently selected from one or more of Ru, Ti, Ta, TiN, and TaN.
[0099] In the embodiments of the present application, the substrate may be a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, a silicon on sapphire (SOS) substrate, a silicon on glass (SOG) substrate, an epitaxial layer of silicon on a base semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si 1-x Ge x , where x can be a mole fraction between 0.2 and 0.8, for example), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate can be doped or undoped.
[0100] In an embodiment of the present application, a method of depositing the first conductive layer, the dielectric layer, and the second conductive layer may be an atomic layer deposition method.
[0101] The manufacturing method of the present application can simultaneously produce a plurality of capacitors with a stacked arrangement and the same structure, and can be used to produce capacitors of semiconductor devices with a 3D structure.
[0102] The present application also provides a capacitor, including:
[0103] a first conductive layer, the first conductive layer comprising a passivation layer;
[0104] a dielectric layer located on one side of the first conductive layer, the thickness of the dielectric layer being less than 10 nm and the dielectric constant of the dielectric layer being greater than 80; and
[0105] a second conductive layer located on a side of the dielectric layer away from the first conductive layer,
[0106] The passivation layer is located on a side of the first conductive layer close to the dielectric layer.
[0107] The capacitor provided in the embodiment of the present application can be obtained by the method for manufacturing a capacitor provided in the embodiment of the present application as above.
[0108] like Figure 6 and Fig.10 As shown, in an exemplary embodiment of the present application, the capacitor includes: a first conductive layer 21 , a dielectric layer 23 and a second conductive layer 22 .
[0109] The first conductive layer 21 includes a passivation layer 21 ′;
[0110] The dielectric layer 23 is located on one side of the first conductive layer 21, the thickness of the dielectric layer 23 is less than 10 nm, and the dielectric constant of the dielectric layer 23 is greater than 80; and
[0111] The second conductive layer 22 is located on a side of the dielectric layer 23 away from the first conductive layer 21.
[0112] The passivation layer 21 ′ is located on a side of the first conductive layer 21 close to the dielectric layer 23 .
[0113] In an embodiment of the present application, the material of the dielectric layer is strontium titanate.
[0114] In the embodiment of the present application, the cross-sections of the first conductive layer 21 , the dielectric layer 23 , and the second conductive layer 22 are annular or rectangular.
[0115] An embodiment of the present application further provides a memory, comprising a transistor and the capacitor as described above, wherein the capacitor is connected to a source or a drain of the transistor.
[0116] Fig.11 A schematic diagram of a memory including a transistor and a capacitor obtained by a method for manufacturing a capacitor according to an exemplary embodiment of the present application.
[0117] like Fig.11 As shown, in an exemplary embodiment of the present application, the memory includes a memory cell 1 disposed on a substrate, the memory cell 1 includes a transistor 10 and a capacitor 20, wherein:
[0118] The transistor 10 includes a semiconductor column 11 and a gate electrode 12. The semiconductor column 11 extends in a direction perpendicular to the substrate. The semiconductor column 11 includes a first electrode region 111 close to the substrate and a second electrode region 113 far from the substrate, and a channel region 112 located between the first electrode region 111 and the second electrode region 113. One of the first electrode region 111 and the second electrode region 113 is a source electrode region, and the other is a drain electrode region. The gate electrode 12 surrounds the channel region 112.
[0119] The capacitor 20 is disposed on the second electrode region 113 of the semiconductor column 11 in a direction perpendicular to the substrate and is connected to the second electrode region 113 of the semiconductor column 11 .
[0120] Fig.12 A schematic diagram of a memory including a transistor and a capacitor obtained by a method for manufacturing a capacitor according to another exemplary embodiment of the present application.
[0121] like Fig.12 As shown, in an exemplary embodiment of the present application, the memory is a 3D memory, including a plurality of memory cells 1 distributed in different layers, stacked along a direction perpendicular to the substrate and periodically distributed; each memory cell includes a transistor 10 and a capacitor 20; wherein,
[0122] The transistor 10 includes a semiconductor layer 13 and a gate electrode 12. The semiconductor layer 13 extends in a direction parallel to the substrate and includes a first electrode region 111, a second electrode region 113, and a channel region 112 located between the first electrode region 111 and the second electrode region 113. One of the first electrode region 111 and the second electrode region 113 is a source electrode region, and the other is a drain electrode region. The gate electrode 12 surrounds the channel region 112.
[0123] The capacitor 20 extends in a direction parallel to the substrate.
[0124] In an exemplary embodiment of the present application, the memory may be a DRAM.
[0125] An embodiment of the present application further provides an electronic device, which includes the 3D stacked semiconductor device provided in the above embodiment of the present application.
[0126] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here. Although the implementation methods disclosed in the present application are as above, the content described is only an implementation method adopted to facilitate the understanding of the present application, and is not used to limit the present application. Any technician in the field to which the present application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application, but the scope of protection of the present application shall still be subject to the scope defined in the attached claims.
Claims
1. A method for manufacturing a capacitor, characterized in that: include: depositing a first conductive layer on the substrate; Performing a passivation treatment on the first conductive layer using a passivation gas; Depositing a dielectric layer on a side of the passivated first conductive layer away from the substrate, and introducing ammonia gas in situ during the deposition of the dielectric layer; as well as A second conductive layer is deposited on a side of the dielectric layer facing away from the substrate.
2. The method according to claim 1, wherein: The passivating gas is selected from nitrogen, nitric oxide, nitrous oxide or nitrogen dioxide.
3. The method according to claim 1, wherein: In-situ introduction of ammonia gas during the deposition of the dielectric layer includes: after the dielectric layer reaches a set thickness, introducing ammonia gas in-situ while continuing to deposit the dielectric layer.
4. The method according to claim 3, wherein: The predetermined thickness accounts for 80%-90% of the total thickness of the dielectric layer.
5. The method according to any one of claims 1 to 4, wherein: The process conditions for in-situ introduction of ammonia include: an ammonia flow rate of 20-200 sccm; and an ammonia introduction time of 1-5 s.
6. The method according to any one of claims 1 to 5, wherein: The passivation treatment of the first conductive layer using a passivation gas includes: forming the passivation gas into plasma, and passivation treatment of the first conductive layer using the plasma.
7. The method according to claim 6, further comprising: After forming the second conductive layer, annealing is performed.
8. The method according to claim 6, further comprising: After forming the dielectric layer and before depositing the second conductive layer, annealing is performed.
9. A capacitor, characterized in that: include: a first conductive layer, the first conductive layer comprising a passivation layer; a dielectric layer located on one side of the first conductive layer, the thickness of the dielectric layer being less than 10 nm and the dielectric constant of the dielectric layer being greater than 80; and a second conductive layer located on a side of the dielectric layer away from the first conductive layer; Wherein, the passivation layer is located on a side of the first conductive layer close to the dielectric layer.
10. The capacitor according to claim 9, wherein The material of the dielectric layer is strontium titanate.
11. A memory, characterized in that: The method comprises a transistor and a capacitor according to claim 9 or 10, wherein the capacitor is connected to a source or a drain of the transistor.
12. The memory according to claim 11, comprising a memory cell disposed on a substrate, the memory cell comprising one of the transistors and one of the capacitors, wherein: The transistor comprises a semiconductor column and a gate electrode, wherein the semiconductor column extends in a direction perpendicular to the substrate, the semiconductor column comprises a first electrode region close to the substrate and a second electrode region far from the substrate, and a channel region between the first electrode region and the second electrode region; one of the first electrode region and the second electrode region is a source electrode region, and the other is a drain electrode region; the gate electrode surrounds the channel region; and The capacitor is disposed on the second electrode region of the semiconductor column in a direction perpendicular to the substrate and is connected to the second electrode region of the semiconductor column.
13. The memory according to claim 11 is a 3D memory, comprising a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to the substrate and periodically distributed; each of the memory cells comprises one of the transistors and one of the capacitors; wherein, The transistor comprises a semiconductor layer and a gate electrode, wherein the semiconductor layer extends in a direction parallel to the substrate and comprises a first electrode region, a second electrode region and a channel region located between the first electrode region and the second electrode region; one of the first electrode region and the second electrode region is a source electrode region, and the other is a drain electrode region; and the gate electrode surrounds the channel region; The capacitor extends in a direction parallel to the substrate.