Pulse etch process

Abstract

A method of etching a sample is described herein. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas stream comprising silicon tetrachloride (SiCl4) and a diluent toward the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first period of time. The source power is then applied to achieve the source state for a second period of time, and then the bias power and the source power are not applied to achieve the recovery state for a third period of time. The plasma etch pulse is repeated until a target amount of sample is etched.

Description

Technical Field

[0001] Embodiments of the present disclosure are generally directed to a method for etching a sample, wherein the method includes a pulsed etching process. Background Art

[0002] In the semiconductor industry, devices are manufactured by a number of manufacturing processes that produce structures with ever-shrinking dimensions. As device geometries shrink, controlling process uniformity and reproducibility of the devices becomes more challenging, especially in upstream processes.

[0003] In current plasma etching processes, there are some chemicals used in combination with a pulsed source and a bias voltage. These chemicals include chlorine (Cl), hydrogen bromide (HBr), or a combination thereof. These plasma etching processes generally have a two-state system, where source power is applied in a first state and then bias power is applied in a second state. It has been found that these systems produce a V-shaped profile in the sample after performing plasma etching. Since the device width varies with depth, the V-shape formed in the etched substrate causes undesirable device performance. Therefore, it is necessary to improve the plasma etching process so that a more uniform profile, such as a straighter profile, is provided over the entire depth of the sample. Summary of the invention

[0004] In some embodiments of the present disclosure, a method for etching a sample is provided. The method may include performing a plasma etching pulse. In some embodiments, the plasma etching pulse may include: directing a gas flow including silicon tetrachloride (SiCl4) and a diluent toward the sample; while directing the flow including the SiCl4 and the diluent toward the sample, applying a bias power to achieve a bias state for a first time period; applying a source power to achieve a source state for a second time period; and not applying the bias power and the source power to achieve a recovery state for a third time period. In some embodiments of the method, the plasma etching pulse may be repeated until a target amount of the sample has been etched.

[0005] In another embodiment of the present disclosure, a method for etching a substrate is provided, wherein the substrate may include a stack of alternating layers of Si and SiGe. The method may include: bringing a chamber including the substrate to a pressure of about 0.1 mT to about 500 mT; bringing the substrate to a temperature of about -50°C to about 300°C; generating a plasma from a gas flow, the gas flow including silicon tetrachloride (SiCl4) and a diluent, the diluent including argon (Ar), helium (He), or a mixture of the two; and directing the plasma toward the substrate to etch the stack of alternating layers of silicon and silicon germanium on the substrate.

[0006] In yet another embodiment of the present disclosure, a method for etching a sample is provided, the method comprising performing a plasma etching pulse and repeating the plasma etching pulse until a target amount of the sample has been etched. The performing of the plasma etching pulse of the method may include: while directing a flow of a gas and a diluent toward the sample, applying bias power to achieve a bias state for a first time period; applying source power to achieve a source state for a second time period; and not applying bias power and source power to achieve a recovery state for a third time period. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements. It should be noted that different references to "one" or "an" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references mean at least one.

[0008] Figure 1 depicts a cross-sectional view of one embodiment of a processing chamber;

[0009] Figure 2A a cross-sectional view of one embodiment depicting multiple layers of a sample;

[0010] Figure 2B A cross-sectional view depicting one embodiment of multiple layers of a sample, wherein the sample has been etched to have a U-shaped profile;

[0011] Figure 3A The figure shows a sample having multiple layers to be etched;

[0012] Figure 3B The figure shows the etching process according to an embodiment of the present disclosure. Figure 3A samples;

[0013] Figure 4A The figure shows the further layers after they have been deposited and before the etching process. Figure 3B samples;

[0014] Figure 4B The figure shows the etching process according to an embodiment of the present disclosure. Figure 4A samples;

[0015] Figure 5 is a flow chart representing a method for etching a sample according to an embodiment of the present disclosure; and

[0016] Figure 6 denoted a plasma etch pulse according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Embodiments disclosed herein describe methods for etching a sample. The method for etching a sample may include performing a plasma etching pulse, the plasma etching pulse including directing a gas flow including silicon tetrachloride (SiCl4) and a diluent toward the sample. In order to improve the profile of the sample, SiCl4 can be used in combination with a three-stage plasma etching pulse process. It was found that when compared with a conventional plasma etching process using chlorine (Cl2), hydrogen bromide (HBr) and / or nitrogen (N2), the use of SiCl4 in combination with the three-stage plasma etching pulse of the present disclosure produces a lower groove width difference across the groove depth in the etched sample (i.e., substrate).

[0018] In the plasma etching process of the present disclosure, a three-state pulse scheme can be used. In the three-state pulse scheme, the first state can be a bias state, in which bias power is applied. The first state can last for a first time period. In some embodiments, the bias power can have a power of about 100W to about 5000W, and can be applied at a bias frequency of about 400kHz to about 60MHz. The second state of the pulse scheme can be a source state, in which source power can be applied for a second time period while no bias power is applied. In multiple embodiments, the source power can be about 100W to about 5000W. The third state can be a recovery state, in which neither bias power nor source power is applied in a third time period. During etching, multiple plasma etching pulses can be applied until the target etching depth is reached.

[0019] Conventional plasma etching processes apply source power before applying bias power, and use a two-state pulse scheme. It has been found that, as performed in the embodiments of this article, applying bias power before source power is conducive to generating capacitively coupled plasma. It has been further found that the bias state followed by the source state (only applying source power in the source state) allows the mask retention of the etching mask on the substrate, because the gas chemical conditions (gas chemistry) of SiCl4 combined with Ar and He and source power can cause the protective layer to be deposited on the sample. The protective layer helps to retain the etching mask (for example, it can be a hard mask) of the sample and increase the selectivity between silicon and the etching mask. In addition, it has been found that when the source power is turned off, the electron density and the electron temperature will drop rapidly. Therefore, by introducing the recovery state after the source state, when repeating the plasma etching pulse, the electron temperature of the next repetition (iteration) of the first state will be lower than the electron temperature of the second state. The inventor has found that the decline of the electron temperature is related to the lower ion temperature, which allows better directionality control when etching. Therefore, if there is no third state in the plasma etch pulse, the plasma density and electron temperature will remain high after the source power is applied. If the electron temperature is high, the ion temperature is also high. When there is a high ion temperature, the ions in the bulk plasma will have a more random motion, resulting in a wider angular distribution and more changes in the etch profile. Therefore, it has been found that a three-state etch pulse including first a bias state, then a source state, and then a recovery state provides improved directional control for etching samples, and is particularly useful for etching samples including alternating stacks of Si and SiGe layers when used with SiCl4 chemistry.

[0020] Thus, embodiments of etching methods according to the present disclosure allow for more directional etching in the first state (ie, with bias power applied) at least in part because the plasma cools in the third state before the next pulse.

[0021] Embodiments of methods for etching a sample are disclosed herein, the method comprising performing a plasma etching pulse and repeating the plasma etching pulse until a target amount of the sample has been etched. The plasma etching pulse may include: directing a gas flow comprising SiCl4 and a diluent toward the sample; while directing the gas flow comprising SiCl4 and the diluent toward the sample, applying a bias power to achieve a bias state for a first time period; then applying a source power to achieve a source state for a second time period; and then not applying the bias power and the source power to achieve a recovery state for a third time period. In some embodiments, the source power is not applied during the bias state, and the bias power is not applied during the source state.

[0022] In some embodiments, the bias power can be from about 100 Watts (W) to about 5000 Watts (W), from about 200 W to about 2000 W, from about 300 W to about 1500 W, from about 500 W to about 1250 W, or from about 600 W to about 1000 W.

[0023] Some embodiments are described herein with reference to samples comprising alternating silicon (Si) layers and silicon germanium (SiGe) layers. The samples may include gate all around transistors, which may be etched using methods according to embodiments of the present disclosure. The methods described herein may also be advantageously used to etch many other types of substrates, such as substrates having Si and / or SiGe layers.

[0024] Now referring to the accompanying drawings, Figure 1 1 is a cross-sectional view of a processing chamber 100 (e.g., a semiconductor processing chamber) having one or more chamber components according to an embodiment of the present disclosure. The processing chamber 100 can be used for processes in which a corrosive plasma environment and / or corrosive chemical conditions are provided. For example, the processing chamber 100 can be a chamber for a plasma etching reactor (also referred to as a plasma etcher). Examples of chamber components that can be exposed to plasma in the processing chamber 100 are a substrate support assembly 148, an electrostatic chuck (ESC), a ring (e.g., a process kit ring or a single ring), a chamber wall, a base, a showerhead 130, a gas distribution plate, a liner, a liner kit, a shield, a plasma shield, a flow equalizer, a cooling base, a chamber viewing port, a chamber cover, a nozzle, a process kit ring, and the like.

[0025] In one embodiment, the processing chamber 100 includes a chamber body 102 and a showerhead 130, which enclose an interior volume 106. The showerhead 130 may or may not include a gas distribution plate. For example, the showerhead may be a multi-piece showerhead, which includes a showerhead base and a showerhead gas distribution plate coupled to the showerhead base. Alternatively, in some embodiments, the showerhead 130 may be replaced by a cover and a nozzle, or in other embodiments by a plurality of pie-shaped showerhead compartments and a plasma generation unit. The chamber body 102 may be made of aluminum, stainless steel, or other suitable materials. The chamber body 102 generally includes a sidewall 108 and a bottom 110. Any of the showerhead 130 (or cover and / or nozzle), the sidewall 108, and / or the bottom 110 may include a multi-layer plasma resistant coating.

[0026] The outer liner 116 may be disposed adjacent to the sidewall 108 to protect the chamber body 102. The outer liner 116 may be a halogen-containing gas resistant material, such as Al2O3 or Y2O3. In some embodiments, the outer liner 116 may be coated with multiple layers of plasma resistant ceramic coatings.

[0027] An exhaust port 126 may be defined in the chamber body 102 and may couple the interior volume 106 to a pump system 128. The pump system 128 may include one or more pumps and throttle valves for evacuating and regulating the pressure of the interior volume 106 of the processing chamber 100.

[0028] The showerhead 130 may be supported on the sidewall 108 of the chamber body 102 and / or on the top portion of the chamber body. The showerhead 130 (or lid) may be opened to allow access to the interior volume 106 of the processing chamber 100 and may provide a seal for the processing chamber 100 when closed. A gas control panel 158 may be coupled to the processing chamber 100 to provide processing gases and / or carrier gases to the interior volume 106 through the showerhead 130 or lid and nozzles. Examples of processing gases that may be delivered by the gas control panel 158 and used to process substrates / samples in the processing chamber 100 include silicon-containing gases such as silicon tetrachloride (SiCl4). Examples of carrier gases (also referred to herein as diluents) include N2, He, Ar, and other gases that are inert to the processing gases (e.g., non-reactive gases). The showerhead 130 includes a plurality of gas delivery holes 132 throughout the showerhead 130. The showerhead 130 may be or may include aluminum, anodized aluminum, an aluminum alloy (e.g., Al 6061), or an anodized aluminum alloy. In some embodiments, the showerhead includes a gas distribution plate (GDP) coupled to the showerhead. The GDP may be, for example, Si or SiC. The GDP may further include a plurality of holes aligned with the holes in the showerhead.

[0029] The substrate support assembly 148 is disposed in the interior volume 106 of the processing chamber 100 below the showerhead 130. The substrate support assembly 148 holds the substrate 144 (e.g., a wafer) during processing. The substrate support assembly 148 may include an electrostatic chuck to secure the substrate 144 during processing, a metal cooling plate coupled to the electrostatic chuck, and / or one or more additional components. An inner liner may cover the periphery of the substrate support assembly 148. The inner liner may be a material that is resistant to halogen-containing gases, such as Al2O3 or Y2O3. In some embodiments, the substrate support assembly, portions of the substrate support assembly, and / or the inner liner may be coated with a metal layer and a barrier layer.

[0030] The processing chamber 100 can be an etching chamber configured to perform the pulse etching process described herein. In various embodiments, the pulse etching process is performed to etch one or more layers disposed on a substrate 144. For example, the substrate 144 can be a semiconductor wafer, a glass plate, a SiGe wafer, or other types of substrates. In one embodiment, one or more layers 144 disposed on the substrate include a stack of alternating layers of Si and Ge.

[0031] Figure 2AA cross-sectional view of an article 200 is shown, the article 200 including a substrate 206 having a stack of alternating silicon (Si) layers and silicon germanium (SiGe) layers. In one embodiment, the article 200 corresponds to Figure 1 The substrate 144 is provided. The substrate 206 includes Si layers 260, 240, 220 and SiGe layers 250, 230, 210 disposed on the substrate in a stack 290. In some embodiments, the Si layer and the SiGe layer may be in the form of nanosheets (e.g., layers having nanoscale thickness). In one embodiment, the Si layer may be 0% to 200% thicker than the SiGe layer. In one embodiment, the Si layer is approximately 20% thicker than the SiGe layer. In one embodiment, all Si layers have approximately the same thickness, and all SiGe layers may have approximately the same thickness, which may be different from the thickness of the Si layer. Alternatively, different Si layers may have different thicknesses and / or different SiGe layers may have different thicknesses. In other embodiments, the Si layer and the SiGe layer may have approximately the same thickness as each other.

[0032] The pattern mask 280 (also referred to as an etch mask) can cover the top layer 260 in the stack 290. The pattern mask 280 can be a soft mask or a hard mask. Some hard masks that can be used include polysilicon hard masks and metal hard masks, such as tungsten hard masks or titanium nitride hard masks. The pattern mask 280 includes an open area 270 that exposes the underlying layer to the etching chemical during the etching process. The pattern mask 280 also includes a cover area that protects the underlying layer from being affected by the etching chemical. The stack 290 area below the open area 270 that is not protected by the pattern mask 280 can undergo the etching process.

[0033] The article 200 may be etched through the pattern mask 280 to produce cavities or trenches having substantially the same shape as the openings in the pattern mask 280. The etchant will also typically etch the pattern mask 280 at a certain etch rate.

[0034] Figure 2B A cross-sectional view of an article 204 is shown, the article 204 comprising a substrate 206 having a stack of alternating Si layers 260, 240, 220 and SiGe layers 250, 230, 210, the substrate 206 having undergone a process according to embodiments of the present disclosure, particularly according to Figure 5The process has etched a cavity 400 in the Si layer and the SiGe layer. In one embodiment, the cavity 400 has a tapered cross-sectional shape, wherein the bottom of the cavity is slightly narrower than the top of the cavity, having a U-shaped profile. It is noteworthy that, in contrast to the sidewalls produced by the previous etching processes, the sidewalls of the trenches or holes formed by the etching processes proposed in the embodiments herein are almost vertical.

[0035] Figure 3A A sample having multiple layers to be etched is shown, and may correspond to a perspective view of article 204 in various embodiments. Figure 3B FIG. 2 shows a first etching process according to an embodiment of the present disclosure after etching. Figure 3A of samples.

[0036] Figure 4A Shown after further layers have been deposited and before a second etching process Figure 3B of samples. Figure 4B FIG. 1 shows a structure after etching according to a second etching process according to an embodiment of the present disclosure. Figure 4A sample.

[0037] exist Figure 3A , an article 300, such as a wrap-around gate transistor, is shown. Article 300 includes a stack of alternating Si layers 310, 330, 350, 370 and SiGe layers 320, 340, 360. The layers of article 300 may be stacked on a substrate 380, wherein substrate 380 may be formed of SiGe, Si, glass, or other materials. In multiple embodiments, Si layers 310, 330, 350, 370 and SiGe layers 320, 340, 360 may be in the form of nanosheets. In one embodiment, the Si layer may be 0% to 200% thicker than the SiGe layer. In one embodiment, the Si layer is approximately 20% thicker than the SiGe layer. In one embodiment, all Si layers have approximately the same thickness, and all SiGe layers may have approximately the same thickness, which may be different from the thickness of Si. Alternatively, different Si layers may have different thicknesses and / or different SiGe layers may have different thicknesses. In other embodiments, the Si layer and the SiGe layer may have approximately the same thickness. After a pattern mask (now shown) is deposited over the top layer (eg, Si layer 310 in the figure), the Figure 5 Method 500 Etching Figure 3A 300 products. Figure 3B According to Figure 5 The method 500 may be used to etch the product 300. Figure 3BAs can be seen, the Si layers 310, 330, 350, 370 and the SiGe layers 320, 340, 360 are etched to produce a plurality of spaces (eg, trenches) 390. A single space 390 may be etched, or a plurality of spaces may be etched.

[0038] exist Figure 4A , an article 400, such as a wrap-around gate transistor, is shown according to an embodiment of the present disclosure. The article 400 may include a pattern mask 414 (e.g., a hard mask) and a spacer 412. The spacer 412 may be approximately orthogonal to a trench 490 (e.g., the trench 490 may correspond to Figure 3B The pattern mask 414 may be formed along the entire length of the spacer 412, or partially along the length of the spacer 412. Multiple spacers 412 may be offset from each other by a gap 492. Only two spacers are shown, but the device being manufactured will typically include many such spacers. The spacers 412 may surround the Si layers 410, 430, 450, 470 and the SiGe layers 420, 440, 460. The article 400 may also include a shallow trench isolation 416 formed in or on a substrate 480, where the substrate may be formed of SiGe, Si, glass, or other materials. In various embodiments, the substrate may be formed according to Figure 5 The method 500 etches the article 400 . Figure 4B 4 shows an article 400 that has undergone etching according to various embodiments described herein. Figure 4B In the embodiment, the Si layers 410, 430, 450, 470 and the SiGe layers 420, 440, 460 have been etched, while any excess layers are removed from outside the spacer 412. In this way, the Si and SiGe layers can be approximately flush with the spacer 412, so that there is no Si and / or SiGe layer outside the spacer 412.

[0039] Figure 5is a flow chart representing a method 500 of etching a sample and / or an article according to an embodiment of the present disclosure. In the method 500, at box 501, a sample and / or an article is inserted into an etching chamber. The etching chamber may be a plasma etching chamber. At box 502, the chamber is brought to a target temperature and pressure (e.g., by using one or more heating elements and / or pumps). The pressure of the chamber may be from about 0.1 mT to about 500 mT, from about 1 mT to about 400 mT, from about 5 mT to about 300 mT, from about 10 mT to about 200 mT, from about 25 mT to about 100 mT, or from about 1 mT to about 100 mT, or any sub-range or value herein. The temperature of the chamber may be from about -50°C to about 300°C, from about -25°C to about 250°C, from about 0°C to about 120°C, from about 25°C to about 100°C, or from about 50°C to about 75°C, or any sub-range or value herein. In one embodiment, the target substrate temperature is at least 40° C. It has been found that temperatures below 40° C. may cause an increase in iso-dense etch rate loading.

[0040] When the target temperature and pressure are reached, a plasma etching process can be performed by forming a plasma comprising SiCl4 and one or more additional gases (e.g., a carrier gas or a diluent). The plasma etching process can be a pulsed plasma etching process. In one embodiment, in box 503, a plasma etching pulse / cycle is performed on the sample and / or the article. In box 504, a plasma etching pulse is performed by directing a gas flow comprising SiCl4 and a diluent toward the sample and / or the article. The total gas feed flow of SiCl4 and the diluent is from about 50 sccm to about 2000 sccm, from about 100 sccm to about 1500 sccm, from about 150 sccm to about 1250 sccm, from about 200 sccm to about 1000 sccm, from about 250 sccm to about 750 sccm, or any sub-range or value herein. The amount of SiCl4 in the total gas feed flow is from about 5 mol% to about 80 mol%, from about 5 mol% to about 70 mol%, from about 5 mol% to about 60 mol%, from about 5 mol% to about 50 mol%, from about 5 mol% to about 40 mol%, from about 10 mol% to about 80 mol%, from about 10 mol% to about 70 mol%, from about 20 mol% to about 70 mol%, from about 20 mol% to about 60 mol%, from about 30 mol% to about 50 mol%, or any sub-range or value herein.

[0041] The diluent may include Ar, He or a combination of the above gases. The diluent may additionally or alternatively include one or more additional inert gases. The amount of Ar in the total gas feed flow may be from about 5mol% to about 15mol%, from about 7.5mol% to about 12.5mol%, or from about 9mol% to about 11mol%, or any sub-range or value herein. The amount of He in the total gas feed flow may be from about 5mol% to about 90mol%, from about 10mol% to about 80mol%, from about 15mol% to about 75mol%, from about 25mol% to about 65mol%, from about 30mol% to about 60mol%, from about 35mol% to about 55mol%, or any sub-range or value herein.

[0042] At block 506, a bias power is applied to the sample / article to achieve a bias state for a first time period. The bias power may be from about 10 watts (W) to about 5000 watts (W), from about 200 W to about 2000 W, from about 300 W to about 3000 W, from about 400 W to about 2500 W, from about 500 W to about 2000 W, from about 600 W to about 1500 W, or from about 750 W to about 1250 W, or any sub-range or value herein. Higher bias powers result in straighter profiles (e.g., more vertical profiles on the sidewalls of the trenches), with reduced profile curvature and lower selectivity to the pattern mask. The bias power may be a time-averaged power. The bias frequency can be from about 400kHz to about 60MHz, from about 400kHz to about 40MHz, from about 400kHz to about 35MHz, from about 400kHz to about 27MHz, from about 400kHz to about 20MHz, from or about 800kHz to about 10MHz, or any sub-range or value herein. Two example frequencies that can be used are 13MHz and 2MHz. The results show that the 2MHz frequency can provide a lower pattern mask selectivity than the 14MHz frequency. The first time period in which the bias power is applied is from about 10 microseconds to about 1 millisecond, from about 30 microseconds to about 1 millisecond, from about 50 microseconds to about 1 millisecond, from about 70 microseconds to about 1 millisecond, or from about 85 microseconds to about 1 millisecond, or any sub-range or value herein. In box 508, the bias power is stopped after the first time period ends.

[0043] After stopping the bias power, in frame 510, subsequently apply source power to realize source state and reach second time period.Source power can be from about 10W to about 5000W, from about 200W to about 2000W, from about 300W to about 3000W, from about 400W to about 2500W, from about 500W to about 2000W, from about 600W to about 1500W, or about 750W to about 1250W, or any sub-range or value herein.Source power can be time average source power (for example, source power multiplied by duty cycle).Source frequency can be about 10MHz to about 15MHz, or about 13MHz, or any sub-range or value herein.

[0044] In some embodiments, the second time period for which source power may be applied is from about 10 microseconds to about 1 millisecond, from about 30 microseconds to about 1 millisecond, from about 50 microseconds to about 1 millisecond, from about 70 microseconds to about 1 millisecond, or from about 85 microseconds to about 1 millisecond, or any sub-range or value herein.

[0045] In some embodiments, the ratio of the first time period to the second time period is from about 1:10 to about 10:1, from about 1:9 to about 9:1, from about 1:8 to about 8:1, from about 1:7 to about 7:1, from about 1:6 to about 6:1, from about 1:5 to about 5:1, from about 1:4 to about 4:1, from about 1:3 to about 3:1, from about 1:2 to about 2:1, or about 1:1, or any sub-range or value herein.

[0046] After the second time period in block 510 ends, in block 511, the source power is stopped. Then, in block 512, the bias power and the source power are not applied in the chamber to achieve the recovery state for a third time period. The third time period can be from about 10 microseconds to about 1 millisecond, from about 50 microseconds to about 1 millisecond, from about 60 microseconds to about 1 millisecond, from about 70 microseconds to about 1 millisecond, from about 80 microseconds to about 1 millisecond, or from about 85 microseconds to about 1 millisecond, or any sub-range or value herein.

[0047] In some embodiments, the ratio of the third time period to the sum of the first time period and the second time period is from about 1:1 to about 90:1, from about 1:1 to about 80:1, from about 1:1 to about 70:1, from about 1:1 to about 60:1, from about 1:1 to about 50:1, from about 1:1 to about 40:1, from about 1:1 to about 30:1, from about 1:1 to about 20:1, from about 1:1 to about 10:1, or from about 1:1 to about 5:1, or any sub-range or value herein. In some embodiments, the third time period of recovery is longer than the first time period or the second time period so that the electron temperature can drop. When the electron temperature drops, it is associated with a lower ion temperature, which allows for better directional control during etching.

[0048] It has been discovered that a three-state etch pulse (505-512) comprising first a bias state (506, 508), then a source state (510, 511), and then a recovery state (512) provides improved directionality control for etching samples, and particularly for etching samples comprising alternating stacks of Si and SiGe layers when used in conjunction with SiCl4 chemistry.

[0049] After the third time period, at block 513, the sample / article may be checked to see if the target amount has been etched. Alternatively or additionally, a determination may be made as to whether the target amount of sample / article has been etched based on the amount of time the etching process has been performed. If the etching process has not been performed for the target amount of time (e.g., according to the etching recipe), the target amount of sample / article may not have been etched. If the target amount of sample / article has not been etched, the plasma etching pulse process of blocks 504 to 512 may be repeated. If the target amount of sample / article has been etched, the sample / article is removed from the etching chamber in block 514.

[0050] Because the bias state is performed before the source state and because a long recovery state is used (e.g., more than 50% of the total pulse time), the pulsed plasma etching process proposed in method 500 achieves a low plasma density. At high plasma density (e.g., as achieved using a continuous wave source power), the etch rate decreases due to increased deposition of the feed gas (SiCl4), which is undesirable. However, the low plasma density achieved in various embodiments results in an increase in the etch rate, i.e., about 0.1 nm / sec. In addition, the pulse scheme described herein produces a highly directional ion flux with a lower plasma density in the bias state while maintaining a low plasma density in the recovery state.

[0051] Figure 6 2 shows a plasma etching pulse cycle according to an embodiment of the present disclosure. Figure 6 In the embodiment, the plasma etching pulse cycle has three states. In the first state, the bias state 605 is realized. The bias state 605 can be based on the reference Figure 5 Block 506 is described as being implemented. Figure 6 The second state is the source state 610. Figure 5 The described block 510 implements the source state. The third state of the plasma etch pulse is the recovery state 615. The recovery state can be as described in reference Figure 5 The above is implemented as described in blocks 511 and 512 of FIG. Figure 6In the embodiment of the present invention, the duration of bias state 605 can be about 2% to about 10%, or about 5% of the plasma etch pulse cycle. The duration of source state 610 can be about 2% to about 10%, or about 5% of the plasma etch pulse cycle, and the duration of recovery state 615 can be about 80% to about 96%, or about 90% of the plasma etch pulse cycle.

[0052] The foregoing description sets forth many specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of several embodiments of the present invention. However, it will be apparent to those skilled in the art that at least some embodiments of the present invention may be practiced without the specific details. In other examples, well-known components or methods are not described in detail, or are presented in the form of simple block diagrams to avoid unnecessary confusion of the present invention. Therefore, the specific details set forth are merely exemplary. Specific implementations may differ from these exemplary details and are still contemplated to be within the scope of the present invention.

[0053] References throughout the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. In addition, the phrase "or" is intended to mean an inclusive "or" rather than an exclusive "or". When the terms "about" or "approximately" are used herein, it is intended to mean that the nominal value presented is accurate to within ±10%.

[0054] Although the operations of the methods herein are shown and described in a particular order, the order of operations of each method may be changed so that certain operations may be performed in reverse order, thereby performing certain operations synchronously with other operations to at least some extent. In another embodiment, instructions or sub-operations of different operations may be in an intermittent and / or alternating manner.

[0055] It should be understood that the above description is intended to be illustrative, rather than restrictive. After reading and understanding the above description, many other embodiments are apparent to those skilled in the art. Therefore, the scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents given by the claims.

Claims

1. A method for etching a sample, include: Performing a plasma etch pulse including: A silicon tetrachloride (SiCl 4 ) and diluent gas flow; The SiCl 4 and simultaneously with the flow of said diluent, applying a bias power to achieve a biased state for a first period of time; applying source power to achieve the source state for a second period of time; and not applying the bias power and the source power to achieve the recovery state for a third period of time; and The plasma etching pulses are repeated until a target amount of the sample has been etched.

2. The method of claim 1, wherein no source power is applied during the bias state, and no bias power is applied during the source state.

3. The method of claim 1, wherein the bias power is from about 100 W to about 5000 W.

4. The method of claim 1, wherein the bias frequency is from about 400 kHz to about 60 MHz.

5. The method of claim 1, wherein the plasma etch pulses are performed at a pressure of about 0.1 mT to about 500 mT.

6. The method of claim 1, wherein the plasma etch pulses are performed at a temperature of about -50°C to about 300°C.

7. The method of claim 1, wherein the source power is from about 100 W to about 5000 W.

8. The method of claim 1, wherein the diluent comprises argon (Ar), helium (He), or a mixture thereof.

9. The method of claim 1, wherein the gas stream comprises SiCl in an amount of about 5 mol % to about 80 mol %. 4 .

10. The method of claim 8, wherein the gas stream comprises Ar in an amount of about 5 mol% to about 15 mol%, and He in an amount of about 5 mol% to about 90 mol%.

11. The method of claim 1, wherein the first time period is about 10 microseconds to about 1 millisecond, wherein the second time period is about 10 microseconds to about 1 millisecond, and wherein the third time period is about 10 microseconds to about 1 millisecond.

12. The method of claim 1, wherein a ratio of the first time period to the second time period is from about 1:10 to about 10:

1.

13. The method of claim 1, wherein a ratio of the third time period to the sum of the first time period and the second time period is from about 1:1 to about 90:

1.

14. The method of claim 1, wherein the gas flow has a rate of about 50 seem to about 2000 seem.

15. The method of claim 1, wherein the portion of the sample etched with the plasma etch pulses comprises a plurality of alternating layers of silicon and silicon germanium.

16. The method of claim 1, wherein the plasma etching process creates a U-shaped profile in the sample.

17. A method of etching a substrate comprising a stack of alternating layers of silicon and silicon germanium, the method include: Bringing a chamber including the substrate to a pressure of about 0.1 mT to about 500 mT; bringing the substrate to a temperature of about -50°C to about 300°C; A plasma is generated from a gas stream containing silicon tetrachloride (SiCl 4 ) and a diluent, wherein the diluent includes argon (Ar), helium (He), or a mixture of the two; as well as The plasma is directed toward the substrate to etch the stack of alternating layers of silicon and silicon germanium on the substrate.

18. The method of claim 17, wherein the gas stream comprises SiCl in an amount of about 5 mol % to about 80 mol %. 4 .

19. A method of etching a sample, include: Performing a plasma etch pulse including: applying a bias power to achieve a bias state for a first period of time while directing a flow of gas and diluent toward the sample; applying source power to achieve the source state for a second period of time; and not applying the bias power and the source power to achieve the recovery state for a third period of time; and The plasma etch pulses are repeated until a target amount of the sample has been etched.

20. The method of claim 19, wherein the gas comprises SiCl 4 , and the diluent includes Ar, He, and a mixture of the two.

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