Method for producing FET structures

Abstract

The invention relates to a method for producing a field effect transistor (FET) structure (10, 10 ', 10' ', 10 '''). The method comprises the steps of: (a) generating a first structure on a substrate (11), the first structure comprising a first stack of layers (12a), a second stack of layers (12b) and a wall (15) between the first stack of layers (12a) and the second stack of layers (12b), the first stack of layers (12a) and the second stack of layers (12b) respectively comprise one or more first material layers (13) and two or more second material layers (14) stacked in an alternating manner, and the walls (15) are non-conductive; (b) removing the one or more first material layers (13) of the first stack of layers (12a) to create one or more cavities in the first stack of layers (12a); (c) etching to one side of the wall (15) through the one or more cavities in the first stack of layers (12a) to recess the side of the wall (15) to create a vertical cavity (19) between the first stack of layers (12a) and the recessed side of the wall (15); (d) filling the cavity and the vertical cavity (19) in the first stack of layers (12a) with a gate dielectric material and a gate metal (17).

Description

Technical Field

[0001] The present invention relates to a method for producing a field-effect-transistor (FET) structure, and to a FET structure obtainable by said method. Background Art

[0002] Metal-oxide semiconductor field-effect transistors (MOSFETs) are the main semiconductor components in various devices such as microprocessors and memory chips. Fin field-effect transistors (FinFETs) are a special type of MOSFET that has a fin-shaped channel surrounded by a gate on two or three sides. Due to this gate design, FinFETs have better scalability than traditional planar MOSFETs.

[0003] A nanosheet field-effect transistor (NS FET) is another type of MOSFET that includes horizontally stacked nanosheets that form the channel of the transistor. In an NS FET, the gate can completely surround the nanosheet channel, forming a gate-all-around (GGA) device, i.e., a transistor device with the gate located on all four sides of the channel. This all-around gate device is generally seen as a next-generation device architecture that will help complementary metal-oxide semiconductor (CMOS) devices further scale beyond the limitations of FinFETs.

[0004] Fork-chip nanosheet devices are proposed as an extension of nanosheet devices. In fork-chip FETs, a vertical nanosheet is separated into a pMOS side and an nMOS side by vertical dielectric isolation. The fork-chip FET design can further expand the area and provide more room for optimizing the effective width of the device. However, the short channel effect in the fork-chip FET may lead to performance loss. Specifically, due to the dielectric isolation in the fork-chip FET, it is usually impossible to completely surround the nanosheet channel of the fork-chip FET with gates on all four sides. Therefore, the fork-chip FET cannot adopt a full-ring gate design, which potentially limits the further expansion of these devices. Summary of the invention

[0005] In view of the above, the present invention aims to provide an improved method for processing a FET structure and an improved FET structure obtainable by the method, which overcomes the above limitations and disadvantages.

[0006] These and other objects are achieved by the technical solutions of the present invention as described in the attached independent claims. Advantageous implementations are further defined in the dependent claims.

[0007] A first aspect of the present invention provides a method for producing a field-effect transistor (FET) structure, comprising the following steps: (a) generating a first structure on a substrate, the first structure comprising a first stack, a second stack and a wall located between the first stack and the second stack, wherein the first stack and the second stack respectively comprise one or more first material layers and two or more second material layers stacked in an alternating manner, and the wall is non-conductive; (b) removing the one or more first material layers of the first stack to generate one or more cavities in the first stack; (c) etching through the one or more cavities in the first stack to one side of the wall so that the side of the wall is recessed, thereby generating a vertical cavity between the first stack and the recessed side of the wall; and (d) filling the cavities and the vertical cavities in the first stack with gate dielectric material and gate metal.

[0008] This provides the advantages of a FET structure with a forked nanosheet design, where the gate can completely surround part or all of the nanosheet channel. Thus, the FET structure provides a full-ring gate design that can reduce performance losses and allow the FET structure to be further expanded.

[0009] In an implementation of the first aspect, the gate dielectric material and the gate metal surround part or all of the second material layer of the first stacked layer on four sides.

[0010] Specifically, the gate dielectric material and the gate metal also cover the second material layer facing the side of the wall. This is usually not possible in conventional fork-sheet FETs where there is no gap between the nanosheet layer and the dielectric barrier layer.

[0011] In an implementation of the first aspect, the wall is formed of a dielectric material.

[0012] This provides the advantage of forming the wall from a non-conductive material.For example, the wall may be formed from a nitride material, such as silicon nitride (Si3N4).

[0013] In an implementation of the first aspect, the step of etching into the side of the wall comprises isotropically etching the wall.

[0014] This provides an advantage that the wall can be effectively recessed from the first layer stack so that the gate material can completely surround the remaining material layers of the first layer stack. Thus, the FET structure can have a full-all-around gate design.

[0015] Isotropic etching means that the etching properties are independent of the etching direction, i.e., the etching rate is substantially the same for all etching directions. Specifically, the isotropic etching of the side of the wall generates a characteristic surface profile (rail shape) of the wall. The railing profile of the wall is visible in the processed FET structure and provides a characteristic fingerprint of the method.

[0016] In an implementation manner of the first aspect, the first material layer and the second material layer are nanolayers.

[0017] The FET structure may be a nanosheet FET, in particular a fork-sheet nanosheet FET.

[0018] In an implementation of the first aspect, the one or more first material layers are one or more silicon germanium (SiGe) layers, and the two or more second material layers are two or more silicon (Si) layers.

[0019] In an implementation of the first aspect, the one or more first material layers are one or more silicon (Si) layers, and the two or more second material layers are two or more silicon germanium (SiGe) layers.

[0020] In an implementation manner of the first aspect, the gate metal includes an n-type work function metal.

[0021] This provides an advantage that the nMOS side of the FET structure can be formed by surrounding the remaining layers of the first layer stack with the n-type work function metal.

[0022] In an implementation of the first aspect, a first portion of the cavity in the first stacked layer is filled with an n-type work function metal, and a second portion of the cavity in the first stacked layer is filled with a p-type work function metal.

[0023] This provides an advantage that nMOS and pMOS structures can be formed on one side of the wall of the FET structure. Thus, the FET structure can be a complementary FET structure comprising nMOS and pMOS structures stacked on each other.

[0024] In one implementation of the first aspect, the method also includes: (e) removing the one or more first material layers or the two or more second material layers of the second stack to generate one or more cavities in the second stack; (f) etching through the one or more cavities in the second stack to the other side of the wall so that the other side of the wall is recessed from the second stack, thereby generating other vertical cavities between the second stack and the other recessed side of the wall; (g) filling the cavities and the other vertical cavities in the second stack with other gate dielectric materials and other gate metals.

[0025] This achieves the advantage that the gate can also completely surround part or all of the nanosheet channel on the other side of the structure. Therefore, the FET structure can be a fork-sheet FET structure with a full-around gate design on both sides of the structure (e.g., nMOS and pMOS sides).

[0026] In an implementation of the first aspect, steps (e) to (g) are performed simultaneously with steps (b) to (d), respectively.

[0027] For example, other gate dielectric materials and / or other gate metals may be the same as the gate dielectric material and / or the gate metal used to fill the cavity in the first layer stack.

[0028] However, it is also possible that only steps (e) and (f) are carried out simultaneously with steps (b) and (c), respectively.

[0029] In an implementation of the first aspect, the other gate dielectric material and the other gate metal surround part or all of the remaining material layers of the second stack on four sides.

[0030] In particular, the other gate dielectric material and the other gate metal also cover the remaining material layer of the second stack of layers on the side facing the wall. The etching (step f) can again be performed by isotropic etching to produce a characteristic railing-shaped wall. Here, the remaining material layer can refer to the material layer of the second stack of layers that is not removed in step (e).

[0031] In an implementation manner of the first aspect, the other gate metal is a p-type work function metal.

[0032] This provides an advantage that the pMOS side of the FET structure can be formed by surrounding the remaining layers of the second layer stack with the p-type work function metal.

[0033] In an implementation of the first aspect, a first portion of the cavity in the second stacked layer is filled with an n-type work function metal, and a second portion of the cavity in the second stacked layer is filled with a p-type work function metal.

[0034] This provides an advantage that nMOS and pMOS structures can also be formed on the other side of the wall of the FET structure.

[0035] In an implementation of the first aspect, the substrate is or includes doped silicon (Si).

[0036] In an implementation manner of the first aspect, the method further includes: doping a source region of the substrate, and doping a drain region of the substrate.

[0037] This offers the advantage that source and drain contacts of the FET structure can be produced.

[0038] In an implementation of the first aspect, forming the first structure on the substrate includes: forming a stacked layer on the substrate, wherein the stacked layer includes one or more first material layers and two or more second material layers stacked in an alternating manner; forming grooves in the stacked layer by etching, thereby generating the first stacked layer and the second stacked layer; filling the grooves with one or more non-conductive materials, thereby generating the wall.

[0039] The stack of layers may be formed by subsequently depositing the first material layer and the second material layer on the substrate using a suitable deposition technique, such as chemical vapor deposition (CVD). The trench locations may be defined by openings in a hard mask on the stack of layers, and the trenches may be formed by etching into the stack of layers.

[0040] A second aspect of the present invention provides a field-effect transistor (FET) structure, which can be obtained by the method according to the first aspect of the present invention.

[0041] The FET structure may be a nanosheet structure or a nanosheet FET structure, in particular a fork-sheet nanosheet FET structure.

[0042] Such FET structures produced by the method of the first aspect of the invention show a clear "fingerprint" of the method. For example, a characteristic railing shape is produced on one or both sides of the wall by etching into one or both sides of the wall using an isotropic etching process. This characteristic wall profile can be seen in the processed structure. For example, structural inspection by cross-sectional transmission electron microscope (TEM) images can reveal this characteristic railing shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In conjunction with the accompanying drawings, the following description of specific embodiments will illustrate the above aspects and their implementation methods, wherein:

[0044] Figure 1 A to Figure 1 D shows the steps of a method for producing a FET structure provided by one embodiment of the present invention;

[0045] Figure 2 A to Figure 2 E shows the steps of a method for producing a FET structure provided by one embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a FET structure provided for one embodiment of the present invention;

[0047] Figure 4 A schematic diagram of a FET structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] Figure 1 A to Figure 1 D shows the steps of a method for producing the FET structure 10 provided by one embodiment of the present invention.

[0049] therefore, Figure 1 A to Figure 1 D shows the processing of a single FET structure. However, the method can be used to produce multiple FET structures in parallel on the same substrate 11.

[0050] like Figure 1 As shown in A, the method includes generating a first structure on a substrate 11. The first structure includes a first stacked layer 12a, a second stacked layer 12b, and a wall 15 located between the first stacked layer 12a and the second stacked layer 12b. Therefore, the first stacked layer 12a and the second stacked layer 12b respectively include one or more first material layers 13 and two or more second material layers 14 stacked in an alternating manner. Specifically, the material layers 13 and 14 are vertically stacked along the z direction and extend along the x direction, perpendicular to the direction defined by the substrate 11. Figure 1 A to Figure 1 The schematic coordinate system in D indicates a cross-sectional view in the yz plane.

[0051] For example, the first structure can be obtained by: Figure 1 A to Figure 1 D) is formed by forming a stack of layers on a substrate 11, wherein the stack of layers includes one or more first material layers 13 and two or more second material layers 14 stacked in an alternating manner; forming grooves in the stack of layers by etching to separate the layer stacks in the first stack of layers 12a and the second stack of layers 12b. The grooves may then be filled with one or more non-conductive materials to generate walls 15. For example, the grooves may be etched in the stack of layers through gaps in an etching mask 16 (e.g., a hard mask).

[0052] The wall 15 is non-conductive. For example, the wall 15 is formed of a dielectric material, such as a nitride such as silicon nitride (Si3N4). The wall may have a thickness (along the width direction) of 15 to 20 nm. Figure 1 A and Figure 1 As shown in B, a portion of the wall 15 may penetrate the substrate 11.

[0053] Part or all of the first material layer 13 and the second material layer 14 may be nanolayers, i.e., layers with a nanometer-level thickness. For example, the first material layer 13 may be a silicon germanium (SiGe) layer; the second material layer may be a silicon (Si) layer. However, the order of the layers 13 and 14 may also be reversed, i.e., the first material layer 13 may be a Si layer, and the second material layer 14 may be a SiGe layer.

[0054] The substrate 11 may be a Si substrate or a silicon on insulator (SOI) substrate. Specifically, the substrate 11 may include doped Si. For example, the source region and the drain region of the substrate 11 are at least partially formed by doped Si. In this regard, the method may include the further steps of doping the source region of the substrate 11, and doping the drain region of the substrate 11. Such doping of the substrate 11 may be performed before forming the first structure on the substrate 11.

[0055] like Figure 1 As shown in FIG. 2B , the method further comprises the step of removing one or more first material layers 13 to produce one or more cavities in the stacked layers 12 a , 12 b .

[0056] The first material layer 13 may be removed by a suitable dry or wet etching process.

[0057] exist Figure 1In B, the first material layer 13 is removed in the first layer stack 12a and the second layer stack 12b. However, it is also possible to remove only the first material layer 13 in the first layer stack 12a while keeping the first material layer 13 in the second layer stack 12b intact. For example, the first (or second) material layer 13, 14 in the second layer stack 12b can then be removed in a subsequent processing step.

[0058] like Figure 1 As shown in FIG. 3 , the method further comprises the step of etching one or more cavities in the stacked layers 12a, 12b to the side of the wall 15 to make the side of the wall concave. Thus, a corresponding vertical cavity 19 is generated between each stacked layer 12a, 12b and the concave side of the wall 15.

[0059] When the first material layer 13 is removed only from the first layer stack 12a but not from the second layer stack 12b, only one side of the wall 15, i.e., the side facing the first layer stack 12a, is etched through one or more cavities in the first layer stack 12a, and thus only one vertical cavity 19 is produced between the first layer stack 12a and the recessed side of the wall 15.

[0060] Specifically, the step of etching into one or more sides of the wall 15 comprises isotropic etching of the wall 15. Isotropic etching means that the etching properties do not depend on the etching direction, that is, the etching rate is substantially the same for all etching directions. This produces a characteristic, railing-shaped surface profile on one or more sides of the wall 15, such as Figure 1 As shown in C.

[0061] The etching of the walls may be a selective etching step, ie there is no etching attack on the material layer 14, the gate and the inner spacers.

[0062] For example, etching of the walls may be performed by a suitable wet etching process, for example using a HF solution.

[0063] like Figure 1 As shown in FIG. 4D , the method further comprises the step of filling the cavities in the layer stacks 12 a , 12 b and the vertical cavity 19 with a gate dielectric material and / or a gate metal.

[0064] For example, the cavity in the first layer stack 12a and the cavity 19 between the first layer stack 12a and one side of the wall can be filled with certain gate dielectric materials and gate metals, especially n-type work function metals, while the cavity in the second layer stack 12b and the cavity 19 between the first layer stack 12a and the other side of the wall can be filled with other gate dielectric materials and gate metals, especially p-type work function metals.

[0065] The gate metal and the other gate metal may both include a mixture of metals or a single type of metal. The gate metal and the other gate metal may be an N high-k metal and a P high-k metal, respectively.

[0066] Specifically, the gate dielectric material and other gate dielectrics can be the same and can be deposited in a single step. Specifically, the gate dielectric material is formed as a second material layer 14 that completely surrounds the first layer stack 12a and the second layer stack 12b. Then, the gate metal and other gate metals can be subsequently or simultaneously deposited on the gate dielectric material.

[0067] In the case of replacement ( Figure 1 A to Figure 1 D), the first material layer 13 is removed only from the first layer stack 12a and a cavity is formed only in the first layer stack 12a and between the first layer stack 12a and the recessed side of the wall 15, and only the cavity on one side of the wall is filled with gate dielectric material and gate metal (e.g., n-type work function metal).

[0068] pass Figure 1 A to Figure 1 D, a FET structure 10 including an nMOS side and a pMOS side can be obtained. Thus, the second material layer 14 of the first stack 12a can form a channel on the nMOS side of the FET structure 10, and the second material layer 14 of the second stack 12b can form a channel on the pMOS side of the FET structure 10. The channel can be a Si channel. The gate dielectric material and the gate metal can surround part or all of the channels on the nMOS side on four sides. The same is true for other gate dielectric materials and other gate metals that can completely surround part or all of the channels on the pMOS side. Therefore, the FET structure 10 can be a gate-all-around (GAA) FET structure with a fork-type nanosheet design. Specifically, the structure 10 is a baluster nanosheet (BNS) MOSFET structure, that is, a NS MOSFET with a dielectric wall having a characteristic baluster profile.

[0069] In all Figure 1 A to Figure 1 The etching mask 16 shown in D may also be formed on the substrate 11 ( Figure 1 A) after forming a first structure or using a gate dielectric material and / or gate metal 17, 18 ( Figure 1 D) The cavities in the fill layer stack 12a, 12b are subsequently removed or at some point between these steps.

[0070] Figure 2 A to Figure 2E shows the steps of a method for producing a FET structure 10 ′ provided by one embodiment of the present invention.

[0071] Figure 2 A to Figure 2 The method shown in E is different from Figure 1 A to Figure 1 The method shown in D is to remove the different material layers 13 , 14 of the first layer stack 12 a and the second layer stack 12 b , respectively, so that the resulting FET structure 10 ′ includes channels of different materials on both sides of the wall 15 .

[0072] like Figure 2 As shown in A, the method again starts with generating a first structure on a substrate 11. Then, as Figure 2 As shown in FIG. 1B , the first material layer 13 of the first stack 12a and the second material layer 14 of the second stack 12b are removed. This can be done in two subsequent selective etching steps. The corresponding N / P protective mask is conducive to the selective removal of the corresponding material layers 13 and 14 in the stack 12a and 12b, for example, to protect the side surfaces that are not etched.

[0073] For example, the first material layer 13 may be a SiGe layer; the second material layer may be a Si layer. Both the material layers 13 and 14 may be nanolayers. However, the SiGe layer 13 may be thicker than the Si layer 14. In order to reduce the thickness of the remaining first material layer 13 in the second stack 12b, the method may include a step of selectively trimming the first material layer 13 in the second stack 12b, such as Figure 2 C. Trimming may be performed by performing through-hole etching on the remaining first material layer 13 .

[0074] Then, if Figure 2 As shown in FIG. 2 , the method comprises the step of etching through the cavity in the laminate layers 12a, 12b into the side of the wall 15 to recess the side of the wall 15 and create a vertical cavity 19 between the laminate layers 12a, 12b and the wall 15. This creates the characteristic railing shape of the wall 15, which in this case is asymmetrical between the two sides of the wall 15 due to the fact that the remaining material layers 13, 14 on the two sides of the wall 15 are vertically offset.

[0075] Figure 2 E shows the final step of filling the cavities in the layer stacks 12a, 12b and the vertical cavity 19 with gate dielectric material and / or gate metal. Thus, the cavity in the first layer stack 12a is filled with an n-type work function metal and the cavity in the second layer stack 12b is filled with a p-type work function metal.

[0076] In this way, a FET structure 10 ′ may be generated which may have channels formed of different materials on the n-side and the p-side, ie, a Si channel on the n-side and a SiGe channel on the p-side.

[0077] Figure 3 A schematic diagram of a FET structure 10" provided in an embodiment of the present invention.

[0078] Figure 3 The FET structure 10" shown includes two stacked layers 12a, 12b separated by a dielectric wall 15. Each of these stacked layers 12a, 12b is also provided at Figure 3 As shown in FIG. 1 , the cavity is filled with different work function metals, for example, an n-type work function metal 17 and a p-type work function metal 18 .

[0079] Therefore, the resulting FET structure 10 ″ is a complementary FET (CFET) structure having nMOS and pMOS portions stacked on each other on both sides of the wall 15 . Specifically, the FET structure 10 ″ is a rail-like nanosheet CFET (BNSCFET).

[0080] Figure 3 The illustrated stacked layers 12a, 12b also include material layers of different thicknesses. For example, the material layer between the nMOS and pMOS portions may be thicker than the material layer within the portions in order to physically separate the nMOS and pMOS portions.

[0081] Figure 3 The FET structure 10" shown in FIG. Figure 1 A to Figure 1 D, where the corresponding cavities in the stack layers 12a, 12b can then be filled with different gate metals 17, 18.

[0082] Figure 4 A schematic diagram of a FET structure 10'' provided in an embodiment of the present invention.

[0083] FET structure 10"' is similar to Figure 3 The structure 10" shown in FIG. 1 includes nMOS and pMOS portions located on both sides of the wall 15. However, in Figure 4 In the illustrated structure 10'', different material layers are removed from the stacked layers 12a, 12b in the pMOS and nMOS portions. Thus, for example, the corresponding nMOS portion includes a Si channel, while the corresponding pMOS portion includes a SiGe channel.

[0084] Specifically, the above-mentioned FET structures 10, 10', 10", 10'" can improve device performance due to the following reasons: (i) better effective width compared to a three-gate fork-piece device (i.e., a fork-piece FET with gates on three sides of the channel); and (ii) better short channel effect due to better gate coverage on each side, while providing standard cell scaling together with the wall 15.

[0085] The FET structures 10, 10', 10", 10'" may be comprised of a processor or processing circuit (not shown) for performing, conducting or initiating various operations. The processing circuit may include hardware and / or the processing circuit may be controlled by software. The hardware may include analog circuits or digital circuits, or both. The digital circuit may include components such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP) or a multi-purpose processor. The device may also include a storage circuit that stores one or more instructions that may be executed by the processor or processing circuit, specifically, under the control of software. For example, the storage circuit may include a non-transitory storage medium that stores executable software code, and when executed by the processor or processing circuit, various operations of the device are performed. In one embodiment, the processing circuit includes one or more processors and a non-transitory memory connected to the one or more processors.

[0086] The invention has been described in conjunction with various embodiments and implementations as examples. However, from a study of the drawings, the invention and the independent claims, a person skilled in the art will be able to understand and implement other variations when practicing the subject matter claimed. In the claims and in the specification, the word "comprising" does not exclude other elements or steps, and "a" does not exclude a plurality of elements or steps. A single element or other unit may fulfil the functions of several entities or items described in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be effectively used.

Claims

1. A method for producing a field-effect transistor (FET) structure (10, 10', 10", 10'"), characterized in that: The following steps are involved: (a) generating a first structure on a substrate (11), the first structure comprising a first stack of layers (12a), a second stack of layers (12b) and a wall (15) located between the first stack of layers (12a) and the second stack of layers (12b), wherein the first stack of layers (12a) and the second stack of layers (12b) respectively comprise one or more first material layers (13) and two or more second material layers (14) stacked in an alternating manner, and the wall (15) is non-conductive; (b) removing the one or more first material layers (13) of the first layer stack (12a) to create one or more cavities in the first layer stack (12a); (c) etching through the one or more cavities in the first stack layer (12a) into one side of the wall (15) to recess the side of the wall (15) thereby creating a vertical cavity (19) between the first stack layer (12a) and the recessed side of the wall (15); (d) filling the cavity and the vertical cavity (19) in the first layer stack (12a) with a gate dielectric material and a gate metal (17).

2. The method according to claim 1, characterized in that The gate dielectric material and the gate metal (17) surround part or all of the second material layer (14) of the first stacked layer (12a) on four sides.

3. The method according to claim 1 or 2, characterized in that: The wall (15) is formed from a dielectric material.

4. The method according to any one of the preceding claims, characterized in that The step of etching into the sides of the wall (15) comprises isotropic etching of the wall.

5. The method according to any one of the preceding claims, characterized in that The first material layer (13) and the second material layer (14) are nanolayers.

6. The method according to any one of the preceding claims, characterized in that The one or more first material layers (13) are one or more silicon germanium (SiGe) layers, and the two or more second material layers (14) are two or more silicon (Si) layers.

7. The method according to any one of claims 1 to 5, characterized in that The one or more first material layers (13) are one or more silicon (Si) layers, and the two or more second material layers (14) are two or more silicon germanium (SiGe) layers.

8. The method according to any one of the preceding claims, characterized in that The gate metal (17) comprises an n-type work function metal.

9. The method according to any one of claims 1 to 7, characterized in that A first portion of the cavity in the first stacked layer (12a) is filled with an n-type work function metal, and a second portion of the cavity in the first stacked layer (12b) is filled with a p-type work function metal.

10. The method according to any one of the preceding claims, characterized in that The method further comprises: (e) removing the one or more first material layers (13) or the two or more second material layers (14) of the second layer stack (12b) to generate one or more cavities in the second layer stack (12b); (f) etching through the one or more cavities in the second stack (12b) to another side of the wall (15) so that the other side of the wall (15) is recessed from the second stack (12b) to create a further vertical cavity (19) between the second stack (12b) and the other recessed side of the wall (15); (g) filling the cavity and the further vertical cavity (19) in the second layer stack with further gate dielectric material and further gate metal (18).

11. The method according to claim 10, characterized in that Steps (e) to (g) are respectively carried out simultaneously with steps (b) to (d).

12. The method according to claim 10 or 11, characterized in that: The further gate dielectric material and the further gate metal (18) surround part or all of the remaining material layers (13, 14) of the second layer stack (12b) on four sides.

13. The method according to any one of claims 10 to 12, characterized in that The other gate metal (18) is a p-type work function metal.

14. The method according to any one of claims 10 to 13, characterized in that A first portion of the cavity in the second stacked layer (12b) is filled with an n-type work function metal, and a second portion of the cavity in the second stacked layer (12b) is filled with a p-type work function metal.

15. The method according to any one of the preceding claims, characterized in that The substrate (11) is doped silicon (Si) or includes doped silicon (Si).

16. The method according to any one of the preceding claims, characterized in that Also includes: A source region of the substrate (11) is doped, and a drain region of the substrate (11) is doped.

17. The method according to any one of the preceding claims, characterized in that The forming the first structure on the substrate comprises: forming a stacked layer on the substrate, wherein the stacked layer comprises one or more first material layers (13) and two or more second material layers (14) stacked in an alternating manner; Forming grooves in the stacked layers by etching, thereby generating the first stacked layers (12a) and the second stacked layers (12b); The trenches are filled with one or more non-conductive materials, thereby creating the walls (15).

18. A field-effect transistor (FET) structure (10, 10', 10", 10'"), characterized in that: Obtainable by the method according to any one of the above claims.

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