Semiconductor device

Abstract

A novel semiconductor device is provided. The present invention is a semiconductor device combining a lateral channel type transistor and a vertical channel type transistor. A CMOS-type semiconductor device is achieved by configuring a p-channel-type transistor using a lateral channel-type transistor and configuring an n-channel-type transistor using a vertical channel-type transistor. An opening in which a vertical channel type transistor is formed is provided in an insulating layer in a region overlapping a gate electrode of a lateral channel type transistor. An oxide semiconductor is used in a semiconductor layer of a vertical channel type transistor.

Description

Technical Field

[0001] One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the invention disclosed in this specification and the like relates to a process, a machine, a product, or a composition of matter. In particular, it relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above-mentioned technical field. Examples of the technical field of one embodiment of the present invention disclosed in the specification, etc. include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input-output devices (e.g., touch panels), driving methods of these devices, or manufacturing methods of these devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, sometimes storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, or include semiconductor devices. Background Art

[0004] In a display device, which is one of semiconductor devices, as one method of achieving weight reduction and narrow frame, it is known that a pixel circuit and at least a part of a driver circuit are manufactured together on the same substrate. In addition, in order to further narrow the frame, it is necessary to reduce the size of the driver circuit.

[0005] Generally, the driving circuit is configured using a CMOS (Complementary Metal Oxide Semiconductor) circuit. A CMOS circuit is configured by combining n-channel transistors and p-channel transistors, and has a high degree of design freedom.

[0006] On the other hand, a driving circuit composed of only n-channel transistors or only p-channel transistors is being studied to achieve a narrow frame. This type of circuit is also called a "unipolar circuit." For example, Patent Document 1 discloses a technology for forming a shift register using a unipolar circuit. [Prior technical literature] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2002-049333 Summary of the invention Technical problem to be solved by the invention

[0008] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a small footprint. Another purpose of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc. Solutions to technical problems

[0010] (1) One embodiment of the present invention is a semiconductor device including a first semiconductor layer provided on an insulating surface, a first insulating layer on the first semiconductor layer, a first conductive layer on the first insulating layer, a second conductive layer electrically connected to a portion of the first semiconductor layer, a third conductive layer electrically connected to another portion of the first semiconductor layer, a second insulating layer covering the first conductive layer, the second conductive layer, and the third conductive layer, a third insulating layer on the second insulating layer, a fourth insulating layer on the third insulating layer, a fourth conductive layer on the fourth insulating layer, an opening penetrating the second insulating layer, the third insulating layer, the fourth insulating layer, and the fourth conductive layer, a second semiconductor layer having a region covering a side surface and a bottom of the opening, a fifth insulating layer having a region overlapping with a side surface and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, and a fifth conductive layer having a region overlapping with a side surface and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, respectively. The second semiconductor layer is electrically connected to the second conductive layer.

[0011] In addition, in (1), the second semiconductor layer may have a region overlapping with the first semiconductor layer via the second conductive layer.

[0012] (2) Another embodiment of the present invention is a semiconductor device including a first semiconductor layer provided on an insulating surface, a first insulating layer on the first semiconductor layer, a first conductive layer on the first insulating layer, a second conductive layer electrically connected to the first semiconductor layer, a third conductive layer electrically connected to the first semiconductor layer, a second insulating layer covering the first conductive layer, the second conductive layer, and the third conductive layer, a third insulating layer on the second insulating layer, a fourth insulating layer on the third insulating layer, a fourth conductive layer on the fourth insulating layer, an opening penetrating the second insulating layer, the third insulating layer, the fourth insulating layer, and the fourth conductive layer, a second semiconductor layer having a region covering a side surface and a bottom of the opening, a fifth insulating layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, and a fifth conductive layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, respectively. The second semiconductor layer is electrically connected to the first conductive layer.

[0013] In the above (1) and (2), the second insulating layer preferably contains silicon and nitrogen. The third insulating layer preferably contains silicon and oxygen. The fourth insulating layer preferably contains silicon and nitrogen.

[0014] In the above (1) and (2), the first semiconductor layer has a composition different from that of the second semiconductor layer. For example, silicon may be used for the first semiconductor layer and an oxide semiconductor may be used for the second semiconductor layer.

[0015] In the above (1) and (2), the first semiconductor layer preferably contains one or both of a Group 13 element and a Group 15 element.

[0016] The oxide semiconductor preferably contains one or both of indium and zinc. Effects of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device with a small footprint can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0018] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is a top view of a semiconductor device. Figure 1B is a cross-sectional view of a semiconductor device. Figure 1CIt is an equivalent circuit diagram of a semiconductor device. Figure 1D It is a timing diagram of a semiconductor device. Figure 1E It is the circuit symbol for an inverter circuit. Figure 2 is a cross-sectional view of a semiconductor device. Figure 3A is a cross-sectional view of a semiconductor device. Figure 3B It is a top view of the opening. Figure 3C is a cross-sectional view of a semiconductor device. Figure 4A is a top view of a semiconductor device. Figure 4B is a cross-sectional view of a semiconductor device. Figure 4C and Figure 4D It is an equivalent circuit diagram of a semiconductor device. Figure 5A is a top view of a semiconductor device. Figure 5B is a cross-sectional view of a semiconductor device. Figure 5C and Figure 5D It is an equivalent circuit diagram of a semiconductor device. Fig. 6A is a top view of a semiconductor device. Figure 6B is a cross-sectional view of a semiconductor device. Figure 6C and Fig.6D It is an equivalent circuit diagram of a semiconductor device. Fig. 7A is a top view of a semiconductor device. Figure 7B is a cross-sectional view of a semiconductor device. Figure 7C and Fig.7D It is an equivalent circuit diagram of a semiconductor device. Fig. 8A is a top view of a semiconductor device. Figure 8B is a cross-sectional view of a semiconductor device. Figure 8C and Fig.8D It is an equivalent circuit diagram of a semiconductor device. Fig.9A is a top view of a semiconductor device. Fig. 9B is a cross-sectional view of a semiconductor device. Fig. 9C and Fig.9D It is an equivalent circuit diagram of a semiconductor device. Fig. 10A is a top view of a semiconductor device. Fig. 10B is a cross-sectional view of a semiconductor device. Fig. 10C and Fig. 10D It is an equivalent circuit diagram of a semiconductor device. Fig.11A is a top view of a semiconductor device. Fig. 11B is a cross-sectional view of a semiconductor device. Fig. 11C and Fig.11D It is an equivalent circuit diagram of a semiconductor device. Fig. 12A is a top view of a semiconductor device. Fig. 12B is a cross-sectional view of a semiconductor device. Fig. 12C and Fig.12D It is an equivalent circuit diagram of a semiconductor device. Fig.13A is a top view of a semiconductor device. Fig. 13B is a cross-sectional view of a semiconductor device. Fig. 13C and Fig.13D It is an equivalent circuit diagram of a semiconductor device. Fig.14A is a top view of a semiconductor device. Fig. 14B is a cross-sectional view of a semiconductor device. Fig. 14C and Fig.14D It is an equivalent circuit diagram of a semiconductor device. FIG. 15A to FIG. 15E It is a diagram for explaining a method for manufacturing a semiconductor device. FIG. 16A to FIG. 16D It is a diagram for explaining a method for manufacturing a semiconductor device. FIG. 17A to FIG. 17D It is a diagram for explaining a method for manufacturing a semiconductor device. 18A to 18C It is a diagram for explaining a method for manufacturing a semiconductor device. FIG. 19A to FIG. 19C It is a diagram for explaining a method for manufacturing a semiconductor device. Fig. 20A It is a perspective view of a display device. Fig. 20B is a block diagram of a display device. FIG. 21A to FIG. 21F It is a diagram for explaining a configuration example of a logic circuit. Fig.22A and Fig. 22B A diagram illustrating a configuration example of a D flip-flop circuit. Fig.23 A diagram illustrating a configuration example of a shift register circuit. Fig.24A and Fig. 24B It is the circuit diagram of a latch circuit. FIG. 25A to FIG. 25D It is the circuit diagram of the demultiplexing circuit. FIG. 26A to FIG. 26D is a circuit diagram of a pixel circuit. FIG. 27A to FIG. 27D is a circuit diagram of a pixel circuit. Fig.28A and Fig.28B is a circuit diagram of a pixel circuit. Fig.29A and Fig.29B is a circuit diagram of a pixel circuit. Fig.30 A diagram illustrating a configuration example of a pixel circuit. FIG. 31A to FIG. 31G is a diagram showing an example of a pixel. FIG. 32A to FIG. 32K is a diagram showing an example of a pixel. FIG. 33A to FIG. 33F is a diagram showing a structural example of a light emitting device. FIG. 34A to FIG. 34C is a diagram showing a structural example of a light emitting device. Fig.35A and Fig.35B is a diagram showing a structural example of a display device. FIG. 36A to FIG. 36D is a diagram showing a structural example of a display device. FIG. 37A to FIG. 37C is a diagram showing a structural example of a display device. FIG. 38A to FIG. 38D is a diagram showing a structural example of a display device. FIG. 39A to FIG. 39F is a diagram showing a structural example of a display device. FIG. 40A to FIG. 40F is a diagram showing a structural example of a display device. FIG. 41A to FIG. 41F is a diagram showing an example of an electronic device. FIG. 42A to FIG. 42F is a diagram showing an example of an electronic device. Modes for Carrying Out the Invention

[0020] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the inventive structure described below, the same figure mark is sometimes used in different drawings to represent the same part or the part with the same function, and repeated description is omitted.

[0021] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings, etc., sometimes do not represent its actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a layer and a resist mask are sometimes unintentionally thinned due to a process such as etching, but for ease of understanding of the invention, the description is sometimes omitted.

[0022] In addition, in particular, in top views (also referred to as plan views) and perspective views, descriptions of some components may be omitted in order to facilitate understanding of the invention. In addition, descriptions of some hidden lines may be omitted in some cases.

[0023] Ordinal numerals such as "first" and "second" in this specification, etc. are added to avoid confusion between constituent elements, and do not indicate a certain order or sequence such as process order or stacking order. Note that for terms that are not added with ordinal numerals in this specification, etc., ordinal numerals are sometimes added to the terms in the claims to avoid confusion between constituent elements. Note that the ordinal numerals added in this specification, etc. are sometimes different from the ordinal numerals added in the claims. Note that for terms that are added with ordinal numerals in this specification, etc., their ordinal numerals are sometimes omitted in the claims, etc.

[0024] In addition, in this specification, "electrode" and "wiring" do not limit their components in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wiring" are provided as one.

[0025] In this specification and the like, when an etching step (removal step) is performed after a resist mask is formed by photolithography, unless otherwise specified, the resist mask is removed after the etching step is completed.

[0026] In addition, depending on the situation or state, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0027] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the drain and the source through the channel formation region. Note that in this specification, etc., the channel formation region refers to a region where current mainly flows.

[0028] In addition, when using transistors with different polarities or when the current direction of the circuit operation changes, the functions of the "source" and "drain" of the transistor are sometimes interchanged. Therefore, in this specification, etc., "source" and "drain" can be interchanged.

[0029] In addition, unless otherwise specified, the transistors shown in this specification are enhancement-type (normally closed) field-effect transistors. In addition, when the transistors shown in this specification are n-channel transistors and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0 V. In addition, when the transistors shown in this specification are p-channel transistors and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistors is less than 0 V.

[0030] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current (also referred to as "Id") when the transistor is in the off state (also referred to as the non-conducting state, the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state in which the potential difference between the gate and the source when the source is referenced (also referred to as "gate voltage" or "Vg") is lower than the threshold voltage, and in a p-channel transistor, the off state refers to a state in which Vg is higher than the threshold voltage. For example, sometimes the off-state current of an n-channel transistor refers to the drain current when Vg is lower than Vth.

[0031] In this specification, the off-state current may be referred to as leakage current. In this specification, the off-state current may refer to, for example, current flowing between a source and a drain when a transistor is in an off state.

[0032] In addition, in this specification, etc., a high power supply potential VDD (hereinafter, also simply referred to as "VDD" or "potential H") refers to a power supply potential of a potential higher than a low power supply potential VSS. In addition, a low power supply potential VSS (hereinafter, also simply referred to as "VSS" or "potential L") refers to a power supply potential of a potential lower than the high power supply potential VDD. In addition, a ground potential GND (hereinafter, simply referred to as "GND") may be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND, and when VSS is GND, VDD is a potential higher than GND.

[0033] In addition, "voltage" generally refers to the potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential, etc.). In addition, "potential" is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential. Therefore, the terms "voltage" and "potential" may sometimes be interchanged. In this specification, VSS is used as the reference potential unless otherwise specified.

[0034] In addition, in this specification, for the sake of convenience, words and phrases such as "upper", "lower", "above" or "below" that indicate configuration are sometimes used to explain the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located below the conductor".

[0035] In addition, the terms "above" and "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the case where other components are included between insulating layer A and electrode B may also be included.

[0036] In this specification, the term "overlap" or the like does not limit the state of the stacking order of the constituent elements. For example, "electrode B overlapping with insulating layer A" is not limited to the state of "electrode B formed on insulating layer A", but also includes the state of "electrode B formed under insulating layer A" or "electrode B formed on the right side (or left side) of insulating layer A".

[0037] In this specification, the words "adjacent" and "close to" do not limit the state of direct contact between components. For example, if it is an expression "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are directly in contact with each other, and it may also include the case where other components are included between insulating layer A and electrode B.

[0038] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0039] In addition, in this specification, unless otherwise stated, when count values ​​or measurement values ​​are "same", "identical", "equal", or "uniform", etc., a variation of ±20% is included as an error.

[0040] In addition, arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings and the like according to this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and sometimes the positive direction and the negative direction are not distinguished except for the cases clearly stated. The "Y direction" and the "Z direction" are also the same as the "X direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, sometimes one of the X direction, the Y direction, and the Z direction is referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0041] In this specification, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol such as "A", "b", "-1", "[n]", "[m, n]" is sometimes added to the symbol for identification. For example, the conductive layer 108 is sometimes divided into the conductive layer 108a and the conductive layer 108b in the figure.

[0042] (Implementation Method 1) A semiconductor device 100A according to one embodiment of the present invention will be described. Figure 1A is a top view of the semiconductor device 100A. Figure 1B It is along Figure 1A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 1C is an equivalent circuit diagram of the semiconductor device 100A. Figure 2 It is along Figure 1A The cross-sectional view of the portion of the dot-dash line B1-B2-B3 in FIG. Figure 1A In the figure, description of some components such as insulating layers is omitted to facilitate understanding of the structure of the semiconductor device.

[0043] <<Structure Example>> The semiconductor device 100A includes a transistor M1 and a transistor M2. The transistor M1 is a p-channel transistor, and the transistor M2 is an n-channel transistor. Figure 3A and Figure 3C yes Figure 1B An enlarged view of transistor M2 is shown. In addition, Figure 3B This is a diagram of the opening 112 as viewed from the Z direction.

[0044] The semiconductor device 100A includes an insulating layer 102 on a substrate 101, and includes a semiconductor layer 103 on the insulating layer 102. In addition, an insulating layer 104 is included on the insulating layer 102 and the semiconductor layer 103. In addition, a conductive layer 105 is included on the insulating layer 104. The semiconductor layer 103 and the conductive layer 105 have a region overlapping each other.

[0045] In addition, an insulating layer 106 is provided over the insulating layer 104 and the conductive layer 105. In addition, an opening 107a is provided in the insulating layer 104 and the insulating layer 106 in a region overlapping with a portion of the semiconductor layer 103. In addition, an opening 107b is provided in the insulating layer 104 and the insulating layer 106 in a region overlapping with another portion of the semiconductor layer 103.

[0046] In addition, a conductive layer 108a is provided on the insulating layer 106 and the opening 107a, and a conductive layer 108b is provided on the insulating layer 106 and the opening 107b. The conductive layer 108a is electrically connected to the semiconductor layer 103 in the opening 107a. In addition, the conductive layer 108b is electrically connected to the semiconductor layer 103 in the opening 107b.

[0047] In addition, the semiconductor layer 103 has a drain region 103a, a channel formation region 103b, and a source region 103c. In the semiconductor layer 103, the region overlapping with the conductive layer 105 is used as the channel formation region 103b. Therefore, the length of the channel formation region 103b in the X direction is the channel length L of the transistor M1 (refer to Figure 1B ). In addition, the length of the channel formation region 103b in the Y direction is equal to the channel width W of the transistor M1 (see Figure 2 ).

[0048] In addition, the drain region 103a is electrically connected to the conductive layer 108a, and the source region 103c is electrically connected to the conductive layer 108b.

[0049] Furthermore, an insulating layer 109 is provided over the insulating layer 106 , the conductive layer 108 a , and the conductive layer 108 b . An insulating layer 110 is provided over the insulating layer 109 . An insulating layer 111 is provided over the insulating layer 110 . Furthermore, a conductive layer 113 is provided over the insulating layer 111 .

[0050] In addition, in a region overlapping with a portion of the conductive layer 108a, the conductive layer 113, the insulating layer 111, the insulating layer 110, and the insulating layer 109, an opening 112 is provided (see Figure 1B and Figure 3A ). In addition, a semiconductor layer 114 is included on the opening 112. In addition, the semiconductor layer 114 has a region overlapping with the bottom of the opening 112 and a region overlapping with the side of the opening 112. In addition, a portion of the semiconductor layer 114 is electrically connected to the conductive layer 113, and another portion of the semiconductor layer 114 is electrically connected to the conductive layer 108a.

[0051] In addition, an insulating layer 115 is provided on the insulating layer 111, the conductive layer 113, and the semiconductor layer 114, and a conductive layer 116 is provided on the insulating layer 115. In addition, an insulating layer 117 is provided on the insulating layer 115 and the conductive layer 116. The insulating layer 115 has a region overlapping with the side surface of the opening 112 via the semiconductor layer 114. The conductive layer 116 has a region overlapping with the side surface of the opening 112 via the insulating layer 115 and the semiconductor layer 114.

[0052] In addition, openings 127 are provided in the insulating layer 115, the insulating layer 111, the insulating layer 110, the insulating layer 109, and the insulating layer 106 in a region overlapping with the conductive layer 105. In the openings 127, the conductive layer 105 and the conductive layer 116 are electrically connected to each other.

[0053] The semiconductor layer 103 is used as a semiconductor layer forming a channel of the transistor M1, the insulating layer 104 is used as a gate insulating layer, and the conductive layer 105 is used as a gate electrode. In addition, the conductive layer 108a is used as a drain electrode of the transistor M1, and the conductive layer 108b is used as a source electrode.

[0054] The semiconductor layer 114 is used as a semiconductor layer forming a channel of the transistor M2, the insulating layer 115 is used as a gate insulating layer, and the conductive layer 116 is used as a gate electrode. In addition, the conductive layer 108a is used as a drain electrode of the transistor M2, and the conductive layer 113 is used as a source electrode. The transistor M2 is provided in a region including the opening 112.

[0055] Since the source electrode and the drain electrode of the transistor M2 are arranged in the Z direction, Id flows in the Z direction (vertical direction). In other words, Id flows in a direction perpendicular to or substantially perpendicular to the surface of the substrate 101. A transistor in which Id flows in the vertical direction is also called a "vertical channel transistor".

[0056] Since the source electrode and the drain electrode of the transistor M1 are arranged in the X direction, Id flows in the X direction (lateral direction). In other words, Id flows in a direction parallel to or substantially parallel to the surface of the substrate 101. A transistor in which Id flows in the lateral direction is also called a "lateral channel transistor". In addition, a transistor in which Id flows in the Y direction is also a "lateral channel transistor".

[0057] The source electrode and the drain electrode of the vertical channel transistor are arranged in the Z direction, so the occupied area can be greatly reduced compared with the lateral channel transistor.

[0058] Here, materials that can be used for a semiconductor device or the like according to one embodiment of the present invention are described.

[0059] [Substrate] There are no major restrictions on the material used for the substrate. It can be determined based on the purpose, such as whether it is necessary to have light transmittance and heat resistance to withstand heat treatment. For example, glass substrates such as barium borosilicate glass and aluminum borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. In addition, semiconductor substrates, flexible substrates, laminated films, base film, etc. can also be used.

[0060] For example, the semiconductor substrate may be a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

[0061] When a semiconductor device of one embodiment of the present invention is used as a substrate for a display device, for example, a glass substrate with a large area such as the sixth generation (1500mm×1850mm), the seventh generation (1870mm×2200mm), the eighth generation (2200mm×2400mm), the ninth generation (2400mm×2800mm), and the tenth generation (2950mm×3400mm) can be used. Thus, a large display device can be manufactured. By enlarging the substrate, more display devices can be manufactured from one substrate, so the manufacturing cost can be reduced.

[0062] Furthermore, in order to improve the flexibility of the semiconductor device, a flexible substrate, a bonding film, a base film, or the like may be used as the substrate.

[0063] As materials for flexible substrates, bonding films, and base films, for example, the following materials can be used: polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyether sulfone (PES), polyamide (nylon, aromatic polyamide, etc.), polysiloxane, cycloolefin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofibers, etc.

[0064] By using the above material as a substrate, a lightweight semiconductor device can be provided. In addition, by using the above material as a substrate, a semiconductor device with high impact resistance can be provided. In addition, by using the above material as a substrate, a semiconductor device that is not easily damaged can be provided.

[0065] The lower the linear expansion coefficient of the flexible substrate used as the substrate, the more deformation due to the environment can be suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. In particular, aramid has a low linear expansion coefficient and is therefore suitable for use in flexible substrates.

[0066] [Conductive layer] As a conductive material that can be used for the gate electrode, source electrode and drain electrode of a transistor, various wirings and electrodes constituting a semiconductor device, etc., a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., an alloy containing the above metal elements as a component, or an alloy combining the above metal elements, etc. In addition, a semiconductor represented by polycrystalline silicon containing impurity elements such as phosphorus and a silicide such as nickel silicide can also be used. There is no particular limitation on the method for forming the conductive material, and various formation methods such as evaporation, CVD, sputtering, and spin coating can be used.

[0067] In addition, as a conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) can also be used. The layer formed using the Cu-X alloy can be processed by a wet etching process, thereby suppressing the manufacturing cost. In addition, as a conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0068] As the conductive material that can be used for the conductive layer, a conductive material containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used. In addition, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, etc. can also be used. In addition, the conductive layer can also adopt a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0069] For example, the conductive layer can adopt a single-layer structure of an aluminum layer containing silicon, a two-layer structure of a titanium layer stacked on an aluminum layer, a two-layer structure of a titanium layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure of a titanium layer, an aluminum layer and a titanium layer stacked in sequence, etc.

[0070] In addition, a plurality of conductive layers formed of the above conductive materials may be stacked. For example, the conductive layer may also adopt a laminated structure in which a material containing the above metal element and a conductive material containing oxygen are combined. In addition, a laminated structure in which a material containing the above metal element and a conductive material containing nitrogen are combined may be adopted. In addition, a laminated structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be adopted.

[0071] For example, the conductive layer may also have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen are sequentially stacked. In this case, it is preferred that the side of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, as the conductive layer, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked.

[0072] [Insulation layer] Each insulating layer may be a single layer or a stacked layer of a material selected from the following: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicate, etc. In addition, a material composed of multiple materials among a mixed oxide material, a nitride material, an oxynitride material, and an oxynitride material may also be used.

[0073] In this specification, etc., nitrogen oxide refers to a material containing more nitrogen than oxygen. In addition, oxynitride refers to a material containing more oxygen than nitrogen. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

[0074] For example, the insulating layer 102 and the insulating layer 117 are preferably formed using an insulating material that does not easily allow impurities to pass through. For example, a single layer or a stack of insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, as an example of an insulating material that does not easily allow impurities to pass through, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, etc. can be cited.

[0075] By using an insulating material that does not easily allow impurities to pass through as the insulating layer 102, diffusion of impurities from the substrate 101 can be suppressed, thereby improving the reliability of the semiconductor device. By using an insulating material that does not easily allow impurities to pass through as the insulating layer 117, diffusion of impurities from above the insulating layer 117 can be suppressed, thereby improving the reliability of the semiconductor device.

[0076] When an oxide semiconductor is used for the semiconductor layer 114, an insulating material through which impurities are less likely to pass is preferably used as the insulating layer 106. By using an insulating material through which impurities are less likely to pass as the insulating layer 106, diffusion of impurities from below the insulating layer 106 can be suppressed, thereby improving the reliability of the semiconductor device.

[0077] In addition, as the insulating layer, an insulating layer used as a planarization layer can also be used. As the insulating layer used as the planarization layer, an organic material with heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above-mentioned organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, multiple insulating layers formed of these materials can also be stacked.

[0078] In addition, siloxane resin is equivalent to a resin containing Si-O-Si bonds formed using a siloxane material as a starting material. Siloxane resin can also use an organic group (such as an alkyl group or an aryl group) or a fluoro group as a substituent. In addition, the organic group can also include a fluoro group.

[0079] In addition, the surface of the insulating layer etc. may be subjected to CMP treatment. By performing CMP treatment, the unevenness of the sample surface can be reduced, and the coverage of the insulating layer and the conductive layer to be formed later can be improved.

[0080] [Semiconductor layer] As the semiconductor layer 103 and the semiconductor layer 114, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. In addition, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can also be used. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

[0081] The band gap of an oxide semiconductor is greater than 2 eV, so the off-state current of a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor of one of the metal oxides in a semiconductor layer in which a channel is formed is extremely small. As a result, the power consumption of the semiconductor device 100A can be reduced. In addition, the OS transistor operates stably even in a high-temperature environment, and the characteristics vary less. For example, even in a high-temperature environment, the off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high-temperature environment, the on-state current is not easy to drop. Therefore, a semiconductor device using an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0082] On the other hand, it is difficult to realize a p-channel transistor using an OS transistor. When a CMOS circuit is constructed using an OS transistor, it is preferably combined with a p-channel transistor using another semiconductor material.

[0083] In this embodiment, a transistor using silicon in a semiconductor layer forming a channel (also referred to as a "Si transistor") is used as the transistor M1. In addition, by using a p-type semiconductor for the drain region 103a and the source region 103c of the semiconductor layer 103, the transistor M1 is used as a p-channel transistor.

[0084] Examples of silicon used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0085] A transistor using amorphous silicon as a semiconductor layer can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon as a semiconductor layer has high field effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon as a semiconductor layer has high field effect mobility compared to a transistor using amorphous silicon and can operate at high speed.

[0086] In this embodiment, an OS transistor is used as the transistor M2. Since the insulation withstand voltage between the source and the drain of the OS transistor is high, the channel length can be shortened. Therefore, the on-state current can be increased.

[0087] As metal oxides that can be used for the semiconductor layer of the OS transistor, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium and tin.

[0088] For example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide, etc. can be used.

[0089] In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium and tin. In particular, the element M is preferably gallium.

[0090] Here, the composition of the metal oxide used for the semiconductor layer has a great influence on the electrical characteristics and reliability of the OS transistor.

[0091] For example, by increasing the indium content of the metal oxide, a transistor with a large on-state current can be realized.

[0092] When In-Zn oxide is used as the semiconductor layer of the OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1 or a metal oxide in the vicinity thereof can be used.

[0093] When In-Sn oxide is used as the semiconductor layer of the OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1 or a metal oxide in the vicinity thereof can be used.

[0094] When In-Sn-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin can be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratios of the metal elements In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn =6:1:6、In:Sn:Zn=10:1:3、In:Sn:Zn=10:1:6、In:Sn:Zn=10:1:7、In:Sn:Zn=10:1:8、In :Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10 or metal oxides near them.

[0095] When In-Al-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum can be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of aluminum. For example, the atomic ratios of the metal elements In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1: 6. In: Al: Zn = 10: 1: 3, In: Al: Zn = 10: 1: 6, In: Al: Zn = 10: 1: 7. In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10 or metal oxides thereof.

[0096] When In-Ga-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer can use a metal element atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga: Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0097] When In-M-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the atomic ratio of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer can use a metal element atomic ratio of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=10:1: 3. In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereof.

[0098] Note that when a plurality of metal elements are included as the element M, the sum of the atomic ratios of the metal elements may be the atomic ratio of the element M. For example, when an In-Ga-Al-Zn oxide including gallium and aluminum is used as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum may be the atomic ratio of the element M. In addition, the atomic ratio of indium, the element M, and zinc is preferably within the above range.

[0099] It is preferable to use a metal oxide in which the ratio of the number of atoms of indium to the number of atoms of the metal element in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, more preferably 70 atomic % or more and 80 atomic % or less. For example, when In-Ga-Zn oxide is used as the semiconductor layer, the ratio of the number of atoms of indium to the total number of atoms of indium, element M and zinc is preferably within the above range.

[0100] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of a contained metal element may be described as the indium content. The same applies to other metal elements.

[0101] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be formed. By using this transistor, a circuit that can work at high speed can be manufactured. Furthermore, the area occupied by the circuit can be reduced. For example, when the transistor is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced when the number of wirings increases, thereby suppressing uneven display. In addition, since the area occupied by the circuit can be reduced, the frame of the display device can be reduced.

[0102] The composition of metal oxides can be analyzed, for example, using energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray spectroscopy), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, multiple of the above methods can be combined for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0103] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the atomic ratio of the target material is sometimes different from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes smaller than the atomic ratio of zinc in the target material. Specifically, the atomic ratio of zinc is sometimes about 40% or more and 90% or less of the atomic ratio of zinc in the target material.

[0104] Here, the reliability of the transistor is explained. As one of the indicators for evaluating the reliability of the transistor, there is a GBT (Gate Bias Temperature: gate bias) stress test in which an electric field is applied to the gate. Among them, the test of maintaining the gate at a high temperature while applying a positive potential (positive bias) relative to the source potential and the drain potential is called a PBTS (Positive Bias Temperature Stress) test, and the test of maintaining the gate at a high temperature while applying a negative potential (negative bias) is called an NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test performed under the state of irradiation with light are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0105] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state where current flows), so the variation in threshold voltage in the PBTS test is one of the important factors to be focused on as a reliability index of the transistor.

[0106] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability for forward bias application can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS test can be realized. In addition, when a metal oxide containing gallium is used, the gallium content is preferably lower than the indium content. Thus, a transistor with high reliability can be realized.

[0107] One of the reasons for the change in threshold voltage in the PBTS test is the defect state at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect state density, the more significant the degradation in the PBTS test. The generation of the defect state can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0108] The reason why the change in threshold voltage in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content as a semiconductor layer is, for example, as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage will change.

[0109] More specifically, when In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga is used for the semiconductor layer.

[0110] For example, the semiconductor layer of the OS transistor may use metal elements with atomic ratios of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In: Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0111] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is higher than 0 atomic % and is less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by including gallium in the metal oxide, it is less likely to generate oxygen vacancies (VO : Oxygen Vacancy) effect.

[0112] As the semiconductor layer of the OS transistor, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. At this time, when the atomic number ratio of indium relative to the atomic number of the metal element in the metal oxide is increased, the field effect mobility of the transistor can be improved. On the other hand, when the atomic number ratio of zinc relative to the atomic number of the metal element in the metal oxide is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as the semiconductor layer, a metal oxide such as indium oxide that does not contain gallium and zinc can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, especially.

[0113] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3, In:Zn=4:1 or a ratio close to this can be used.

[0114] Note that although gallium is used as an example for the description, the invention can also be applied to the case where element M is used instead of gallium. As the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M is preferably used. In addition, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is preferably used.

[0115] A transistor having high reliability in case of forward bias application can be realized by using a metal oxide having a low content of element M as a semiconductor layer. A semiconductor device having high reliability can be realized by using this transistor as a transistor that needs to have high reliability in case of forward bias application.

[0116] Next, the reliability of transistors with respect to light will be described.

[0117] When light enters a transistor, the electrical characteristics of the transistor may change. It is particularly preferred that the transistor used in an area where light may enter has small changes in electrical characteristics under light irradiation and high reliability to light. Reliability to light can be evaluated, for example, by the change in threshold voltage in an NBTIS test.

[0118] By increasing the content of the element M in the metal oxide used for the semiconductor layer, a transistor with high reliability to light can be realized. That is, a transistor with a small change in threshold voltage in the NBTIS test can be realized. Specifically, the band gap of the metal oxide in which the atomic number ratio of the element M is greater than the atomic number ratio of indium is larger, and the change in threshold voltage in the NBTIS test of the transistor can be reduced. The band gap of the metal oxide contained in the semiconductor layer is preferably greater than 2.0 eV, more preferably greater than 2.5 eV, more preferably greater than 3.0 eV, more preferably greater than 3.2 eV, more preferably greater than 3.3 eV, more preferably greater than 3.4 eV, and more preferably greater than 3.5 eV.

[0119] For example, the semiconductor layer can use a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4 or thereabouts.

[0120] The semiconductor layer can especially appropriately use the following metal oxide: the ratio of the number of atoms of element M relative to the number of atoms of the metal element contained is greater than 20 atomic % and less than 70 atomic %, preferably greater than 30 atomic % and less than 70 atomic %, more preferably greater than 30 atomic % and less than 60 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0121] When In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium to the atomic ratio of the metal element is less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4 or a metal oxide in the vicinity thereof can be used.

[0122] The semiconductor layer particularly preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is greater than 20 atomic % and less than 60 atomic %, preferably greater than 20 atomic % and less than 50 atomic %, more preferably greater than 30 atomic % and less than 50 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0123] A transistor with high reliability against light can be realized by using a metal oxide having a high content of the element M for the semiconductor layer. A semiconductor device with high reliability can be realized by using this transistor as a transistor that needs to have high reliability against light.

[0124] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a display device having both excellent electrical characteristics and high reliability can be realized.

[0125] The semiconductor layer may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form it, thereby reducing the manufacturing cost.

[0126] The compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto disposed on the first metal oxide layer may be appropriately used. In addition, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0127] As the semiconductor layer, a crystalline metal oxide layer is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc. can be used. By using a crystalline metal oxide layer for the semiconductor layer, the defect state density in the semiconductor layer can be reduced, thereby realizing a display device with high reliability.

[0128] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0129] When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. In addition, the higher the flow rate ratio of the oxygen gas relative to the entire deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) is, the more crystalline the metal oxide layer can be formed.

[0130] The semiconductor layer of the OS transistor may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure may have a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target to make the oxygen flow ratio different, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0131] The channel length L of the transistor M2 shown in this embodiment is determined by the thickness of the insulating layer provided between the conductive layer 113 and the conductive layer 108a. Therefore, a transistor with a small channel length can be manufactured with high precision. In addition, the non-uniformity of characteristics among the plurality of transistors M2 is also reduced. Therefore, the operation of the semiconductor device using the transistor M2 is very stable and the reliability can be improved. In addition, when the non-uniformity of characteristics is reduced, the circuit design freedom of the semiconductor device is improved, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can also be reduced.

[0132] When an oxide semiconductor is used for the semiconductor layer 114, a material containing hydrogen is preferably used as the insulating layer 109 and the insulating layer 111. When an insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor is converted to an n-type and can be used as a source region or a drain region. For example, silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.

[0133] In addition, when an oxide semiconductor is used for the semiconductor layer 114, the conductive layer 108 in contact with the semiconductor layer 114 and the conductive layer 113 in contact with the semiconductor layer 114 preferably use a conductive material that converts the oxide semiconductor into an n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. In addition, other conductive materials may be provided in a manner overlapping with the conductive material containing nitrogen.

[0134] On the other hand, it is preferable to use a material that reduces hydrogen and contains oxygen for the insulating layer 110. For example, silicon oxide (SiOx) or the like may be used. Hydrogen is an impurity element in an oxide semiconductor, so when the semiconductor layer 114 of an oxide semiconductor contacts the insulating layer 110 that reduces hydrogen, it is not easy to cause n-type conversion. In addition, when the semiconductor layer 114 of an oxide semiconductor contacts the insulating layer 110 that contains oxygen, oxygen vacancies in the semiconductor layer 114 are reduced, and the characteristics of the transistor M2 become stable, thereby improving reliability.

[0135] In addition, when an oxide semiconductor is used for the semiconductor layer 114, the insulating layer 110 preferably contains excess oxygen. In this specification, etc., oxygen released by heating is sometimes referred to as excess oxygen. In addition, when a material containing excess oxygen is used for the insulating layer 110, a material that does not easily allow oxygen to pass through is preferably used as the insulating layer 109 and the insulating layer 111. As a material that does not easily allow oxygen to pass through, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material that does not easily allow oxygen to pass through as the insulating layer 109 and the insulating layer 111, excess oxygen in the insulating layer 110 does not easily detach to the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor.

[0136] When an oxide semiconductor is used as the semiconductor layer 114, the thickness t of the insulating layer 110 corresponds to the channel length L of the transistor M2 (see Figure 3A ). In addition, the semiconductor layer 114 is disposed in the opening 112, so the perimeter p of the opening 112 is equivalent to the channel width W of the transistor M2 (refer to Figure 3B ). More specifically, the perimeter p at a position where the thickness t of the insulating layer 110 is half (t / 2) corresponds to the channel width W of the transistor M2. Note that the perimeter p at any position of the opening 112 may be used as the channel width W as required. For example, the perimeter p at the bottom of the opening 112 may be used as the channel width W, and the perimeter p at the top of the opening 112 may be used as the channel width W.

[0137] In addition, materials containing no hydrogen or very little hydrogen may be used as the insulating layer 109 and the insulating layer 111. For example, silicon nitride containing very little hydrogen or silicon nitride oxide containing very little hydrogen may be used. In this case, the region where the semiconductor layer 114 contacts the insulating layer 109 and the region where the semiconductor layer 114 contacts the insulating layer 111 are not converted to n-type. Therefore, the thickness ts obtained by adding the thicknesses of the insulating layer 109, the insulating layer 110, and the insulating layer 111 corresponds to the channel length L of the transistor M2 (see Figure 3C ). In addition, the perimeter p at the position of half the thickness ts (ts / 2) corresponds to the channel width W of the transistor M2.

[0138] In this way, by using materials with different compositions for the semiconductor layers of transistors M1 and M2, a CMOS circuit with a reduced occupied area can be realized. In other words, a semiconductor device with a reduced occupied area can be realized. In addition, a CMOS circuit with reduced power consumption can be realized. In other words, a semiconductor device with reduced power consumption can be realized. In addition, a CMOS circuit with small characteristic variations and high reliability can be realized. In other words, a semiconductor device with small characteristic variations and high reliability can be realized.

[0139] In addition, the semiconductor device 100A shown in FIG. 1 is used as a CMOS type inverter circuit (also referred to as an “inverter circuit” or a “NOT circuit”), in which the conductive layer 113 is supplied with a potential L (VSS) and the conductive layer 108 b is supplied with a potential H (VDD) to use the conductive layer 116 as an input terminal (IN) and the conductive layer 108 a as an output terminal (OUT) (see Figure 1C ). In the inverter circuit, when a potential H is input to the input terminal, a potential L is output from the output terminal, and when a potential L is input to the input terminal, a potential H is output from the output terminal. Figure 1D 1 is a timing chart showing an operation example of the semiconductor device 100A used as an inverter circuit. Figure 1E Shows the circuit symbol for an inverter circuit.

[0140] <Deformation Example 1> A semiconductor device 100B which is a modified example of the semiconductor device 100A will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100B and the semiconductor device 100A will be mainly described. Figure 4A It is a top view of the semiconductor device 100B. Figure 4B It is along Figure 4A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 4C is an equivalent circuit diagram of the semiconductor device 100B.

[0141] An n-channel transistor may be used as the transistor M1. The n-channel transistor M1 can be realized by using an n-type semiconductor for the drain region 103a and the source region 103c of the semiconductor layer 103. In the semiconductor device 100B, an n-channel transistor is used as the transistor M1.

[0142] Furthermore, an LDD (Lightly Doped Drain) region may be provided between the drain region 103a and the channel formation region 103b of the semiconductor layer 103. By providing the LDD region, the electric field between the gate and the drain can be relaxed, and the characteristic degradation of the transistor M1 can be reduced.

[0143] Note that in a transistor in which the source and the drain are interchanged in circuit operation, an LDD region may be provided not only between the drain region 103a and the channel formation region 103b but also between the source region 103c and the channel formation region 103b.

[0144] In addition, FIG. 4A to FIG. 4C In the semiconductor device 100B shown in the figure, an example is shown in which the gate electrodes of the transistor M1 and the transistor M2 are not electrically connected to each other, but the gate electrodes may be electrically connected to each other. Figure 4D An equivalent circuit diagram of a semiconductor device 100B in which gate electrodes of a transistor M1 and a transistor M2 are electrically connected to each other is shown.

[0145] When the gate electrodes of transistor M1 and transistor M2 are electrically connected to each other, transistor M1 and transistor M2 can be substantially used as one transistor. By adopting such a structure, the insulation withstand voltage between the source and the drain can be improved. In addition, the off-state current can be reduced.

[0146] <Deformation Example 2> A semiconductor device 100C that is a modified example of the semiconductor device 100A and the semiconductor device 100B will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100C and the semiconductor device 100A and the semiconductor device 100B will be mainly described. Figure 5A is a top view of the semiconductor device 100C. Figure 5B It is along Figure 5A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 5C and Figure 5D is an equivalent circuit diagram of the semiconductor device 100C.

[0147] The semiconductor device 100C is different from the semiconductor device 100A and the semiconductor device 100B in that it includes a conductive layer 119 between the substrate 101 and the insulating layer 102. The conductive layer 119 is used as a back gate electrode of the transistor M1. Therefore, the conductive layer 119 preferably overlaps with the channel formation region 103b and extends beyond the end of the channel formation region 103b. In other words, the conductive layer 119 is preferably larger than the channel formation region 103b. In addition, the conductive layer 119 preferably extends beyond the end of the semiconductor layer 103. In other words, the conductive layer 119 is preferably larger than the semiconductor layer 103.

[0148] The back gate electrode is configured to sandwich the channel formation region of the semiconductor layer with the gate electrode. In addition, by changing the potential of the back gate electrode, the threshold voltage of the transistor can be changed. The potential of the back gate electrode can be the ground potential or an arbitrary potential.

[0149] The back gate electrode is formed using a conductive layer and can play the same role as the gate electrode. For example, the potential of the back gate electrode can be made the same as the potential of the gate electrode. Figure 5D FIG. 1 shows an equivalent circuit diagram when the back gate electrode and the gate electrode included in the transistor M1 are electrically connected. Figure 5C and Figure 5D In the equivalent circuit diagram shown, the transistor M1 is a p-channel transistor, but the transistor M1 may also be an n-channel transistor.

[0150] The back gate electrode can be formed using the same material and method as the gate electrode, source electrode, drain electrode, etc. In addition, since the gate electrode and the back gate electrode are conductive layers, they have the function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity). That is, it is possible to prevent the electrical characteristics of the transistor from changing due to the influence of external electric fields such as static electricity. In addition, by providing a back gate electrode, the change in the threshold voltage of the transistor before and after the BT (Bias Temperature) stress test can be reduced. By providing a back gate electrode, the unevenness of the characteristics of the transistor is reduced, and the reliability of the semiconductor device can be improved.

[0151] <Deformation Example 3> A semiconductor device 100D which is a modified example of the semiconductor device 100A will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100D and the semiconductor device 100A will be mainly described. The semiconductor device 100D can also be said to be a modified example of the semiconductor device 100B and the semiconductor device 100C. Fig. 6A It is a top view of the semiconductor device 100D. Figure 6B It is along Fig. 6A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 6C and Fig.6D is an equivalent circuit diagram of the semiconductor device 100D.

[0152] The semiconductor device 100D is different from the semiconductor device 100A in that the opening 112 is provided so as to overlap with the conductive layer 105 serving as the gate electrode of the transistor M1. Therefore, in the semiconductor device 100D, the transistor M2 is provided so as to overlap on the gate electrode of the transistor M1. In the semiconductor device 100D, a portion of each of the conductive layer 113, the insulating layer 111, the insulating layer 110, the insulating layer 109, and the insulating layer 106 is selectively removed in a region overlapping with the conductive layer 105 to form the opening 112.

[0153] exist Fig. 6A and Figure 6BIn the embodiment, the opening 112 is provided so as to overlap the channel formation region 103b, but the present invention is not limited thereto. The opening 112 may be provided so as not to overlap the channel formation region 103b but to overlap the conductive layer 105. In the semiconductor device 100D, the conductive layer 105 is used as a gate electrode of the transistor M1 and as a drain electrode of the transistor M2.

[0154] By overlapping the transistor M1 and the transistor M2 , a semiconductor device with a further reduced occupied area can be realized.

[0155] Note that Figure 6C In the equivalent circuit diagram shown in FIG. 1 , transistor M1 is a p-channel transistor, but Fig.6D As shown in the equivalent circuit diagram of , the transistor M1 can also be an n-channel transistor.

[0156] <Deformation Example 4> A semiconductor device 100E which is a modified example of the semiconductor device 100D will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100E and the semiconductor device 100D will be mainly described. Fig. 7A It is a top view of the semiconductor device 100E. Figure 7B It is along Fig. 7A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 7C and Fig.7D is an equivalent circuit diagram of the semiconductor device 100E.

[0157] The semiconductor device 100E is different from the semiconductor device 100D in that, like the semiconductor device 100C, it includes a conductive layer 119 between the substrate 101 and the insulating layer 102. As described in the above-mentioned modification example 2, the conductive layer 119 is used as the back gate electrode of the transistor M1. By providing the back gate electrode, the characteristics of the transistor are reduced, and the reliability of the semiconductor device can be improved.

[0158] Note that Figure 7C In the equivalent circuit diagram shown in FIG. 1 , transistor M1 is a p-channel transistor, but Fig.7D As shown in the equivalent circuit diagram of , transistor M1 can also be an n-channel transistor. Figure 7C and Fig.7D In the embodiment, the back gate electrode and the gate electrode of the transistor M1 are electrically connected. However, an arbitrary potential may be supplied to the back gate electrode without electrically connecting the back gate electrode and the gate electrode.

[0159] <Deformation Example 5> A semiconductor device 100F which is a modified example of the semiconductor device 100D will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100F and the semiconductor device 100D will be mainly described. Fig. 8A It is a top view of the semiconductor device 100F. Figure 8B It is along Fig. 8A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Figure 8C and Fig.8D : is an equivalent circuit diagram of the semiconductor device 100F.

[0160] The semiconductor device 100F is different from the semiconductor device 100D in the structures of the openings 107 (openings 107 a and 107 b ) and the conductive layers 108 (conductive layers 108 a and 108 b ).

[0161] In the semiconductor device 100F, a portion of each of the insulating layer 111, the insulating layer 110, the insulating layer 109, the insulating layer 106, and the insulating layer 104 is selectively removed in a region overlapping the drain region 103a of the semiconductor layer 103 to form an opening 107a. In addition, in the semiconductor device 100F, a portion of each of the insulating layer 111, the insulating layer 110, the insulating layer 109, the insulating layer 106, and the insulating layer 104 is selectively removed in a region overlapping the source region 103c of the semiconductor layer 103 to form an opening 107b.

[0162] In semiconductor device 100F, conductive layer 108a is provided on insulating layer 111 and electrically connected to drain region 103a at the bottom of opening 107a. In semiconductor device 100F, conductive layer 108b is provided on insulating layer 111 and electrically connected to source region 103c at the bottom of opening 107b.

[0163] In the semiconductor device 100F, the conductive layer 108 and the conductive layer 113 can be formed simultaneously using the same material and the same manufacturing process. Since the conductive layer 108 and the conductive layer 113 do not need to be formed separately, the manufacturing process of the semiconductor device can be shortened, thereby improving the productivity of the semiconductor device.

[0164] Note that Figure 8C In the equivalent circuit diagram shown in FIG. 1 , transistor M1 is a p-channel transistor, but Fig.8D As shown in the equivalent circuit diagram of , the transistor M1 can also be an n-channel transistor.

[0165] <Deformation Example 6> A semiconductor device 100G which is a modified example of the semiconductor device 100F will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100G and the semiconductor device 100F will be mainly described. Fig.9A It is a top view of the semiconductor device 100G. Fig. 9B It is along Fig.9A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 9C and Fig.9D : is an equivalent circuit diagram of the semiconductor device 100G.

[0166] The semiconductor device 100G is different from the semiconductor device 100F in that the insulating layer 106 is not included. The formation of the insulating layer 106 can be omitted by using an insulating material that does not easily allow impurities to pass through as the insulating layer 109. When the insulating layer 106 is not provided, the number of layers to be removed when forming openings (openings 107a, 107b, and openings 112, etc.) is reduced, so the manufacturing process of the semiconductor device can be shortened to improve the productivity of the semiconductor device.

[0167] <Deformation Example 7> A semiconductor device 100H which is a modified example of the semiconductor device 100A will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100H and the semiconductor device 100A will be mainly described. Fig. 10A It is a top view of the semiconductor device 100H. Fig. 10B It is along Fig. 10A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 10C and Fig. 10D is an equivalent circuit diagram of the semiconductor device 100H.

[0168] The semiconductor device 100H is different from the semiconductor device 100A in that the transistor M2 is provided in a manner overlapping the drain region 103a. In the semiconductor device 100H, the opening 112 and the drain region 103a are provided overlappingly. Therefore, the semiconductor device 100H has a region where the transistor M1 and the transistor M2 overlap with each other. Specifically, there is a region where the semiconductor layer 114 overlaps with the semiconductor layer 103. More specifically, there is a region where the drain region 103a, which is a part of the semiconductor layer 103, overlaps with the semiconductor layer 114 via the conductive layer 108a.

[0169] By overlapping the transistor M1 and the transistor M2 , a semiconductor device with a further reduced occupied area can be realized.

[0170] In addition, as in the semiconductor device 100C shown in FIG5 , a conductive layer 119 serving as a back gate electrode may be provided between the substrate 101 and the insulating layer 102. Fig. 10C In the example, transistor M1 is a p-channel transistor, but Fig. 10D As shown, the transistor M1 may also be an n-channel transistor.

[0171] <Deformation Example 8> A semiconductor device 100I which is a modified example of the semiconductor device 100H will be described. Note that in order to avoid duplication of description, differences between the semiconductor device 100I and the semiconductor device 100H will be mainly described. Fig.11A It is a top view of the semiconductor device 100I. Fig. 11B It is along Fig.11A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 11C and Fig.11D is an equivalent circuit diagram of the semiconductor device 100I.

[0172] The semiconductor device 100I is different from the semiconductor device 100H in that the conductive layer 108a is not included. It can also be said that the opening 112 in the semiconductor device 100I also serves as the opening 107a. The semiconductor device 100I has a region where the semiconductor layer 114 overlaps with the semiconductor layer 103. In addition, in the semiconductor device 100I, the semiconductor layer 114 is directly connected to the semiconductor layer 103 at the bottom of the opening 112.

[0173] In the semiconductor device 100I, the opening 107b is provided so as to penetrate a portion of each of the insulating layer 104, the insulating layer 106, the insulating layer 109, the insulating layer 110, and the insulating layer 111. In the semiconductor device 100I, the conductive layer 108b is provided in the opening 107b and on the insulating layer 111.

[0174] In the region overlapping the source region 103c, the insulating layer 104, the insulating layer 106, the insulating layer 109, the insulating layer 110, and the insulating layer 111 are selectively removed to form an opening 107b. In addition, the conductive layer 108b provided on the insulating layer 111 is electrically connected to the source region 103c of the semiconductor layer 103 at the bottom of the opening 107b.

[0175] When the conductive layer 108a is not provided, a semiconductor device with a further reduced occupied area can be realized. Fig. 11B In the semiconductor device 100I shown, the semiconductor layer 103 and the semiconductor layer 114 are in contact at the bottom of the opening 112, so the semiconductor layer 103 and the semiconductor layer 114 preferably contain a common element. When the semiconductor layer 103 and the semiconductor layer 114 contain a common element, the contact resistance can be reduced. For example, an oxide semiconductor can be used for both the semiconductor layer 103 and the semiconductor layer 114.

[0176] exist Fig. 11C In the example, transistor M1 is a p-channel transistor, but Fig.11D As shown, the transistor M1 may also be an n-channel transistor.

[0177] <Deformation Example 9> A semiconductor device 100J which is a modified example of the semiconductor device 100I will be described. Note that in order to avoid duplication of description, the semiconductor device 100J will be mainly described in terms of differences from the semiconductor device 100I. Fig. 12Ais a top view of the semiconductor device 100J. Fig. 12B It is along Fig. 12A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 12C and Fig.12D is an equivalent circuit diagram of the semiconductor device 100J.

[0178] The semiconductor device 100J is different from the semiconductor device 100I in that the insulating layer 106 is not included. The formation of the insulating layer 106 can be omitted by using an insulating material that does not easily allow impurities to pass through as the insulating layer 109. When the insulating layer 106 is not provided, the number of layers to be removed when forming openings (opening 107b and opening 112, etc.) is reduced, so the manufacturing process of the semiconductor device can be shortened to improve the productivity of the semiconductor device.

[0179] <Modification Example 10> Next, a semiconductor device 100K will be described. The semiconductor device 100K is also a modified example of the semiconductor device 100A, the semiconductor device 100F, etc. Note that, in order to avoid duplication of description, the differences between the semiconductor device 100K and the semiconductor device 100A, the semiconductor device 100F, etc. will be mainly described. Fig.13A It is a top view of the semiconductor device 100K. Fig. 13B It is along Fig.13A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 13C and Fig.13D is an equivalent circuit diagram of the semiconductor device 100K.

[0180] The semiconductor device 100K includes a conductive layer 118 on the insulating layer 104. In addition, the transistor M2 is formed in a region different from the region where the transistor M1 is formed on the substrate 101. The transistor M2 includes at least a portion of the conductive layer 118. When the conductive layer 113 is used as a source electrode of the transistor M2, the conductive layer 118 is used as a drain electrode. In addition, when the conductive layer 113 is used as a drain electrode of the transistor M2, the conductive layer 118 is used as a source electrode.

[0181] The conductive layer 118 can be formed simultaneously with the conductive layer 105 using the same material and the same manufacturing process. In addition, in the semiconductor device 100K, the conductive layer 113, the insulating layer 111, the insulating layer 110, the insulating layer 109, and the insulating layer 106 each have an opening 112 in a portion thereof. In addition, in the semiconductor device 100K, the insulating layer 115, the insulating layer 111, the insulating layer 110, the insulating layer 109, the insulating layer 106, and the insulating layer 104 each have an opening 107a in a portion thereof, and have an opening 107b in another portion thereof.

[0182] In addition, a portion of the conductive layer 116 disposed on the insulating layer 115 covers the opening 107a and is electrically connected to the drain region 103a at the bottom of the opening 107a. In addition, the conductive layer 108b and the conductive layer 116 of the semiconductor device 100K can be formed simultaneously using the same material and the same manufacturing process. The conductive layer 108b is electrically connected to the source region 103c at the bottom of the opening 107b.

[0183] In the semiconductor device 100K, part of the conductive layer 116 is used as the conductive layer 108a of the semiconductor device 100A, etc. Therefore, the conductive layer 116 in the semiconductor device 100K is used not only as the gate electrode of the transistor M2 but also as the drain electrode.

[0184] In addition, as in the semiconductor device 100C shown in FIG5 , a conductive layer 119 serving as a back gate electrode may be provided between the substrate 101 and the insulating layer 102. Fig. 13C In the example, transistor M1 is a p-channel transistor, but Fig.13D As shown, the transistor M1 may also be an n-channel transistor.

[0185] <Variation Example 11> A semiconductor device 100L which is a modified example of the semiconductor device 100K will be described. Note that in order to avoid duplication of description, the differences between the semiconductor device 100L and the semiconductor device 100K will be mainly described. Fig.14A It is a top view of the semiconductor device 100L. Fig. 14B It is along Fig.14A A schematic cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 14C and Fig.14D : is an equivalent circuit diagram of the semiconductor device 100L.

[0186] The semiconductor device 100L is different from the semiconductor device 100K in that the insulating layer 106 is not included. The formation of the insulating layer 106 can be omitted by using an insulating material that does not easily allow impurities to pass through as the insulating layer 109. When the insulating layer 106 is not provided, the number of layers to be removed when forming openings (opening 107b and opening 112, etc.) is reduced, so the manufacturing process of the semiconductor device can be shortened to improve the productivity of the semiconductor device.

[0187] <<Manufacturing method>> Next, an example of a method for manufacturing the semiconductor device 100A will be described. First, constituent materials of each layer and a method for forming each layer will be described.

[0188] [Method for forming each layer] Insulating layers, semiconductor layers, conductive layers for forming electrodes or wiring, etc. can be formed by sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, vacuum evaporation method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, atomic layer deposition (ALD: Atomic Layer Deposition) method, etc. CVD method can also be plasma enhanced chemical vapor deposition (PECVD) method or thermal CVD method, etc. In addition, as an example of thermal CVD method, organic metal chemical vapor deposition (MOCVD: Metal Organic CVD) method can be cited.

[0189] In addition, the insulating layer, semiconductor layer and conductive layer that constitute the semiconductor device can also be formed by spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, slit coating, roller coating, curtain coating, doctor blade coating and the like.

[0190] By utilizing the PECVD method, a high-quality film can be obtained at a lower temperature. When a deposition method that does not use plasma is used, such as the MOCVD method, the ALD method, or the thermal CVD method, it is not easy to cause damage to the formed surface. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the case of a deposition method that does not use plasma, the yield of the semiconductor device can be improved. In addition, since no plasma damage occurs during deposition, a film with fewer defects can be obtained.

[0191] Unlike a deposition method in which particles released from a target material or the like are deposited, the CVD method and the ALD method are deposition methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0192] The CVD method and the ALD method can control the composition of the obtained film according to the flow ratio of the source gases. For example, when the CVD method and the ALD method are used, a film of any composition can be deposited according to the flow ratio of the source gases. In addition, for example, when the CVD method and the ALD method are used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gases while performing deposition. When deposition is performed while changing the flow ratio of the source gases, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0193] When processing the layer (thin film) constituting the semiconductor device, photolithography or the like can be used. In addition, an island-shaped layer can be formed by a deposition method using a shadow mask. In addition, the layer can be processed by a nanoimprint method, a sandblasting method, a stripping method, etc. In the photolithography method, there are the following methods: forming a resist mask on the layer (thin film) to be processed, selectively removing a part of the layer (thin film) by using the resist mask as a mask, and then removing the resist mask; after depositing a photosensitive layer, exposing and developing the layer to process it into a desired shape.

[0194] In the case of using light in the photolithography method, as the light for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as the light for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used. In addition, instead of the light for exposure, an electron beam can also be used. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0195] As the removal (etching) of the layer (thin film), dry etching, wet etching, sand blasting, etc. can be used. In addition, these etching methods can also be used in combination.

[0196] Next, an example of a method for manufacturing the semiconductor device 100A is described. First, an insulating layer 102 is provided on a substrate 101, and a semiconductor layer 103A is provided on the insulating layer 102 (see Fig.15A ).

[0197] For example, an insulating substrate having an insulating surface is used as the substrate 101. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate.

[0198] In addition, a semiconductor substrate or a conductive substrate may be used as the substrate 101 as required. As a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide, etc. may be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate may be cited, such as an SOI (Silicon On Insulator) substrate. As a conductive substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. may be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. may be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductive substrate provided with a semiconductor or an insulator, etc. may be cited. Alternatively, a substrate having elements provided on these substrates may be used. As elements provided on the substrate, capacitors, resistors, switching elements, light-emitting elements, storage elements, etc. may be cited.

[0199] Silicon oxide is formed as the insulating layer 102 over the substrate 101. Examples of the insulating layer that can be used for the semiconductor device 100A include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, metal oxynitrides, and the like that have insulating properties.

[0200] For example, when miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulating layer. By using a high-k material as an insulating layer used as a gate insulating layer, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulating layer used as an interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer.

[0201] As insulating layers with a relatively high dielectric constant, there are gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0202] As the insulating layer with a relatively low dielectric constant, there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin.

[0203] Note that in this specification, etc., nitrogen oxides refer to compounds containing more nitrogen than oxygen. Also, oxynitrides refer to compounds containing more oxygen than nitrogen. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

[0204] In addition, amorphous silicon is formed as the semiconductor layer 103A. As the semiconductor layer 103A, although it varies depending on the hydrogen content, it is preferably heated at 400°C to 550°C for several hours to perform dehydrogenation treatment, adjust the hydrogen content to less than 5 atomic %, and perform the subsequent crystallization process. In addition, the amorphous semiconductor film can also be formed by other manufacturing methods such as sputtering or vacuum evaporation, and it is preferred to fully reduce impurity elements such as oxygen and nitrogen in the film.

[0205] Note that the semiconductor used for the semiconductor layer 103A is not limited to silicon, and for example, silicon germanium can be used. When silicon germanium is used, the germanium concentration is preferably about 0.01 atomic % to 4.5 atomic %.

[0206] The insulating layer 102 and the semiconductor layer 103A may be formed continuously without being exposed to the atmosphere. By continuously depositing without being exposed to the atmosphere, surface contamination due to exposure to the atmosphere can be minimized, and variations in characteristics of the manufactured transistor can be reduced.

[0207] Next, the semiconductor layer 103A is crystallized to form a crystalline semiconductor layer 103B (see Fig. 15B ). As a method for improving the crystallinity of the semiconductor layer 103A (also referred to as "crystallization"), a laser annealing method, a thermal annealing method (solid phase growth method) or a rapid thermal annealing method (RTA method) can be used. When a glass substrate or a plastic substrate with low heat resistance is used as the substrate 101, it is particularly preferred to use a laser annealing method. As a laser, for example, an excimer laser using XeCl, a second harmonic or third harmonic of a YAG laser, etc. can be used. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, etc. are used as a light source. Alternatively, for example, a semiconductor layer 103B having crystallinity can be formed by a crystallization method using a catalyst element according to the technology disclosed in Japanese Patent Application Publication No. 7-130652.

[0208] The semiconductor layer 103A may be crystallized by combining the above methods. For example, after the semiconductor layer 103A is crystallized by a solid phase growth method, laser irradiation may be performed to form a semiconductor layer 103B having few defects and high crystallinity.

[0209] In particular, when laser annealing is used, it is preferred to release hydrogen in the amorphous semiconductor layer first. Heat treatment is performed at 400° C. to 550° C. for about 1 hour to adjust the hydrogen content to 5 atomic % or less, and then crystallization is performed, thereby preventing the roughness of the film surface. In this embodiment, laser annealing is used to crystallize the semiconductor layer 103A. Specifically, the semiconductor layer 103A having a hydrogen content of 5 atomic % or less is irradiated with laser 151 to form the semiconductor layer 103B.

[0210] Note that when an oxide semiconductor is used as the semiconductor layer 103A, the above-mentioned treatment for improving crystallinity does not necessarily have to be performed.

[0211] In addition, an impurity element that changes the semiconductor layer 103A into a p-type semiconductor (also referred to as a "p-type impurity element") or an impurity element that changes the semiconductor layer 103A into an n-type semiconductor (also referred to as an "n-type impurity element") may be added at a low concentration before crystallization of the semiconductor layer 103A (also referred to as "channel doping"). Channel doping may be performed on the entire semiconductor layer 103A or selectively on a portion of the semiconductor layer 103A.

[0212] As the p-type impurity element, for example, one or more selected from Group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) can be used. As the n-type impurity element, one or more selected from Group 15 elements such as phosphorus (P) or arsenic (As) can be used.

[0213] By channel doping the semiconductor layer, the threshold voltage of the transistor including the semiconductor layer can be controlled. 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 Adding boron to a semiconductor layer at a concentration below the above range can change the threshold voltage of a transistor including the semiconductor layer in a positive direction.

[0214] By performing channel doping, an enhancement-type (normally off) transistor and a depletion-type (normally on) transistor can be formed respectively.

[0215] Next, a resist mask (not shown) is formed on the semiconductor layer 103B by photolithography. The resist mask is used as a mask to selectively remove the semiconductor layer 103B to form the semiconductor layer 103 (see FIG. Fig. 15C ).

[0216] Next, an insulating layer 104 is formed over the insulating layer 102 and the semiconductor layer 103. The insulating layer 104 can be formed using the same material and method as those of the insulating layer 102 (see Fig.15D ).

[0217] When an oxide semiconductor is used as the semiconductor layer 103, microwave treatment is preferably performed in an oxygen-containing atmosphere after forming the insulating layer 104. Here, microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0218] Microwave treatment, for example, preferably uses a microwave processing device that includes a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is set to be greater than 300 MHz and less than 300 GHz, preferably greater than 2.4 GHz and less than 2.5 GHz, for example, 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is greater than 1000 W and less than 10000 W, preferably greater than 2000 W and less than 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide semiconductor.

[0219] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is 10Pa or more and 1000Pa or less, preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is 750°C or less, preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment in a manner not exposed to the atmosphere after microwave treatment in an oxygen-containing atmosphere. For example, the treatment temperature is 100°C or more and 750°C or less, preferably 300°C or more and 500°C or less.

[0220] In addition, for example, the above-mentioned microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) can be greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. By performing microwave treatment in an oxygen-containing atmosphere, hydrogen and oxygen vacancies in the oxide semiconductor are reduced. Therefore, the carrier concentration in the oxide semiconductor can be reduced.

[0221] Next, a conductive layer 105A is formed on the insulating layer 104 (see Fig.15EAs the conductive layer 105A, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are preferably used.

[0222] As the conductive layer 105A, a plurality of conductive layers formed of the above-mentioned materials may be stacked and used. For example, a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a stacked structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0223] Next, a resist mask (not shown) is formed on the conductive layer 105A by photolithography. The resist mask is used as a mask to selectively remove the conductive layer 105A to form the conductive layer 105 (see FIG. Fig.16A ).

[0224] Next, in order to form a drain region 103a, a channel formation region 103b, and a source region 103c in the semiconductor layer 103, an impurity element is introduced into the semiconductor layer 103. Specifically, the impurity element (dopant 128) is introduced into the semiconductor layer 103 using the conductive layer 105 as a mask (see Fig. 16B ) The dopant 128 can be introduced by a method such as ion implantation or plasma doping.

[0225] Note that when an oxide semiconductor is used as the semiconductor layer 103 , a rare gas element, carbon, nitrogen, or the like can be used as the dopant 128 .

[0226] The dopant 128 is not introduced into the region of the semiconductor layer 103 overlapping with the conductive layer 105. In addition, the dopant 128 is introduced into the region of the semiconductor layer 103 not overlapping with the conductive layer 105. In the semiconductor layer 103, the region overlapping with the conductive layer 105 and not introduced with the dopant 128 is used as the channel formation region 103b. In addition, in the semiconductor layer 103, the region introduced with the dopant 128 is used as the drain region 103a or the source region 103c.

[0227] The channel formation region 103b is formed in a self-aligned manner by using the conductive layer 105 as a mask. The concentration profile of the dopant 128 in the depth direction and the concentration of the metal element can be determined by a processing method and processing conditions.

[0228] In this embodiment, since silicon is used as the semiconductor layer 103, boron (B), which is one of the elements of Group 13, is used as the dopant 128 for converting the transistor M1 into a p-channel transistor. A Group 15 element (for example, phosphorus (P)) may be used as the dopant 128 for converting the transistor M1 into an n-channel transistor.

[0229] After the introduction of the impurity element into the semiconductor layer 103 is completed, heat treatment is performed. The introduced impurity element is activated by the heat treatment, and a portion of the semiconductor layer 103 that has become amorphous due to the introduction of the impurity element is recrystallized. In this specification, etc., this heat treatment is also referred to as activation treatment.

[0230] After the activation treatment, hydrogenation treatment is performed. Hydrogenation treatment is a treatment in which hydrogen excited by heat treatment or plasma treatment is added to the semiconductor layer 103. When heat treatment is used, the heat treatment step is performed at 300° C. to 450° C. for 2 to 6 hours in an atmosphere containing 3% to 100% hydrogen.

[0231] Note that when an oxide semiconductor is used as the semiconductor layer 103, activation treatment and hydrogenation treatment do not necessarily have to be performed.

[0232] Next, an insulating layer 106 is formed on the insulating layer 104 and the conductive layer 105 (see Fig. 16C Since the insulating layer 106 is used as an interlayer insulating layer, a material having a low relative dielectric constant may be used.

[0233] When an oxide semiconductor is used for the semiconductor layer 114 to be formed later, an insulating material that does not easily transmit impurities is preferably used as the insulating layer 106. By using an insulating material that does not easily transmit impurities as the insulating layer 106, diffusion of impurities from below the insulating layer 106 can be suppressed, thereby improving the reliability of the semiconductor device. For example, hydrogen contained on the transistor M1 side can be prevented from diffusing to the transistor M2 side.

[0234] Next, a resist mask (not shown) is formed on the insulating layer 106 by photolithography. Using the resist mask as a mask, a portion of each of the insulating layer 106 and the insulating layer 104 is selectively removed to form an opening 107a overlapping the drain region 103a and an opening 107b overlapping the source region 103c (see FIG. Fig.16D ). A portion of the drain region 103a is exposed at the bottom of the opening 107a, and a portion of the source region 103c is exposed at the bottom of the opening 107b. In addition, the side surfaces of the insulating layer 106 and the side surfaces of the insulating layer 104 are exposed in the openings 107a and 107b.

[0235] Next, a conductive layer 108A is formed on the insulating layer 106. The conductive layer 108A may be formed using the same material and method as the conductive layer 105A (see Fig.17A ).

[0236] Next, a resist mask (not shown) is formed on the conductive layer 108A by photolithography. The resist mask is used as a mask to selectively remove the conductive layer 108A to form the conductive layer 108 (the conductive layer 108a and the conductive layer 108b) (see FIG. Fig. 17B ). The conductive layer 108a is electrically connected to the drain region 103a in the opening 107a, and the conductive layer 108b is electrically connected to the source region 103c in the opening 107b. Thus, the transistor M1 can be formed.

[0237] Next, an insulating layer 109, an insulating layer 110, an insulating layer 111, and a conductive layer 113A are sequentially formed on the insulating layer 106 and the conductive layer 108 (see Fig. 17C ). The insulating layer 109 and the insulating layer 111 are formed using an insulating material containing hydrogen. For example, silicon nitride containing hydrogen is used.

[0238] The insulating layer 110 is formed using an insulating material that reduces hydrogen. For example, silicon oxide or silicon oxynitride may be used. In addition, the insulating layer 110 preferably contains excess oxygen.

[0239] The conductive layer 113A may be formed using the same material and method as those of the conductive layer 105A or the conductive layer 108A.

[0240] Next, a resist mask (not shown) is formed on the conductive layer 113A by photolithography. The resist mask is used as a mask to selectively remove the conductive layer 113A to form the conductive layer 113 (see FIG. 1 ). Fig.17D ).

[0241] Next, a resist mask (not shown) is formed on the insulating layer 111 by photolithography. By using the resist mask as a mask, a portion of each of the conductive layer 113, the insulating layer 111, the insulating layer 110, and the insulating layer 109 is selectively removed, and an opening 112 is formed in a region overlapping the conductive layer 108a (see Fig.18A ). A portion of the conductive layer 108 a is exposed at the bottom of the opening 112. In addition, in the opening 112, the side surface of the insulating layer 111, the side surface of the insulating layer 110, and the side surface of the insulating layer 109 are exposed.

[0242] Next, a semiconductor layer 114A (see FIG. 1A ) which will later become the semiconductor layer 114 of the transistor M2 is formed on the insulating layer 111. Fig.18B ) In this embodiment, an oxide semiconductor is formed as the semiconductor layer 114A.

[0243] For example, the oxide semiconductor preferably contains indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium) and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium and tin.

[0244] In particular, as the semiconductor layer of the OS transistor, it is preferred to use an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also recorded as "IGZO"). Alternatively, as the semiconductor layer, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also recorded as "IAZO") may be used. Alternatively, as the semiconductor layer, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also recorded as "IAGZO") may be used. Alternatively, as the semiconductor layer, an oxide containing indium (In), aluminum (Al), gallium (Ga) and tin (Sn) (also recorded as "IGZTO") may be used.

[0245] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than the atomic ratio of M. Examples of the atomic ratio of the metal elements in the In-M-Zn oxide include a composition of In:M:Zn=1:1:1 or in the vicinity thereof, a composition of In:M:Zn=1:1:1.2 or in the vicinity thereof, a composition of In:M:Zn=1:3:2 or in the vicinity thereof, a composition of In:M:Zn=1:3:4 or in the vicinity thereof, a composition of In:M:Zn=2:1:3 or in the vicinity thereof, a composition of In:M:Zn=3:1:2 or in the vicinity thereof, and a composition of In:M:Zn=1:3:4 or in the vicinity thereof. =4:2:3 or a composition in the vicinity thereof, In:M:Zn=4:2:4.1 or a composition in the vicinity thereof, In:M:Zn=5:1:3 or a composition in the vicinity thereof, In:M:Zn=5:1:6 or a composition in the vicinity thereof, In:M:Zn=5:1:7 or a composition in the vicinity thereof, In:M:Zn=5:1:8 or a composition in the vicinity thereof, In:M:Zn=6:1:6 or a composition in the vicinity thereof, In:M:Zn=5:2:5 or a composition in the vicinity thereof, etc. In addition, the nearby compositions include a range of ±30% of the desired atomic number ratio.

[0246] For example, when the composition with an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts is described, the following cases are included: when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when the composition with an atomic ratio of In:Ga:Zn=5:1:6 or thereabouts is described, the following cases are included: when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. In addition, when the composition with an atomic ratio of In:Ga:Zn=1:1:1 or thereabouts is described, the following cases are included: when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0247] The semiconductor layer 114A is formed not only on the insulating layer 111 but also covers the inner side of the opening 112. Therefore, the semiconductor layer 114A is preferably formed by a deposition method having high step coverage. For example, the semiconductor layer 114A is preferably formed by an ALD method.

[0248] Next, a resist mask (not shown) is formed on the semiconductor layer 114A by photolithography. The resist mask is used as a mask to selectively remove a portion of the semiconductor layer 114A to form the semiconductor layer 114 (see FIG. Fig.18C ).

[0249] In the opening 112, the semiconductor layer 114 has a region in contact with the conductive layer 113, a region in contact with the insulating layer 111, a region in contact with the insulating layer 110, a region in contact with the insulating layer 109, and a region in contact with the conductive layer 108a. More specifically, the semiconductor layer 114 has a region in contact with the side surface of the conductive layer 113, a region in contact with the side surface of the insulating layer 111, a region in contact with the side surface of the insulating layer 110, and a region in contact with the conductive layer 108a at the bottom of the opening 112.

[0250] Next, an insulating layer 115 is formed on the insulating layer 111, the conductive layer 113, and the semiconductor layer 114 (see Fig.19A ). The insulating layer 115 is used as a gate insulating layer of the transistor M2. In this embodiment and the like, since an oxide semiconductor is used as the semiconductor layer 114, it is preferable that an insulating layer containing excess oxygen is used as the insulating layer 115.

[0251] Note that when an oxide semiconductor is used as the semiconductor layer 114, microwave treatment is preferably performed in the above-mentioned oxygen-containing atmosphere after the insulating layer 115 is formed.

[0252] Next, a resist mask is formed on the insulating layer 115 by photolithography, and the resist mask is used as a mask to selectively remove a portion of each of the insulating layer 115, the insulating layer 111, the insulating layer 110, the insulating layer 109, and the insulating layer 106 in a region overlapping with the conductive layer 105, thereby forming an opening 127 (not shown). A portion of the conductive layer 105 is exposed at the bottom of the opening 127.

[0253] Next, a conductive layer 116A is formed on the insulating layer 115 (see Fig.19B ).

[0254] Next, a resist mask (not shown) is formed on the conductive layer 116A by photolithography. The resist mask is used as a mask to selectively remove a portion of the conductive layer 116A to form the conductive layer 116 (see FIG. 1 ). Fig.19C ). Thus, the transistor M2 can be formed.

[0255] As described above, the conductive layer 116 is used as the gate electrode of the transistor M2. In addition, the conductive layer 116 is electrically connected to the conductive layer 105 in the opening 127 (see Figure 2 ).

[0256] Next, an insulating layer 117 is formed on the insulating layer 115 and the conductive layer 116 (see Fig.19C ). Thus, the semiconductor device 100A can be manufactured.

[0257] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0258] (Implementation Method 2) In this embodiment, a metal oxide (hereinafter, also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0259] The metal oxide used for the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium and tin, and more preferably gallium.

[0260] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method such as a metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method, or an atomic layer deposition (ALD: Atomic Layer Deposition) method.

[0261] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.

[0262] <Classification of Crystal Structure> Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0263] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, an XRD spectrum measured by GIXD (Grazing-Incidence XRD) can be used for evaluation. In addition, the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement is sometimes simply referred to as an XRD spectrum.

[0264] For example, the peak shape of the XRD spectrum of a quartz glass substrate is roughly bilaterally symmetrical. On the other hand, the peak shape of the XRD spectrum of an In-Ga-Zn oxide film having a crystalline structure is not bilaterally symmetrical. The fact that the peak shape of the XRD spectrum is not bilaterally symmetrical indicates that there is crystal in the film or substrate. In other words, unless the peak shape of the XRD spectrum is bilaterally symmetrical, it cannot be said that the film or substrate is in an amorphous state.

[0265] In addition, the crystal structure of the film or substrate can be evaluated using a diffraction pattern observed by nanobeam electron diffraction (NBED: Nano Beam Electron Diffraction) (also called a nanobeam electron diffraction pattern). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-like pattern is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature, but no halo is observed. Therefore, it can be inferred that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state that is neither single crystal nor polycrystalline nor amorphous, and it cannot be concluded that the In-Ga-Zn oxide is amorphous.

[0266] 〔Structure of oxide semiconductor〕 In addition, when the structure of the oxide semiconductor is focused, the classification of the oxide semiconductor is sometimes different from the above classification. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors other than single crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductors) and amorphous oxide semiconductors.

[0267] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0268] [CAAC-OS] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axis of the plurality of crystalline regions is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0269] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystallizations with a maximum diameter less than 10 nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10 nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, the maximum diameter of the crystallization region is sometimes about tens of nm.

[0270] In addition, in In-Ga-Zn oxide, CAAC-OS has a tendency to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing gallium (Ga), zinc (Zn) and oxygen (hereinafter, (Ga, Zn) layer) are stacked. In addition, indium and gallium can replace each other. Therefore, sometimes the (Ga, Zn) layer contains indium. In addition, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. This layered structure is observed as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image, for example.

[0271] For example, when the CAAC-OS film is structurally analyzed using an XRD device, a peak indicating c-axis orientation is detected at or near 2θ = 31° in Out-of-plane XRD measurement using θ / 2θ scanning. Note that the position (2θ value) of the peak indicating c-axis orientation sometimes varies depending on the type or composition of the metal elements constituting the CAAC-OS.

[0272] In addition, for example, multiple bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when the spot of the incident electron beam passing through the sample (also called the direct spot) is used as the symmetry center, a certain spot and other spots are observed at point-symmetrical positions.

[0273] When observing the crystallized region from the above-mentioned specific direction, although the lattice arrangement in the crystallized region is basically a hexagonal lattice, the unit lattice is not limited to a regular hexagon, and there are cases where it is a non-regular hexagon. In addition, in the above-mentioned distortion, sometimes there is a pentagonal, heptagonal, and other lattice arrangement. In addition, no clear grain boundary is observed near the distortion of CAAC-OS. In other words, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because CAAC-OS can accommodate distortion due to the low density of the arrangement of oxygen atoms in the ab plane direction or the change in the bonding distance between atoms due to the substitution of metal atoms.

[0274] In addition, a crystalline structure in which clear grain boundaries are confirmed is called a so-called polycrystalline. The grain boundaries become recombination centers and carriers are captured, which may lead to a decrease in the on-state current of the transistor and a decrease in the field effect mobility. Therefore, CAAC-OS, in which no clear grain boundaries are confirmed, is one of the crystalline oxides that provide the semiconductor layer of the transistor with an excellent crystalline structure. Note that in order to form CAAC-OS, a structure containing Zn is preferably used. For example, compared with In oxide, In-Zn oxide and In-Ga-Zn oxide can further suppress the occurrence of grain boundaries, so they are preferred.

[0275] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the mixing of impurities and / or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0276] [nc-OS] In nc-OS, the atomic arrangement in a tiny region (for example, a region of 1 nm or more and 10 nm or less, especially a region of 1 nm or more and 3 nm or less) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is 1 nm or more and 10 nm or less, especially 1 nm or more and 3 nm or less, and the tiny crystal is called a nanocrystal. In addition, no regularity of crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS and amorphous oxide semiconductors in certain analysis methods. For example, when an XRD device is used to perform structural analysis on an nc-OS film, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scanning. In addition, when an electron diffraction (also called selected area electron diffraction) is performed on the nc-OS film using an electron beam whose beam diameter is larger than that of a nanocrystal (for example, 50 nm or more), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction using an electron beam whose beam diameter is close to or smaller than the size of the nanocrystal (for example, greater than 1 nm and less than 30 nm) (also called nanobeam electron diffraction), an electron diffraction pattern is sometimes obtained in which multiple spots are observed in a ring-shaped area centered on the direct spot.

[0277] [a-like OS] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0278] [Composition of oxide semiconductor] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0279] [CAC-OS] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0280] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is divided into a first region and a second region to form a mosaic shape and the first region is distributed in the film (hereinafter also referred to as a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0281] Here, each of the atomic ratios of In, Ga, and Zn relative to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide is recorded as [In], [Ga], and [Zn]. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. In addition, the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. In addition, for example, the first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. In addition, the second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0282] Specifically, the first region is a region with indium oxide or indium zinc oxide as a main component. In addition, the second region is a region with gallium oxide or gallium zinc oxide as a main component. In other words, the first region can be referred to as a region with In as a main component. In addition, the second region can be referred to as a region with Ga as a main component.

[0283] Note that a clear boundary between the first region and the second region may not be observed.

[0284] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a part of the main component of Ga and a part of the main component of In exist irregularly in a mosaic shape in a material structure containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0285] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is made greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0286] For example, in CAC-OS in In-Ga-Zn oxide, based on the EDX surface analysis (mapping) image obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that the structure has a region with In as the main component (first region) and a region with Ga as the main component (second region) that are unevenly distributed and mixed.

[0287] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, the conductivity as a metal oxide is exhibited. Therefore, when the first region is distributed in the metal oxide in a cloud-like manner, a high field effect mobility (μ) can be achieved.

[0288] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0289] Therefore, when CAC-OS is used for a transistor, the complementary effect of the conductivity caused by the first region and the insulation caused by the second region can make CAC-OS have a switching function (a function of controlling on / off). In other words, a part of the material of CAC-OS has a conductive function and another part has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on ), high field effect mobility (μ) and good switching performance.

[0290] In addition, transistors using CAC-OS have high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

[0291] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0292] <Transistor Having Oxide Semiconductor> Next, a case where the above-mentioned oxide semiconductor is used in a transistor is described.

[0293] By using the above oxide semiconductor for a transistor, a transistor having high field effect mobility can be realized. In addition, a transistor having high reliability can be realized.

[0294] In particular, as a semiconductor layer forming a channel, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also recorded as IGZO) is preferably used. Alternatively, as a semiconductor layer, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also recorded as IAZO) may be used. Alternatively, as a semiconductor layer, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also recorded as IAGZO) may be used.

[0295] It is preferable to use an oxide semiconductor with a low carrier concentration for a transistor. For example, the carrier concentration in an oxide semiconductor is 1×10 17 cm -3 Below, preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration in the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0296] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0297] Charges trapped in trap states of an oxide semiconductor take a long time to disappear, and may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0298] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0299] <Impurities> Here, the influence of each impurity in the oxide semiconductor is described.

[0300] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0301] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0302] When an oxide semiconductor contains nitrogen, electrons as carriers are easily generated, which increases the carrier concentration and turns into n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0303] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, electrons as carriers are sometimes generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0304] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0305] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0306] (Implementation method 3) In this embodiment, a structural example of a display device 200 to which the semiconductor device 100A or the like which is one embodiment of the present invention can be applied will be described.

[0307] Fig. 20A FIG. 2 shows a perspective view of a display device 200. The display device 200 has a structure in which a substrate 152 and a substrate 101 are bonded together. Fig. 20A In FIG. 1 , the substrate 152 is indicated by a dotted line.

[0308] The display device 200 includes a display portion 235 , a connection portion 140 , a first driving circuit portion 231 , a second driving circuit portion 232 , wiring 165 , and the like. Fig. 20A FIG. 2 shows an example in which the IC 173 and the FPC 172 are mounted in the display device 200. Fig. 20A The structure shown is called a display module including a display device 200, an IC (integrated circuit), and an FPC.

[0309] The connection portion 140 is disposed outside the display portion 235. The connection portion 140 may be disposed along one side or multiple sides of the display portion 235. The number of the connection portions 140 may also be one or more. Fig. 20A An example is shown in which the connection portion 140 is provided so as to surround four sides of the display portion. In the connection portion 140, the common electrode of the light emitting device is electrically connected to the conductive layer, and power can be supplied to the common electrode.

[0310] The wiring 165 has a function of supplying signals and power to the display portion 235, the first driver circuit portion 231, and the second driver circuit portion 232. The signals and power are input to the wiring 165 from the outside through the FPC 172 or from the IC 173.

[0311] Fig. 20A An example of providing IC 173 on substrate 101 by COG (Chip On Glass) method or COF (Chip On Film) method is shown. IC 173 may include, for example, a scanning line driving circuit or a signal line driving circuit. Note that the display device 200 and the display module do not necessarily have to be provided with IC. Alternatively, the IC may be mounted on FPC by COF method or the like.

[0312] The display unit 235 includes a plurality of pixels 230 arranged in a matrix of m rows (m is an integer greater than 1) and n columns (n ​​is an integer greater than 1). In addition, the plurality of pixels 230 are classified into, for example, pixels 230a, pixels 230b, and pixels 230c. The pixels 230a, pixels 230b, and pixels 230c have functions of presenting different light. For example, the pixels 230a, pixels 230b, and pixels 230c may also have functions of presenting red (R) light, presenting green (G) light, and presenting blue (B) light, respectively. Alternatively, for example, the pixels 230a, pixels 230b, and pixels 230c may also have functions of presenting yellow (Y) light, presenting cyan (C) light, and presenting magenta (M) light, respectively.

[0313] By using one pixel 230a, one pixel 230b, and one pixel 230c to form one pixel 240, full-color display can be achieved. Therefore, the pixel 230 is used as a sub-pixel. Fig. 20A In the display device 200 shown, an example of a pixel 230 used as a sub-pixel in a stripe arrangement is shown. The number of sub-pixels constituting one pixel 240 is not limited to three, and may be four or more. For example, four sub-pixels presenting light of R, G, B, and white (W) may be included. Alternatively, four sub-pixels presenting four types of light of R, G, B, and Y may be included.

[0314] Fig. 20B 2 is a block diagram for explaining the display device 200. The display device 200 includes a display unit 235, a first driving circuit unit 231, and a second driving circuit unit 232. Fig. 20B In the display unit 235, the pixel 230 in the first row and the nth column is recorded as pixel 230[1,n], the pixel 230 in the mth row and the first column is recorded as pixel 230[m,1], and the pixel 230 in the mth row and the nth column is recorded as pixel 230[m,n]. In addition, an arbitrary pixel 230 in the display unit 235 is sometimes recorded as pixel 230[r,s]. r is an integer greater than 1 and less than m, and s is an integer greater than 1 and less than n.

[0315] The circuit included in the first driving circuit portion 231 is used as, for example, a scanning line driving circuit. The circuit included in the second driving circuit portion 232 is used as, for example, a signal line driving circuit. Note that a certain circuit may be provided at a position opposite to the first driving circuit portion 231 across the display portion 235. A certain circuit may be provided at a position opposite to the second driving circuit portion 232 across the display portion 235. Note that the circuits included in the first driving circuit portion 231 and the second driving circuit portion 232 are sometimes collectively referred to as a peripheral driving circuit 233.

[0316] As the peripheral drive circuit 233, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit can be used. In the peripheral drive circuit 233, transistors and capacitors can be used. The transistors in the peripheral drive circuit 233 can also be formed using the same process as the transistors in the pixel 230.

[0317] The display device 200 includes m wirings 236 arranged substantially in parallel with each other and whose potentials are controlled by the circuit in the first driving circuit portion 231 , and n wirings 237 arranged substantially in parallel with each other and whose potentials are controlled by the circuit in the second driving circuit portion 232 .

[0318] exist Fig. 20B2 shows an example in which the wiring 236 and the wiring 237 are connected to the pixel 230. However, the wiring 236 and the wiring 237 are just examples, and the wiring connected to the pixel 230 is not limited to the wiring 236 and the wiring 237.

[0319] <Circuit Configuration Example> As an example of a logic circuit to which the semiconductor device according to one embodiment of the present invention can be applied, a configuration example of a NOR circuit and a NAND circuit will be described.

[0320] Fig.21A 2 is a circuit diagram showing a configuration example of a 2-input 1-output NOR circuit (NOR). Fig. 21B Shows the circuit symbol for a NOR circuit. Fig.21A The NOR circuit shown includes a transistor Tr11, a transistor Tr12, a transistor Tr13, and a transistor Tr14. P-channel transistors are used as the transistor Tr11 and the transistor Tr12, and n-channel transistors are used as the transistor Tr13 and the transistor Tr14.

[0321] Therefore, the transistor M1 can be used as the transistor Tr11 and the transistor Tr12. Also, the transistor M2 can be used as the transistor Tr13 and the transistor Tr14.

[0322] Fig.21A and Fig. 21B The NOR circuit shown has a function of outputting a potential H (VDD) from a terminal Y when a potential L (VSS) is input to both terminals A and B. Also, it has a function of outputting a potential L (VSS) from a terminal Y when a potential H (VDD) is input to one or both of the terminals A and B.

[0323] In addition, if Fig. 21C As shown, an OR circuit (OR) can be realized by combining a NOR circuit and an inverter circuit (INV).

[0324] Fig.21D 1 is a circuit diagram showing a configuration example of a 2-input 1-output NAND circuit (NAND). Fig.21E A circuit symbol showing a NAND circuit. Fig.21D The NAND circuit shown includes a transistor Tr21, a transistor Tr22, a transistor Tr23, and a transistor Tr24. P-channel transistors are used as the transistor Tr21 and the transistor Tr22, and n-channel transistors are used as the transistor Tr23 and the transistor Tr24.

[0325] Therefore, the transistor M1 can be used as the transistor Tr21 and the transistor Tr22 , and the transistor M2 can be used as the transistor Tr23 and the transistor Tr24 .

[0326] Fig.21D and Fig.21E The NAND circuit shown has a function of outputting a potential L (VSS) from a terminal Y when a potential H (VDD) is input to both terminals A and B. Also, it has a function of outputting a potential H (VDD) from a terminal Y when a potential L (VSS) is input to one or both of the terminals A and B.

[0327] In addition, if Fig.21F As shown, an AND circuit (AND) can be realized by combining a NAND circuit and an inverter circuit (INV).

[0328] Next, a configuration example of a D flip-flop circuit (DFF: Delay Flip Flop) will be described as an example of a circuit to which the semiconductor device according to one embodiment of the present invention can be applied.

[0329] Fig.22A is a circuit diagram showing a configuration example of a D flip-flop circuit (DFF). Fig. 22B Shows the circuit symbol for a D flip-flop circuit. Fig.22A The D flip-flop circuit shown includes transistors Tr61 to Tr69, transistors Tr71 to Tr79, transistor Tr81, transistor Tr82, transistor Tr91, and transistor Tr92. P-channel transistors are used as transistors Tr61 to Tr69, transistor Tr81, and transistor Tr82, and n-channel transistors are used as transistors Tr71 to Tr79, transistor Tr91, and transistor Tr92.

[0330] Therefore, the transistor M1 can be used as the transistors Tr61 to Tr69, the transistor Tr81, and the transistor Tr82. In addition, the transistor M2 can be used as the transistors Tr71 to Tr79, the transistor Tr91, and the transistor Tr92.

[0331] Fig.22A and Fig. 22B The DFF shown includes a clock signal input terminal CK, an input terminal D, and an output terminal Q. Fig.22A and Fig. 22B The DFF shown has the following functions: while the potential H is input to the clock signal input terminal CK, information (potential) is written to the input terminal D, and when the signal input to the clock signal input terminal CK changes from the potential H to the potential L, the information is retained until the next time the clock signal input terminal CK is written with the potential H. In addition, a signal (potential H or potential L) based on the information retained by the DFF is always output from the output terminal Q.

[0332] Fig.23 This is a block diagram showing an example of the structure of a shift register circuit (SR). The SR is composed of a plurality of DFFs. In addition, in this specification, the first-stage (first) DFF is described as "DFF[1]", and the potential (data) output from the output terminal Q of DFF[1] is described as "data OUT[1]". Fig.23 A block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]) is shown in FIG. Fig.23 In FIG. 1 , the data output from the output terminals Q of DFF[1] to DFF[4] are recorded as data OUT[1] to data OUT[4].

[0333] Data OUT[1] is input to input terminal D of DFF[2], data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0334] The signal SPL is input to the input terminal D of DFF[1]. The signal SPL input to DFF[1] is sequentially transferred to the subsequent DFF in synchronization with the clock signal CLK. The data OUT has a value corresponding to the data held by the DFF. In addition, the timing at which the value of the data OUT changes is synchronized with the clock signal CLK. SR can sequentially switch the data OUT output from multiple DFFs in synchronization with the clock signal CLK.

[0335] As an example of a circuit to which the semiconductor device according to one embodiment of the present invention can be applied, a configuration example of a latch circuit LAT will be described.

[0336] Fig.24A : is a circuit diagram showing a configuration example of the latch circuit LAT. Fig.24A The latch circuit LAT shown includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV1. Fig.24A In FIG. 1 , a node electrically connecting one of the source and the drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitor C31 is referred to as a node N.

[0337] exist Fig.24AIn the latch circuit LAT shown, when a high potential signal is input to the terminal SMP, the transistor Tr33 becomes an on state. Therefore, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and the data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After writing data to the latch circuit LAT, by making the potential of the terminal SMP a low potential, the transistor Tr33 becomes a closed state. Therefore, the potential of the node N is maintained, and the data written to the latch circuit LAT is maintained. Specifically, for example, when the potential of the node N is a low potential, the latch circuit LAT can maintain data "0", and when the potential of the node N is a high potential, the latch circuit LAT can maintain data "1".

[0338] The transistor Tr33 is preferably a transistor with a small off-state current such as an OS transistor. Therefore, the latch circuit LAT can hold data for a long period of time. Therefore, the frequency of rewriting data to the latch circuit LAT can be reduced.

[0339] Fig. 24B Shown with Fig.24A Examples of different structures of the latch circuit LAT. Fig. 24B The latch circuit LAT of the structure shown includes transistor Tr51, transistor Tr52, transistor Tr53, transistor Tr54, transistor Tr55, transistor Tr56, transistor Tr57, transistor Tr58, transistor Tr59, transistor Tr60, transistor Tr61, transistor Tr62, inverter circuit INV2_1, inverter circuit INV2_2 and inverter circuit INV2_3.

[0340] An analog switch circuit is formed by using transistor Tr59 and transistor Tr60. An analog switch circuit is formed by using transistor Tr61 and transistor Tr62.

[0341] The transistor Tr53, the transistor Tr54, the transistor Tr57, the transistor Tr58, the transistor Tr59 and the transistor Tr61 may be n-channel transistors, and the transistor Tr51, the transistor Tr52, the transistor Tr55, the transistor Tr56, the transistor Tr60 and the transistor Tr62 may be p-channel transistors.

[0342] The transistor Tr53, the transistor Tr54, the transistor Tr57, the transistor Tr58, the transistor Tr59 and the transistor Tr61 may be, for example, OS transistors or Si transistors. The transistor Tr51, the transistor Tr52, the transistor Tr55, the transistor Tr56, the transistor Tr60 and the transistor Tr62 may be, for example, Si transistors.

[0343] As described above, by inputting a high potential signal to the terminal SMP, data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. For example, when the potential of the terminal ROUT is low, data "0" can be written to the latch circuit LAT, and when the potential of the terminal ROUT is high, data "1" can be written to the latch circuit LAT. After writing data to the latch circuit LAT, the data written to the latch circuit LAT is retained by changing the potential of the terminal SMP to a low potential.

[0344] The latch circuit LAT can output the signal input from the terminal ROUT to the terminal LIN when the potential of the terminal SP1 is low. In addition, the latch circuit LAT can not output the signal from the terminal LIN or change the potential of the terminal LIN to a low potential when the potential of the terminal SP1 is high and the latch circuit LAT holds data "0". Furthermore, the latch circuit LAT can output the signal input from the terminal SP1 to the terminal LIN when the potential of the terminal SP1 is high and the latch circuit LAT holds data "1".

[0345] In this specification, etc., "writing data to the latch circuit LAT so that the signal input from the terminal SP1 is output to the terminal LIN" is sometimes referred to as "writing data to the latch circuit LAT". That is, for example, "writing data of "1" to the latch circuit LAT" is sometimes referred to as "writing data to the latch circuit LAT".

[0346] As the inverter circuit INV1 , the inverter circuit INV2_1 , the inverter circuit INV2_2 , and the inverter circuit INV2_3 , the semiconductor device 100A according to one embodiment of the present invention or the like can be used.

[0347] In addition, the transistor M1 can be used as a p-channel transistor constituting the latch circuit LAT. In addition, the transistor M1 or the transistor M2 can be used as an n-channel transistor constituting the latch circuit LAT. The semiconductor device 100A according to one embodiment of the present invention and the like can be used in various circuits.

[0348] Fig.25A 2 is a circuit diagram showing a configuration example of a demultiplexing circuit DeMUX. The demultiplexing circuit DeMUX includes a demultiplexing circuit D.

[0349] The demultiplexing circuit DeMUX has a structure that divides each stage into two systems, and there are m paths in total. That is, the demultiplexing circuits D are connected in a knockout manner. The input terminal of the demultiplexing circuit D of the first stage is electrically connected to the terminal SPI. The output terminal of the demultiplexing circuit D of the last stage, the log2(m)th stage, is electrically connected to the two terminals SP (terminal SP[1], terminal SP[2]).

[0350] The selection signal input terminal of the demultiplexing circuit D is electrically connected to the terminal DSL and the terminal DSLB. Here, the complementary signal of the signal input to the terminal DSL is input to the terminal DSLB. For example, when a 1-bit digital signal of "0" is input to the terminal DSL(1), a 1-bit digital signal of "1" is input to the terminal DSLB(1). On the other hand, when a 1-bit digital signal of "1" is input to the terminal DSL(1), a 1-bit digital signal of "0" is input to the terminal DSLB(1). The same is true for the terminals DSLB(2) to DSLB(log2(m)).

[0351] By making the demultiplexing circuit DeMUX have Fig.25A With the structure shown, the demultiplexing circuit DeMUX can output the signal input to the terminal SPI to the terminal SP corresponding to the value represented by the signal input to the terminal DSL(1) to the terminal DSL(log2(m)).

[0352] Fig.25B , Fig.25C and Fig.25D is a circuit diagram showing a configuration example of a demultiplexing circuit D. Fig.25B The demultiplexing circuit D of the structure shown includes a transistor Tr121, a transistor Tr122, a transistor Tr123 and a transistor Tr124. The transistors Tr121 to Tr124 can be, for example, n-channel transistors.

[0353] exist Fig.25BIn the demultiplexing circuit D of the structure shown, the terminal DSL is electrically connected to one of the source and drain of the transistor Tr121. The other of the source and drain of the transistor Tr121 is electrically connected to the gate of the transistor Tr123. The terminal DSLB is electrically connected to one of the source and drain of the transistor Tr122. The other of the source and drain of the transistor Tr122 is electrically connected to the gate of the transistor Tr124. One of the source and drain of the transistor Tr123 and one of the source and drain of the transistor Tr124 are electrically connected to the input terminal of the demultiplexing circuit D. The other of the source and drain of the transistor Tr123 is electrically connected to the first output terminal of the demultiplexing circuit D. The other of the source and drain of the transistor Tr124 is electrically connected to the second output terminal of the demultiplexing circuit D. In addition, the gate of the transistor Tr121 and the gate of the transistor Tr122 can be supplied with a high potential.

[0354] exist Fig.25B In the demultiplexing circuit D of the structure shown, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistor Tr123 is turned on and the transistor Tr124 is turned off. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the first output terminal of the demultiplexing circuit D. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistor Tr123 is turned off and the transistor Tr124 is turned on. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the second output terminal of the demultiplexing circuit D.

[0355] Fig.25C yes Fig.25B A modified example of the demultiplexing circuit D shown. Fig.25C The demultiplexing circuit D shown in FIG. Fig.25B The demultiplexing circuit D shown is different in that it includes transistor Tr125 and transistor Tr126.

[0356] exist Fig.25C In the demultiplexing circuit D of the structure shown, one of the source and drain of transistor Tr125 is electrically connected to the second output terminal of the demultiplexing circuit D, and the gate of transistor Tr125 is electrically connected to the gate of transistor Tr123. In addition, one of the source and drain of transistor Tr126 is electrically connected to the first output terminal of the demultiplexing circuit D, and the gate of transistor Tr126 is electrically connected to the gate of transistor Tr124. The other of the source and drain of transistor Tr125 and the other of the source and drain of transistor Tr126 can be supplied with a low potential.

[0357] exist Fig.25CIn the demultiplexing circuit D of the structure shown, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistor Tr123 and the transistor Tr125 are turned on, and the transistor Tr124 and the transistor Tr126 are turned off. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the first output terminal of the demultiplexing circuit D, and the potential of the second output terminal of the demultiplexing circuit D becomes low. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistor Tr123 and the transistor Tr125 are turned off, and the transistor Tr124 and the transistor Tr126 are turned on. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the second output terminal of the demultiplexing circuit D, and the potential of the first output terminal of the demultiplexing circuit D becomes low.

[0358] Fig.25D The demultiplexing circuit D of the structure shown includes a transistor Tr131, a transistor Tr132, a transistor Tr133, and a transistor Tr134. The transistor Tr131 and the transistor Tr133 may be n-channel transistors, and the transistor Tr132 and the transistor Tr134 may be p-channel transistors.

[0359] exist Fig.25D In the demultiplexing circuit D of the structure shown, the terminal DSL is electrically connected to the gate of the transistor Tr131 and the gate of the transistor Tr134. The terminal DSLB is electrically connected to the gate of the transistor Tr132 and the gate of the transistor Tr133. The input terminal of the demultiplexing circuit D is electrically connected to one of the source and drain of the transistor Tr131, one of the source and drain of the transistor Tr132, one of the source and drain of the transistor Tr133, and one of the source and drain of the transistor Tr134. The other of the source and drain of the transistor Tr131 and the other of the source and drain of the transistor Tr132 are electrically connected to the first output terminal of the demultiplexing circuit D. The other of the source and drain of the transistor Tr133 and the other of the source and drain of the transistor Tr134 are electrically connected to the second output terminal of the demultiplexing circuit D.

[0360] exist Fig.25DIn the demultiplexing circuit D of the structure shown, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistors Tr131 and Tr132 are turned on, and the transistors Tr133 and Tr134 are turned off. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the first output terminal of the demultiplexing circuit D. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistors Tr131 and Tr132 are turned off, and the transistors Tr133 and Tr134 are turned on. Therefore, the signal input from the input terminal of the demultiplexing circuit D is output from the second output terminal of the demultiplexing circuit D.

[0361] The semiconductor device according to one embodiment of the present invention can be used for a demultiplexing circuit D. The transistor M1 can be used as a p-channel transistor constituting the demultiplexing circuit D. Alternatively, the transistor M1 or the transistor M2 can be used as an n-channel transistor constituting the demultiplexing circuit D.

[0362] <Configuration Example of Pixel Circuit> FIG. 26A to FIG. 26D , FIG. 27A to FIG. 27D , Fig.28A and Fig.28B 2 shows an example of the structure of the pixel 230. The pixel 230 includes a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, a pixel circuit 51D, or a pixel circuit 51E) and a light emitting element 61.

[0363] The light-emitting element (also called light-emitting device) described in this embodiment and the like refers to a self-luminous light-emitting device such as an organic EL element (also called an OLED (Organic Light Emitting Diode)). In addition, the light-emitting element electrically connected to the pixel circuit may be a self-luminous light-emitting element such as an LED (Light Emitting Diode), a micro-LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0364] Fig.26A The pixel circuit 51A shown is a 2Tr1C type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53 .

[0365] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. The other of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B. One of the source and drain of the transistor 52B and one terminal of the capacitor 53 are electrically connected to the wiring ANO. The other terminal of the capacitor 53 is electrically connected to the gate of the transistor 52B. The region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and the other terminal of the capacitor 53 are electrically connected is used as a node FN. The other of the source and drain of the transistor 52B is electrically connected to the anode of the light emitting element 61. The cathode of the light emitting element 61 is electrically connected to the wiring VCOM.

[0366] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 237. The wiring VCOM is a wiring for supplying a potential for supplying a current to the light emitting element 61. The transistor 52A has a function of controlling the conduction state or non-conduction state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0367] By turning on the transistor 52A, the image signal is supplied from the wiring SL to the node FN. Then, by turning off the transistor 52A, the image signal is held in the node FN. In order to surely hold the image signal supplied to the node FN, it is preferable to use a transistor with a small off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0368] The transistor 52B has a function of controlling the amount of current flowing through the light emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light emitting element 61 is controlled according to an image signal supplied to the gate (node ​​FN) of the transistor 52B.

[0369] exist Fig.26A In the pixel circuit 51A shown in FIG. 1 , an n-channel transistor is used as the transistor 52A, and a p-channel transistor is used as the transistor 52B. Fig.26B As in the pixel circuit 51A shown in the figure, an n-channel transistor may be used as the transistor 52B. When an n-channel transistor is used as the transistor 52B, one terminal of the capacitor 53 may be electrically connected to the other of the source and the drain of the transistor 52B.

[0370] Fig.26C The pixel circuit 51B shown is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53 . Fig.26C The pixel circuit 51B shown has a Fig.26AThe pixel circuit 51A shown in the figure has a structure in which a transistor 52C is added.

[0371] When an n-channel transistor is used as transistor 52B, Fig.26D The circuit structure of the pixel circuit 51B shown. Fig.26D The pixel circuit 51B shown has a Fig.26B The pixel circuit 51A shown in the figure has a structure in which a transistor 52C is added.

[0372] One of the source and the drain of the transistor 52C is electrically connected to the other of the source and the drain of the transistor 52B. The other of the source and the drain of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential.

[0373] The transistor 52C has a function of controlling the conduction state or non-conduction state between the other of the source and the drain of the transistor 52B and the wiring V0 according to the potential of the wiring GL. The wiring V0 is a wiring for supplying a reference potential. When an n-channel transistor is used as the transistor 52B, the potential variation between the gate and the source of the transistor 52B can be suppressed by the reference potential of the wiring V0 supplied through the transistor 52C.

[0374] In addition, the wiring V0 can be used to obtain a current value that can be used for setting pixel parameters. More specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A / D converter or the like and output to the outside.

[0375] Fig.27A The pixel circuit 51C shown has a Fig.26C The pixel circuit 51B shown has a structure in which a transistor 52D is added. Fig.27A The pixel circuit 51C shown is a 4Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53 .

[0376] In the transistor 52D, one of the source and the drain is electrically connected to the wiring ANO, and the other of the source and the drain is electrically connected to the other of the source and the drain of the transistor 52A, the other terminal of the capacitor 53, and the gate of the transistor 52B. The region where the other of the source and the drain of the transistor 52D, the other of the source and the drain of the transistor 52A, the other terminal of the capacitor 53, and the gate of the transistor 52B are electrically connected is used as a node FN.

[0377] The wiring GL1, the wiring GL2, and the wiring GL3 are electrically connected to the pixel circuit 51C. Note that in this embodiment and the like, the wiring GL1, the wiring GL2, and the wiring GL3 may be collectively referred to as the wiring GL. Therefore, the wiring GL is not limited to one, and may be a plurality.

[0378] The wiring GL1 is electrically connected to the gate of the transistor 52A, the wiring GL2 is electrically connected to the gate of the transistor 52C, and the wiring GL3 is electrically connected to the gate of the transistor 52D.

[0379] When transistor 52D is turned on, the source and gate of transistor 52B have the same potential, so that transistor 52B can be turned off. As a result, the current flowing through light emitting element 61 can be forcibly shielded. This pixel circuit is suitable for the case where a display method that alternately sets a display period and a light-off period is used. When transistor 52D is turned on, transistor 52C can also be turned on.

[0380] exist Fig.27A In the pixel circuit 51C shown in FIG. 1 , n-channel transistors are used as transistors 52A, 52C, and 52D, and p-channel transistors are used as transistor 52B. Fig.27B As shown in the pixel circuit 51C, an n-channel transistor may be used as the transistor 52B. When an n-channel transistor is used as the transistor 52B, one terminal of the capacitor 53 may be electrically connected to the other of the source and drain of the transistor 52B. In addition, one of the source and drain of the transistor 52D may be electrically connected to the wiring V0.

[0381] Fig.27C The pixel circuit 51D shown has a Fig.27A The pixel circuit 51C shown in the figure has a structure in which a capacitor 53A is added. Fig.27C In the pixel circuit 51D shown, one terminal of the capacitor 53A is electrically connected to the other terminal of the source and drain of the transistor 52B, and the other terminal of the capacitor 53A is electrically connected to the gate of the transistor 52B. The region where the other terminal of the source and drain of the transistor 52D, the other terminal of the source and drain of the transistor 52A, the other terminal of the capacitor 53, the other terminal of the capacitor 53A, and the gate of the transistor 52B are electrically connected is used as a node FN.

[0382] Fig.27D The pixel circuit 51D shown has a Fig.27B The pixel circuit 51C shown in the figure has a structure in which a capacitor 53A is added. Fig.27DIn the pixel circuit 51D shown, one terminal of the capacitor 53A is electrically connected to the wiring ANO, and the other terminal is electrically connected to the gate of the transistor 52B. The capacitor 53 and the capacitor 53A are used as storage capacitors. Fig.27C and Fig.27D The pixel circuit 51D shown is a 4Tr2C type pixel circuit.

[0383] The transistor 52A, the transistor 52B, the transistor 52C, and the transistor 52D preferably include a back gate electrode. In this case, a structure in which the same signal as the gate electrode is supplied to the back gate electrode or a structure in which a signal different from the gate electrode is supplied to the back gate electrode can be adopted.

[0384] In addition to the transistor 52B, p-channel transistors may be used as the transistor 52A, the transistor 52C, and the transistor 52D.

[0385] Fig.28A The pixel circuit 51E shown is a 6Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, a transistor 52E, a transistor 52F, and a capacitor 53 .

[0386] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL1. One of the source and drain of the transistor 52D is electrically connected to the wiring ANO, and the gate of the transistor 52D is electrically connected to the wiring GL2. The other of the source and drain of the transistor 52D is electrically connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52B is electrically connected to the other of the source and drain of the transistor 52A and one of the source and drain of the transistor 52F. The gate of the transistor 52F is electrically connected to the wiring GL3.

[0387] One of the source and drain of transistor 52E is electrically connected to the other of the source and drain of transistor 52D and one of the source and drain of transistor 52B. The other of the source and drain of transistor 52E is electrically connected to the gate of transistor 52B and one terminal of capacitor 53. The other terminal of capacitor 53 is electrically connected to the other of the source and drain of transistor 52F, the anode of light emitting element 61, and one of the source and drain of transistor 52C. The gate of transistor 52E and the gate of transistor 52C are electrically connected to wiring GL4. The other of the source and drain of transistor 52C is electrically connected to wiring V0. The region where the other of the source and drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are electrically connected is used as node FN.

[0388] exist Fig.28AIn the pixel circuit 51E shown, n-channel transistors are used as transistors 52A to 52F. For example, an n-channel Si transistor is used as transistor 52B used as a driving transistor, and OS transistors are used as transistors 52A and transistors 52C to 52F. The transistor M1 shown in the above embodiment can be used as the Si transistor, and the transistor M2 shown in the above embodiment can be used as the OS transistor. In particular, in order to reliably maintain the image signal supplied to the node FN, it is preferable to use an OS transistor as the transistor 52E.

[0389] The transistor 52B used as a driver transistor is preferably a normally-off transistor. In particular, a Si transistor can be easily made into a normally-off transistor by performing channel doping, and is therefore suitable for the transistor 52B. Note that if the OS transistor is a normally-off transistor, it can be used for the transistor 52B.

[0390] In addition, if Fig.28B As shown, a transistor including a back gate may be used as the transistor 52B. The back gate of the transistor 52B may be electrically connected to the gate of the transistor 52B or to the other of the source and the drain of the transistor 52B.

[0391] exist Fig.28A and Fig.28B In the embodiment, an n-channel transistor is used as the transistor 52B serving as a driving transistor, but a p-channel transistor may also be used as the transistor 52B.

[0392] Fig.29A FIG. 5 shows a pixel circuit 51E in which a p-channel transistor is used as the transistor 52B. Fig.29A The pixel circuit 51E shown is Fig.28A The connection method of transistor 52A, transistor 52E and capacitor 53 is different between the pixel circuits 51E shown. Fig.29A In the pixel circuit 51E shown, the other of the source and drain of the transistor 52A is electrically connected to the other of the source and drain of the transistor 52D and one of the source and drain of the transistor 52B. In addition, the other terminal of the capacitor 53 is electrically connected to one of the source and drain of the transistor 52D. In addition, one of the source and drain of the transistor 52E is electrically connected to the other of the source and drain of the transistor 52B.

[0393] In addition, if Fig.29B As shown in the pixel circuit 51E, a p-channel transistor including a back gate may be used as the transistor 52B. When a p-channel transistor is used as the transistor 52B, the back gate of the transistor 52B may be electrically connected to the gate of the transistor 52B or one of the source and drain of the transistor 52B. Fig.29B, an example is shown in which the back gate of the transistor 52B is electrically connected to one of the source and the drain of the transistor 52B.

[0394] The structure of the semiconductor device 100 (semiconductor device 100A to semiconductor device 100L) according to one embodiment of the present invention can be used not only for a driver circuit of a display device but also for a pixel circuit. Fig.30 1 is a cross-sectional view illustrating a configuration example of a pixel circuit 51E. In order to avoid repeated description, this embodiment mainly describes portions not described in other embodiments. Therefore, for contents not described in this embodiment, other embodiments can be referred to.

[0395] exist Fig.30 In the configuration example of the pixel circuit 51E shown in FIG. 1 , the transistor 52A, the transistor 52D, and the transistor 52F have the same Fig. 12B The transistor 52E has the same structure as the transistor M2 shown in FIG. Fig. 9B The transistor M2 shown in FIG. 1 has the same structure as the transistor M2 shown in FIG. Fig. 9B The transistor M1 shown has the same structure.

[0396] exist Fig.30 In the illustrated example of the structure of the pixel circuit 51E, a conductive layer 175 is provided on the insulating layer 104. The conductive layer 175 is formed on the insulating layer 104 after the step of introducing an impurity element for forming the drain region 103a and the source region 103c into the semiconductor layer 103 and before forming the insulating layer 109. The conductive layer 175 may be formed using the same material and the same manufacturing method as the conductive layer 105.

[0397] In addition, a conductive layer 176 is included over the insulating layer 111. The conductive layer 176 can be formed simultaneously with the conductive layer 113 using the same material and the same manufacturing process. The conductive layer 176 serves as the other of the source and the drain of the transistor 52F. A region where the conductive layer 175 and the conductive layer 176 overlap each other serves as the capacitor 53. The conductive layer 175 serves as one terminal of the capacitor 53. The conductive layer 175 is electrically connected to the conductive layer 105 in a region not shown.

[0398] In addition, Fig.30 In the example of the structure of the pixel circuit 51E shown in the figure, an insulating layer 181 is included instead of the insulating layer 117. In addition, an insulating layer 182 is included on the insulating layer 181, and an insulating layer 183 is included on the insulating layer 182. The insulating layer 181 may be formed using the same material and method as the insulating layer 109. The insulating layer 182 may be formed using the same material and method as the insulating layer 110. The insulating layer 183 may be formed using the same material and method as the insulating layer 111.

[0399] In addition, a conductive layer 184 is provided over the insulating layer 183. The conductive layer 184 may be formed using the same material and method as the conductive layer 113. In addition, in a region overlapping with the conductive layer 176, an opening 129 is provided in a portion of each of the conductive layer 184, the insulating layer 183, the insulating layer 182, the insulating layer 181, and the insulating layer 115, and the transistor 52C is provided in the region including the opening 129.

[0400] Transistor 52C has Figure 1B The same structure as the transistor M2 shown in the figure. Specifically, a semiconductor layer 189 is included in the opening 129, a part of the semiconductor layer 189 is electrically connected to the conductive layer 176, and another part of the semiconductor layer 189 is electrically connected to the conductive layer 184. The conductive layer 176 is used as one of the source and the drain of the transistor 52C. In addition, the conductive layer 184 is used as the other of the source and the drain of the transistor 52C. The semiconductor layer 189 can be formed using the same material and method as the semiconductor layer 114. In addition, an insulating layer 185 is included on the insulating layer 183 and the semiconductor layer 189. The insulating layer 185 can be formed using the same material and method as the insulating layer 115. A part of the insulating layer 185 is used as the gate insulating layer of the transistor 52C.

[0401] In addition, a conductive layer 191 having a region overlapping with the opening 129 is provided over the insulating layer 185. The conductive layer 191 may be formed using the same material and method as the conductive layer 116. A portion of the conductive layer 191 is used as a gate electrode of the transistor 52C. In addition, an insulating layer 186 is provided over the insulating layer 185 and the conductive layer 191, and an insulating layer 187 is provided over the insulating layer 186. The insulating layer 186 may be formed using the same material and method as the insulating layer 117.

[0402] The insulating layer 187 is preferably used as a planarization layer for reducing steps caused by transistors, capacitors, wiring, etc. formed in the lower layer. As a material for the planarization layer, an organic insulating film is preferred. As materials that can be used for the organic insulating film, acrylic resins, epoxy resins, polyimides, polyamides, polyimide amides, siloxane resins, benzocyclobutene resins, phenolic resins, and their precursors can be cited. In addition, after the insulating layer 187 is formed using an inorganic material or an organic material, the insulating layer 187 can be planarized using a chemical mechanical polishing (CMP) method or the like.

[0403] In addition, Fig.30In the illustrated example of the structure of the pixel circuit 51E, a conductive layer 188 serving as an anode of the light-emitting element 61 is provided on the insulating layer 187. In addition, an opening provided in a portion of each of the insulating layer 187, the insulating layer 186, the insulating layer 185, the conductive layer 184, the insulating layer 183, the insulating layer 182, the insulating layer 181, and the insulating layer 115 is provided in a region overlapping with the conductive layer 176. The conductive layer 188 is electrically connected to the conductive layer 176 at the bottom of the opening. The conductive layer 188 corresponds to, for example, the lower electrode 761 described later.

[0404] By using the structure of the semiconductor device 100 according to one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Therefore, the definition of the display device can be improved. For example, a display device having a definition of 1000 ppi or more, preferably 2000 ppi or more, more preferably 3000 ppi or more, further preferably 4000 ppi or more, further preferably 5000 ppi or more, further preferably 6000 ppi or more and 10000 ppi or less, 9000 ppi or less, or 8000 ppi or less can be realized.

[0405] In addition, by reducing the area occupied by the pixel circuit, the number of pixels of the display device can be increased (the resolution can be improved). For example, extremely high-resolution display devices such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K2K (3840×2160 pixels), or 8K4K (7680×4320 pixels) can be realized.

[0406] Therefore, by using the structure of the semiconductor device 100 according to one embodiment of the present invention in a pixel circuit of a display device, the display quality of the display device can be improved. In addition, the aperture ratio of the pixel can be increased in a bottom emission type display device using an EL element. A pixel with a high aperture ratio can emit light with the same brightness as a pixel with a low aperture ratio at a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.

[0407] <Pixel Layout> use FIG. 31A to FIG. 31G and FIG. 32A to FIG. 32K Main description and Fig. 20A Different pixel layouts. There is no particular limitation on the arrangement of sub-pixels, and various pixel layouts can be used. Examples of sub-pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, Pentile arrangement, and the like.

[0408] Notice, Fig. 20A, FIG. 31A to FIG. 31G and FIG. 32A to FIG. 32K The top surface shape of the sub-pixel shown corresponds to the top surface shape of the light-emitting region.

[0409] Examples of the top surface shape of the sub-pixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, the above polygonal shapes with rounded corners, an ellipse, or a circle.

[0410] The pixel circuit 51 included in the sub-pixel (pixel 230 ) may be arranged to overlap with the light-emitting region or may be arranged outside the light-emitting region.

[0411] Fig.31A The pixels 240 shown are arranged in an S-striped pattern. Fig.31A In the illustrated pixel 240 , the pixel 230 a , the pixel 230 b , and the pixel 230 c are used as sub-pixels.

[0412] Fig.31B The pixel 240 shown includes a pixel 230a having a top surface shape of a trapezoid or a triangle with rounded corners, a pixel 230b having a top surface shape of a trapezoid or a triangle with rounded corners, and a pixel 230c having a top surface shape of a quadrangular or a hexagonal with rounded corners. In addition, the light-emitting area of ​​pixel 230b is larger than that of pixel 230a. In this way, the shape and size of each sub-pixel can be determined independently. For example, the size of a sub-pixel including a light-emitting device with high reliability can be smaller.

[0413] Fig.31C The pixel 240A and the pixel 240B shown are arranged in a Pentile arrangement. Fig.31C An example is shown in which pixels 240A including pixels 230 a and pixels 230 b and pixels 240B including pixels 230 b and pixels 230 c are alternately arranged.

[0414] FIG. 31D to FIG. 31F The pixel 240A and the pixel 240B shown are arranged in a delta arrangement. The pixel 240A includes two sub-pixels (pixel 230a and pixel 230b) in the upper row (first row) and one sub-pixel (pixel 230c) in the lower row (second row). The pixel 240B includes one sub-pixel (pixel 230c) in the upper row (first row) and two sub-pixels (pixel 230a and pixel 230b) in the lower row (second row).

[0415] Fig.31D This is an example in which each sub-pixel has a top surface shape that is approximately quadrangular with rounded corners. Fig.31E is an example in which each sub-pixel has a circular top surface shape, Fig.31F This is an example in which each sub-pixel has a top surface shape that is approximately hexagonal with rounded corners.

[0416] exist Fig.31F In the embodiment, each sub-pixel is arranged inside the hexagonal area that is arranged most closely. Each sub-pixel is arranged in a manner that it is surrounded by six sub-pixels when focusing on one of the sub-pixels. In addition, sub-pixels that present light of the same color are arranged in a manner that they are not adjacent. For example, each sub-pixel is arranged in a manner that three pixels 230b and three pixels 230c that are alternately arranged surround the pixel 230a when focusing on the pixel 230a.

[0417] Figure 31G An example is shown in which the sub-pixels of each color are arranged in a zigzag shape. Specifically, in a plan view, the positions of the upper sides of two sub-pixels arranged in the column direction (for example, pixel 230a and pixel 230b or pixel 230b and pixel 230c) are offset.

[0418] exist FIG. 31A to FIG. 31G In the illustrated pixels, for example, preferably, pixel 230a is a sub-pixel R emitting red light, pixel 230b is a sub-pixel G emitting green light, and pixel 230c is a sub-pixel B emitting blue light. Note that the structure of the sub-pixels is not limited thereto, and the colors emitted by the sub-pixels and the arrangement order can be appropriately determined. For example, pixel 230b may also be a sub-pixel R emitting red light, and pixel 230a may also be a sub-pixel G emitting green light.

[0419] In photolithography, the finer the pattern being processed, the more important it is to ignore the effect of light diffraction. Therefore, when the pattern of the photomask is transferred by exposure, its fidelity decreases, and it is difficult to process the resist mask into a desired shape. Therefore, even if the pattern of the photomask is rectangular, it is easy to form a pattern with rounded corners. Therefore, the top surface shape of the sub-pixel is sometimes a polygon with rounded corners, an ellipse, or a circle.

[0420] Furthermore, when the EL layer is processed into an island shape using a resist mask, the resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the material of the EL layer and the curing temperature of the resist material, the curing of the resist film may be insufficient. The insufficiently cured resist film may have a shape that is far from the desired shape when processed. As a result, the top surface shape of the EL layer may be a polygonal shape with rounded corners, an ellipse, a circle, or the like. For example, when a resist mask having a square top surface shape is to be formed, a resist mask having a circular top surface shape may be formed, and the top surface shape of the EL layer may be circular.

[0421] In order to make the top surface shape of the EL layer a desired shape, a technique (OPC (Optical Proximity Correction) technique) of pre-correcting the mask pattern so that the design pattern and the transfer pattern coincide with each other can be used. Specifically, in the OPC technique, correction patterns are added to the pattern corners on the mask pattern.

[0422] like FIG. 32A to FIG. 32I As shown, a pixel may include four types of sub-pixels.

[0423] FIG. 32A to FIG. 32C The pixels 240 are shown in a striped arrangement.

[0424] Fig.32A is an example in which each sub-pixel has a rectangular top surface shape, Fig.32B This is an example in which each sub-pixel has a top surface shape connecting two semicircles and a rectangle. Fig.32C This is an example in which each sub-pixel has an elliptical top surface shape.

[0425] FIG. 32D to FIG. 32F The pixels 240 are shown arranged in a matrix.

[0426] Fig.32D is an example in which each sub-pixel has a square top surface shape, Fig.32E This is an example in which each sub-pixel has a top surface shape that is approximately square with rounded corners. Fig.32F This is an example in which each sub-pixel has a circular top surface shape.

[0427] Figure 32G and Fig.32H An example is shown in which one pixel 240 is formed using sub-pixels arranged in two rows and three columns.

[0428] Figure 32G The pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) of the pixel 240 and one sub-pixel (pixel 230d) in the lower row (second row). In other words, the pixel 240 includes the pixel 230a in the left column (first column), the pixel 230b in the middle column (second column), the pixel 230c in the right column (third column), and the pixel 230d spanning the three columns.

[0429] Fig.32HThe pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) and three pixels 230d in the lower row (second row). In other words, the pixel 240 includes pixel 230a and pixel 230d in the left column (first column) of the pixel 240, includes pixel 230b and pixel 230d in the middle column (second column), and includes pixel 230c and pixel 230d in the right column (third column). Fig.32H As shown, by adopting a structure in which the sub-pixels of the upper row and the lower row are aligned, dust and the like that may be generated in the manufacturing process can be efficiently removed. Therefore, a display device with high display quality can be provided.

[0430] Fig.32I An example is shown in which one pixel 240 is formed using sub-pixels arranged in three rows and two columns.

[0431] Fig.32I The illustrated pixel 240 includes a pixel 230a in the upper row (first row) of the pixel 240, includes a pixel 230b in the middle row (second row), includes a pixel 230c that spans the first row to the second row, and includes a sub-pixel (pixel 230d) in the lower row (third row). In other words, the pixel 240 includes the pixel 230a and the pixel 230b in the left column (first column) of the pixel 240, includes the pixel 230c in the right column (second column), and includes a pixel 230d that spans the two columns.

[0432] FIG. 32A to FIG. 32I The pixel 240 shown is composed of four sub-pixels, namely, a pixel 230 a , a pixel 230 b , a pixel 230 c , and a pixel 230 d .

[0433] The pixels 230a, 230b, 230c, and 230d may include light emitting devices that emit light of different colors. The pixels 230a, 230b, 230c, and 230d may include sub-pixels of four colors: R, G, B, and white (W); sub-pixels of four colors: R, G, B, and Y; and sub-pixels of R, G, B, and infrared light (IR); and the like.

[0434] exist FIG. 32A to FIG. 32I In the pixels 240 shown, for example, pixel 230a may be a sub-pixel R emitting red light, pixel 230b may be a sub-pixel G emitting green light, pixel 230c may be a sub-pixel B emitting blue light, and pixel 230d may be a sub-pixel W emitting white light, a sub-pixel Y emitting yellow light, or a sub-pixel IR emitting near-infrared light. Figure 32G and Fig.32HIn the pixel 240 shown in FIG. 1 , the layout of R, G, and B is a stripe arrangement, so the display quality can be improved. Fig.32I In the pixel 240 shown, the layout of R, G, and B is a so-called S-stripe arrangement, so the display quality can be improved.

[0435] In addition, the pixel 240 may include a sub-pixel having a light-receiving element (also referred to as a light-receiving device).

[0436] exist FIG. 32A to FIG. 32I In each pixel 240 shown, any one of the pixels 230 a to 230 d may be a sub-pixel including a light-receiving device.

[0437] exist FIG. 32A to FIG. 32I In the pixels 240 shown, for example, pixel 230a may be a sub-pixel R emitting red light, pixel 230b may be a sub-pixel G emitting green light, pixel 230c may be a sub-pixel B emitting blue light, and pixel 230d may be a sub-pixel S including a light receiving device. Figure 32G and Fig.32H In the pixel 240 shown in FIG. 1 , the layout of R, G, and B is a stripe arrangement, so the display quality can be improved. Fig.32I In the pixel 240 shown, the layout of R, G, and B is a so-called S-stripe arrangement, so the display quality can be improved.

[0438] There is no particular limitation on the wavelength of light detected by the sub-pixel S including the light-receiving device. The sub-pixel S can detect one or both of visible light and infrared light.

[0439] like Fig.32J and Figure 32K As shown, one pixel 240 may also include five sub-pixels.

[0440] Fig.32J An example is shown in which one pixel 240 is formed using sub-pixels arranged in two rows and three columns.

[0441] Fig.32J The pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) of the pixel 240 and two sub-pixels (pixel 230d, pixel 230e) in the lower row (second row). In other words, the pixel 240 includes the pixel 230a and the pixel 230d in the left column (first column) of the pixel 240, includes the pixel 230b in the middle column (second column), includes the sub-pixel 230c in the right column (third column), and includes the pixel 230e spanning from the second column to the third column.

[0442] Figure 32KAn example is shown in which one pixel 240 is formed using sub-pixels arranged in three rows and two columns.

[0443] Figure 32K The pixel 240 shown includes a pixel 230a in the upper row (first row) of the pixel 240, a pixel 230b in the middle row (second row), a pixel 230c spanning from the first row to the second row, and two sub-pixels (pixel 230d and pixel 230e) in the lower row (third row). In other words, the pixel 240 includes a pixel 230a, a pixel 230b, and a pixel 230d in the left column (first column), and includes a pixel 230c and a pixel 230e in the right column (second column).

[0444] exist Fig.32J and Figure 32K In the pixels 240 shown, for example, preferably, the pixel 230a is a sub-pixel R emitting red light, the pixel 230b is a sub-pixel G emitting green light, and the pixel 230c is a sub-pixel B emitting blue light. Fig.32J In the pixel 240 shown in FIG. 1 , the sub-pixels are arranged in a stripe pattern, so the display quality can be improved. Figure 32K In the pixel 240 shown, the layout of the sub-pixels is a so-called S-stripe arrangement, so that the display quality can be improved.

[0445] exist Fig.32J and Figure 32K In each pixel 240 shown, for example, a sub-pixel S including a light-receiving device may also be used as at least one of the pixel 230d and the pixel 230e. When a light-receiving device is used in both the pixel 230d and the pixel 230e, the structure of the light-receiving device may also be different from each other. For example, at least a portion of the wavelength region of the detected light may also be different from each other. Specifically, one of the pixel 230d and the pixel 230e may include a light-receiving device that mainly detects visible light, and the other may include a light-receiving device that mainly detects infrared light.

[0446] In addition, Fig.32J and Figure 32K In each pixel 240 shown, for example, a sub-pixel S including a light-receiving device may be used as one of the pixel 230d and the pixel 230e, and a sub-pixel including a light-emitting device that can be used as a light source may be used as the other. For example, a sub-pixel IR emitting infrared light may be used as one of the pixel 230d and the pixel 230e, and a sub-pixel S including a light-receiving device that detects infrared light may be used as the other.

[0447] In a pixel including sub-pixels R, G, B, IR, and S, images can be displayed using sub-pixels R, G, and B and sub-pixel IR can be used as a light source while sub-pixel S detects reflected light of infrared light emitted by sub-pixel IR.

[0448] As described above, in the display device of one embodiment of the present invention, various sub-pixel (pixel 230) layouts can be adopted as pixel 240. In addition, a structure including both a light-emitting device and a light-receiving device in pixel 240 can also be adopted. In this case, various layouts can also be adopted.

[0449] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0450] (Implementation 4) In this embodiment, a light-emitting device that can be used as the light-emitting element 61 is described.

[0451] like Fig.33A As shown in FIG. 1 , the light-emitting device includes an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 may be composed of a plurality of layers such as a layer 780, a light-emitting layer 771, and a layer 790.

[0452] The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

[0453] In the case where the lower electrode 761 and the upper electrode 762 are respectively the anode and the cathode, the layer 780 includes one or more of a layer containing a substance with high hole injection property (hole injection layer), a layer containing a substance with high hole transport property (hole transport layer), and a layer containing a substance with high electron blocking property (electron blocking layer). In addition, the layer 790 includes one or more of a layer containing a substance with high electron injection property (electron injection layer), a layer containing a substance with high electron transport property (electron transport layer), and a layer containing a substance with high hole blocking property (hole blocking layer). In the case where the lower electrode 761 and the upper electrode 762 are respectively the cathode and the anode, the structures of the layers 780 and 790 are reversed from the above.

[0454] The structure including the layer 780 disposed between a pair of electrodes, the light-emitting layer 771, and the layer 790 can be used as a single light-emitting unit. Fig.33A The structure is called a simple structure.

[0455] Fig.33B Show Fig.33A 1 is a modified example of the EL layer 763 included in the light-emitting device shown in FIG. Fig.33B The light-emitting device shown includes a layer 781 on a lower electrode 761 , a layer 782 on layer 781 , a light-emitting layer 771 on layer 782 , a layer 791 on light-emitting layer 771 , a layer 792 on layer 791 , and an upper electrode 762 on layer 792 .

[0456] When the lower electrode 761 and the upper electrode 762 are respectively an anode and a cathode, for example, the layers 781, 782, 791, and 792 may be respectively a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In addition, when the lower electrode 761 and the upper electrode 762 are respectively a cathode and an anode, the layers 781, 782, 791, and 792 may be respectively an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer. By adopting the above-mentioned layer structure, carriers can be efficiently injected into the light-emitting layer 771, thereby improving the efficiency of the recombination of carriers in the light-emitting layer 771.

[0457] In addition, if Fig.33C and Fig.33D As shown in FIG. 1 , a structure in which a plurality of light-emitting layers (light-emitting layers 771, 772, and 773) are provided between layer 780 and layer 790 is also a modified example of a single structure. Fig.33C and Fig.33D An example including three light-emitting layers is shown, but the light-emitting layers in the light-emitting device with a single structure may be two layers, or may be four or more layers. In addition, the light-emitting device with a single structure may also include a buffer layer between the two light-emitting layers. The buffer layer may use, for example, a carrier transport layer (hole transport layer and electron transport layer).

[0458] In addition, if Fig.33E and Fig.33F As shown, in this specification, a structure in which multiple light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785 (also referred to as an intermediate layer) is referred to as a series structure. In addition, the series structure may also be referred to as a stacked structure. By adopting a series structure, a light-emitting device capable of emitting light with high brightness can be realized. In addition, the series structure can improve reliability because it can reduce the current required to obtain the same brightness compared to a single structure.

[0459] Fig.33D and Fig.33F An example is shown in which the display device includes a layer 764 overlapping the light-emitting device. Fig.33D Layer 764 is shown overlapping Fig.33C The example of the light emitting device shown, Fig.33F Layer 764 is shown overlapping Fig.33E An example of a light emitting device is shown. Fig.33D and Fig.33F In the embodiment, the upper electrode 762 uses a conductive film that transmits visible light to extract light to the upper electrode 762 side.

[0460] As the layer 764, one or both of a color conversion layer and a color filter (coloring layer) can be used.

[0461] exist Fig.33C and Fig.33D In the embodiment, a luminescent material that emits light of the same color, or even the same luminescent material, may be used for the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773. For example, a luminescent material that emits blue light may be used for the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773. For a sub-pixel that emits blue light, the blue light emitted by the light-emitting device may be extracted. In addition, for a sub-pixel that emits red light and a sub-pixel that emits green light, by using Fig.33D The layer 764 shown is provided with a color conversion layer, which can convert the blue light emitted by the light-emitting device into light with a longer wavelength and extract it as red light or green light. In addition, it is preferred to use both a color conversion layer and a coloring layer as the layer 764. A part of the light emitted by the light-emitting device sometimes passes through without being converted by the color conversion layer. By extracting the light that passes through the color conversion layer through the coloring layer, the color purity of the light presented by the sub-pixel can be improved by absorbing light other than the desired color light by the coloring layer.

[0462] exist Fig.33C and Fig.33D In the embodiment, luminescent materials emitting light of different colors may be used for the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773. When the light emitted by the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773 is in a complementary color relationship, white light emission can be obtained. For example, a light-emitting device having a single structure preferably includes a luminescent layer containing a luminescent material emitting blue light and a luminescent layer containing a luminescent material emitting visible light having a wavelength longer than blue.

[0463] As Fig.33D The layer 764 shown may also be provided with a color filter, and light of a desired color may be obtained by passing white light through the color filter.

[0464] For example, in the case where a light-emitting device having a single structure includes three light-emitting layers, it is preferred to include a light-emitting layer containing a light-emitting substance that emits red (R) light, a light-emitting layer containing a light-emitting substance that emits green (G) light, and a light-emitting layer containing a light-emitting substance that emits blue (B) light. As the stacking order of the light-emitting layers, the order of stacking R, G, and B in sequence from the anode side or the order of stacking R, B, and G in sequence from the anode side can be adopted. At this time, a buffer layer can also be provided between R and G or B.

[0465] For example, when a light-emitting device having a single structure includes two light-emitting layers, it is preferable to adopt a structure including a light-emitting layer containing a light-emitting substance emitting blue (B) light and a light-emitting layer containing a light-emitting substance emitting yellow (Y) light. This structure is sometimes called a BY single structure.

[0466] A light-emitting device that emits white light preferably includes two or more light-emitting substances. In order to obtain white light emission, the light-emitting substances may be selected in such a way that the light emission of the two or more light-emitting substances is in a complementary color relationship. For example, by making the light emission color of the first light-emitting layer and the light emission color of the second light-emitting layer in a complementary color relationship, a light-emitting device that emits white light as a whole can be obtained. In addition, the same is true for a light-emitting device including three or more light-emitting layers.

[0467] Notice, Fig.33C , Fig.33D The layers 780 and 790 in the embodiment may also be independently selected. Fig.33B The laminated structure shown is composed of two or more layers.

[0468] exist Fig.33E and Fig.33F In the embodiment, a luminescent material that emits light of the same color, or even the same luminescent material, may be used for the luminescent layer 771 and the luminescent layer 772. For example, in a luminescent device included in a sub-pixel that presents light of each color, a luminescent material that emits blue light may be used for the luminescent layer 771 and the luminescent layer 772. For a sub-pixel that presents blue light, the blue light emitted by the luminescent device can be extracted. In addition, for a sub-pixel that presents red light and a sub-pixel that presents green light, by using Fig.33F The layer 764 shown is provided with a color conversion layer, which can convert the blue light emitted by the light-emitting device into light with a longer wavelength and extract it as red light or green light. In addition, it is preferable to use both a color conversion layer and a coloring layer as the layer 764.

[0469] In the Fig.33E or Fig.33F When the light-emitting device of the structure shown is used to present sub-pixels of each color, different light-emitting materials can be used according to the sub-pixels. Specifically, in the light-emitting device included in the sub-pixel presenting red light, the light-emitting material that emits red light can also be used for the light-emitting layer 771 and the light-emitting layer 772. Similarly, in the light-emitting device included in the sub-pixel presenting green light, the light-emitting material that emits green light can also be used for the light-emitting layer 771 and the light-emitting layer 772. In the light-emitting device included in the sub-pixel presenting blue light, the light-emitting material that emits blue light can also be used for the light-emitting layer 771 and the light-emitting layer 772. It can be said that the display device with such a structure uses a light-emitting device with a series structure and has an SBS structure. Thus, it has the advantages of both the series structure and the SBS structure. Thus, a light-emitting device with high brightness and high reliability can be realized.

[0470] In addition, Fig.33E and Fig.33FIn the embodiment, luminescent materials that emit light of different colors may be used for the luminescent layer 771 and the luminescent layer 772. When the light emitted by the luminescent layer 771 and the light emitted by the luminescent layer 772 are in a complementary color relationship, white light emission can be obtained. Fig.33F The layer 764 shown may also be provided with a color filter. By passing white light through the color filter, light of a desired color may be obtained.

[0471] Note that although Fig.33E and Fig.33F The example in which the light-emitting unit 763a includes one light-emitting layer 771 and the light-emitting unit 763b includes one light-emitting layer 772 is shown, but the present invention is not limited thereto. The light-emitting unit 763a and the light-emitting unit 763b may each include two or more light-emitting layers.

[0472] Although Fig.33E and Fig.33F The light emitting device including two light emitting units is shown as an example, but is not limited thereto. The light emitting device may also include more than three light emitting units. Note that the structure including two light emitting units and the structure including three light emitting units may also be referred to as a two-stage series structure and a three-stage series structure, respectively.

[0473] exist Fig.33E and Fig.33F In the embodiment, the light emitting unit 763a includes a layer 780a, a light emitting layer 771, and a layer 790a, and the light emitting unit 763b includes a layer 780b, a light emitting layer 772, and a layer 790b.

[0474] In the case where the lower electrode 761 and the upper electrode 762 are respectively an anode and a cathode, the layers 780a and 780b each include one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, the layers 790a and 790b each include one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. In the case where the lower electrode 761 and the upper electrode 762 are respectively a cathode and an anode, the structures of the layers 780a and 790a are reversed from the above, and the structures of the layers 780b and 790b are also reversed from the above.

[0475] In the case where the lower electrode 761 and the upper electrode 762 are respectively the anode and the cathode, for example, the layer 780a includes a hole injection layer and a hole transport layer on the hole injection layer, and may also include an electron blocking layer on the hole transport layer. In addition, the layer 790a includes an electron transport layer, and may also include a hole blocking layer between the light-emitting layer 771 and the electron transport layer. In addition, the layer 780b includes a hole transport layer, and may also include an electron blocking layer on the hole transport layer. In addition, the layer 790b includes an electron transport layer and an electron injection layer on the electron transport layer, and may also include a hole blocking layer between the light-emitting layer 772 and the electron transport layer. In the case where the lower electrode 761 and the upper electrode 762 are respectively the cathode and the anode, for example, the layer 780a includes an electron injection layer and an electron transport layer on the electron injection layer, and may also include a hole blocking layer on the electron transport layer. In addition, the layer 790a includes a hole transport layer, and may also include an electron blocking layer between the light-emitting layer 771 and the hole transport layer. In addition, layer 780b includes an electron transport layer and may also include a hole blocking layer on the electron transport layer. In addition, layer 790b includes a hole transport layer and a hole injection layer on the hole transport layer and may also include an electron blocking layer between the light emitting layer 772 and the hole transport layer.

[0476] When manufacturing a light-emitting device having a tandem structure, two light-emitting units are stacked via a charge generation layer 785. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes.

[0477] As an example of a tandem structure light emitting element, there can be cited FIG. 34A to FIG. 34C The structure shown.

[0478] Fig.34A FIG. 4 shows a structure including three light emitting units. Fig.34A In the embodiment, a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series with each other via a charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b, and light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c. Note that layer 780c may adopt a structure applicable to layer 780a and layer 780b, and layer 790c may adopt a structure applicable to layer 790a and layer 790b.

[0479] exist Fig.34AIn the embodiment, the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 preferably contain a light-emitting substance that emits light of the same color. Specifically, the following structures can be adopted: a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a red (R) light-emitting substance (so-called R\R\R three-stage tandem structure); a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a green (G) light-emitting substance (so-called G\G\G three-stage tandem structure); or a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a blue (B) light-emitting substance (so-called B\B\B three-stage tandem structure). Note that "a\b" means that a light-emitting unit containing a light-emitting substance that emits light a is provided with a light-emitting unit containing a light-emitting substance that emits light b via a charge generation layer, and a and b represent colors.

[0480] exist Fig.34A In the embodiment, light-emitting materials that emit light of different colors may be used for part or all of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. As a combination of light-emitting colors of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773, for example, a structure in which any two of them are blue (B) and the remaining one is yellow (Y) and a structure in which any one of them is red (R), another one is green (G), and the remaining one is blue (B) can be cited.

[0481] Note that the light-emitting materials that emit the same color are not limited to the above structures. Fig.34B As shown, a tandem light emitting device in which light emitting units including a plurality of light emitting layers are stacked may also be used. Fig.34B In the embodiment, two light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771a, light-emitting layer 771b, light-emitting layer 771c, and layer 790a, and light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b.

[0482] exist Fig.34B In the embodiment, the luminescent materials of the luminescent layer 771a, the luminescent layer 771b, and the luminescent layer 771c are selected to be in a complementary color relationship, so that the luminescent unit 763a has a structure capable of achieving white luminescence (W). In addition, the luminescent materials of the luminescent layer 772a, the luminescent layer 772b, and the luminescent layer 772c are also selected to be in a complementary color relationship, so that the luminescent unit 763b has a structure capable of achieving white luminescence (W). That is, Fig.34BThe structure shown is a W\W two-stage series structure. Note that there is no particular restriction on the stacking order of the luminescent materials in a complementary color relationship. The implementer can appropriately select the most appropriate stacking order. Although not shown in the figure, a W\W\W three-stage series structure or a series structure of four or more stages can also be used.

[0483] In addition, when using a light-emitting device with a series structure, examples include: a B\Y or Y\B two-stage series structure including a light-emitting unit emitting yellow (Y) light and a light-emitting unit emitting blue (B) light; an R·G\B or B\R·G two-stage series structure including a light-emitting unit emitting red (R) light and green (G) light and a light-emitting unit emitting blue (B) light; a B\Y\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting yellow (Y) light, and a light-emitting unit emitting blue (B) light in sequence; a B\YG\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting yellow-green (YG) light, and a light-emitting unit emitting blue (B) light in sequence; and a B\G\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting green (G) light, and a light-emitting unit emitting blue (B) light in sequence, etc. Note that “a·b” means that one light-emitting unit includes a light-emitting substance that emits light of a and a light-emitting substance that emits light of b.

[0484] like Fig.34C As shown, a light-emitting unit including one light-emitting layer and a light-emitting unit including a plurality of light-emitting layers may also be combined.

[0485] Specifically, in Fig.34C In the structure shown, a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series with each other via a charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b, and light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c.

[0486] For example, in Fig.34C The structure shown can adopt a B\R·G·YG\B three-stage series structure, wherein the light-emitting unit 763a is a light-emitting unit that emits blue (B) light, the light-emitting unit 763b is a light-emitting unit that emits red (R) light, green (G) light and yellow-green (YG) light, and the light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0487] For example, as the number of layers and color sequence of the light-emitting unit, there can be cited a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and the light-emitting unit X are stacked, a three-stage structure in which B, Y and B are stacked, and a three-stage structure in which B, X and B are stacked. As the number of layers and color sequence of the light-emitting layer in the light-emitting unit X, there can be adopted a two-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R and G are stacked, or a three-stage structure in which R, G and R are stacked. In addition, another layer may be provided between two light-emitting layers.

[0488] Next, materials that can be used for the light-emitting device are described.

[0489] A conductive film that transmits visible light is used as the electrode on the light extraction side of the lower electrode 761 and the upper electrode 762. In addition, a conductive film that reflects visible light is preferably used as the electrode on the side that does not extract light. In addition, when the display device includes a light-emitting device that emits infrared light, it is preferred that a conductive film that transmits visible light and infrared light is used as the electrode on the light extraction side, and a conductive film that reflects visible light and infrared light is used as the electrode on the side that does not extract light.

[0490] Alternatively, a conductive film that transmits visible light may be used as the electrode on the side that does not extract light. In this case, the electrode is preferably arranged between the reflective layer and the EL layer 763. In other words, light emitted from the EL layer 763 can also be reflected by the reflective layer and extracted from the display device.

[0491] As the material for forming a pair of electrodes of the light-emitting device, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As the material, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys appropriately combined therewith can be cited. In addition, as the material, indium tin oxide (also referred to as In-Sn oxide, ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as the material, aluminum-containing alloys (aluminum alloys) such as alloys of aluminum, nickel and lanthanum (Al-Ni-La) and silver-containing alloys such as alloys of silver and magnesium and alloys of silver, palladium and copper (Ag-Pd-Cu, also referred to as APC) can be cited. Examples of the material include elements belonging to Group 1 or Group 2 of the periodic table that are not listed above (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0492] The light emitting device preferably adopts an optical microcavity resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light emitting device preferably includes an electrode that is transparent and reflective to visible light (semi-transmissive-semi-reflective electrode), and the other preferably includes an electrode that is reflective to visible light (reflective electrode). When the light emitting device has a microcavity structure, the light emitted from the light emitting layer can be resonated between the two electrodes, and the light emitted from the light emitting device can be increased.

[0493] The light transmittance of the electrode having visible light transmittance is 40% or more. For example, when using an electrode having visible light transmittance for a light-emitting device, it is preferred to use an electrode having a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more. The reflectivity of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0494] The light-emitting device includes at least a light-emitting layer. In addition, as a layer other than the light-emitting layer, the light-emitting device may also include a layer containing a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, an electron blocking material, a substance with high electron injection property, or a bipolar material (a substance with high electron transport property and hole transport property). For example, the light-emitting device may include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer in addition to the light-emitting layer.

[0495] The light emitting device may use a low molecular weight compound or a high molecular weight compound, and may also contain an inorganic compound. The layers constituting the light emitting device may be formed by a method such as evaporation (including vacuum evaporation), transfer, printing, inkjet, or coating.

[0496] The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange or red is appropriately used. In addition, as the light-emitting substance, a substance that emits near-infrared light can also be used.

[0497] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0498] Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0499] As phosphorescent materials, for example, there can be mentioned organic metal complexes (especially iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, a pyridine skeleton, organic metal complexes (especially iridium complexes) with phenylpyridine derivatives having electron-withdrawing groups as ligands, platinum complexes, rare earth metal complexes, and the like.

[0500] The light-emitting layer may also contain one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As one or more organic compounds, one or both of a substance with high hole transport (hole transport material) and a substance with high electron transport (electron transport material) may be used. As a hole transport material, the following substances with high hole transport that can be used for a hole transport layer may be used. As an electron transport material, the following substances with high electron transport that can be used for an electron transport layer may be used. In addition, as one or more organic compounds, a bipolar material or a TADF material may also be used.

[0501] For example, the light-emitting layer preferably includes a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, light emission by ExTET (Exciplex-Triplet Energy Transfer) utilizing energy transfer from the exciplex to the luminescent substance (phosphorescent material) can be efficiently obtained. By selecting a combination of exciplexes that form light emitting at a wavelength overlapping with the absorption band on the lowest energy side of the luminescent substance, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting device can be achieved simultaneously.

[0502] The hole injection layer is a layer containing a substance with high hole injection property, which injects holes from the anode into the hole transport layer. Examples of substances with high hole injection property include aromatic amine compounds and composite materials containing a hole transport material and an acceptor material (electron acceptor material).

[0503] As the hole transport material, the following substances having high hole transport properties that can be used in the hole transport layer can be used.

[0504] As the acceptor material, for example, an oxide of a metal belonging to Group 4 to Group 8 of the periodic table can be used. Specifically, molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide and rhenium oxide can be cited. Molybdenum oxide is particularly preferably used because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle. In addition, an organic acceptor material containing fluorine can also be used. In addition to the above, organic acceptor materials such as quinone dimethane derivatives, tetrachlorobenzoquinone derivatives and hexaazatriphenylene derivatives can also be used.

[0505] For example, as the substance having a high hole injecting property, a material including a hole transport material and an oxide of the metal belonging to Group 4 to Group 8 of the periodic table (typically molybdenum oxide) can be used.

[0506] The hole transport layer is a layer that transports holes injected from the anode through the hole injection layer to the light-emitting layer. The hole transport layer is a layer containing a hole transport material. As the hole transport material, preferably a hole transport material having a hole mobility of 1×10 -6 cm 2 / Vs or more. Note that as long as the hole transport property is higher than the electron transport property, substances other than the above can be used. As hole transport materials, it is preferred to use substances with high hole transport properties such as π-electron-rich heteroaromatic compounds (such as carbazole derivatives, thiophene derivatives, furan derivatives, etc.) or aromatic amines (compounds having an aromatic amine skeleton).

[0507] The electron blocking layer is provided in contact with the light emitting layer. The electron blocking layer is a layer having hole transport properties and containing a material capable of blocking electrons. The electron blocking material among the hole transport materials can be used for the electron blocking layer.

[0508] The electron blocking layer has a hole transporting property, so it can also be called a hole transporting layer. In addition, the layer having an electron blocking property in the hole transporting layer can also be called an electron blocking layer.

[0509] The electron transport layer is a layer that transports electrons injected from the cathode through the electron injection layer to the light-emitting layer. The electron transport layer is a layer containing an electron transport material. As the electron transport material, it is preferred to use an electron transport material with an electron mobility of 1×10 -6 cm 2 / Vs or above. Note that as long as the electron transport property is higher than the hole transport property, substances other than the above can be used. As electron transport materials, metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, or metal complexes having a thiazole skeleton can be used. Substances with high electron transport properties such as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives with quinoline ligands, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, or nitrogen-containing heteroaromatic compounds and other π-electron-deficient heteroaromatic compounds can also be used.

[0510] The hole blocking layer is provided in contact with the light emitting layer. The hole blocking layer is a layer having electron transport properties and containing a material capable of blocking holes. The hole blocking material among the above-mentioned electron transport materials can be used for the hole blocking layer.

[0511] The hole blocking layer has an electron transporting property, so it may also be called an electron transporting layer. In addition, the layer having a hole blocking property in the electron transporting layer may also be called a hole blocking layer.

[0512] The electron injection layer is a layer containing a substance with high electron injection property that injects electrons from the cathode into the electron transport layer. As a substance with high electron injection property, an alkali metal, an alkaline earth metal or a compound thereof can be used. As a substance with high electron injection property, a composite material containing an electron transport material and a donor material (electron donor material) can also be used.

[0513] It is preferable that the difference between the lowest unoccupied molecular orbital (LUMO) energy level of the substance having high electron injectability and the work function value of the material used for the cathode be small (specifically, 0.5 eV or less).

[0514] The electron injection layer can be made of, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF x , X is an arbitrary number), 8-(hydroxyquinoline) lithium (abbreviated as Liq), 2-(2-pyridyl) phenol lithium (abbreviated as LiPP), 2-(2-pyridyl)-3-hydroxypyridine (pyridinolato) lithium (abbreviated as LiPPy), 4-phenyl-2-(2-pyridyl) phenol lithium (abbreviated as LiPPP), lithium oxide (LiO x ) or alkali metals such as cesium carbonate, alkaline earth metals or their compounds. In addition, the electron injection layer can also have a stacked structure of more than two layers. As this stacked structure, for example, a structure in which lithium fluoride is used as the first layer and ytterbium is provided as the second layer can be cited.

[0515] The electron injection layer may also contain an electron transport material. For example, a compound having a non-shared electron pair and an electron-deficient heteroaromatic ring may be used as the electron transport material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring) and a triazine ring may be used.

[0516] The LUMO energy level of an organic compound having an unshared electron pair is preferably greater than -3.6 eV and less than -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) energy level and the LUMO energy level of an organic compound can be estimated using CV (cyclic voltammetry), photoelectron spectroscopy, absorption spectroscopy, or inverse photoelectron spectroscopy.

[0517] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalene-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as the organic compound having a non-shared electron pair. In addition, NBPhen has a high glass transition point (Tg) compared to BPhen, thereby having high heat resistance.

[0518] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably includes an acceptor material, for example, preferably includes a hole transport material and an acceptor material that can be used in the hole injection layer.

[0519] The charge generation layer preferably includes a layer containing a substance with high electron injection. This layer may also be referred to as an electron injection buffer layer. The electron injection buffer layer is preferably disposed between the charge generation region and the electron transport layer. By providing an electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be relaxed, so that the electrons generated in the charge generation region are easily injected into the electron transport layer.

[0520] The electron injection buffer layer preferably comprises an alkali metal or an alkaline earth metal, for example, a compound of an alkali metal or a compound of an alkaline earth metal. Specifically, the electron injection buffer layer preferably comprises an inorganic compound containing an alkali metal and oxygen or an inorganic compound containing an alkaline earth metal and oxygen, more preferably an inorganic compound containing lithium and oxygen (lithium oxide (Li2O) etc.). In addition, as the electron injection buffer layer, a material applicable to the above-mentioned electron injection layer can be appropriately used.

[0521] The charge generation layer preferably includes a layer containing a substance with high electron transportability. This layer may also be referred to as an electron relay layer. The electron relay layer is preferably disposed between the charge generation region and the electron injection buffer layer. When the charge generation layer does not include an electron injection buffer layer, the electron relay layer is preferably disposed between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing the interaction between the charge generation region and the electron injection buffer layer (or electron transport layer) and smoothly transferring electrons.

[0522] As the electron relay layer, it is preferable to use a phthalocyanine material such as copper (II) phthalocyanine (abbreviation: CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0523] Note that the charge generation region, the electron injection buffer layer, and the electron relay layer may not be clearly distinguished from each other due to their cross-sectional shape, characteristics, or the like.

[0524] In addition, the charge generation layer may include a donor material instead of an acceptor material. For example, the charge generation layer may include a layer containing an electron transport material applicable to the electron injection layer and a donor material.

[0525] When stacking light-emitting units, by providing a charge generation layer between two light-emitting units, an increase in driving voltage can be suppressed.

[0526] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0527] (Implementation method 5) In this embodiment, a configuration example of the light emitting element 61 for realizing full-color display in the display device 200 is described.

[0528] The plurality of light emitting elements 61 provided in the display portion 235 of the display device 200 can be formed by photolithography without using a shadow mask such as a metal mask. Therefore, a display device having high definition and high aperture ratio, which is difficult to achieve at present, can be realized. In addition, leakage current between adjacent EL layers is reduced, so that a display device having very clear, high contrast and high display quality can be realized.

[0529] For example, in the formation method using a metal mask, it is difficult to achieve a distance between adjacent light-emitting elements 61 of less than 10 μm, but by using a photolithography method, the distance can be reduced to less than 8 μm, less than 3 μm, less than 2 μm, or less than 1 μm. Here, the distance between adjacent light-emitting elements 61 can be specified based on the distance between the ends of two adjacent pixel electrodes. Alternatively, the distance between adjacent light-emitting elements 61 can be specified based on the distance between the ends of two adjacent EL layers.

[0530] In this specification, etc., a display device manufactured using a metal mask or FMM (Fine Metal Mask) is sometimes referred to as a display device having an MM (Metal Mask) structure. In addition, in this specification, etc., a display device manufactured without using a metal mask or FMM is sometimes referred to as a display device having an MML (Metal Mask Less) structure.

[0531] By reducing the distance between adjacent light emitting elements 61, the area of ​​the non-light emitting region that may exist between two light emitting elements can be greatly reduced, and the aperture ratio can be close to 100%. For example, an aperture ratio of more than 50%, more than 60%, more than 70%, more than 80%, or even more than 90% and less than 100% can be achieved.

[0532] In addition, the pattern of the EL layer itself (also referred to as the processing size) can also be significantly reduced compared to the case of using a metal mask. In addition, for example, when the EL layer is formed separately using a metal mask, the thickness of the center and the end of the EL layer is different, so the effective area that can be used as the light-emitting area relative to the area of ​​the EL layer becomes smaller. On the other hand, in the above-mentioned manufacturing method, the EL layer is formed by processing a film deposited to a uniform thickness, so the thickness of the EL layer can be made uniform, and almost all of its area can be used as a light-emitting area even if a fine pattern is used. Therefore, the above-mentioned manufacturing method can achieve both high definition and high aperture ratio.

[0533] Most organic films formed using FMM (Fine Metal Mask) are films with extremely small taper angles (for example, greater than 0 degrees and less than 30 degrees) where the thickness decreases as it approaches the end. Therefore, the side of the organic film formed using FMM is continuously connected to the top surface, and it is difficult to clearly identify the side. On the other hand, one embodiment of the present invention includes an EL layer that is not processed using FMM, so it has a clear side. In particular, in one embodiment of the present invention, it is preferred to have a portion where the taper angle of the EL layer is greater than 30 degrees and less than 120 degrees, and preferably a portion where the taper angle is greater than 60 degrees and less than 120 degrees.

[0534] Note that in this specification, etc., the tapered shape of the end of an object means that the angle between the side surface (surface) and the formed surface (bottom surface) in the region of the end is greater than 0 degrees and less than 90 degrees, and the object has a cross-sectional shape in which the thickness continuously increases from the end. In addition, the taper angle refers to the angle between the bottom surface (formed surface) and the side surface (surface) of the end of the object.

[0535] A more specific structural example is described below.

[0536] Fig.35AA top view schematic diagram showing a part of the display unit 235 included in the display device 200. The display device 200 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light on a substrate 101 including a semiconductor circuit. In Fig.35A order to simply distinguish each light-emitting element, symbols R, G, and B are attached to the light-emitting regions of the respective light-emitting elements. The substrate 101 is the substrate on which the semiconductor device shown in the above embodiment is formed, and the detailed content can be referred to the description of the above embodiment. Note that the description of the semiconductor device provided on the substrate 101 is omitted in FIG. 35.

[0537] The light-emitting elements 61R, the light-emitting elements 61G, and the light-emitting elements 61B are all arranged in a stripe shape. Fig.35A A structure in which two elements are alternately arranged in one direction is shown. Note that the arrangement method of the light-emitting elements is not limited to this, and arrangement methods such as S stripe arrangement, Delta arrangement, Bayer arrangement, or zigzag arrangement can be used, and Pentile arrangement or Diamond arrangement can also be used.

[0538] In addition, Fig.35A a connection electrode 311C electrically connected to the common electrode 313 is shown. The connection electrode 311C is supplied with a potential (for example, an anode potential or a cathode potential) to be supplied to the common electrode 313. The connection electrode 311C is provided outside the display region where the light-emitting elements 61R and the like are arranged. In addition, in Fig.35A the common electrode 313 is indicated by a dotted line.

[0539] The connection electrode 311C can be provided along the outer periphery of the display region. For example, it can be provided along one side of the outer periphery of the display region, or can straddle two or more sides of the outer periphery of the display region. That is, in the case where the top surface shape of the display region is rectangular, the top surface shape of the connection electrode 311C can be strip-shaped, L-shaped, "冂"-shaped (bracket-shaped), or quadrangular.

[0540] Fig.35B is a cross-sectional schematic diagram corresponding to the dotted lines A1 - A2 and C1 - C2 in Fig.35A . Fig.35B is a cross-sectional schematic diagram of the light-emitting element 61B, the light-emitting element 61R, the light-emitting element 61G, and the connection electrode 311C.

[0541] The light emitting element 61B includes a pixel electrode 311, an organic layer 312B, an organic layer 314, and a common electrode 313. The light emitting element 61R includes a pixel electrode 311, an organic layer 312R, an organic layer 314, and a common electrode 313. The light emitting element 61G includes a pixel electrode 311, an organic layer 312G, an organic layer 314, and a common electrode 313. The organic layer 314 and the common electrode 313 are provided in common in the light emitting element 61B, the light emitting element 61R, and the light emitting element 61G. The organic layer 314 can also be said to be a common layer. The pixel electrode 311 is provided between each light emitting element away from each other.

[0542] The organic layer 312R, the organic layer 312G, and the organic layer 312B correspond to the EL layer 763 in the above embodiment.

[0543] The organic layer 312R includes a light-emitting organic compound that emits light having an intensity at least in the red wavelength region. The organic layer 312G includes a light-emitting organic compound that emits light having an intensity at least in the green wavelength region. The organic layer 312B includes a light-emitting organic compound that emits light having an intensity at least in the blue wavelength region. The organic layer 312R, the organic layer 312G, and the organic layer 312B may also be referred to as an EL layer.

[0544] The organic layer 312R, the organic layer 312B, and the organic layer 312G may further include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. The organic layer 314 may have a structure that does not include a light-emitting layer. For example, the organic layer 314 includes one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0545] Here, the uppermost layer in the stacked structure of the organic layer 312R, the organic layer 312B, and the organic layer 312G, that is, the layer in contact with the organic layer 314, is preferably a layer other than the light-emitting layer. For example, it is preferred to adopt a structure in which an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, or a layer other than these is provided to cover the light-emitting layer and to make the layer contact with the organic layer 314. In this way, when manufacturing each light-emitting element, the top surface of the light-emitting layer is protected by other layers, thereby improving the reliability of the light-emitting element.

[0546] By processing each EL layer using photolithography, the distance between each pixel can be reduced to less than 8μm, less than 3μm, less than 2μm, or less than 1μm. Here, the distance between each pixel can be specified, for example, based on the distance between the opposite ends of the organic layer 312B and the organic layer 312R, the distance between the opposite ends of the organic layer 312B and the organic layer 312G, and the distance between the opposite ends of the organic layer 312R and the organic layer 312G. Alternatively, it can be specified based on the distance between the opposite ends of adjacent EL layers of the same color. Alternatively, it can be specified based on the distance between the opposite ends of adjacent pixel electrodes 311. In this way, by reducing the distance between each pixel, a display device with high definition and high aperture ratio can be provided.

[0547] The pixel electrodes 311 are respectively arranged in each element. In addition, the common electrode 313 and the organic layer 314 are arranged as a continuous layer commonly used by each light-emitting element. A conductive film having light transmittance to visible light is used on one side of each pixel electrode and the common electrode 313, and a conductive film having reflectivity is used on the other side. By making each pixel electrode light transmittance and making the common electrode 313 reflective, a bottom emission type (bottom emission structure) display device can be realized. In contrast, by making each pixel electrode reflective and making the common electrode 313 light transmittance, a top emission type (top emission structure) display device can be realized. In addition, by making both the pixel electrode and the common electrode 313 light transmittance, a double-sided emission type (double-sided emission structure) display device can be realized.

[0548] The pixel electrode 311 is electrically connected to a transistor in a semiconductor circuit provided on the substrate 101. As shown in the above embodiment, the channel length of the transistor provided on the substrate 101 is reduced and miniaturized. Therefore, even if the display device is made high-definition and the pixel area is reduced as described above, the pixel circuit can be accommodated in the reduced pixel area.

[0549] An insulating layer 331 is provided to cover the end of the pixel electrode 311. The end of the insulating layer 331 preferably has a tapered shape. Note that in this specification, etc., "the end of the object has a tapered shape" means that the object has a cross-sectional shape in which the angle formed by the surface and the formed surface in the region of the end is greater than 0° and less than 90°; and the thickness gradually increases from the end.

[0550] In addition, by using an organic resin for the insulating layer 331, the surface thereof can have a gently curved surface. Therefore, the coverage of a film formed on the insulating layer 331 can be improved.

[0551] As a material that can be used for the insulating layer 331 , for example, acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be used.

[0552] Alternatively, an inorganic insulating material may be used for the insulating layer 331. As the inorganic insulating material that can be used for the insulating layer 331, for example, oxides or nitrides such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide may be used. In addition, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, and neodymium oxide may also be used.

[0553] like Fig.35B As shown, two organic layers are provided between light-emitting elements of different light-emitting colors, with a gap therebetween. Thus, the organic layer 312R, the organic layer 312B, and the organic layer 312G are preferably provided in a non-contact manner. Thus, it is suitable to prevent the current from flowing through two adjacent organic layers and generating unintended light emission. Thus, the contrast can be improved, and a display device with higher display quality can be realized.

[0554] The cone angle of the organic layer 312R, the organic layer 312B, and the organic layer 312G is preferably 30 degrees or more. The angle between the side surface (surface) and the bottom surface (formed surface) of the end of the organic layer 312R, the organic layer 312G, and the organic layer 312B is preferably 30 degrees or more and 120 degrees or less, more preferably 45 degrees or more and 120 degrees or less, and further preferably 60 degrees or more and 120 degrees or more. Alternatively, the cone angles of the organic layer 312R, the organic layer 312G, and the organic layer 312B are preferably 90 degrees or thereabouts (for example, 80 degrees or more and 100 degrees or less).

[0555] A protective layer 321 is provided on the common electrode 313. The protective layer 321 has a function of preventing impurities such as water from diffusing from above toward each light emitting element.

[0556] The protective layer 321 may have, for example, a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used as the protective layer 321.

[0557] In addition, a laminated film of an inorganic insulating film and an organic insulating film can also be used as the protective layer 321. For example, it is preferred to sandwich an organic insulating film between a pair of inorganic insulating films. In addition, the organic insulating film is preferably used as a planarization layer. Therefore, the top surface of the organic insulating film can be made flat, so the coverage of the inorganic insulating film thereon is improved, thereby improving the barrier properties. In addition, the top surface of the protective layer 321 becomes flat, so when a structure (for example, a color filter, an electrode or a lens array of a touch sensor, etc.) is set above the protective layer 321, the influence of the concave-convex shape caused by the lower structure can be reduced, so it is preferred.

[0558] In the connection portion 330, a common electrode 313 is provided on the connection electrode 311C to be in contact therewith, and a protective layer 321 is provided to cover the common electrode 313. In addition, an insulating layer 331 is provided to cover the end of the connection electrode 311C.

[0559] The following pairs Fig.35B Specifically, an example in which the insulating layer 331 is not provided is shown.

[0560] FIG. 36A to FIG. 36C An example is shown in which the side surface of the pixel electrode 311 is substantially consistent with the side surface of the organic layer 312R, the organic layer 312B, or the organic layer 312G.

[0561] exist Fig.36A In the embodiment, an organic layer 314 is provided to cover the top and side surfaces of the organic layer 312R, the organic layer 312B, and the organic layer 312G. The organic layer 314 can prevent the pixel electrode 311 and the common electrode 313 from contacting each other and causing an electrical short circuit.

[0562] Fig.36B The example shown includes an insulating layer 325 provided in contact with the organic layers 312R, 312B, 312G, and the side of the pixel electrode 311. The insulating layer 325 can effectively prevent the pixel electrode 311 and the common electrode 313 from being electrically short-circuited and leakage current therebetween.

[0563] The insulating layer 325 may be an insulating layer containing an inorganic material. As the insulating layer 325, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used. The insulating layer 325 may have a single-layer structure or a stacked-layer structure. As the oxide insulating film, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film may be cited. As the nitride insulating film, a silicon nitride film and an aluminum nitride film may be cited. As the oxynitride insulating film, an oxynitride silicon film and an oxynitride aluminum film may be cited. As the nitride oxide insulating film, a nitride oxide silicon film and an oxynitride aluminum film may be cited. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method for the insulating layer 325 , the insulating layer 325 can have fewer pinholes and an excellent function of protecting an organic layer.

[0564] The insulating layer 325 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. Preferably, the insulating layer 325 is formed by an ALD method having excellent coverage.

[0565] exist Fig.36C In the embodiment, a resin layer 326 is provided between two adjacent light emitting elements to fill the gap between two opposing pixel electrodes and the gap between two opposing organic layers. The resin layer 326 can flatten the formed surface of the organic layer 314, the common electrode 313, etc., and can prevent the common electrode 313 from being disconnected due to poor coverage of the step between adjacent light emitting elements.

[0566] As the resin layer 326, an insulating layer containing an organic material can be suitably used. For example, as the resin layer 326, acrylic resin, epoxy resin, polyimide, polyamide, polyimide amide, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can be used. In addition, as the resin layer 326, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide can also be used. In addition, as the resin layer 326, a photosensitive resin can also be used. As the photosensitive resin, a photoresist can also be used. As the photosensitive resin, a positive material or a negative material can also be used.

[0567] In addition, by using a colored material (for example, a material containing a black pigment) as the resin layer 326, a function of shielding stray light from adjacent pixels and suppressing color mixing may be added.

[0568] exist Fig.36DIn the embodiment, an insulating layer 325 and a resin layer 326 are provided on the insulating layer 325. Since the insulating layer 325 does not contact the organic layer 312R and the resin layer 326, impurities such as moisture in the resin layer 326 can be prevented from diffusing into the organic layer 312R and the like, thereby providing a highly reliable display device.

[0569] In addition, a mechanism may be provided in which a reflective film (for example, a metal film comprising one or more selected from silver, palladium, copper, titanium and aluminum) is provided between the insulating layer 325 and the resin layer 326 so that the reflective film reflects light emitted by the light-emitting layer to improve light extraction efficiency.

[0570] FIG. 37A to FIG. 37C The example in which the width of the pixel electrode 311 is larger than the width of the organic layer 312R, the organic layer 312B, or the organic layer 312G is shown. The organic layer 312R and the like are located inside the end of the pixel electrode 311 .

[0571] Fig.37A The example in which the insulating layer 325 is included is shown. The insulating layer 325 is provided so as to cover the side surfaces of the organic layer included in the light-emitting element and a part of the top surface and the side surfaces of the pixel electrode 311.

[0572] Fig.37B An example is shown in which a resin layer 326 is included. The resin layer 326 is located between two adjacent light-emitting elements and is provided so as to cover the side surfaces of the organic layer and the top surface and side surfaces of the pixel electrode 311 .

[0573] Fig.37C An example is shown in which both the insulating layer 325 and the resin layer 326 are included. The insulating layer 325 is provided between the organic layer 312R and the resin layer 326 .

[0574] FIG. 38A to FIG. 38D The example in which the width of the pixel electrode 311 is smaller than the width of the organic layer 312R, the organic layer 312B, or the organic layer 312G is shown. The organic layer 312R and the like extend to the outside beyond the end portion of the pixel electrode 311 .

[0575] Fig.38B The example includes an insulating layer 325. The insulating layer 325 is provided in contact with the side surfaces of the organic layers of two adjacent light-emitting elements. In addition, the insulating layer 325 may be provided to cover not only the side surfaces of the organic layer 312R, etc. but also a part of the top surface thereof.

[0576] Fig.38C The example including the resin layer 326 is shown. The resin layer 326 is located between two adjacent light emitting elements and is provided so as to cover the side surfaces and a part of the top surface of the organic layer 312R, etc. Alternatively, the resin layer 326 may be in contact with the side surfaces of the organic layer 312R, etc. without covering the top surface.

[0577] Fig.38D An example is shown in which both the insulating layer 325 and the resin layer 326 are included. The insulating layer 325 is provided between the organic layer 312R and the resin layer 326 .

[0578] Here, a structural example of the resin layer 326 will be described.

[0579] The top surface of the resin layer 326 is preferably as flat as possible, but the surface of the resin layer 326 may be concave or convex depending on the concavo-convex shape of the surface on which the resin layer 326 is formed, the formation conditions of the resin layer 326, and the like.

[0580] FIG. 39A to FIG. 40F It is an enlarged view of an end portion of a pixel electrode 311R included in a light emitting element 61R, an end portion of a pixel electrode 311G included in a light emitting element 61G, and their vicinities.

[0581] Fig.39A , Fig.39B and Fig.39C An enlarged view of the resin layer 326 and its vicinity when the top surface of the resin layer 326 is flat is shown. Fig.39A An example is shown in which the width of the organic layer 312R and the like is larger than that of the pixel electrode 311 . Fig.39B An example is shown in which the widths of the pixel electrode 311 and the organic layer 312R and the like are substantially equal. Fig.39C An example is shown in which the width of the organic layer 312R and the like is smaller than that of the pixel electrode 311 .

[0582] like Fig.39A As shown, since the organic layer 312R and the like are provided to cover the end of the pixel electrode 311, the end of the pixel electrode 311 is preferably tapered. Thus, the step coverage of the organic layer 312R and the like can be improved, thereby providing a highly reliable display device.

[0583] Fig.39D , Fig.39E and Fig.39F An example is shown in which the top surface of the resin layer 326 is concave. Fig.39D , Fig.39E and Fig.39F Corresponding to Fig.39A , Fig.39B and Fig.39C At this time, the top surfaces of the organic layer 314 , the common electrode 313 , and the protective layer 321 have concave portions that reflect the concave top surface of the resin layer 326 .

[0584] Fig.40A , Fig.40B and Fig.40C An example is shown in which the top surface of the resin layer 326 is convex. Fig.40A, Fig.40B and Fig.40C Corresponding to Fig.39A , Fig.39B and Fig.39C At this time, convex portions reflecting the convex top surface of the resin layer 326 are formed on the top surfaces of the organic layer 314 , the common electrode 313 , and the protective layer 321 .

[0585] Fig.40D , Fig.40E and Fig.40F An example is shown in which a portion of the resin layer 326 covers a portion of the upper end portion and the top surface of the organic layer 312R and a portion of the upper end portion and the top surface of the organic layer 312G. Fig.40D , Fig.40E and Fig.40F Corresponding to Fig.39A , Fig.39B and Fig.39C At this time, an insulating layer 325 is provided between the resin layer 326 and the top surface of the organic layer 312R or the organic layer 312G.

[0586] in addition, Fig.40D , Fig.40E and Fig.40F An example is shown in which a part of the top surface of the resin layer 326 is concave. In this case, the organic layer 314 , the common electrode 313 , and the protective layer 321 are formed with concave and convex shapes reflecting the shape of the resin layer 326 .

[0587] The above is the description of the structural example of the resin layer.

[0588] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0589] (Implementation 6) In this embodiment, an electronic device to which a semiconductor device according to one embodiment of the present invention can be applied is described.

[0590] The semiconductor device of one embodiment of the present invention can be used in the display part of an electronic device. Thus, an electronic device with high display quality can be realized. Alternatively, an electronic device with extremely high precision can be realized. Alternatively, an electronic device with high reliability can be realized.

[0591] Electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and computers that reproduce and store data stored in DVDs (Digital Versatile Disc: digital versatile disc) and other recording media such as a still image or a moving image reproducing device, a portable CD player, a radio, a tape recorder, a headphone stereo, a stereo, a table clock, a wall clock, a cordless telephone handset, a radio transceiver, a car phone, a mobile phone, a portable information terminal, a tablet terminal, a portable game console, a fixed game console such as a pinball machine, a calculator, an electronic notebook, an e-book reader terminal, an electronic translator, a voice input device, a video camera, a digital still camera, an electric scraper, a microwave oven and other high-frequency heating device, an electric rice cooker, an electric washing machine, an electric vacuum cleaner, a water heater, an electric fan, an electric hair dryer, air conditioning equipment such as an air conditioner, a humidifier, a dehumidifier, etc., a dishwasher, a dishwashing machine, a dryer, a dryer, a quilt dryer, an electric refrigerator, an electric freezer, an electric freezer for storing DNA, tools such as a flashlight and a chain saw, a smoke detector, a dialysis device and other medical equipment, etc. Furthermore, industrial equipment such as guide lights, signal lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, power storage devices for power equalization and smart grids, etc. can also be cited. In addition, mobile bodies propelled by engines using fuel or electric motors using power from power storage bodies are sometimes included in the category of electronic equipment. As the above-mentioned mobile bodies, for example, electric vehicles (EV), hybrid vehicles (HV) with both internal combustion engines and electric motors, plug-in hybrid vehicles (PHV), tracked vehicles using tracks instead of wheels, bicycles with engines including electric-assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, airplanes, rockets, artificial satellites, space probes, planetary probes, spacecraft, etc. can be cited.

[0592] The electronic device according to one embodiment of the present invention may include a secondary battery (battery), and the secondary battery is preferably charged by contactless power transmission.

[0593] Examples of the secondary battery include lithium ion secondary batteries, nickel hydrogen batteries, nickel cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel zinc batteries, and silver zinc batteries.

[0594] The electronic device according to one embodiment of the present invention may also include an antenna. By receiving a signal with the antenna, an image or data can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0595] An electronic device according to one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0596] An electronic device according to one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0597] In addition, an electronic device including a plurality of display units may have a function of mainly displaying image information on a part of the display unit and mainly displaying text information on other parts of the display unit, or a function of displaying a three-dimensional image by displaying an image taking parallax into consideration on a plurality of display units, etc. Furthermore, an electronic device having an image receiving unit may have the following functions: capturing a still image; capturing a moving image; automatically or manually correcting the captured image; storing the captured image in a recording medium (external or built into the electronic device); displaying the captured image on the display unit; etc. In addition, the functions of an electronic device according to one embodiment of the present invention are not limited thereto, and the electronic device may have various functions.

[0598] A semiconductor device according to one embodiment of the present invention can display high-definition images. Therefore, it can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, etc. For example, it can be suitably used in xR devices such as VR devices or AR devices.

[0599] Fig.41A FIG. 8 is an external view of a camera 8000 equipped with a viewfinder 8100 .

[0600] The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. In addition, the camera 8000 is provided with a detachable lens 8006. In the camera 8000, the lens 8006 and the housing may be formed integrally.

[0601] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 serving as a touch panel.

[0602] The housing 8001 includes an embedder having electrodes, and can be connected to a flash device or the like in addition to the viewfinder 8100 .

[0603] The viewfinder 8100 includes a housing 8101 , a display portion 8102 , a button 8103 , and the like.

[0604] The housing 8101 is attached to the camera 8000 via an inserter that fits into the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on the display portion 8102.

[0605] Button 8103 is used as a power button or the like.

[0606] The semiconductor device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. Alternatively, the viewfinder 8100 may be built in the camera 8000.

[0607] Fig.41B This is an appearance diagram of the head mounted display 8200.

[0608] The head mounted display 8200 includes a mounting portion 8201 , a lens 8202 , a main body 8203 , a display portion 8204 , a cable 8205 , and the like. In addition, a battery 8206 is built in the mounting portion 8201 .

[0609] Power is supplied from a battery 8206 to a main body 8203 via a cable 8205. The main body 8203 includes a wireless receiver and the like, and can display received image information on a display portion 8204. In addition, the main body 8203 includes a camera, thereby making it possible to use information on the movement of the user's eyeballs or eyelids as an input method.

[0610] In addition, multiple electrodes may be provided at the position of the mounting portion 8201 touched by the user to detect the current flowing through the electrodes according to the movement of the user's eyeballs, thereby realizing the function of recognizing the user's line of sight. In addition, it may also have a function of monitoring the user's pulse according to the current flowing through the electrodes. The mounting portion 8201 may also have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, and may also have a function of displaying the user's biological information on the display portion 8204 or a function of changing the image displayed on the display portion 8204 in synchronization with the movement of the user's head.

[0611] The semiconductor device according to one embodiment of the present invention can be used for the display portion 8204 .

[0612] FIG. 41C to FIG. 41E 8300 is an external view of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a belt-shaped fixing tool 8304, and a pair of lenses 8305.

[0613] The user can see the display on the display unit 8302 through the lens 8305. Preferably, the display unit 8302 is arranged in a curved manner. This is because the user can experience a high sense of reality. In addition, the images displayed on different areas of the display unit 8302 are respectively seen through the lens 8305, so that three-dimensional display using parallax can be performed. In addition, one embodiment of the present invention is not limited to a structure in which one display unit 8302 is provided, and two display units 8302 can also be provided so that one display unit is respectively provided for a pair of eyes of the user.

[0614] A semiconductor device according to one embodiment of the present invention can be used for the display portion 8302. A semiconductor device according to one embodiment of the present invention can also achieve extremely high definition. Fig.41E As shown, even if the display is magnified and viewed using the lens 8305, the pixels are not easily visible to the user. That is, the display portion 8302 can be used to allow the user to see an image with a higher sense of reality.

[0615] Fig.41F 8400. The head mounted display 8400 includes a pair of housings 8401, a mounting portion 8402, and a buffer member 8403. A display portion 8404 and a lens 8405 are provided in each of the pair of housings 8401. By making the pair of display portions 8404 display different images, a three-dimensional display using parallax can be performed.

[0616] The user can see the display on the display unit 8404 through the lens 8405. The lens 8405 has a focus adjustment mechanism, and the focus adjustment mechanism can adjust the position of the lens 8405 according to the user's vision. The display unit 8404 is preferably a square or a horizontally long rectangle. This can improve the sens...

Claims

1. A semiconductor device comprising: a first semiconductor layer disposed on the insulating surface; a first insulating layer on the first semiconductor layer; a first conductive layer on the first insulating layer; a second conductive layer electrically connected to the first semiconductor layer; a third conductive layer electrically connected to the first semiconductor layer; a second insulating layer covering the first conductive layer, the second conductive layer and the third conductive layer; a third insulating layer on the second insulating layer; a fourth insulating layer on the third insulating layer; a fourth conductive layer on the fourth insulating layer; an opening penetrating the second insulating layer, the third insulating layer, the fourth insulating layer and the fourth conductive layer; a second semiconductor layer having an area covering the side and bottom of the opening; a fifth insulating layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer; as well as a fifth conductive layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, respectively; Wherein, the second semiconductor layer is electrically connected to the second conductive layer.

2. The semiconductor device according to claim 1, The second semiconductor layer has a region overlapping the first semiconductor layer via the second conductive layer.

3. A semiconductor device comprising: a first semiconductor layer disposed on the insulating surface; a first insulating layer on the first semiconductor layer; a first conductive layer on the first insulating layer; a second conductive layer electrically connected to the first semiconductor layer; a third conductive layer electrically connected to the first semiconductor layer; a second insulating layer covering the first conductive layer, the second conductive layer and the third conductive layer; a third insulating layer on the second insulating layer; a fourth insulating layer on the third insulating layer; a fourth conductive layer on the fourth insulating layer; an opening penetrating the second insulating layer, the third insulating layer, the fourth insulating layer and the fourth conductive layer; a second semiconductor layer having an area covering the side and bottom of the opening; a fifth insulating layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer; as well as a fifth conductive layer having a region overlapping with a side surface of the opening and a region overlapping with a bottom of the opening via the second semiconductor layer and the fifth insulating layer, respectively; Wherein, the second semiconductor layer is electrically connected to the first conductive layer.

4. The semiconductor device according to any one of claims 1 to 3, The first semiconductor layer contains a Group 13 element.

5. The semiconductor device according to any one of claims 1 to 3, The first semiconductor layer contains a Group 15 element.

6. The semiconductor device according to any one of claims 1 to 3, The second insulating layer includes silicon and nitrogen.

7. The semiconductor device according to any one of claims 1 to 3, The third insulating layer includes silicon and oxygen.

8. The semiconductor device according to any one of claims 1 to 3, The fourth insulating layer includes silicon and nitrogen.

9. The semiconductor device according to any one of claims 1 to 3, The first semiconductor layer has a different composition from that of the second semiconductor layer. 10 . The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises silicon. 11 . The semiconductor device according to claim 1 , wherein the second semiconductor layer includes an oxide semiconductor.

12. The semiconductor device according to claim 11, The oxide semiconductor includes one or both of indium and zinc.

Images