Chip and preparation method thereof

Abstract

The invention provides a chip, which comprises a chip substrate, and regularly arranged geometric structures are formed on at least one surface of the chip substrate; the height of the geometric structure in the direction perpendicular to the surface of the chip is 10 nm-100 microns, and the maximum size of the geometric structure in the horizontal direction of the surface of the chip is 10 nm-100 microns; and the distance between the adjacent geometric structures is 10nm-100mu m. According to the present invention, the regularly arranged geometric structures are formed on the chip substrate, such that the biomolecule detection site arrangement is controllable, the density is high, the detection flux can be improved, and the detection cost can be reduced. The geometric structure size parameters of the biochip provided by the invention can improve the sequencing quality, and the biochip is high in repeatability, good in stability and resistant to multi-cycle reagent washing.

Description

Technical Field

[0001] The present invention relates to the field of biotechnology, and in particular to a chip and a preparation method thereof. Background Art

[0002] The chip used for the biomolecule detection platform integrates the biochemical analysis process on the chip surface based on the principle of specific interactions between biomolecules, thereby realizing high-throughput rapid detection of DNA, RNA, peptides, proteins and other biological components. Biochips have the advantages of high throughput, miniaturization, and automated detection. They are widely used in gene sequencing, protein detection, biological small molecule detection (such as sugars) and other fields, providing feasible technical solutions for nucleic acid sequence analysis, drug screening, and large-scale biological sample detection technology.

[0003] The chip surface can form biomolecule detection sites through geometric structures of specific shapes. By forming a patterned arrangement of the sites, it is beneficial to control the density of the geometric structure arrangement on the chip surface, and can realize the simultaneous detection of a variety of detection samples, thereby improving the detection throughput. Setting the chip surface to a patterned surface with a regular arrangement of geometric structures is conducive to increasing the arrangement density of the chip and improving the surface utilization.

[0004] The determination of nucleic acid sequences on the surface of a chip is widely used. Studies have found that the chip structure, as a carrier for sequencing and a device for sequencing reaction, affects various parameter indicators that reflect the sequencing results, and thus affects the accuracy of the sequencing results. How to design a suitable chip micro-nano structure so that the chip can improve sequencing stability and accuracy when used for sequencing has become a matter of great concern to technicians in the field. Summary of the invention

[0005] The inventors have found that in the chip-based nucleic acid sequencing method, the size of the chip surface geometric structure, including the height of the geometric structure in the vertical direction, the size in the horizontal direction, and the depth of the geometric structure, will affect the stability and accuracy of the sequencing results. This influence is reflected in the sequencing indicators or parameters obtained during the sequencing process, such as: the stability of the clone cluster obtained after amplification of the nucleic acid molecules in the geometric structure, the signal brightness captured during the sequencing process, the quality parameters of the sequencing sequence (read segment) such as Q30, the splitting rate of the sample multi-tags, and the comparison rate of the sequencing results with the reference genome.

[0006] In view of this, the present invention provides a chip and a preparation method thereof that are beneficial to improving sequencing quality by designing the size of the geometric structure of the chip.

[0007] A first aspect of the present invention provides a patterned chip, comprising a chip substrate, wherein the chip substrate has regularly arranged geometric structures formed on at least one surface; the height of the geometric structures in a direction perpendicular to the chip surface is 10nm to 100μm, and the maximum size in a direction horizontal to the chip surface is 10nm to 100μm; the distance between adjacent geometric structures is 10nm to 100μm.

[0008] The present invention can improve the stability of sequencing and the accuracy of sequencing results by forming regularly arranged geometric structures on the substrate. Moreover, the regularly arranged geometric structures can increase the arrangement density of the geometric structures on the chip and improve the detection flux; and the regularly arranged geometric structures can be used to locate the detection sites corresponding to the geometric structures, thereby facilitating the simultaneous detection of multiple nucleic acid molecules on the same chip surface and reducing the detection cost.

[0009] As a possible implementation, the height of the geometric structure in a direction perpendicular to the surface is 100 nm to 1 μm, and the maximum dimension in a direction horizontal to the surface is 100 nm to 1 μm;

[0010] The distance between adjacent geometric structures is 100nm~1μm.

[0011] As a possible implementation, the height of the geometric structure in a direction perpendicular to the chip surface is 100 nm to 1 μm, and the maximum dimension in a direction horizontal to the chip surface is 100 nm to 1 μm;

[0012] The distance between adjacent geometric structures is 100nm~1μm.

[0013] As a possible implementation manner, the geometric structure is a depression or a protrusion formed on the surface of the chip substrate.

[0014] As a possible implementation manner, the geometric structure is formed by one or a combination of a cylinder, a cone, a truncated cone, a prism, a pyramid, a truncated pyramid and an irregular shape.

[0015] As a possible implementation, the surface has at least one array unit, and the array unit has a regularly arranged geometric structure.

[0016] As a possible implementation manner, the array unit is one or more of a square array unit, a rectangular array unit and a honeycomb array unit.

[0017] As a possible implementation manner, the chip further includes a first cover plate combined with a surface of one side of the chip substrate on which the geometric structure is arranged, and the first cover plate is made of a material having a light transmittance greater than or equal to 95%.

[0018] As a possible implementation manner, a surface of the first cover plate facing the chip substrate is a flat surface.

[0019] As a possible implementation manner, a surface of the first cover plate facing the chip substrate is provided with a regularly arranged geometric structure, and the geometric structure of the first cover plate is the same as or different from the geometric structure of the chip substrate.

[0020] As a possible implementation manner, the chip substrate has regularly arranged geometric structures on both surfaces.

[0021] As a possible implementation manner, the chip includes a first cover plate and a second cover plate respectively bonded to two side surfaces of the chip substrate, and the first cover plate and the second cover plate are made of a material with a light transmittance greater than or equal to 95%.

[0022] As a possible implementation manner, both surfaces of the first cover plate and the second cover plate are flat surfaces.

[0023] As a possible implementation manner, the first cover plate is a cover plate with a geometric structure disposed on a surface, and the geometric structure of the first cover plate is disposed opposite to the geometric structure of the chip substrate, and both surfaces of the second cover plate are flat surfaces.

[0024] As a possible implementation manner, the first cover plate and the second cover plate are both cover plates with geometric structures disposed on one surface, and the geometric structures on the first cover plate and the second cover plate are disposed opposite to the geometric structures on two surfaces of the chip substrate.

[0025] As a possible implementation, the chip includes a polymer layer, and the polymer layer is disposed on a surface of the geometric structure.

[0026] As a possible implementation, the polymer layer is formed of a polymer containing a first functional group, wherein the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group and an azide group.

[0027] As a possible implementation manner, the polymer layer is bonded to the surface of the chip substrate and / or the cover plate through coupling molecules.

[0028] As a possible implementation, the molecular formula of the coupling molecule is as follows: a Si(Y b )M c Z,

[0029] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C1-6 Alkoxy;

[0030] Y is selected from C 1-10 alkyl;

[0031] M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ;

[0032] Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl;

[0033] The a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0034] As a possible implementation manner, the chip further includes a first film layer disposed between the chip substrate and / or the cover plate and the polymer layer, and the material of the first film layer is different from the material of the surface to which it is bonded.

[0035] As a possible implementation manner, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film.

[0036] As a possible implementation manner, the material of the first film layer is at least one of Au, Al and SiO2.

[0037] As a possible implementation manner, the thickness of the first film layer is 10 to 1000 nm.

[0038] As a possible implementation, a glue layer is arranged between the chip substrate and the cover plate, and the glue layer has a channel arranged in the length direction of the chip, and the geometric structure is arranged on the surface of the chip substrate and / or the cover plate in the area where the channel is located, and the shape and / or arrangement of the geometric structure in different channels on the same surface are the same or different.

[0039] A second aspect of the present invention provides a method for preparing a chip, comprising the following steps:

[0040] a) forming regularly arranged geometric structures on at least one surface of a substrate;

[0041] The height of the geometric structure in the direction perpendicular to the substrate surface is 10 nm to 100 μm, and the maximum size in the direction horizontal to the substrate surface is 10 nm to 100 μm;

[0042] The distance between adjacent geometric structures is 10nm~100μm.

[0043] As a possible implementation manner, the substrate is a chip base and / or a cover plate.

[0044] As a possible implementation, the method further includes:

[0045] b) forming a polymer layer on the geometric structure.

[0046] As a possible implementation manner, the geometric structure is a depression formed on the surface of the chip substrate and / or the cover plate, and b) includes:

[0047] attaching a polymer having a first functional group to the surface where the geometric structure is located;

[0048] The polymer is polished to remove the polymer outside the area where the geometric structure is located, so as to form a polymer layer on the geometric structure.

[0049] As a possible implementation manner, the polishing is chemical polishing and / or mechanical polishing.

[0050] As a possible implementation manner, the geometric structure is a protrusion formed on the surface of the chip substrate and / or the cover plate, and before a), the method includes:

[0051] A polymer containing a first functional group is attached to the surface of the substrate.

[0052] As a possible implementation manner, the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group and an azide group.

[0053] As a possible implementation manner, before connecting the polymer, the method further includes: treating the substrate with coupling molecules.

[0054] As a possible implementation, the molecular formula of the coupling molecule is as follows: a Si(Y b )M c Z,

[0055] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy;

[0056] Y is selected from C1-10 alkyl;

[0057] M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ;

[0058] Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl;

[0059] The a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0060] As a possible implementation, the method further includes: before step a), or after step a) and before step b), preparing a first film layer on the surface where the geometric structure is located, wherein the first film layer and the substrate are made of different materials.

[0061] As a possible implementation manner, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film.

[0062] As a possible implementation manner, the material of the first film layer is at least one of Au, Al and SiO2.

[0063] As a possible implementation manner, the thickness of the first film layer is 10 to 1000 nm.

[0064] As a possible implementation manner, the substrate at least includes a chip base, and the method further includes:

[0065] Adhesive material is used to combine the cover plate on the surface of one side of the chip substrate where the geometric structure is arranged, and the adhesive material forms a channel in the length direction of the chip.

[0066] As a possible implementation manner, the chip is the chip described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a schematic cross-sectional view of a chip substrate having a cylindrical concave structure provided by an embodiment of the present invention;

[0068] Figure 2is a schematic plan view of a chip substrate having a cylindrical concave structure in a geometric structure provided by an embodiment of the present invention;

[0069] Figure 3 is a physical cross-sectional view of a chip substrate having a cylindrical concave structure provided by an embodiment of the present invention;

[0070] Figure 4 It is a physical plane diagram of a chip substrate having a cylindrical concave structure provided by an embodiment of the present invention;

[0071] Figure 5 is a cross-sectional schematic diagram of a chip substrate having a cylindrical protruding structure in an embodiment of the present invention;

[0072] Figure 6 is a schematic plan view of a chip substrate having a cylindrical protruding structure in a geometric structure provided by an embodiment of the present invention;

[0073] Figure 7 is a physical cross-sectional view of a chip substrate having a cylindrical protruding structure provided by an embodiment of the present invention;

[0074] Figure 8 This is a schematic diagram of a chip structure in which a surface of a chip substrate provided by an embodiment of the present invention has a geometric structure;

[0075] Fig. 9 is a schematic diagram of another chip structure in which one surface of a chip substrate provided by an embodiment of the present invention has a geometric structure;

[0076] Fig.10 This is a schematic diagram of a chip structure in which two surfaces of a chip substrate provided by an embodiment of the present invention have geometric structures;

[0077] Fig.11 is a schematic diagram of another chip structure in which two surfaces of a chip substrate provided by an embodiment of the present invention have geometric structures;

[0078] Fig.12 is a schematic diagram of another chip structure in which two surfaces of a chip substrate provided by an embodiment of the present invention have geometric structures;

[0079] Fig.13 is a schematic flow chart of a method for preparing a biochip provided in Example 1 of the present invention;

[0080] Fig.14 is a physical plan view of the biochip provided in Example 1 of the present invention;

[0081] Fig.15 is a physical cross-sectional view of the biochip provided in Example 1 of the present invention;

[0082] Fig.16It is a statistical graph of fluorescence brightness of biochips with different well depths provided in Examples 1-4 of the present invention after nucleic acid amplification;

[0083] Fig.17 It is a statistical graph of sequencing amplification occupancy, Q30, splitting rate and alignment rate of biochips with different well depths provided in Examples 1-4 of the present invention;

[0084] Fig.18 is a schematic diagram of the preparation process of the biochip provided in Example 5 of the present invention;

[0085] Fig.19a This is a schematic diagram of the structure of the biochip prepared in Comparative Example 1;

[0086] Fig.19b This is a multi-channel fluorescence image of the biochip prepared in Comparative Example 1;

[0087] Fig.19c The local surface fluorescence image of the biochip prepared in Comparative Example 1;

[0088] Fig.19d This is a schematic diagram of the structure of the biochip prepared in Example 5;

[0089] Fig.19e This is a multi-channel fluorescence image of the biochip prepared in Example 5;

[0090] Fig.19f The local surface fluorescence image of the biochip prepared in Example 5;

[0091] Fig. 20 is a schematic diagram of a method for preparing a biochip provided in Example 6 of the present invention;

[0092] Fig.21a This is a surface structure diagram of the biochip prepared in Comparative Example 2;

[0093] Figure 21b for Fig.21a A partial enlarged view of

[0094] Fig.21c This is a surface structure diagram of the biochip prepared in Example 6;

[0095] Fig.21d This is an enlarged fluorescence image of the surface of the biochip prepared in Example 6;

[0096] Fig. 22 is a schematic diagram of the preparation process of the biochip provided in Example 7 of the present invention;

[0097] Fig.23a This is a surface structure diagram of the biochip prepared in Comparative Example 3;

[0098] Figure 23bThis is a multi-channel fluorescence image of the biochip prepared in Comparative Example 3;

[0099] Fig.23c This is an enlarged image of the surface fluorescence of the biochip prepared in Comparative Example 3;

[0100] Fig.23d This is a surface structure diagram of the biochip prepared in Example 5;

[0101] Fig.23e This is an enlarged image of the surface fluorescence of the biochip prepared in Example 5. DETAILED DESCRIPTION

[0102] The present invention provides a patterned biochip and a method for preparing the same. Those skilled in the art can refer to the contents of this article and appropriately improve the process parameters to achieve the same. It should be particularly noted that all similar substitutions and modifications are obvious to those skilled in the art and are considered to be included in the present invention. The methods and applications of the present invention have been described through preferred embodiments, and relevant personnel can obviously modify or appropriately change and combine the methods and applications of this article without departing from the content, spirit and scope of the present invention to implement and apply the technology of the present invention.

[0103] The embodiment of the present application provides a chip, the chip includes a chip substrate, the chip substrate is used to carry the nucleic acid molecules to be tested, and provide a reaction site or detection site for the nucleic acid molecules. In the embodiment of the present application, at least one surface of the chip substrate forms a geometric structure, so the chip can also be called a patterned chip. After the chip is packaged, a fluid passage containing a reaction area can be formed, so the chip with this geometric structure is also called a flow chamber or flow cell.

[0104] In the embodiment of the present application, the chip substrate has good stability and chemical reaction inertness, so that after the nucleic acid molecules are fixed on the surface of the chip substrate, the physical and chemical properties and structure of the nucleic acid molecules are not changed due to the material of the chip substrate. The structure includes but is not limited to the composition of the nucleic acid molecules, the spatial conformation of the nucleic acid molecules, the two-dimensional structure and even the three-dimensional structure. In some specific implementations, the material of the chip substrate includes but is not limited to: glass; quartz; silicon-based materials, such as silicon dioxide, polycrystalline silicon, single crystal silicon, etc.; polymers, such as hexamethyldisilazane (HMDS), polyethylene (PE), polypropylene (PP), etc.; metals, such as aluminum, etc., can be one of them, or a composite substrate material composed of two or more combinations. It should be understood that when the chip substrate is composed of multiple materials, its composition method includes at least the following two situations. In one embodiment, two or more materials are mixed to form a mixed material, and the chip substrate is prepared using the mixed material as a raw material. At this time, the chip substrate is displayed as a layer of material layer. Preferably, considering the processability of the chip substrate and the obtained product performance, it is preferred to select materials of similar or similar materials for mixing to prepare the chip substrate. For example, a mixture containing silicon dioxide and polysilicon is used to prepare the chip substrate, and a mixture containing polyethylene (PE) and polypropylene (PP) is used to prepare the chip substrate, and so on. In another embodiment, two or more materials of different materials are selected to prepare a composite layer containing at least two layer structures as the chip substrate. Each layer structure can be made of a material of the same material, or it can be made by compounding two or more materials of different materials with reference to the previous embodiment. Multiple layer structures can be arranged according to a certain structure, such as forming a stacked structure, and so on.

[0105] The present application has no special restrictions on the size of the substrate, and it can be designed according to the requirements. In some embodiments, for the convenience of processing, a regularly arranged geometric structure is formed on a large-area wafer, and then the wafer is cut to obtain a chip substrate with a size that meets the requirements. There is no restriction on the size specifications of the wafer structure, for example, it can be various specifications such as 6 inches, 8 inches, and 12 inches.

[0106] The chip substrate provided in the embodiment of the present application has a geometric structure. The geometric structure includes but is not limited to a cylinder, a cone, a truncated cone, a prism, a pyramid, a prism or an irregular shape, and can also be a combination of two of the cylinder, the cone, the truncated cone, the prism, the pyramid, the prism and the irregular shape.

[0107] In the embodiment of the present application, the shape of the geometric structure on the surface of the chip substrate can be a protrusion formed on the surface of the chip substrate, that is, a three-dimensional structure protruding from the surface of the chip substrate; or a depression formed by a concave inward on the surface of the chip substrate, that is, a concave cavity structure formed on the substrate. For example, taking the geometric structure as a cylindrical concave structure as an example, the cross-sectional schematic diagram and the plan schematic diagram of the chip substrate are respectively as follows: Figure 1 and Figure 2 As shown, 11 is a cylindrical depression, 12 is a chip substrate; the physical cross-sectional view and the physical plan view are respectively as shown in Figure 3 and Figure 4 As shown; Taking the cylindrical protruding structure as an example, the cross-sectional schematic diagram and the plane schematic diagram of the chip substrate are respectively as shown in Figure 5 and Figure 6 As shown, 21 is a cylindrical protrusion, 22 is a chip substrate, and the actual cross-sectional view is as shown in Figure 7 shown.

[0108] In the embodiment of the present application, the geometric structure is disposed on at least one surface of the chip substrate.

[0109] In one embodiment, the geometric structure of the chip substrate is formed on a surface of the chip substrate. At this time, the material of the chip substrate can be selected from the materials listed above, for example, glass; quartz; silicon-based materials, such as silicon dioxide, polycrystalline silicon, single crystal silicon, etc.; polymers, such as hexamethyldisilazane (HMDS), polyethylene (PE), polypropylene (PP), etc.; metals, such as aluminum, etc., and the chip substrate can be composed of one of them, or it can be made of a composite material composed of two or more of the above materials. In some embodiments, the chip substrate can be set as a single layer, and the single-layer chip substrate can be made of one material or a mixture of multiple materials; the chip substrate can also be set as a stacked structure, and the layers constituting the stacked structure can be made of the same material or a mixture of multiple materials. The geometric structure is set on the surface of the stacked structure and can penetrate the surface and sink to at least one other layer of the stacked structure.

[0110] In another embodiment, the geometric structure of the chip substrate is formed on two surfaces of the chip substrate, and the chip substrate obtained thereby provides two surfaces for biochemical reactions and / or detections such as nucleic acid sequencing, which is beneficial to improve the throughput of biochemical reactions and / or detections. In one embodiment, the chip substrate is a single layer, and at this time, the transmittance of the single layer chip substrate is less than 70% or the thickness of the single layer chip substrate is 500 μm or more, so that when the imaging device collects optical signals from the two surfaces of the chip substrate (especially the geometric structure), the interference between the optical signals of the two surfaces is reduced. The single layer chip substrate can be made of opaque materials, which can be silicon-based materials, such as silicon dioxide, polycrystalline silicon, monocrystalline silicon, etc.; metals, such as aluminum, etc. The single layer chip substrate can also be made of a variety of mixed materials, and the transmittance of the film layer formed by the mixed material is less than 70% or the thickness of the film layer formed by the mixed material is 500 μm or more. For example, a silicon-based material is mixed with other substrates in a suitable proportion to obtain a chip substrate. In another embodiment, the chip substrate is a laminated structure, which includes at least one laminate with a transmittance of less than 70% or a thickness of 500μm or more, which is used to reduce the mutual interference of optical signals generated by the two surfaces (especially geometric structures) of the chip substrate. Exemplarily, the chip substrate is a laminated structure including two laminates. In one case, one laminate is a laminate with a transmittance greater than 95%, and the other laminate is a laminate with a transmittance less than 70%; geometric structures are respectively arranged on the opposite surfaces of the two laminates. In another case, both laminates are laminates with a transmittance less than 70%; geometric structures are respectively arranged on the opposite surfaces of the two laminates. In yet another case, both laminates are laminates with a transmittance greater than 95%, and the total thickness of the two laminates is 500μm or more; geometric structures are respectively arranged on the opposite surfaces of the two laminates.

[0111] In the embodiment of the present application, the size of the geometric structure can meet the detection needs of biomolecules. Specifically, the height of the geometric structure in the direction perpendicular to the chip surface is 10nm to 100μm, and the maximum size in the horizontal direction of the chip surface is 10nm to 100μm. Here, the height of the geometric structure in the direction perpendicular to the chip surface can be understood as the depth of the geometric structure (the geometric structure is a depression) or the height (the geometric structure is a protrusion). The maximum size in the horizontal direction of the chip surface can be understood as the maximum distance between any two points on the outer edge of the cross section of the geometric structure (a cross section along the direction horizontal to the chip substrate surface). In some embodiments, the height of the geometric structure in the direction perpendicular to the chip surface is 50nm to 10μm, preferably 100nm to 1μm, and more preferably 200nm to 800nm; the maximum size in the horizontal direction of the chip surface is 50nm to 10μm, preferably 100nm to 1μm, and more preferably 200nm to 800nm. In the embodiment of the present application, the distance between adjacent geometric structures, that is, the center-to-center distance of adjacent geometric structures, is 10nm to 100μm. In some embodiments, the distance between adjacent geometric structures is 50 nm to 10 μm, preferably 100 nm to 1 μm, and more preferably 200 nm to 800 nm.

[0112] In one embodiment, the height of the geometric structure in the direction perpendicular to the chip surface is 300nm to 500nm; the maximum dimension in the horizontal direction of the chip surface is 300nm to 500nm, and the distance between adjacent geometric structures is 300nm to 700nm. When the chip provided in this case is used for sequencing, the sequencing quality can be improved, the sequencing results have high repeatability, good stability, and can withstand multiple cycles of reagent flushing.

[0113] In some embodiments, the geometric structure forms a regular arrangement on the surface of the chip substrate, which can be understood as the geometric structure is arranged in a certain regular pattern to form a pattern with a certain shape. In some embodiments, the surface has at least one array unit, and the array unit has a regularly arranged geometric structure. Specifically, the array unit is a square array unit, that is, the figure formed by the collection of multiple geometric structures is a square. Exemplarily, the geometric structures are arranged in rows and columns, the distance between adjacent rows is equal to the distance between adjacent columns, and the collection of multiple geometric structures includes the same number of rows and columns. The array unit is a rectangular array unit, that is, the figure formed by the collection of multiple geometric structures is a rectangle. Exemplarily, the geometric structures are arranged in rows and columns, the distance between adjacent rows is equal to the distance between adjacent columns, and the collection of multiple geometric structures includes different numbers of rows and columns. The array unit is a honeycomb array unit, that is, the figure formed by the collection of multiple geometric structures is a honeycomb, that is, multiple geometric structures are arranged in a certain regular pattern, and the collection of these geometric structures forms a honeycomb. Of course, for the same surface, two or more array units of square array units, rectangular array units and honeycomb array units can be contained at the same time. In one embodiment, the same surface of the chip substrate may include one or more geometric structure sets, and the geometric structures in each set are arranged according to the same rules. In another embodiment, the same surface of the chip substrate includes one or more geometric structure sets, and the arrangement of the geometric structures in at least one set is different from the arrangement of the geometric structures in another set, that is, the same chip substrate includes a combination of multiple arrangement modes, such as splicing or nesting.

[0114] In one embodiment, the geometric structure is a circular hole structure, the depth of the circular hole is 300nm-500nm; the diameter of the circular hole structure is 300nm-500nm, and the distance between adjacent circular holes is 300nm-900nm.

[0115] In some implementations, the chip may further include a packaging layer disposed on the chip substrate, the packaging layer being used to package the surface of the chip substrate having a geometric structure to protect the chip substrate and form a reaction area for solution flow.

[0116] In one embodiment, the chip includes a first cover plate bonded to a surface of a side of the chip substrate where a geometric structure is set. The material of the first cover plate is a material with a light transmittance greater than or equal to 95%, so that light can pass through the first cover plate to reach the surface of the chip substrate where the geometric structure is set. The material of the first cover plate can be the same as the chip substrate or different from the chip substrate, and there is no special limitation in this application. Exemplarily, the material of the cover plate can be glass, quartz, polymer film, etc.

[0117] In some embodiments, Figure 8 and Fig. 9As shown, the geometric structure of the chip substrate 82 is formed on one surface of the chip substrate 82, and the first cover plate 81 is combined on the side surface where the geometric structure of the chip substrate 82 is located to realize chip packaging. The first cover plate 81 can be a patterned material or a non-patterned material.

[0118] In one embodiment, Figure 8 As shown, the first cover plate 81 is an ordinary cover plate without a geometric structure, that is, the two surfaces of the cover plate are untreated flat surfaces. At this time, the surface of the first cover plate 81 facing the chip substrate 82 is a flat surface. In one embodiment, an adhesive layer 83 is provided between the first cover plate 81 and the chip substrate 82 for bonding the first cover plate 81 and the chip substrate 82, and the adhesive layer 83 has a channel provided in the length direction of the chip, and the geometric structure is provided on the surface of the chip substrate 82 in the area where the channel is located, and the shape and / or arrangement of the geometric structure in different channels on the same surface are the same or different.

[0119] In other embodiments, Fig. 9 As shown, the first cover plate 91 is a cover plate with a regularly arranged geometric structure on one side surface, and the geometric structure of the first cover plate 91 is arranged relative to the geometric structure of the chip substrate 92, that is, the surface of the first cover plate 91 facing the chip substrate 92 is provided with a regularly arranged geometric structure. At this time, a chip has two surfaces that can be sequenced, thereby improving the sequencing throughput. In this embodiment, the geometric structure of the first cover plate 91 and the geometric structure of the chip substrate 92 can be the same or different. In order to save space, it is not repeated here. In one embodiment, a glue layer 93 is provided between the first cover plate 91 and the chip substrate 92, which is used to bond the first cover plate 91 and the chip substrate 92, and the glue layer 93 has a channel arranged in the length direction of the chip, and the geometric structure is arranged on the surface of the chip substrate 92 and the first cover plate 91 in the area where the channel is located, and the shape and / or arrangement of the geometric structure in different channels on the same surface are the same or different.

[0120] In another embodiment, the chip substrate has regularly arranged geometric structures on both surfaces, and the arrangement of the geometric structures on the two surfaces may be the same or different. For the arrangement of the geometric structures on the two surfaces of the chip substrate, refer to the above, and will not be repeated here to save space. At this time, the transmittance of the chip substrate is less than 70% or the thickness of the chip substrate is 500μm or more, so that when the imaging device collects optical signals from the two surfaces of the chip substrate (especially the geometric structure), the interference between the optical signals on the two surfaces is reduced. In this embodiment, a cover plate is combined with at least one side surface of the geometric structure of the chip substrate to achieve chip packaging. In some embodiments, the chip includes a first cover plate and a second cover plate respectively combined with the two side surfaces of the chip substrate, wherein the material of the first cover plate and the second cover plate is a material with a transmittance greater than or equal to 95%, so that light passes through the first cover plate and the second cover plate respectively to reach the two surfaces of the chip substrate where the geometric structure is set.

[0121] In some embodiments, the cover plate is a common cover plate without any geometric structure, that is, both surfaces of the cover plate are untreated flat surfaces. Fig.10 As shown, the first cover plate 101 and the second cover plate 104 are respectively combined on the side surfaces of the geometric structure of the chip substrate 102, and the first cover plate 101 and the second cover plate 104 are ordinary cover plates without geometric structures, that is, the two surfaces of the first cover plate 101 and the second cover plate 104 are flat surfaces. In one embodiment, an adhesive layer 103 is provided between the first cover plate 101 and the chip substrate 102 and between the second cover plate 104 and the chip substrate 102, for bonding the first cover plate 101 and the chip substrate 102 and the second cover plate 104 and the chip substrate 102, and the adhesive layer 103 has a channel provided in the length direction of the chip, and the geometric structure is provided on the surface of the chip substrate 102 in the area where the channel is located, and the shape and / or arrangement of the geometric structures in different channels on the same surface are the same or different.

[0122] In some embodiments, the first cover plate and / or the second cover plate is a cover plate with a geometric structure disposed on one surface.

[0123] In one embodiment, Fig.11As shown, the first cover plate 111 and the second cover plate 114 are respectively combined on the two side surfaces of the geometric structure of the chip substrate 112, wherein the first cover plate 111 is a cover plate with a geometric structure, and the geometric structure of the first cover plate 111 is arranged opposite to the geometric structure of the chip substrate 112; the second cover plate is an ordinary cover plate without a geometric structure, and the two surfaces of the second cover plate 114 are flat surfaces. It should be understood that the geometric structure of the first cover plate 111 can be the same as or different from the geometric structure of the chip substrate 112. In one embodiment, an adhesive layer 113 is arranged between the first cover plate 111 and the chip substrate 112 and between the second cover plate 114 and the chip substrate 112, for bonding the first cover plate 111 and the chip substrate 112 and the second cover plate 114 and the chip substrate 112, and the adhesive layer 113 has a channel arranged in the length direction of the chip, and the geometric structure is arranged on the surface of the chip substrate 112 and the first cover plate 111 in the area where the channel is located, and the shape and / or arrangement of the geometric structures in different channels on the same surface are the same or different.

[0124] In one embodiment, Fig.12 As shown, the first cover plate 121 and the second cover plate 124 are respectively combined on the two side surfaces of the geometric structure of the chip substrate 122, and both cover plates are cover plates with geometric structures, and the geometric structure of the cover plate is arranged relative to the geometric structure of the chip substrate 122, forming a similar double-chip stacked structure. It should be understood that the geometric structure of each cover plate can be the same as or different from the geometric structure of the chip substrate; the geometric structures of the two cover plates can be the same or different. In one embodiment, an adhesive layer 123 is arranged between the first cover plate 121 and the chip substrate 122 and between the second cover plate 124 and the chip substrate 122, which is used to bond the first cover plate 121 and the chip substrate 122 and the second cover plate 124 and the chip substrate 122, and the adhesive layer 123 has a channel arranged in the length direction of the chip, and the geometric structure is arranged on the surface of the chip substrate 122, the first cover plate 121 and the second cover plate 122 in the area where the channel is located, and the shape and / or arrangement of the geometric structures in different channels on the same surface are the same or different.

[0125] When the chip is used for sequencing, the above embodiment can increase the reaction and / or detection sites of nucleic acid molecules on the chip surface by setting a regularly arranged geometric structure on the surface of the cover plate facing the chip substrate, which is conducive to increasing the sequencing throughput. It should be understood that when the cover plate is provided with a regularly arranged geometric structure, which can increase the reaction and / or detection sites of nucleic acid molecules on the chip surface, which is conducive to increasing the sequencing throughput, the cover plate also has the function of a chip substrate and can also be called a chip substrate.

[0126] In some embodiments, the chip includes a polymer layer, and the polymer layer is arranged on the surface of the geometric structure. Since the geometric structure is arranged on at least one surface of the chip substrate, the polymer layer is at least arranged on the surface of the chip substrate having the geometric structure. When both surfaces of the chip substrate have geometric structures, polymer layers are arranged on both surfaces. Correspondingly, when the cover plate includes a first cover plate and a second cover plate and a geometric structure is arranged on one surface, the polymer layer is also arranged on the surface of the cover plate where the geometric structure is arranged. In this embodiment, the surface of the geometric structure refers to the area where the geometric structure is parallel to the surface of the chip substrate. When the geometric structure is a recessed structure, the surface of the geometric structure is the bottom surface of the recessed structure, and in this case, the polymer layer is arranged on the bottom surface of the recessed structure. Possibly, the polymer layer may extend to the inner wall surface of the recessed structure. When the geometric structure is a convex structure, the surface of the geometric structure is the top surface of the convex structure, and in this case, the polymer layer is arranged on the top surface of the convex structure.

[0127] The polymer layer provides a capture site or detection site for the analysis and / or detection of nucleic acid molecules by combining with nucleic acid probes, antigen-antibodies, nucleic acid-protein complexes and other nucleic acid molecule connectors. Precisely because of this, the embodiment of the present application sets the size and arrangement of the geometric structure so that the nucleic acid molecules are fixed on the surface of the chip with a certain arrangement density and arrangement. Even if the nucleic acid molecules form detection or analysis sites with a certain density and arrangement, it is beneficial to obtain and locate the information generated by the nucleic acid molecules during the reaction and / or detection process in the later stage, which helps to improve the stability of the detection results of the nucleic acid molecules.

[0128] In some embodiments, the polymer layer is formed by a polymer containing a first functional group, and the first functional group is selected from one or more of a thiol, an aldehyde, a hydroxyl, a carboxyl, an amino, an alkenyl, an alkynyl, and an azide group. These functional groups are chemically reactive or adsorbable functional groups, and can react with other reactive functional groups to achieve binding to nucleic acid molecules or nucleic acid molecule connectors such as nucleic acid probes, antigen antibodies, and nucleic acid-protein complexes. That is, illustratively, the polymer constituting the polymer layer can be polyethylene glycol, polypropylene, polyacrylic acid, polymethyl methacrylate, etc., but is not limited thereto. The embodiment of the present application forms a polymer on the surface of the chip geometry structure, which can optimize the environment of the chip sequencing reaction. Specifically, the formed polymer layer has high transparency and low optical background in the visible light band of 400nm-700nm.

[0129] The present application has no particular limitation on the thickness of the polymer layer, as long as it can fix nucleic acid molecules or nucleic acid molecule connectors.

[0130] In this implementation, since the chip substrate and / or cover plate material has a relatively weak reactivity, in some embodiments, the polymer layer is bonded to the surface of the chip substrate and / or cover plate through a coupling molecule. In one embodiment, the molecular formula of the coupling molecule is as follows: a Si(Y b )M c Z, X, and Z are reactive groups used to connect the chip substrate and the functional groups of the polymer, respectively.

[0131] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy, exemplary, such as Cl, CH3O-, CH3CH2O-, etc.; Y is selected from C 1-10 Alkyl, such as CH3-, CH3CH2-, etc.; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl, at least one R a Replacement, R a Each is independently selected from halogen, nitro, ester, amino, carboxyl, hydroxyl, azido, and epoxy; a, b, and c are all integers, and the values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0132] Exemplarily, the coupling molecule can be at least one of the following structures:

[0133]

[0134] Wherein, X is a halogen, and illustratively, X is F, Cl, Br or I;

[0135] R b is -CH3, -C2H5, -C3H7 or -C4H9;

[0136] n1 is an integer selected from 2 to 10, and exemplary n1 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0137] n2 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0138] n3 is an integer selected from 2-10, and exemplary n3 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0139] n4 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0140] n5 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0141] n6 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0142] n7 is an integer selected from 1-10, and exemplary n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0143] n8 is an integer selected from 5 to 10, and exemplary n2 is 5, 6, 7, 8, 9 or 10;

[0144] n9 is an integer selected from 1-10, and exemplary n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0145] n10 is an integer selected from 1-10, and exemplary n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10.

[0146] In some embodiments, the chip further includes a first film layer disposed between the chip substrate and / or the cover plate and the polymer layer. Specifically, the first film layer is optionally disposed on the surface of the chip substrate and the cover plate having a geometric structure, and its material is different from the material of the surface to which it is combined, so as to reduce the surface defects of the chip substrate and / or the cover plate and improve the uniformity of the chip surface. In addition, during the chip preparation process, considering the feasibility of the process, it is preferred to react on the entire surface of the chip substrate and / or the cover plate to generate a polymer layer; then the polymer layer on the surface of the chip substrate and / or the cover plate is processed to retain only the polymer formed in the geometric structure to meet the need for detecting the optical signal generated by the nucleic acid molecule reaction. In some embodiments, the polymer is connected within the geometric structure by a selective modification process. In some embodiments, the polymer outside the geometric structure is removed by a polishing process. At this time, the first film layer can be disposed on the surface of the chip substrate and / or the cover plate, and the physical and chemical properties of the first film layer can be detected to indicate the degree of the polishing reaction, thereby determining the polishing end point.

[0147] In this embodiment, the first film layer includes but is not limited to a metal film, such as an Al film, an Au film, etc.; a metal oxide film, such as an Al2O3 film, etc.; an inorganic oxide film, such as a SiO2 film, etc., and can be one or more of them, preferably one or more of an Al film, an Al2O3 film, and a SiO2 film. Exemplarily, when a SiO2 film is used as the first film layer, the SiO2 film can stabilize the surface properties of the chip, which is specifically reflected in: it can avoid the reaction of raw materials, reagents, etc. introduced by the reaction and / or test with the chip substrate to generate bubbles. In addition, SiO2 can also improve the bonding strength of the polymer and reduce the risk of the polymer layer falling off the chip surface.

[0148] In some embodiments, the thickness of the first film layer is 10 to 1000 nm, preferably 15 nm to 800 nm, more preferably 20 to 500 nm, and most preferably 20 to 200 nm. Within this thickness range, the first film layer can exert the above-mentioned effects. If the thickness is too thick, such as when the thickness of the first film layer is greater than 1500 nm, the brightness of the bases collected from the geometric structure during sequencing of the chip with the first film layer is reduced compared to the chip without the first film layer, thereby affecting the judgment of the sequencing signal. Exemplarily, the thickness of the first film layer can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 250nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm and the like.

[0149] In some embodiments, the chip substrate and the cover plate are bonded by an adhesive material, and the adhesive material is hollowed out to form a channel structure to provide a reaction area for the chip substrate. The adhesive material can be an adhesive, a double-sided adhesive, or a light-curing material such as a UV adhesive. Considering the influence of reagents in the sequencing process, the adhesive material is selected to have no influence on the nucleic acid molecules and the reagents used in the sequencing process, and the adhesive itself is stable to the reagents used in the sequencing process. Exemplarily, the adhesive material is a UV curing adhesive, a heat curing adhesive, a pressure sensitive adhesive, etc., but is not limited thereto.

[0150] In some embodiments, the chip has at least one channel arranged in the length direction, such as forming one or more channels between the chip substrate and the packaging layer to achieve the liquid flow function. Specifically, the geometric structure is arranged on the surface of the chip substrate in the area where the channel is located, and the solution reacts with the nucleic acid molecules fixed by the geometric structure when flowing through the channel. It should be understood that the shape and / or arrangement of the geometric structures in different channels are the same or different.

[0151] The chip provided in the embodiment of the present application can improve the stability of sequencing and the accuracy of sequencing results by forming regularly arranged geometric structures on the substrate. Moreover, the regularly arranged geometric structures can increase the arrangement density of the geometric structures on the chip and improve the detection throughput; and the regularly arranged geometric structures can be used to locate the detection sites corresponding to the geometric structures, thereby facilitating the simultaneous detection of multiple nucleic acid molecules on the same chip surface.

[0152] The chip provided in the embodiment of the present application can be manufactured by the following method, but is not limited thereto.

[0153] Accordingly, the present invention also provides a method for preparing a chip, comprising the following steps:

[0154] a) forming regularly arranged geometric structures on at least one surface of a substrate;

[0155] The height of the geometric structure in the vertical direction is 10nm~100μm, and the maximum dimension in the horizontal direction is 10nm~100μm;

[0156] The distance between adjacent geometric structures is 10nm~100μm.

[0157] In step a), the substrate is a target substrate on which a geometric structure needs to be set, and at least includes a chip substrate. In some embodiments, the target substrate on which a geometric structure needs to be set is a chip substrate, in which case the substrate is a chip substrate. In some embodiments, the target substrate on which a geometric structure needs to be set is a cover plate, in which case the substrate is a cover plate. In some embodiments, the target substrate on which a geometric structure needs to be set includes a chip substrate and a cover plate, in which case the substrate includes a chip substrate and a cover plate. The material of the substrate can refer to the material selection of the chip substrate and the cover plate above, and will not be repeated here.

[0158] In the embodiment of the present application, a regularly arranged geometric structure is prepared on the surface of a substrate. The shape, size parameters and arrangement rules of the geometric structure are as described above and will not be described in detail in the present application.

[0159] In the embodiments of the present application, regularly arranged geometric structures can be prepared on the surface of the substrate by means of photolithography technology, nanoimprint technology, screen printing technology, etc.

[0160] Exemplarily, the use of photolithography to prepare a geometric structure includes the following steps: after cleaning and drying the substrate, coating a photoresist, and etching after exposure and development to obtain a regularly arranged geometric structure, that is, directly obtaining a pattern. It may also include the following steps: coating a photoresist on other substrates, and etching after exposure and development to obtain a regularly arranged geometric structure, and transferring the geometric structure to a target substrate to form a pattern. The embodiments of the present application have no special restrictions on the reagents and methods of photolithography, wherein the etching method can be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0161] Exemplarily, the use of nanoimprinting technology to prepare a geometric structure may include the following steps: preparing a template of a desired pattern, coating a photoresist on a substrate, pressing the template on the surface of the photoresist, transferring the pattern to the photoresist by pressurization, and obtaining a regularly arranged geometric structure, that is, directly obtaining a pattern. It may also include the following steps: preparing a template of a desired pattern on a substrate, coating a photoresist on a second substrate, pressing the template on the surface of the photoresist, transferring the pattern to the photoresist by pressurization, and obtaining a regularly arranged geometric structure after the photoresist is cured, and then transferring the geometric structure to the chip substrate by etching to form a pattern. The embodiments of the present application have no special restrictions on the reagents, methods, etc. of the nanoimprinting technology, wherein the etching method may be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0162] Exemplarily, the preparation of geometric structures by screen printing technology specifically includes the following steps: obtaining a regularly arranged geometric structure by screen printing on a chip substrate, that is, directly obtaining a pattern. It may also include the following steps: obtaining a regularly arranged geometric structure by screen printing on a substrate, and then transferring the geometric structure to a chip substrate by etching to form a pattern. The embodiments of the present application have no special restrictions on the reagents, methods, etc. of the screen printing technology, wherein the etching method can be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0163] In some implementations, the pattern can be prepared by one of the above methods, or by a combination of two or more methods. After the geometric structure is obtained, it can be post-processed to obtain the final patterned surface. In some specific implementations, post-processing includes but is not limited to enhancement treatments, such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating, etc.; or removal treatments, such as plasma ashing, solution etching, dry oxidation, etc. The embodiments of the present application do not have any special restrictions on the specific process parameters of the above-mentioned treatments, and those skilled in the art can select them according to their needs.

[0164] In some implementations, the chip preparation method further includes: preparing a first film layer on the surface where the chip substrate geometric structure is located, and the first film layer and the substrate are made of different materials. The parameters and materials of the first film layer and the substrate are as above and are not repeated here. In some embodiments, the first film layer is selected from one or more of a metal film, a metal oxide film, and an inorganic oxide film. In some embodiments, the material of the first film layer is at least one of Au, Al, and SiO2. In some embodiments, the thickness of the first film layer is 10 to 1000 nm.

[0165] In the embodiment of the present application, a first film layer can be formed on a substrate by deposition, and then used to prepare a geometric structure; or the first film layer can be deposited after the geometric structure is formed on the chip base substrate. That is, the first film layer can be prepared before step a) or after step a). In the embodiment of the present application, there is no special limitation on the deposition method, which can be physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating or oxidation treatment.

[0166] In some specific implementations, after forming a regularly arranged geometric structure, the following steps are further included:

[0167] b) Forming a polymer layer within the geometric structure.

[0168] After regularly arranged geometric structures are formed on a substrate, the surface is modified to provide capture or detection sites.

[0169] In some embodiments, before forming the polymer layer, the chip substrate is preferably pretreated. In some specific implementations, the pretreatment includes cleaning and plasma activation. Cleaning can be solution cleaning, and plasma activation is performed after cleaning. In some specific implementations, the gas used for plasma activation includes but is not limited to air, nitrogen, argon, hydrogen, carbon tetrafluoride, etc., and can be a mixed gas of one or more thereof. In some specific implementations, the power of plasma activation is 10W to 2kW.

[0170] In one embodiment, the geometric structure is a depression formed on the surface of the chip substrate and / or the cover plate, and in this case, b) includes:

[0171] attaching a polymer having a first functional group to the surface where the geometric structure is located;

[0172] The polymer is polished to remove the polymer outside the area where the geometric structure is located, forming a polymer layer on the geometric structure.

[0173] It should be understood that this embodiment includes the case where the polymer is connected to the surface where the geometric structure is located through a coupling molecule. In this way, the polymer outside the geometric structure can be removed to reduce non-specific adsorption on the chip surface.

[0174] In an embodiment of the present application, the polymer is polished to remove the polymer outside the area where the geometric structure is located, wherein the removal method is not particularly limited, including but not limited to solution cleaning, chemical polishing, mechanical polishing, chemical mechanical polishing and other methods. Among them, solution cleaning specifically uses a reagent that can dissolve and remove polymer molecules, such as acid, alkali, solvent, surfactant, etc. to remove polymer molecules outside the geometric structure, preferably under ultrasonic conditions, or by flushing. In some embodiments, the polymer is removed by polishing, and the polishing can be chemical polishing based on chemical reaction removal, mechanical polishing based on mechanical removal, or a combination of the above two polishing methods. The embodiment of the present application can use a chemical polishing reagent, for example, it can be a reagent including one or more of acid, alkali, organic solvent, and surfactant for polishing, and mechanical polishing can also be used, for example, polishing with one or more reagents such as diamond, silica sol, calcium carbonate, cerium oxide, zirconium oxide, etc. as polishing agents.

[0175] In the technical solution provided in the present application, when the substrate is processed by polishing, the chip base is preferably a structure including a substrate and a first film layer. At this time, the first film layer can be used as a polishing endpoint indicator to indicate the polishing endpoint, which is beneficial to control the degree of surface polishing and obtain a chip with a stable and uniform surface, which is more conducive to the stability of detection.

[0176] In another embodiment, the geometric structure is a protrusion formed on the surface of the chip substrate and / or the cover plate, in which case a) includes: connecting a polymer containing a first functional group to the surface of the substrate, and then patterning the substrate with the polymer formed on the surface to form a geometric structure with regular arrangement on the surface.

[0177] In the above two embodiments, in some examples, the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group and an azide group.

[0178] In the above two embodiments, in some embodiments, the substrate is treated with coupling molecules to form coupling molecules on the surface of the substrate to be treated or the surface where the geometric structure is located, and the polymer is modified on the coupling molecules to form a polymer layer. Before coupling molecules on the surface of the chip substrate, the chip substrate is preferably pretreated. In some specific implementations, the pretreatment includes cleaning and plasma activation. Cleaning can be solution cleaning, and plasma activation is performed after cleaning. In some specific implementations, the gas used for plasma activation includes but is not limited to air, nitrogen, argon, hydrogen, carbon tetrafluoride, etc., which can be a mixed gas of one or more thereof. In some specific implementations, the power of plasma activation is 10W to 2kW. After pretreatment, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition, magnetron sputtering, solution method, spin coating, spray coating and the like can be used to combine coupling molecules to provide active sites for the fixation of polymers.

[0179] The molecular formula of the coupling molecule is as follows: a Si(Y b )M c Z, X, and Z are reactive groups used to connect the chip substrate and the functional groups of the polymer, respectively.

[0180] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy, exemplary, such as Cl, CH3O-, CH3CH2O-, etc.; Y is selected from C 1-10 Alkyl, such as CH3-, CH3CH2-, etc.; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl, at least one R a Replacement, R aEach is independently selected from halogen, nitro, ester, amino, carboxyl, hydroxyl, azido, and epoxy; a, b, and c are all integers, and the values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0181] In some possible implementations, the polymer and the coupling molecule can be connected by solution method, spin coating, screen printing, spray coating, etc. In some specific implementations, the temperature for modifying the polymer on the coupling molecule to form a polymer layer is 25-100° C. and the time is 1 h to 48 h.

[0182] In some embodiments, after the polymer layer is formed, the polymer and coupling molecules on the periphery of the geometric structure are removed by post-processing to reduce the non-specific adsorption on the surface of the biochip. The present application embodiment has no special restrictions on the removal method, including but not limited to solution cleaning, chemical polishing, mechanical polishing, chemical mechanical polishing and other methods. Among them, solution cleaning specifically uses reagents that can dissolve and remove coupling molecules, such as acids, bases, solvents, surfactants, etc. to remove coupling molecules on the periphery of the geometric structure, preferably under ultrasonic conditions. Solution cleaning, or flushing is used for solution cleaning. In some embodiments, the coupling molecules are removed by polishing. Polishing can be chemical polishing based on chemical reaction removal, or mechanical polishing based on mechanical removal, or a combination of the above two polishings. The present application embodiment can use chemical polishing reagents, such as one or more reagents including acids, bases, organic solvents, and surfactants for polishing, or mechanical polishing can be used, such as polishing with one or more reagents such as diamond, silica sol, calcium carbonate, cerium oxide, zirconium oxide, etc. as polishing agents.

[0183] Similarly, when the chip substrate is processed by polishing, the chip substrate is preferably a structure including a chip substrate and a first film layer. At this time, the first film layer can be used as a polishing endpoint indicator to indicate the polishing endpoint, which is beneficial to control the degree of surface polishing, thereby making the surface polishing and coupling molecule modification uniform, obtaining a chip with a stable and uniform surface, which is more conducive to the stability of detection.

[0184] In some specific implementations, the preparation method of the chip also includes modifying capture molecules or detection molecules on the polymer layer, such as nucleic acid probes, antigen antibodies, nucleic acid-protein complexes. The embodiment of the present application does not specifically limit the modification method of the capture molecules or detection molecules. For example, they can be modified by chemical coupling, including hydroxyl-carboxyl coupling, amino-carboxyl coupling, thiol-thiol coupling, click chemistry coupling, etc. In some specific implementations, the capture molecules or detection molecules can be modified after post-treatment, or after the polymer layer is formed, and then the excess polymer, capture molecules or detection molecules are removed by post-treatment.

[0185] In the embodiment of the present application, the chip includes a chip substrate, and at least the chip substrate is prepared by the above method. In some specific implementations, the prepared chip substrate is packaged so that the geometric structure on the chip substrate forms one or more flow channels to achieve the liquid flow function, realize the flow reaction of different reagents switching on the chip during the detection process, and withstand multiple cycles of reagent flushing.

[0186] In some specific implementations, the packaging material can be bonded to the chip substrate, and the bonding method includes but is not limited to thermal bonding, laser bonding, chemical and physical bonding, etc., wherein the chemical and physical bonding can be performed by UV curing adhesives, heat curing adhesives, pressure sensitive adhesives, etc. In some specific implementations, the packaging layer can be a cover plate with a geometric structure, and the geometric structure can be the same or different from the geometric structure of the chip substrate; or it can be a cover plate without a pattern.

[0187] In one embodiment, Figure 8 As shown, the first cover plate is an ordinary cover plate without a geometric structure, that is, the two surfaces of the first cover plate are untreated flat surfaces. The first cover plate is attached to the surface of the chip substrate with the geometric structure, and during the attachment process, a fluid channel is formed in the length direction of the surface with the geometric structure so that the fluid can flow through the geometric structure.

[0188] In one embodiment, Fig. 9 As shown, the first cover plate is a cover plate with a regularly arranged geometric structure on one side surface, and the geometric structure of the first cover plate is arranged relative to the geometric structure of the chip substrate. At this time, the side of the first cover plate with the bonding structure is relatively fitted with the side of the chip substrate with the geometric structure, and during the fitting process, a fluid channel is formed in the length direction of the surface with the geometric structure, through which the fluid can flow through the geometric structure. In this embodiment, the geometric structure of the first cover plate can be the same as or different from the geometric structure of the chip substrate. In order to save space, it will not be described here.

[0189] In one embodiment, Fig.10 As shown, the first cover plate and the second cover plate are respectively combined on the two side surfaces of the chip substrate geometric structure, and the first cover plate and the second cover plate are ordinary cover plates without geometric structures, that is, the two surfaces of the first cover plate and the second cover plate are flat surfaces. The first cover plate and the second cover plate are respectively attached to the two surfaces of the chip substrate with geometric structures, and during the attachment process, a fluid channel for the fluid to flow through the geometric structure is formed in the length direction of the surface with the geometric structure.

[0190] In one embodiment, Fig.11As shown, a first cover plate and a second cover plate are respectively combined on both side surfaces of the chip substrate geometric structure, wherein the first cover plate is a cover plate with a geometric structure, and the geometric structure of the first cover plate is arranged opposite to the geometric structure of the chip substrate; the second cover plate is an ordinary cover plate without a geometric structure, and the two surfaces of the second cover plate are flat surfaces. At this time, one side of the first cover plate with a combined structure is relatively fitted with a surface of the chip substrate with a geometric structure; the second cover plate is separately fitted with the other surface of the chip substrate with a geometric structure, and during the fitting process, the chip is formed with fluid channels in the length direction of the surface with the geometric structure, through which fluid can flow through the geometric structure. It should be understood that the geometric structure of the first cover plate can be the same as or different from the geometric structure of the chip substrate.

[0191] In one embodiment, Fig.12 As shown, the first cover plate and the second cover plate are respectively combined on the two side surfaces of the chip substrate geometric structure, and both cover plates are cover plates with geometric structures, and the geometric structures of the cover plates are arranged relative to the geometric structures of the chip substrate, forming a similar double-chip stacked structure. At this time, the side of the first cover plate with the combined structure is relatively fitted with one surface of the chip substrate with the geometric structure, and the side of the second cover plate with the combined structure is relatively fitted with the other surface of the chip substrate with the geometric structure, and during the fitting process, the chip is formed in the length direction of the surface with the geometric structure, respectively, so that fluid can flow through the geometric structure. It should be understood that the geometric structure of each cover plate can be the same as or different from the geometric structure of the chip substrate; the geometric structures of the two cover plates can be the same or different.

[0192] When the cover plate is a cover plate with a geometric structure, the cover plate can be prepared by the above method. The material of the cover plate can be the same as or different from the material of the chip substrate, including but not limited to glass; quartz; silicon-based materials, such as silicon dioxide, polycrystalline silicon, monocrystalline silicon, etc.; polymers, such as HMDS, PE, PP, etc. For various situations, please refer to the description of the chip above. In some specific implementations, encapsulation can be performed between any steps of forming coupling molecules, forming polymer layers, post-processing, modifying detection molecules or capturing molecules, without affecting subsequent processing.

[0193] In some embodiments, the above steps are performed on a chip substrate similar to a wafer to improve production efficiency. Therefore, before packaging, the chip can be cut to obtain a chip of a desired size.

[0194] After obtaining the biochip, gene sequencing can be performed on the biochip, which can improve the detection throughput and the stability and reliability of the sequencing structure.

[0195] Specifically, by amplifying the fixed nucleic acid molecules in the chip geometry, an amplification cluster containing 10-100,000 copies of DNA molecules is formed, and then the amplification cluster is sequenced. Because the geometric structure confines the amplification cluster to a certain space, the amplification cluster can present a shape, density, and brightness that meet the detection requirements, thereby improving the stability and reliability of the detection flux and sequencing structure. Not only that, by constraining the amplification cluster in the geometric structure of the chip provided in the embodiment of the present application, the stability of the amplification cluster during the sequencing process can be improved, so that it can withstand liquid environments including acidic reagents, alkaline reagents, organic solvents, etc., a wide reaction temperature of 4°C-90°C, more than 100 times of solution washing, etc., and can maintain good stability in this environment; moreover, using the geometric structure as a sequencing site will not only not affect the biochemical functions of biomolecules such as polymerases and amplification enzymes, but also reduce the adsorption of fluorescent dyes and nucleic acid molecules.

[0196] In this embodiment, the method for amplifying the fixed nucleic acid molecules in the chip geometry is not strictly limited, and surface polymerase chain reaction (PCR) amplification such as bridge amplification, template walking amplification, etc., or rolling circle amplification can be used, but is not limited to this.

[0197] The patterned biochip and the preparation method thereof provided in the present application are further described below in conjunction with the embodiments.

[0198] Example 1

[0199] A probe is introduced into the biochip provided in Examples 1-4, and the probe is fixed in the micropore through the polymer; a nucleic acid library (a nucleic acid sample to be tested) is introduced and surface amplification is performed to form an amplification cluster in the micropore;

[0200] Add the nucleic acid substrate ATCG with a fluorescent group and polymerase to carry out base extension reaction, collect the impact signal of each base extension reaction, and determine the type of bases involved in each round of base extension reaction in turn through image analysis to determine the sequence of the nucleic acid library.

[0201] A silane molecular film layer with an amino functional group is formed on the surface of a quartz wafer, and a polymer monomer containing a carboxyl group is used to react on the silane molecular layer to form a polymer film layer;

[0202] The coated chip substrate is cut and cleaned, and is packaged with a cover plate whose surface is not treated to obtain a biochip.

[0203] Example 2

[0204] Same as Example 1, except that the depth of the circular hole is 50 nm.

[0205] Example 3

[0206] Same as Example 1, except that the depth of the circular hole is 500 nm.

[0207] Example 4

[0208] Same as Example 1, except that the depth of the circular hole is 800 nm.

[0209] Verification Example 1

[0210] Amplification and sequencing were performed in the biochips prepared in Examples 1 to 4, respectively, and the process was as follows:

[0211] A probe is introduced into the biochip provided in Examples 1-4, and the probe is fixed in the micropore through the polymer; a nucleic acid library (a nucleic acid sample to be tested) is introduced and surface amplification is performed to form a copy of the amplification cluster in the micropore;

[0212] Add the nucleic acid substrate ATCG with a fluorescent group and polymerase to carry out base extension reaction, collect the impact signal of each base extension reaction, and determine the type of bases involved in each round of base extension reaction in turn through image analysis to determine the sequence of the nucleic acid library.

[0213] The brightness of ATCG in the fluorescent images collected by the chip provided in Examples 1-4 was statistically analyzed, and the results were as follows: Fig.16 As shown, the results show that when the well depth is 300-800 nm, ATCG has a higher brightness in the fluorescence image, indicating that when the well depth is 300-800 nm, the nucleic acid library has a higher copy number in the microwell.

[0214] The amplification occupancy, Q30, resolution rate and alignment rate in the chip amplification process provided in Examples 1-4 were statistically analyzed, and the results are as follows: Fig.17 shown.

[0215] The amplification occupancy rate refers to the percentage of the number of microwells involved in nucleic acid amplification in the patterned chip to the total number of microwells in the patterned chip;

[0216] Q30 refers to the percentage of bases with a Q value greater than or equal to 30 among all bases, and the calculation formula of Q value is: Q = -10log 10 P, where P is the error rate. Q30 can also be understood as the percentage of bases with base recognition error rates lower than 0.1% to the total number of sequenced bases. Q30 reflects the quality of sequencing. The higher the value, the better the sequencing quality.

[0217] The splitting rate refers to the percentage of nucleic acid molecules that can be matched to each labeled sample in the total number of nucleic acid molecules in the mixed sample when multiple samples are mixed and sequenced;

[0218] The alignment rate refers to the percentage of sequencing sequences that align with the sample standard sequence.

[0219] Fig.17 Display: When the pore depth is 300-800nm, ATCG has a higher brightness in the fluorescence image; when the pore depth is 50-500nm, the amplification occupancy is higher and the sequencing has a higher accuracy.

[0220] Example 5

[0221] See also Fig.18 , Fig.18 The preparation method of the biochip provided in Example 5 of the present application is as follows:

[0222] First, a silicon dioxide film with a thickness of 10 nm is formed on the surface of a silicon chip substrate by chemical vapor deposition; then a patterned glue layer is formed on the surface of the silicon dioxide film by nanoimprinting, and the chip substrate is etched according to the pattern. After removing the glue layer, regularly arranged cylindrical depressions are formed on the silicon chip substrate, the depth of the cylindrical depressions is 300 nm, the diameter of the cross section is 500 nm, and the spacing between adjacent cylindrical depressions (i.e., center to center) is 3 μm; the cylindrical depressions are arranged in a honeycomb shape, that is, the cylindrical depressions are arranged in rows and columns, the cylindrical depressions of two adjacent rows are not located in the same column, and the cylindrical depressions of the alternate row are located in the same column; the cylindrical depressions of two adjacent columns are not located in the same row, and the cylindrical depressions of the alternate column are located in the same row.

[0223] After forming a chip substrate with a pattern, a silane molecular film layer with an amino functional group is formed in the cylindrical depression, and then the polymer is fixed on the chip substrate by amino-carboxyl condensation; the silicon dioxide film is used as the polishing end point, and the biological macromolecule layer, small molecule layer and part of the silicon dioxide film outside the cylindrical depression are polished away; the polished chip substrate is cut, cleaned and packaged to obtain a biochip.

[0224] During polishing, the silicon dioxide film is used as the polishing end point. The polishing degree is monitored in real time by detecting the thickness of the remaining silicon dioxide nanofilm, which can ensure the stability and controllability of the polishing process and higher uniformity. At the same time, the SiO2 film can be used as a passivation protective layer for the substrate to keep the chip stable during the surface modification polishing process and the chip use process.

[0225] Comparative Example 1

[0226] The same as Example 4, except that the pattern glue layer is formed directly on the surface of the silicon chip substrate by nano-imprinting, without using a silicon dioxide film.

[0227] The polished biochip surfaces of Example 5 and Comparative Example 1 were tested, and the results are shown in Figures 19a-19f .in, Fig.19a This is a schematic diagram of the structure of the biochip prepared in Comparative Example 1. Fig.19bThis is a multi-channel fluorescence image of the biochip prepared in Comparative Example 1. Fig.19c This is a local surface fluorescence image of the biochip prepared in Comparative Example 1. Fig.19d This is a schematic diagram of the structure of the biochip prepared in Example 4. Fig.19e This is a multi-channel fluorescence image of the biochip prepared in Example 4. Fig.19f This is a local surface fluorescence image of the biochip prepared in Example 4.

[0228] Depend on Figures 19a-19f It can be seen that the polishing results of biochips without SiO2 film on the surface are uneven, the surface pattern is destroyed after polishing, and there are a lot of bubbles in the surface modification, which makes the surface macromolecules and subsequent detection molecule modification (nucleic acid probes, proteins, etc.) uneven and a lot of bubbles appear ( Fig.19a , Fig.19b and Fig.19c ). By depositing SiO2 thin film on the surface, and then performing surface patterning and subsequent surface modification and polishing, the degree of surface polishing can be well controlled, so that the surface polishing and modification are uniform, and the subsequent surface processes (detection molecule modification and biomolecule detection process) are stable.

[0229] Example 6

[0230] See also Fig. 20 , Fig. 20 The preparation method of the biochip provided in Example 6 of the present application is as follows:

[0231] First, a silicon dioxide film with a thickness of 10 nm is formed on the surface of a silicon chip substrate by chemical vapor deposition; then a pattern glue layer is formed on the surface of the silicon dioxide film by nanoimprinting, and the chip substrate is etched according to the pattern to form regularly arranged cylindrical depressions on the silicon chip substrate, the depth of the cylindrical depressions is 300 nm, the diameter of the cross section is 500 nm, and the spacing between adjacent cylindrical depressions (i.e., center to center) is 3 μm; the cylindrical depressions are arranged in a honeycomb shape, that is, the cylindrical depressions are arranged in rows and columns, the cylindrical depressions of two adjacent rows are not located in the same column, and the cylindrical depressions of the alternate row are located in the same column; the cylindrical depressions of two adjacent columns are not located in the same row, and the cylindrical depressions of the alternate column are located in the same row.

[0232] After forming a chip substrate with a pattern, a silane molecular film layer with an amino functional group is formed in the cylindrical depression, and then the polymer is fixed on the chip substrate by amino-carboxyl condensation; the obtained chip substrate is polished with a zirconium oxide polishing liquid, and the silicon dioxide film is used as the polishing end point to remove the biological macromolecule layer, small molecule layer, glue layer and part of the silicon dioxide film outside the cylindrical depression; the polished chip substrate is cut, cleaned and packaged to obtain a biochip.

[0233] During polishing, the silicon dioxide film is used as the polishing end point. The polishing degree is monitored in real time by detecting the thickness of the remaining silicon dioxide nanofilm, which can ensure the stability and controllability of the polishing process and higher uniformity. At the same time, the SiO2 film can be used as a passivation protective layer for the substrate to keep the chip stable during the surface modification polishing process and the chip use process.

[0234] Comparative Example 2

[0235] The same as Example 6, except that the pattern glue layer is formed directly on the surface of the silicon chip substrate by nano-imprinting, without using a silicon dioxide film.

[0236] The polished biochip surfaces of Example 6 and Comparative Example 2 were tested, and the results are shown in Figures 21a-21d .in, Fig.21a This is the surface structure diagram of the biochip prepared in Comparative Example 2. Figure 21b for Fig.21a A partial enlarged view of Fig.21c This is the surface structure diagram of the biochip prepared in Example 6. Fig.21d This is an enlarged image of the surface fluorescence of the biochip prepared in Example 6.

[0237] Depend on Figures 21a-21d It can be seen that using the silicon dioxide film as the detection endpoint can avoid the uncontrollable mechanical damage to the surface during the chemical mechanical polishing process and ensure the integrity of the surface pattern to the greatest extent.

[0238] Example 7

[0239] See also Fig. 22 , Fig. 22 The preparation method of the biochip provided in Example 7 of the present application is as follows:

[0240] Depositing a 50nm thick Al / Al2O3 film on a quartz chip substrate wafer to form a chip substrate;

[0241] A photoresist is arranged on a chip substrate, and etching is performed after exposure and development. After the photoresist is removed, a geometric structure arranged in a honeycomb shape is formed. The geometric structure is a cylindrical depression. The depth of the cylindrical depression is 300nm, the diameter of the circular bottom surface is 400nm, and the distance between the centers of adjacent cylindrical depressions is 800nm; the cylindrical depressions are arranged in rows and columns, and the cylindrical depressions of two adjacent rows are not located in the same column, and the cylindrical depressions of alternate rows are located in the same column; the cylindrical depressions of two adjacent columns are not located in the same row, and the cylindrical depressions of alternate columns are located in the same row.

[0242] A silane molecular film layer is formed on the geometric structure; a polymer monomer solution is reacted with the silane molecular layer to graft the polymer onto the silane molecules, and then polishing is performed to remove the macromolecules in the non-pattern area to obtain a biochip.

[0243] During polishing, the Al / Al2O3 film is taken as the polishing end point, and the polishing degree is monitored in real time by detecting the thickness of the remaining Al / Al2O3 nanofilm after polishing, which can ensure that the polishing process is stable and controllable with higher uniformity.

[0244] Comparative Example 3

[0245] The same as Example 7, except that a photoresist is directly disposed on the quartz chip substrate, and after exposure and development, etching is performed to form a patterned resist layer, and no Al / Al2O3 film is used.

[0246] The polished biochip surfaces of Example 7 and Comparative Example 3 were tested, and the results are shown in Figures 23a-23e .in, Fig.23a This is the surface structure diagram of the biochip prepared in Comparative Example 3. Figure 23b This is a multi-channel fluorescence image of the biochip prepared in Comparative Example 3. Fig.23c This is an enlarged image of the surface fluorescence of the biochip prepared in Comparative Example 3. Fig.23d This is the surface structure diagram of the biochip prepared in Example 5. Fig.23e This is an enlarged image of the surface fluorescence of the biochip prepared in Example 5. As can be seen from the figure, there is no end point detection surface ( Fig.23a ) can easily cause uneven polishing, and chips polished with endpoint detection method ( Fig.23d ) surface uniformity. By using a common fluorescent staining method to stain and photograph the surface, it can be seen that the uneven polishing area will lead to uneven surface modification and a large number of defects will appear in the pattern area due to excessive polishing that destroys the macromolecular modification ( Figure 23b and Fig.23c ), the polishing result with relatively detectable polishing endpoint is more uniform and the pattern area has fewer defects ( Fig.23e ). Using this surface nanofilm to detect the polishing endpoint can produce a more stable and uniform chip surface.

[0247] Example 8

[0248] First, a silicon dioxide film is formed on the surface of a silicon chip substrate by physical vapor deposition; then, a photoresist is coated on the surface of the silicon dioxide film, and after exposure, development and etching, regularly arranged cylindrical depressions are formed on the silicon chip substrate, the depth of the cylindrical depressions is 300nm, the diameter of the cross section is 300nm, and the spacing between adjacent cylindrical depressions (i.e., center to center) is 1μm; the cylindrical depressions are arranged in a honeycomb shape, that is, the cylindrical depressions are arranged in rows and columns, the cylindrical depressions of two adjacent rows are not located in the same column, and the cylindrical depressions of the alternate row are located in the same column; the cylindrical depressions of two adjacent columns are not located in the same row, and the cylindrical depressions of the alternate column are located in the same row.

[0249] After forming a chip substrate with a pattern, a silane molecular layer with an amino functional group is formed in the cylindrical depression, and then the polymer is fixed on the chip substrate by amino-carboxyl condensation; the obtained chip substrate is polished with a zirconium oxide polishing liquid, and the aluminum film is used as the polishing end point to remove the biological macromolecule layer, small molecule layer and aluminum film outside the cylindrical depression; the polished chip substrate is cut, cleaned and packaged to obtain a biochip.

[0250] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip, It is characterized in that The chip substrate comprises a chip substrate, wherein the chip substrate has regularly arranged geometric structures formed on at least one surface; The height of the geometric structure in the direction perpendicular to the chip surface is 10nm-100μm, and the maximum size in the direction horizontal to the chip surface is 10nm-100μm; the distance between adjacent geometric structures is 10nm-100μm.

2. The chip according to claim 1, It is characterized in that The height of the geometric structure in the direction perpendicular to the chip surface is 100nm to 1μm, and the maximum dimension in the direction horizontal to the chip surface is 100nm to 1μm; The distance between adjacent geometric structures is 100nm~1μm.

3. The chip according to claim 1, It is characterized in that The geometric structure is a depression or a protrusion formed on the surface of the chip substrate; Optionally, the geometric structure is formed by one or a combination of a cylinder, a cone, a truncated cone, a prism, a pyramid, a prism and an irregular shape; Optionally, the surface has at least one array unit, and the array unit has a regularly arranged geometric structure; Optionally, the array unit is one or more of a square array unit, a rectangular array unit and a honeycomb array unit.

4. The chip according to any one of claims 1 to 3, It is characterized in that The chip further comprises a first cover plate combined with a surface of one side of the chip substrate on which the geometric structure is arranged, wherein the first cover plate is made of a material with a light transmittance greater than or equal to 95%; Optionally, the surface of the first cover plate facing the chip substrate is a flat surface; or A surface of the first cover plate facing the chip substrate is provided with a regularly arranged geometric structure, and the geometric structure of the first cover plate is the same as or different from the geometric structure of the chip substrate.

5. The chip according to any one of claims 1 to 3, It is characterized in that The chip substrate has regularly arranged geometric structures on both surfaces; Optionally, the chip includes a first cover plate and a second cover plate respectively bonded to two side surfaces of the chip substrate, and the first cover plate and the second cover plate are made of a material with a light transmittance greater than or equal to 95%; Optionally, both surfaces of the first cover plate and the second cover plate are flat surfaces; or The first cover plate is a cover plate with a geometric structure arranged on a surface, and the geometric structure of the first cover plate is arranged opposite to the geometric structure of the chip substrate, and both surfaces of the second cover plate are flat surfaces; or The first cover plate and the second cover plate are both cover plates with geometric structures arranged on one surface, and the geometric structures on the first cover plate and the second cover plate are arranged opposite to the geometric structures on two surfaces of the chip substrate respectively.

6. The chip according to any one of claims 1 to 5, It is characterized in that The chip comprises a polymer layer, and the polymer layer is arranged on the surface of the geometric structure; Optionally, the polymer layer is formed of a polymer containing a first functional group, wherein the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group and an azide group; Optionally, the polymer layer is bonded to the surface of the chip substrate and / or the cover plate through coupling molecules; Optionally, the molecular formula of the coupling molecule is as follows: X a Si(Y b )M c Z, Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy; Y is selected from C 1-10 alkyl; M c Selected from C 1-50 Alkylene, -(OCH 2 CH 2 ) c -、-(CH(OH)CH 2 -) c ; Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50; Optionally, the chip further comprises a first film layer disposed between the chip substrate and / or the cover plate and the polymer layer, and the material of the first film layer is different from the material of the surface to which it is bonded; Optionally, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film; Optionally, the material of the first film layer is Au, Al and SiO 2 At least one of; Optionally, the thickness of the first film layer is 10-1000 nm.

7. The chip according to any one of claims 4 to 6, It is characterized in that A glue layer is arranged between the chip substrate and the cover plate, and the glue layer has a channel arranged in the length direction of the chip, and the geometric structure is arranged on the surface of the chip substrate and / or the cover plate in the area where the channel is located, and the shape and / or arrangement of the geometric structures in different channels on the same surface are the same or different.

8. A method for preparing a chip, It is characterized in that The following steps are involved: a) forming regularly arranged geometric structures on at least one surface of a substrate; The height of the geometric structure in the direction perpendicular to the substrate surface is 10 nm to 100 μm, and the maximum size in the direction horizontal to the substrate surface is 10 nm to 100 μm; The distance between adjacent geometric structures is 10nm~100μm.

9. The preparation method according to claim 8, It is characterized in that The substrate is a chip base and / or a cover plate; Optionally, the method further includes: b) forming a polymer layer on the geometric structure; Optionally, the geometric structure is a depression formed on the surface of the chip substrate and / or the cover plate, and b) includes: attaching a polymer having a first functional group to the surface where the geometric structure is located; polishing the polymer to remove the polymer outside the area where the geometric structure is located, and forming a polymer layer on the geometric structure; Optionally, the polishing is chemical polishing and / or mechanical polishing; Optionally, the geometric structure is a protrusion formed on the surface of the chip substrate and / or the cover plate, and before a), the method includes: attaching a polymer containing a first functional group to the surface of the substrate; Optionally, the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group and an azide group; Optionally, before connecting the polymer, the method further comprises: treating the substrate with a coupling molecule; Optionally, the molecular formula of the coupling molecule is as follows: X a Si(Y b )M c Z, Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy; Y is selected from C 1-10 alkyl; M c Selected from C 1-50 Alkylene, -(OCH 2 CH 2 ) c -、-(CH(OH)CH 2 -) c ; Z is selected from the following unsubstituted or substituted groups: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50; Optionally, the method further comprises: before step a), or after step a) and before step b), preparing a first film layer on the surface where the geometric structure is located, wherein the first film layer and the substrate are made of different materials; Optionally, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film; Optionally, the material of the first film layer is Au, Al and SiO 2 At least one of; Optionally, the thickness of the first film layer is 10 to 1000 nm; Optionally, the substrate at least includes a chip base, and the method further includes: Adhesive material is used to combine the cover plate on the surface of the chip substrate on one side where the geometric structure is arranged, and the adhesive material forms a channel in the length direction of the chip.

10. The preparation method according to claim 8 or 9, It is characterized in that The chip is the chip according to any one of claims 1 to 7.

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