System-on-chip testing method and testing device

Abstract

The invention provides a testing method and a testing device for a system-on-chip. The test device comprises an upper computer, a test board and performance detection equipment. The upper computer generates a test instruction of the chip; each test board is provided with a plurality of chip slots, a test power supply module and a temperature control module, each slot corresponds to one chip, and the temperature control module is used for controlling the chip in a set temperature interval; the performance detection module is connected with the test board and the upper computer, and tests the to-be-tested chip according to a test instruction after acquiring the test instruction set by the upper computer; testing results of the chips at different temperatures are obtained through testing and transmitted to the classification module, and the upper computer classifies the chips according to the results.

Description

Technical Field

[0001] The present invention relates to a testing device and a testing method, and in particular to a testing device capable of testing the function of a chip at different temperatures and reducing the testing time. Background Art

[0002] Currently, System on Chip (SoC) has been applied to many fields, such as processors used to complete general computing tasks in smart phones and tablet computers; processors designed for specific applications such as multimedia processing, network communication or industrial control, etc. How the chip performance plays a vital role in the application process. At the same time, SoC is a microchip that integrates a large number of semiconductor devices. It needs to be tested to ensure that all components and circuits can work properly. The testing of SoC is a key factor because it directly affects the production cost and efficiency. Therefore, the present invention proposes a method for completing the test of the chip at different temperatures while reducing the test time. Summary of the invention

[0003] The present invention provides a system-level chip testing method and testing device, which can reduce the time required for testing multiple chips and can test multiple chips under testing conditions of different temperatures.

[0004] The system-on-chip test device of the present invention is used to test multiple system-on-chips. The system-on-chip test device is mainly composed of a host computer, a test board, a data detection module, and a classification module. The host computer generates test instructions and test methods by combining a bat algorithm (BatAlgorithm) and an artificial bee colony algorithm (Artificial Bee Colony, ABC). The test board includes a chip slot; a test power supply module; and a temperature control module. There are multiple chip slots on the test board, which correspond to the chips to be tested one by one; the temperature control module is integrated on the test board, and its cold end or hot end is in contact with the chip, which is used to control the temperature of the chip during testing, so that the test device can test the performance of the chip at different temperatures. The temperature control module mainly uses a Peltier module to control the temperature; the test power supply module is integrated on the test board, which is used to supply power to the temperature control module and the chip slot during testing, so that the temperature control module and the chip can work normally; the data detection module is coupled to the host computer and the test board, receives the test instructions generated by the host computer and controls each module on the test board to perform preset steps; the classification module is coupled to the host computer and the test board, and classifies each chip according to the test results of the chip.

[0005] The system-level chip testing method of the present invention is used to test multiple system-level chips. The main process of the chip testing method is that the host computer generates test instructions and test methods by combining the bat algorithm and the artificial bee colony algorithm and transmits them to the data detection module; after the test board is powered on, it receives the start instruction from the data detection module, the temperature control module controls the chip to reach the preset temperature, and the chip is tested according to the instruction of the data detection module; the data collection system in the data detection module collects the test results and feeds the results back to the host computer; the host computer generates a corresponding number for each chip and corresponds to the respective results, and transmits the number and the result to the classification module; after the classification module receives the information from the host computer, the tested chips are classified according to the results.

[0006] Based on the above, the system-on-chip testing device and the system-on-chip testing method of the present invention enable the chip to be tested to complete performance testing on a test board in a shorter testing time and achieve classification purposes.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is the overall structure diagram of the test device;

[0009] Figure 2 is a test method flow chart;

[0010] Figure 3 It is the bat algorithm flow chart;

[0011] Figure 4 It is the artificial bee colony algorithm flow chart;

[0012] Figure 5 It is a flow chart of the algorithm in the present invention. Specific implementation methods

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1It is a schematic diagram of a SoC chip testing device drawn according to an embodiment of the present invention. In this embodiment, the SoC chip testing device is suitable for testing the SoC chip to be tested. The system-level chip testing device includes a host computer, a test board, a performance detection module, and a classification module. The host computer can program the test method, and in the present invention, it mainly completes the writing of the bat algorithm and the artificial bee colony algorithm, and the host computer can be an industrial computer, a personal laptop computer or a desktop host computer and other central control electronic devices with a data transmission interface. In this example, the SoC chip to be tested is a chip used in various mobile smart products for processing various types of data information.

[0015] In this embodiment, the host computer is mainly used to write the test algorithm, transmit the test method to the performance detection module and receive the feedback test results. The test algorithm used in this embodiment is a new algorithm BeeBat OptimizationAlgorithm that combines the bat algorithm and the artificial bee colony algorithm.

[0016] Furthermore, the bat algorithm is an optimization algorithm that simulates the echolocation predation behavior of bats, proposed by Xin-SheYang in 2010. It is a swarm-based metaheuristic algorithm suitable for optimization problems in continuous space. It simulates the method of bats using high-frequency sound waves for echolocation and determining the distance and size of the target by receiving the reflected sound waves. In the algorithm, each bat represents a solution, and the optimal solution is found by simulating the flight and search behavior of bats. The main process of the algorithm is to first initialize the position and speed of the bat group; secondly, in the iterative process, update the position and speed of each bat to simulate the bat approaching the optimal solution; then use a combination of random search and local search to explore the solution space; finally update the global optimal solution. The advantages of the bat algorithm are that it is simple and easy to implement, with few parameters; it has good global search capabilities; and it converges quickly. At the same time, its disadvantages are that for some complex problems, it may fall into the local optimum; and it is necessary to adjust the parameters to adapt to specific problems.

[0017] Furthermore, the construction process of the bat algorithm requires initializing the position and speed of each bat. The formula is as follows: f i =f min +(f max -f min )*β Where β is a random vector between 0 and 1, X * is the current local optimal solution in the group, f i is the frequency of the bat's sound waves, ranging from [f min ,f max ].

[0018] For local search, once a solution is selected among the current optimal solutions, new local solutions are generated using a random walk approach. x new =x old +εA t Among them, the interval of ε is [-1,1], A t is the average loudness of the entire group in the same iteration.

[0019] When bats search, they will continuously narrow the search range according to the target location. The method for updating the sound wave loudness and frequency of the i-th bat is as follows: Among them, α is the sound wave loudness attenuation coefficient, and its interval is (0,1). γ>0, is the pulse frequency enhancement coefficient; represents the initial pulse frequency of bat i.

[0020] Furthermore, the artificial bee colony algorithm is an optimization algorithm that simulates the foraging behavior of bees. It was proposed by Dervis Karaboga in 2005. It is an algorithm based on swarm intelligence and is suitable for solving various optimization problems. The algorithm includes three types of bees: worker bees, observer bees, and scout bees. Worker bees perform local searches near the food source. Observer bees select food sources based on the information of worker bees. Scout bees are used to randomly search for new food sources. The main process of the algorithm is: first initialize the food source (solution), worker bee stage: worker bees perform local searches near the current food source. Observer bee stage: observer bees select and search for food sources based on the information of worker bees. Scout bee stage: scout bees randomly search for new food sources. Update the global optimal solution. Its advantage is that it simulates natural foraging behavior and has a good search strategy. The scout bee mechanism effectively avoids falling into the local optimum. It is suitable for many types of optimization problems. The disadvantage is that there are many parameters and they need to be adjusted to adapt to specific problems. For high-dimensional problems, the efficiency may be low.

[0021] Furthermore, in the initialization phase, the algorithm sets the number of initial solutions, and each solution is regarded as a bee, where the initial solution can be generated randomly or set according to work experience.

[0022] Furthermore, in the worker bee stage, the algorithm will let the currently generated bees conduct local search based on the current solution space to find a new solution suitable for the current problem, which can be obtained through the following formula: Among them, x ij represents the current solution, x ij(new) represents the new solution, x kjrepresents the solution represented by another worker bee, is a random number uniformly distributed between [-1,1].

[0023] Furthermore, in the observation bee stage, each observation bee will search again based on the previous worker bee solution and select a suitable new solution, which can be obtained by the following formula: Among them, f ik Represents the current solution x ij The fitness of the bees is N, and N represents the number of bees. The probability of each solution being selected is calculated based on the fitness, and then a solution is obtained using roulette.

[0024] Furthermore, in the scout bee stage, if the worker bees and observer bees do not find a better solution during the search process, a scout bee will be generated. Each scout bee randomly selects a new solution in the solution space and updates the current optimal solution. If the new solution generated by a scout bee is better than the current optimal solution, the new solution will replace the current optimal solution.

[0025] Furthermore, a termination condition is set according to the algorithm, such as the number of iterations or the target threshold. The algorithm continuously repeats the iterative process of the three stages of worker bees, observer bees, and scout bees until the set termination condition is met.

[0026] In order to shorten the chip test time more efficiently, the bat algorithm and the artificial bee colony algorithm are combined to propose a new algorithm BeeBat Optimization Algorithm. The algorithm is mainly divided into an initialization phase, a search phase, and a parameter adjustment phase.

[0027] Furthermore, in the initialization phase, the number, position, and speed of bats are initialized according to the bat algorithm, while the position of the solution initialized by the artificial bee colony algorithm is referenced.

[0028] Furthermore, the search phase is divided into two parts: local search and global search. In the global search, the global search method of the bat algorithm is used to explore the solution space; then the worker bee method in the artificial bee colony algorithm is used to perform local search to refine the current solution area. This can reduce the occurrence of local optimal situations in the algorithm as much as possible.

[0029] Furthermore, in the parameter adjustment stage, we first refer to the relationship between worker bees and observer bees in the artificial bee colony algorithm, so that bats have an information sharing mechanism, adjust the search direction according to the optimal solution found, and let some bats follow the bat with the current best solution; then, according to the method of adjusting parameters according to fitness in the artificial bee colony algorithm, dynamically adjust the frequency and volume of the bats; finally, when the bats have not been updated for a long time, the scout bee strategy will be adopted to find out whether there is a better solution. If so, the current optimal solution will be replaced. If not, the current optimal solution will be used as the final solution of the algorithm.

[0030] The algorithm proposed in the present invention combines the bat algorithm and the artificial bee colony algorithm, utilizing the global exploration capability of the bat algorithm and the local development capability of the ABC algorithm, and simultaneously runs multiple search processes through information sharing, strategy fusion, and dynamic parameter adjustment, thereby utilizing the parallel processing capabilities of the two algorithms to improve the efficiency and accuracy of the optimization process.

[0031] Furthermore, the algorithm in the present invention can be implemented using the Python programming language, but is not limited to the Python programming language.

[0032] Furthermore, the test module of the performance detection module in the test device can adopt a series of test equipment such as automatic test equipment (ATE). Its main task in the chip test process is to apply the required stimulus signal to the chip input pipeline and monitor the chip output pin to see whether its output signal is the expected value.

[0033] The host computer transmits the written algorithm to the performance detection module. In the test module in the performance detection module, the various parameter data of the chip when working normally are first set as the target value; then the algorithm in the present invention is used for optimization, and we can find the optimal test parameter combination more quickly, thereby reducing the chip test time. The test module sends an excitation signal to the chip in the test board according to the optimized test parameters to make the chip start working.

[0034] The test board is powered on through the test power supply module on the test board, so that the chip and the temperature control module start working. The chip receives the excitation signal from the test module and starts working, and the temperature control module controls the chip at the set temperature.

[0035] Furthermore, the temperature control module of the present invention adopts a Peltier module, but is not limited to a Peltier module. A Peltier module, also known as a thermoelectric module or a semiconductor refrigeration module, is a solid-state device that can transfer heat when an electric current is applied. They work based on the Peltier effect, in which a current flowing through two different conductive materials produces a thermal difference. This phenomenon enables the Peltier module to act as both a heater and a cooler depending on the direction of the current. The advantage of the Peltier module is that the temperature of a specific area can be accurately controlled with an accuracy of ±0.05°C; when the heating and cooling states need to be switched, it can be achieved by simply changing the direction of the current; at the same time, the Peltier module is small in size and noiseless. The simple operation and efficient performance of the Peltier module can make the testing process of the present invention more convenient and efficient.

[0036] When the chip works at different temperatures, the data acquisition system in the performance test module will detect the output pins of the chip to observe whether the output signal of the chip has reached the expected value. It can also test in which temperature range the chip can fully exert its performance and in which temperature range the chip's performance will be abnormal.

[0037] The data acquisition module collects the test results of each chip to be tested, and sends the test results to the host computer after each chip test is completed. At this time, the host computer will number the chips and match them one by one with the test results.

[0038] The host computer transmits the classification results to the classification module, and the classification module classifies the chips according to the chip numbers and the corresponding test results.

[0039] Furthermore, the test results are divided according to the performance of the chip at normal temperature and the performance at high temperature. The test results of different chips at normal temperature or high temperature are classified. At normal temperature, chips with normal working performance are divided into one category, and chips with abnormal performance are divided into another category; at high temperature, chips with normal working performance are divided into one category, and chips with abnormal performance are divided into another category.

[0040] The main process of the system-level chip testing method proposed by the present invention includes writing an algorithm program for optimizing the test process through a host computer, transmitting the algorithm program to the test module in the performance test module, and the detection module sets the target value of each parameter according to the chip data. By using the optimization algorithm to find a better combination of test parameters, the test can be completed more efficiently. Start the test power supply module of the test board to power on the chip and the temperature control module. The chip starts after receiving the excitation signal of the test module, and the temperature control module controls the working temperature of the chip; the data acquisition module of the performance detection module collects the chip performance data working at different temperatures and transmits it to the host computer one by one; the host computer numbers the chips and corresponds them to the test results one by one, and then transmits them to the classification module; the classification module classifies the chips according to the chip number and the test results at different temperatures.

[0041] The present invention proposes a testing device and a testing method for a system-level chip, which can realize the testing task of the chip at different temperatures. Through the innovative optimization algorithm, the test efficiency is improved and the test time is reduced. The temperature control module also adopts a small, easy-to-operate and efficient module, making the entire test process easier to control.

[0042] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A system-on-chip test device for testing a plurality of chips to be tested, characterized in that: The timing test device comprises: Host computer; Test board; Chip slot; Test the power supply module; Temperature control module; Performance detection module; Classification module; Among them: the host computer and the performance detection module are connected; the performance detection module is connected to the host computer and the test board; the temperature control module is integrated on the test board; the test power supply module is integrated on the test board; and the classification module is coupled to the host computer.

2. The system-on-chip test device according to claim 1, characterized in that: The test chip is a SOC chip used in smart products such as mobile phones.

3. The system-on-chip test device according to claim 1, characterized in that: The test board comprises: The test power supply module is used to supply power to each module on the test board when starting the test board.

4. The system-on-chip test device according to claim 1, characterized in that: The test board also includes: The temperature control module is integrated on the test board and controls the chip to perform tests within multiple pre-set test temperature ranges.

5. The system-on-chip testing device according to claim 1, characterized in that: The performance detection module includes: The performance detection module is coupled to the test board and the host computer, receives the test instruction from the host computer, and controls the module on the test board to respond according to the test instruction.

6. The system-on-chip test device according to claim 1, characterized in that: The classification module comprises: The classification module is coupled to the data detection module, receives the test result of the data detection module obtained by the host computer, and classifies the tested chips according to the test result.

7. The temperature control module according to claim 4, characterized in that: The temperature control module comprises: The Peltier module is integrated into the test board, and its cold end or hot end is in contact with the chip to control the increase or decrease of the chip temperature.

8. The performance detection module according to claim 5, characterized in that: The performance detection module includes: Central processing unit (CPU), used to coordinate all operations and test processes of the data detection module; The performance test system combines the artificial bee colony algorithm and the bat algorithm to test the performance of the chip at different temperatures while reducing the test time; Data acquisition system to collect test results.

9. A system-on-chip testing method, using a system-on-chip testing device to test a chip to be tested, wherein the system-on-chip testing device comprises a testing board, a performance detection module, and a classification module, and the testing method comprises: The host computer generates a test command and sends it to the performance detection module. After the test board is powered on, the performance detection module controls the temperature control module on the test board so that the chip is tested at a preset temperature. After obtaining the test data, the performance detection module feeds it back to the classification module, and the classification module classifies the chips that have completed the test according to the results.

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