Test pattern generation using multiple scan enabled

Abstract

The invention relates to test pattern generation using multiple scan enable. An integrated circuit includes first and second sets of scan flip-flops, a circuit under test, and a controller. Each scan flip-flop in the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip-flop downstream of the logic element. Each scan flip-flop in the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic element by shifting a test pattern into the first set while asserting the first scan enable signal and the second scan enable signal, transmitting the test pattern, and capturing a result from the second set while continuing asserting the first scan enable signal and de-asserting the second scan enable signal.

Description

Technical Field

[0001] The present invention relates generally to test pattern generation for testing of integrated circuits and, in a particular embodiment, to structures of integrated circuits having designs for testability functionality implemented with scan chains and methods of operating the same. Background Art

[0002] With the rapid increase in the number of circuit elements in integrated circuits and the correspondingly rapid decrease in the size of these circuit elements, it is becoming increasingly important to develop efficient and effective test methods for integrated circuits. In addition, more and more components in integrated circuits are becoming internalized and the number of logic levels is also increasing (e.g., in complex implementations such as systems on a chip (SoC)). Automatic test pattern generation (ATPG) can be used to improve test efficiency and test coverage of possible faults. However, the size and complexity of modern integrated circuits increases pattern counts and test times.

[0003] To ensure reliable operation of integrated circuits, many different types of faults must be tested. One particular class of faults involving signal timing includes faults such as path delay faults and transition delay faults. Because identifying timing faults depends on system timing, these faults must be tested at system speed. This "at-speed testing" transmits a test pattern along a path (e.g., through the combinational logic being tested) and captures the results after a time defined by the system timing (e.g., one or more system clock cycles).

[0004] Before launching, the test pattern is shifted into a test register (e.g., a scan flip-flop configured to operate in either a functional mode or a scan mode depending on the signal received at the scan enable input). During the shift, the scan flip-flop operates in the scan mode. Before capturing, the scan flip-flop must be in the functional mode, which may cause timing problems for the transition of the scan enable signal. There are two basic methods to ensure that the scan enable signal is fully transitioned between the last shift and capture: the launch-off-capture (LOC) method and the launch-off-shift (LOS) method.

[0005] In the LOC method, there is a dead cycle after the last shift to allow the scan enable signal to transition at a slower speed than the system clock. This allows the test clock (for the shift pulse) to be at a lower speed than the system clock. However, LOC sacrifices control because the scan enable signal transitions the scan flip-flop to functional mode (capture mode) before the launch pulse. As a result, the launch is based on the functional logic, causing the ATPG pattern to be continuous, which increases the pattern count.

[0006] On the other hand, the LOS method transmits the pattern on the last shift, requiring the scan enable signal to transition between the transmit pulse and the capture pulse (two full-speed pulses). Compared to LOC, the scan enable signal holds the scan flip-flop in the scan mode (transmit mode) during the transmit pulse in LOS. This provides more control but has strict timing requirements that may be difficult or impossible to meet. Therefore, a full-speed test method that reduces the pattern count compared to LOC without the strict timing requirements of LOS can be expected. Summary of the invention

[0007] According to an embodiment of the present invention, an integrated circuit includes a first set of scan triggers, a circuit under test, a second set of scan triggers, and a controller. Each scan trigger in the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes a logic element downstream of the first set of scan triggers. The second set of scan triggers includes at least one scan trigger downstream of the logic element. Each scan trigger in the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic element by shifting a test pattern into the first set while asserting both the first scan enable signal and the second scan enable signal, emitting the test pattern, and capturing a result from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

[0008] According to another embodiment of the present invention, an integrated circuit includes: a circuit under test, including an initiator logic element and a target logic element; a first scan chain of scan triggers, including the initiator logic element; a second scan chain of scan triggers, including the target logic element; and a controller configured to test the circuit under test. Each scan trigger in the first scan chain includes a scan enable input coupled to a first scan enable signal. Each scan trigger in the second scan chain includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the circuit under test by shifting a first test pattern into the first scan chain while both the initiator logic element and the target logic element are operating in a transmission mode, transmitting the first test pattern, and capturing a result from the second scan chain while the initiator logic element is operating in the transmission mode and the target logic element is operating in the capture mode.

[0009] According to yet another embodiment of the present invention, a method of testing an integrated circuit includes: shifting a first test pattern into a first set of scan flip-flops of an integrated circuit upstream of a first logic element of the integrated circuit while asserting both a first scan enable signal and a second scan enable signal. Each scan flip-flop in the first set includes a scan enable input coupled to the first scan enable signal. The method also includes deasserting the second scan enable signal while continuing to assert the first scan enable signal, emitting the first test pattern, and capturing results from a second set of scan flip-flops of the integrated circuit downstream of the first logic element while the first scan enable signal is asserted and the second scan enable signal is deasserted. Each scan flip-flop in the second set includes a scan enable input coupled to the second scan enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 An example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal;

[0012] Figure 2 Another example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first scan chain coupled to a first scan enable signal and a second scan chain coupled to a second scan enable signal, wherein the integrated circuit comprises a first-in-first-out circuit;

[0013] Figure 3 An example integrated circuit having DFT functionality in accordance with an embodiment of the present invention is illustrated, the integrated circuit including a controller having a scan enable input, the controller controlling a first scan enable signal coupled to a first set of scan flip-flops and also controlling a second scan enable signal coupled to a second set of scan flip-flops;

[0014] Figure 4 Another example integrated circuit having DFT functionality in accordance with an embodiment of the present invention is illustrated, the integrated circuit including a controller having a scan enable input, the controller controlling a first scan enable signal coupled to a first set of scan flip-flops and also controlling a second scan enable signal coupled to a second set of scan flip-flops;

[0015] Figure 5An example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal;

[0016] Figure 6 Another example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal, wherein the integrated circuit comprises a first-in, first-out circuit;

[0017] Figure 7 An example scan flip-flop of an integrated circuit with DFT functionality according to an embodiment of the present invention is illustrated, wherein the scan flip-flop has a local scan enable; and

[0018] Figure 8 An example method of testing an integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit including a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal.

[0019] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the range of the features. DETAILED DESCRIPTION

[0020] The making and using of various embodiments are discussed in detail below. However, it should be appreciated that the various embodiments described herein are applicable to a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the various embodiments, and should not be construed as limited in scope. Unless otherwise specified, the expressions "approximately," "approximately," and "substantially" mean within 10% of a given value, and preferably within 5%, or, such as in the case of substantially zero, less than 10% and preferably less than 5% of a comparable amount.

[0021] As electronic circuits (e.g., integrated circuits such as SoCs) grow in size and become more complex (e.g., increased logic levels), the number of test patterns required to test the electronic circuits also increases. This increase in pattern count results in a corresponding increase in test time. At the same time, due to the poor controllability of conventional full-speed test methods, test coverage (e.g., DFT coverage) is reduced. The increase in circuit complexity also results in physical design constraints in order to meet full-speed high fan-out non-functional paths, which may further reduce test coverage. These issues become increasingly important as the size and complexity of integrated circuits such as SoCs increase.

[0022] While DFT tools are also becoming more advanced, there are still many tool limitations in terms of high mode counts and huge mode generation times. Designs that launch and capture using the LOC method have higher mode counts due to reduced control, while the LOS method has strict (and often unfeasible) timing requirements. Power consumption is another area that can affect mode count. For example, relying on the tool to reduce capture power can also lead to severe mode expansion. Therefore, it is recognized that while current DFT tools are advanced, there are still undesirable limitations. Therefore, methods that are both timing friendly and can reduce mode counts are desired.

[0023] Conventional solutions for pattern generation are LOC and LOS methods. In LOS, the scan enable signal is high between the launch pulse and the capture pulse (i.e., the scan trigger is in scan mode). The scan enable signal will transition to low (functional mode) between the launch pulse and the capture pulse (strict full-speed timing requirements), but the scan enable signal is asserted during the launch (based on the scan input (SI input) of the scan trigger). This allows more control over the downstream logic, allowing the tool to more easily generate patterns and reduce pattern counts. However, the full-speed clock (e.g., system clock) that defines the duration between the launch pulse and the capture pulse may be very high relative to the test clock (e.g., a 1GHz system clock requires a transition of less than 1ns compared to a 50MHz test clock). It will be very difficult or impossible to meet this transition timing requirement on the scan enable path (e.g., due to high fan-out transitions). For this reason, the conventional LOS method is not feasible in many cases.

[0024] The LOC method avoids the timing requirements for the scan enable path by generating a mode that allows the scan enable signal to transition to low before the transmit pulse during a dead test cycle (or more than one dead test cycle). Because the scan enable signal is low (functional mode) during the transmit pulse, the emission is based on functional logic (e.g., the functional input terminal (D input terminal) of the scan trigger). This control using only upstream logic limits the ability to target faults, such as path delay faults and transition delay faults. The downstream logic will be captured at the functional input terminal of another scan trigger. Due to the reliance on upstream functional logic to control downstream logic, the conventional LOC method reduces tool flexibility and increases pattern count, which in turn reduces coverage. That is, due to the increase in pattern count and the reduction in DFT coverage, conventional LOC has limitations.

[0025] In various embodiments, the integrated circuits described herein with DFT functionality include separate scan enables used simultaneously during emission and capture of a test mode. For example, a first set of scan flip-flops are coupled to a first scan enable signal, and a second set of scan flip-flops are coupled to a second scan enable signal. The set of scan flip-flops may be selected based on knowledge of a given design (e.g., by identifying similarly located elements as initiators or targets when testing certain logic elements). Alternatively, some or all of the set of scan flip-flops may be connected without regard to design details (e.g., according to a script during scan insertion).

[0026] The controller (internal or external) can be configured to test the logic element by moving into a test mode while the scan trigger is in a scan mode (transmit mode). For example, while moving into the test mode, the first scan enable signal and the second scan enable signal can be asserted. The controller can also be configured to transmit the test mode and capture the results from the second set of scan triggers while the second set is in a functional mode (capture mode) and the first set remains in the scan mode (transmit mode). For example, the second scan enable signal can be de-asserted and the first scan enable signal can be asserted.

[0027] Embodiments described herein can reduce or eliminate the disadvantages of conventional pattern generation methods previously discussed. For example, embodiment integrated circuits can provide an efficient scanning method by ensuring that pattern counts are reduced to reduce test time (e.g., compared to conventional LOC methods) while avoiding strict timing requirements on scan enable paths (e.g., compared to conventional LOS methods). In other words, embodiment launch and capture methods and corresponding integrated circuits described herein can advantageously provide the advantages of conventional LOS and LOC while reducing or eliminating their disadvantages.

[0028] The embodiments described herein may also be advantageously implemented in any project having a scan implementation, such as a SoC or other integrated circuit. Various embodiments, such as embodiments that take into account the details of a given design during scan insertion, may be advantageous for use in future designs, while some embodiments, such as embodiments that use tool options for scan insertion without taking into account design details, may have the advantage of being immediately usable for current devices as well as future devices.

[0029] The embodiments provided below describe various integrated circuits having DFT functionality, and in particular, DFT functionality including a set of scan flip-flops coupled to a scan enable signal that is asserted during shifting and de-asserted during capturing and including another set of scan flip-flops coupled to a different scan enable signal that is asserted during both shifting and capturing. The following description describes embodiments. Figure 1 Used to describe an example integrated circuit. Figure 2 An example integrated circuit having a circuit under test including a FIFO circuit is described. Figure 3 and Figure 4 Two example integrated circuits having a controller configured to simultaneously drive a first scan enable signal and a second scan enable signal are described. Figure 5 Describe another integrated circuit. Use Figure 6 Another example integrated circuit having a circuit under test including a FIFO circuit is described. Figure 7 Describes the example scan trigger. Figure 8 Example methods of testing integrated circuits are described.

[0030] Figure 1 An example integrated circuit having DFT functionality in accordance with an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal.

[0031] refer to Figure 1 , the integrated circuit 100 includes a circuit under test 110, a first set of scan flip-flops 111, and a second set of scan flip-flops 112. The circuit under test 110 includes a logic element 126 to be tested using the first set of scan flip-flops 111 and the second set of scan flip-flops 112. The circuit under test 110 may be any circuit including logic elements, such as a FIFO circuit, a Joint Test Action Group (JTAG) state machine, a memory circuit, a bus register, and a peripheral read / write register. The circuit under test 110 may include various combinations of combinational logic elements and sequential logic elements.

[0032] The first set of scan flip-flops 111 may be similarly located within the design. For example, the first set of scan flip-flops 111 may be an initiator logic element relative to the logic element 126 (e.g., located upstream of the logic element 126). Similarly, the second set of scan flip-flops 112 may be a target logic element relative to the logic element 126 (e.g., located downstream of the logic element 126). In various embodiments, the first set of scan flip-flops 111 and the second set of scan flip-flops 112 are sequential logic elements of a combinational logic element coupled to the logic element 126. The first set of scan flip-flops 111 may be a first scan chain 121 (e.g., of an initiator logic element) (or a portion thereof), and the second set of scan flip-flops 112 may be a second scan chain 122 (e.g., of a target logic element separate from the first scan chain 121) (or a portion thereof), as shown. Alternatively, one or more scan flip-flops with different scan enable signals may be part of the same chain (i.e., a hybrid chain).

[0033] Some or all of the scan flip-flops may have a function during normal operation in addition to the test function as part of the scan chain. For example, when the circuit under test 110 includes a FIFO circuit, the first set 111 of scan flip-flops may be configured to write to the FIFO circuit (and read from the FIFO), and the second set 112 of scan flip-flops may include a FIFO shift register (functional logic). As another example, when the circuit under test 110 includes a JTAG state machine, the first set 111 of scan flip-flops may include a common data shift register, and the second set 112 of scan flip-flops may include multiple test data registers.

[0034] In another example, when the circuit under test 110 includes a memory circuit, the first set of scan triggers 111 may be configured to write (and / or read) from a memory cell of the memory circuit (e.g., BIST), and the second set of scan triggers 112 may include a memory cell (e.g., a bit). In yet another example, when the circuit under test 110 includes a bus interface and a peripheral interface, the first set of scan triggers 111 may include the bus interface and the second set of scan triggers 112 may include the peripheral interface.

[0035] Each scan trigger 13 includes a functional input terminal 17 (D input terminal) and a functional output terminal 18 (Q output terminal). In addition, each scan trigger 13 includes a scan input terminal 23 (SI input terminal) and a scan output terminal 19 (SO output terminal). Specifically, the scan enable input terminal 16 (SE input terminal) of each scan trigger 13 selects between the functional input terminal 17 and the scan input terminal 23. Conceptually, the scan trigger 13 is shown as having two separate output terminals. However, in practice, the scan trigger 13 can have only one output terminal (Q output terminal), and the selected input terminal (functional input terminal 17 or scan input terminal 23) is propagated to the clock input terminal 24 (CLK input terminal) using a pulse.

[0036] Logic element 126 is located downstream of first set 111 of scan flip-flops. In one embodiment, logic element 126 is a combinational logic element. Logic element 126 may also be a single logic element (such as a single logic gate, etc.). At least one of second set 112 of scan flip-flops is located downstream of logic element 126, as shown.

[0037] The integrated circuit 100 includes a first scan enable signal 31 and a second scan enable signal 32 that can be controlled separately, and the scan enable input terminal 16 of each scan trigger in the first set 111 of scan triggers is coupled to the first scan enable signal 31, while the scan enable input terminal 16 of each scan trigger in the second set 112 of scan triggers is coupled to the second scan enable signal 32.

[0038] The first scan enable signal 31 (shown as SE_A) and the second scan enable signal 32 (shown as SE_B) can be coupled to dedicated external connections, such as the first test pin 14 and the second test pin 15 shown. For example, the first test pin 14 and the second test pin 15 can be test pads of the integrated circuit 100. In this way, the first scan enable signal 31 and the second scan enable signal 32 can be controlled externally (e.g., completely controlled by external test equipment). Alternatively, the first test pin 14 and the second test pin 15 can be combined into a single external connection (e.g., test pin / pad), or the first scan enable signal 31 and the second scan enable signal 32 can be completely controlled internally (e.g., as in a logic built-in self-test (LBIST)). The first scan enable signal 31 and the second scan enable signal 32 can be dynamically switched by the tool during testing.

[0039] A controller 130 may be included to control some or all aspects of the shift, transmit, and capture phases of the test process. For example, the controller 130 may be configured to control the timing and transitions of the first scan enable signal 31 and the second scan enable signal 32. In the case where the first scan enable signal 31 and the second scan enable signal 32 are separate and provided externally, the controller 130 may be configured to control the generation of test pulses such as the shift pulse 91, the transmit pulse 92, and the capture pulse 93 for each test mode. The test pulses may also be driven externally (e.g., this may be made possible by relaxed timing requirements compared to the strict timing requirements of conventional LOS).

[0040] When the first scan enable signal 31 and the second scan enable signal 32 are combined (whether as a single external connection or as a single internal connection), the controller 130 can be configured to control the first scan enable signal 31 and the second scan enable signal 32 using, for example, a combination of scan flip-flops, logic gates, multiplexers, and / or inverters. These scan flip-flops can be part of one or more scan chains (e.g., control scan chains) to facilitate control of the first scan enable signal 31 and the second scan enable signal 32. The controller 130 can also be configured to test the logic element 126 by shifting a test pattern into the scan flip-flops, emitting the test pattern, and capturing the result from the scan flip-flops.

[0041] Partitioning the scan flip-flops into separate groups connected to separate scan enables can allow for favorable timing properties during shifting, emission, and capture. For example, a test pattern can be shifted into the scan flip-flops (e.g., the first set of scan flip-flops 111) while both the first scan enable signal 31 and the second scan enable signal 32 are asserted (e.g., high "1"), thereby placing the first set of scan flip-flops 111 and the second set of scan flip-flops 112 in a scan mode (emission mode).

[0042] Because there are two separate scan enable signals, the second scan enable signal 32 can be de-asserted (e.g., low "0") before the launch pulse 92 places the second set of scan flip-flops 112 in the functional mode (capture mode), and the test pattern can be launched with the first set of scan flip-flops 111 (e.g., upstream scan flip-flops, initiator logic elements) in the launch mode. The result can then be captured from one or more of the second set of scan flip-flops 112 in the capture mode (e.g., downstream of the logic element 126, the target logic element). Therefore, compared to conventional LOC, the launch advantages and corresponding flexibility and pattern reduction benefits can be obtained without the strict timing requirements of conventional LOS. In addition, the ability to launch with upstream flip-flops in the launch mode can advantageously allow the test mode to be only a combination test mode, which can reduce the pattern count.

[0043] When the first set 111 of scan flip-flops and the second set 112 of scan flip-flops are selected based on design knowledge, a greater pattern reduction can be advantageously obtained. For example, using design knowledge (e.g., by reading and analyzing the design), the initiator and target logic can be divided into different partitions at the register transfer level (RTL) scan insertion level, and different scan enable signals can be connected to them (either externally or internally). The scan flip-flops can be inserted as different scan chains (as shown). This can be suitable for the first device iteration / first cut of a product (e.g., of a product family) because partitioning can be performed.

[0044] Various criteria can be used to divide the logic of a given design into several categories in order to connect different scan enable signals. For example, logic of similar types can be grouped, logic that is spatially or functionally similar can be grouped (e.g., logic blocks), and so on. In some cases, classification by type of logic can provide better coverage because scan triggers in similar locations will be connected to the same scan enable signal. In some cases, tools can be designed to splice related logic into a single scan chain based on their clock and hierarchy. For example, master (e.g., initiator) logic elements and slave (e.g., target) logic elements may already be placed in different hierarchies, allowing separate scan enable signals to be connected to an already existing scan chain.

[0045] Using the initiator / target approach, the tool can advantageously always (or at least most of the time) transmit in a manner similar to LOS and capture in a manner similar to LOC, which can provide greater coverage for the same pattern count than conventional LOC, and the scan enable path is constant between the transmit pulse 92 and the capture pulse 93 (there is no scan enable switching between the two full-speed pulses as in LOS).

[0046] Alternatively, (e.g. Figure 5-Figure 7 ) can connect some or all of the scan flip-flops regardless of the design, and the tool can use a launch similar to LOS and a capture similar to LOC when possible, and otherwise use a conventional LOC. This can still have the effect of providing more coverage than using only a conventional LOC for the same pattern count, and the scan enable path remains constant between the launch pulse 92 and the capture pulse 93. The hybrid approach may require slightly more patterns to achieve the same coverage than the initiator / target approach, but does not require any design knowledge. Therefore, the decision of how to connect the separate scan enable signals is a choice that can be made based on the specific requirements of a given application.

[0047] The timing diagram showing clock signal 90 and the corresponding scan enable signal for conventional LOS and conventional LOC is provided for comparison with the embodiments described herein, which use multiple (e.g., two) scan enable signals to transmit similar to LOS and capture similar to LOC. As shown, shifting the test pattern uses a test clock pulse (shift pulse 91, which is clocked slower than the system clock), and transmitting the test pattern and capturing the result uses two full-speed pulses (transmit pulse 92 and capture pulse 93, which are faster than the test clock and can be as fast as the system clock).

[0048] In LOS, the scan enable signal is high during the emission pulse 92, but the fall time of the scan enable path (plus the logic settling time) must be shorter (as short as 1 ns or even faster) than the time between the emission pulse 92 and the capture pulse 93. In LOC, there is a delay between the last shift pulse 91 and the emission pulse 92 to allow the scan enable signal to transition, but the scan enable signal is low during the emission pulse 92. In contrast, when two scan enable signals (SE_A and SE_B) are used, the scan enable signal for the upstream scan flip-flop (the first scan enable signal 31, SE_A) is high during the emission pulse 92, and the scan enable signal for the captured scan flip-flop (the downstream scan flip-flop) is low during the capture pulse 93, while still allowing for a delay between the last shift pulse 91 and the emission pulse 92.

[0049] The roles of a collection of scan triggers (e.g., initiator versus target) can be switched depending on the specifics of what is being tested. In one specific example, when testing memory, both reads and writes are tested. To test write functionality, an initiator logic (e.g., BIST) configured to write to memory can play the initiator role, while the memory itself (memory cell) can play the target role.

[0050] However, to test read functionality, the memory can play the initiator role and the BIST plays the target role. In this case, the timing diagrams for the SE_A and SE_B signals will switch because the roles are switched. That is, the upstream for write testing is now downstream, so SE_A will go low and SE_B will remain high before the launch pulse 92. That is, the initiator logic element and the target logic element will both be in the launch mode during the shift, and the initiator logic element will transition to the capture mode before the launch and be in the capture mode during the capture, while the target logic element continues to operate in the launch mode.

[0051] Figure 2Another example integrated circuit with DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first scan chain coupled to a first scan enable signal and a second scan chain coupled to a second scan enable signal, wherein the integrated circuit comprises a FIFO circuit. For example, Figure 2 The integrated circuit may be any other integrated circuit described herein (such as Figure 1 Components with similar labels may be as described above.

[0052] refer to Figure 2 , integrated circuit 200 includes a circuit under test 210, which includes a FIFO circuit. It should be noted that here and below, for the sake of brevity and clarity, a convention is adopted where elements following the pattern [x10] can be related implementations of the circuit under test in various embodiments, where "x" is a figure number. For example, unless otherwise specified, the circuit under test 210 can be similar to the circuit under test 110. Similar conventions are adopted for other elements, which is made clear by using similar terms in conjunction with the numbering system mentioned above.

[0053] In this specific example, the circuit under test 210 includes a FIFO circuit and includes a first scan chain 221 configured to write to the FIFO circuit (and read from the FIFO) selected as a first category (initiator logic) in the circuit under test 210 and a second scan chain 222 selected as a second category (target logic) in the circuit under test 210 including a shift register (i.e., functional logic) of the FIFO circuit. In particular, the first set 211 of scan flip-flops is coupled to the first scan enable signal 31 and the second set 212 of scan flip-flops is coupled to the second scan enable signal 32 (here shown as the first scan chain 221 and the second scan chain 222, but additional scan flip-flops as part of the same scan chain or different scan chains may also be included).

[0054] Here, SE_A (first scan enable signal 31) can be made high during emission, so that emission passes through the SI input terminal of the first scan chain 221 (similar to LOS). There is no control restriction like the conventional LOC because the upstream scan flip-flop is coupled to SE_A, and SE_A is kept at "1". That is, the value of the test pattern is directly driven when it is shifted in.

[0055] On the other hand, SE_B (second scan enable signal 32) is made low during capture, but is not subject to the timing constraints of conventional LOS because a delay (e.g., one or more dummy test cycles) may be included between the last shift and the transmit pulse. Thus, the functional output (Q output) of the second scan chain 222 is captured during the capture pulse. SE_B does not need to be high during transmit to transmit through the SI input because the transmit is from the first scan chain 221 coupled to SE_A.

[0056] The first scan enable signal 31 and the second scan enable signal 32 can be driven from a controller. The controller scan trigger can be part of another scan chain. The logic element 226 of the FIFO circuit is tested using the first scan chain 221 and the second scan chain 222. For example, as shown here, the logic element 226 can include combinational logic. The scan trigger in the first scan chain 221 is located upstream of the logic element 226, while the scan trigger of the second scan chain 222 is located downstream of the logic element 226.

[0057] Figure 3 An example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit including a controller having a scan enable input terminal, the controller controlling a first scan enable signal coupled to a first set of scan flip-flops and also controlling a second scan enable signal coupled to a second set of scan flip-flops. For example, Figure 3 The integrated circuit may be any other integrated circuit described herein (such as Figure 1 Components with similar labels may be as described above.

[0058] refer to Figure 3 , the integrated circuit 300 includes a circuit under test 310, which includes a first set 311 of scan triggers coupled to a first scan enable signal 31 (SE_A) and a second set 312 of scan triggers coupled to a second scan enable signal 32 (SE_B). The integrated circuit 300 also includes a controller 330, which is configured to drive both SE_A and SE_B simultaneously using a combination test pin 41. It should be noted that the combination test pin 41 can be an external connection (such as a test pad), but can also be an internal connection (such as an LBIST circuit). For example, in applications with pin limitations, the use of the combination test pin 41 can be advantageous. In contrast to embodiments using separate pins, both the first scan enable signal 31 and the second scan enable signal 32 can be controlled by reading from an internal scan trigger using the combination test pin 41.

[0059] The controller 330 includes a scan enable input 35 coupled to the combination test pin 41. The first scan enable signal 31 is coupled to the output 77 of the first scan enable multiplexer 37, and the second scan enable signal 32 is coupled to the output 79 of the second scan enable multiplexer 39. The first scan enable multiplexer 37 and the second scan enable multiplexer 39 are used to select between the output of the internal scan flip-flop(s) or the scan enable input 35, which is coupled to both the first input 57 of the first scan enable multiplexer 37 and the first input 59 of the second scan enable multiplexer 39. The selection of the first scan enable multiplexer 37 and the second scan enable multiplexer 39 can be controlled using a test control unit (TCU) bit (tcu_bit_0).

[0060] The scan enable input 35 is also coupled to the first input 56 of the first OR gate 36 and the first input 58 of the second OR gate 38. Intermediate scan enable signals (SE_A_int and SE_B_int) are generated by the OR gates at outputs 76 and 78, respectively. Additional inputs of the OR gates (second input 66 and second input 68) are connected to the internal scan flip-flops to provide control to the controller 330.

[0061] For example, as shown here, the output terminal (Q) of the first controller scan trigger 33 can be coupled to the second input terminal 66 of the first OR gate 36, and the output terminal (Q) of the second controller scan trigger 34 can be coupled to the second input terminal 68 of the second OR gate 38. The output terminals of the first controller scan trigger 33 and the second controller scan trigger 34 can be coupled to their respective functional input terminals (D). The first controller scan trigger 33 and the second controller scan trigger 34 can be part of an internal scan chain. Alternatively, (as shown in reference Figure 4 As discussed) a single controller scan trigger can also be used instead of the two shown here.

[0062] When the scan enable input 35 is "1", due to the OR logic of the first OR gate 36 and the second OR gate 38, both the first scan enable signal 31 and the second scan enable signal 32 are "1". However, when the scan enable input 35 is "0", all four options ("00", "01", "10", "11") are possible. In this way, the controller 330 can be configured to simultaneously drive the first scan enable signal 31 and the second scan enable signal 32 to test the logic element by controlling, for example, the transition between asserting both the first scan enable signal 31 and the second scan enable signal 32 during shifting and deasserting only one (or even both) during emission and / or capture. This allows the emission and capture timing discussed previously, as well as other timings that may be clear to those skilled in the art.

[0063] Figure 4 Another example integrated circuit with DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit including a controller having a scan enable input terminal, the controller controlling a first scan enable signal coupled to a first set of scan flip-flops and also controlling a second scan enable signal coupled to a second set of scan flip-flops. For example, Figure 4 The integrated circuit may be any other integrated circuit described herein (such as Figure 1 Components with similar labels may be as described above.

[0064] refer to Figure 4 , the integrated circuit 400 includes a circuit under test 410, which includes a first set 411 of scan flip-flops and a second set 412 of scan flip-flops, similar to the integrated circuit 300. Also similar to the integrated circuit 300, the integrated circuit 400 includes a controller 430, which has a scan enable input 35 coupled to the combination test pin 41 and transmits at least two scan enable signals (here, the first scan enable signal 31 and the second scan enable signal 32) to the set of scan flip-flops at its output. However, in contrast to the controller 330, the controller 430 includes a combination controller scan flip-flop 43, the output (Q) of which is coupled to both the second input 66 of the first OR gate 36 and to the inverter 42, which is coupled to the second input 68 of the second OR gate 38.

[0065] The controller 430 is functionally similar to the controller 330 embodiment. For example, when the scan enable input 35 is "1", due to the OR logic of the first OR gate 36 and the second OR gate 38, both the first scan enable signal 31 and the second scan enable signal 32 are still "1". However, unlike the controller 430, when the scan enable input 35 is "0", due to the inverter 42, only two options ("01", "10") are possible. This can be seen as a minor difference because the "11" state is still available when the scan enable input 35 is "1". In any case, the controller 430 can also be configured to simultaneously drive the first scan enable signal 31 and the second scan enable signal 32 to test the logic element by controlling, for example, the transition between asserting both the first scan enable signal 31 and the second scan enable signal 32 during the shift and deasserting one of the two during the emission and / or capture.

[0066] The combined scan flip-flop implementation of controller 430 may have a slightly higher pattern count than the two scan flip-flop implementation of controller 330 while still maintaining the lower pattern count advantage over conventional approaches.

[0067] Figure 3 and Figure 4 The controller implementation may be useful for low pin count applications. Connections between the scan flip-flops in each set have been intentionally omitted because controller 330 and controller 430 may be used to control first scan enable signal 31 and second scan enable signal 32 regardless of the specific method of grouping the scan flip-flops in the circuit under test (e.g., considering design in an initiator / target configuration, not considering design according to script rules, or some combination thereof).

[0068] In the previous example, separate scan enable signals can be connected to a set of scan flip-flops (e.g., a scan chain) based on the role / situation / location within the design. However, the possibility of connecting separate scan enable signals to a set of flip-flops without considering the design details is also mentioned. Figure 5-Figure 7 Several examples are shown of how separate scan enable signals can be connected to a collection of scan flip-flops without regard to design details of some or all of the scan flip-flops in the design. That is, these embodiments advantageously do not require knowledge of either the initiator logic or the target logic in a given design.

[0069] Figure 5 An example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal. Figure 5 The integrated circuit may be any other integrated circuit described herein (such as Figure 1 Components with similar labels may be as described above.

[0070] refer to Figure 5 , the integrated circuit 500 includes a circuit under test 510, a first set of scan triggers 511 and a second set of scan triggers 512. Optionally, a controller 530 may be included in the integrated circuit 500 to drive the first scan enable signal 31 and the second scan enable signal 32 to test the logic element 526 of the circuit under test 510. Alternatively, the test control may be completely external. Figure 1 Similar to the integrated circuit 100 of the present invention, the first set 511 of scan flip-flops are each coupled to the first scan enable signal 31, and the second set 512 of scan flip-flops are each coupled to the second scan enable signal 32. However, unlike the integrated circuit 100, the first scan chain 521 includes scan flip-flops from each set (e.g., the first scan chain 521 is a "hybrid" scan chain).

[0071] Although the first scan chain 521 may include all scan flip-flops in both the first set 511 of scan flip-flops and the second set 512 of scan flip-flops, it may also include a subset of each (as shown) to reflect the common case of inserting multiple scan chains. For example, the second scan chain 522 may include some or all or the remaining scan flip-flops in the first set 511 of scan flip-flops and some or all of the remaining scan flip-flops in the second set 512 of scan flip-flops, and so on.

[0072] One approach to inserting a scan chain in this manner may be to insert the scan chain with a single scan enable signal, regardless of the details of the design. A script may then be used to remove scan enable connections to a subset of the scan flip-flops of the inserted scan chain according to some rule or rules, and replace those connections with one or more additional scan enable signals. For example, adjacent scan flip-flops throughout the design may be coupled to different scan enable signals (e.g., alternating between a first scan enable signal 31 and a second scan enable signal 32, as shown).

[0073] This allows the tool to use LOS transmit and LOC capture when possible, and revert to conventional LOC otherwise (i.e., hybrid). In this way, the timing requirements of conventional LOS are still advantageously avoided, while the pattern count is still reduced over pure conventional LOC due to the ability to use LOS transmit and LOC capture at certain times. Since this method of connecting separate scan enable signals does not require any design knowledge, it can be beneficial for use in delivery equipment, production cutting, etc., for example.

[0074] Figure 6 Another example integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit comprising a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal, wherein the integrated circuit comprises a FIFO circuit. For example, Figure 6 The integrated circuit may be any other integrated circuit described herein (such as Figure 5 Components with similar labels may be as described above.

[0075] refer to Figure 6 , the integrated circuit 600 includes a circuit under test 610 including a FIFO circuit having a logic element 626. Like the circuit under test 210 also including a FIFO circuit, the circuit under test 610 includes a first scan chain 621 configured to write to the FIFO circuit (and read from the FIFO) and a second scan chain 622 including a shift register of the FIFO circuit.

[0076] However, unlike the circuit under test 210, the first scan enable signal 31 and the second scan enable signal 32 are connected to the first set 611 and the second set 612 of scan flip-flops, respectively, without knowing the underlying design. In this specific example, adjacent scan flip-flops are coupled to different scan enable signals (e.g., alternating between the first scan enable signal 31 and the second scan enable signal 32 as shown).

[0077] Figure 7 An example scan flip-flop of an integrated circuit with DFT functionality according to an embodiment of the present invention is illustrated, wherein the scan flip-flop has a local scan enable. For example, Figure 7 The integrated circuit may be a specific embodiment of other scan triggers described herein and may be included in an integrated circuit described herein (such as Figure 1 Components with similar labels may be as described above.

[0078] refer to Figure 7 , the scan trigger 713 can be used in any of the sets or scan chains of scan triggers included in the circuit under test of the integrated circuit described herein. As shown, the scan trigger 713 is configured with a local scan enable (e.g., by a script without regard to the design) using an OR gate 71 coupled to a test pin 74. The local scan enable can also avoid the strict timing requirements of the scan enable path of the conventional LOS by enabling a local LOS transmission paradigm.

[0079] Figure 8 An example method of testing an integrated circuit having DFT functionality according to an embodiment of the present invention is illustrated, the integrated circuit including a first set of scan flip-flops coupled to a first scan enable signal and a second set of scan flip-flops coupled to a second scan enable signal. Figure 8 The method can be combined with other methods and performed using the systems and devices described herein. For example, Figure 8 The method can be used with Figure 1-Figure 7 Although shown in a logical order, Figure 8 The arrangement and numbering of the steps are not intended to be limiting. Figure 8 The method steps may be performed in any suitable order, or concurrently with each other, as may be apparent to those skilled in the art.

[0080] refer to Figure 8, step 801 of the method 800 for testing an integrated circuit includes shifting a first test pattern into a first set of scan triggers of the integrated circuit. The first set of scan triggers is located upstream of a first logic element of the integrated circuit. The shifting of the first test pattern is performed while asserting a first scan enable signal and a second scan enable signal. Each scan trigger in the first set includes a scan enable input terminal coupled to the first scan enable signal.

[0081] In step 802, the second scan enable signal is de-asserted while the first scan enable signal continues to be asserted. In step 803, the first test pattern is emitted. Then, in step 804, a result is captured from a second set of scan flip-flops of the integrated circuit. The second set of scan flip-flops is located downstream of the first logic element. In contrast to the first set of scan flip-flops coupled to the first scan enable signal, each scan flip-flop in the second set includes a scan enable input coupled to the second scan enable signal. The capture of the result is performed while the first scan enable signal is asserted and the second scan enable signal is de-asserted.

[0082] Example embodiments of the invention are summarized herein. Other embodiments may be understood from the entire specification and claims filed herein.

[0083] Example 1. An integrated circuit comprising: a first set of scan triggers, each scan trigger in the first set including a scan enable input terminal coupled to a first scan enable signal; a circuit under test, including a logic element downstream of the first set of scan triggers; a second set of scan triggers, including at least one scan trigger downstream of the logic element, each scan trigger in the second set including a scan enable input terminal coupled to a second scan enable signal; and a controller configured to test the logic element by shifting a test mode into the first set while asserting both the first scan enable signal and the second scan enable signal, emitting the test mode, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

[0084] Example 2. The integrated circuit of Example 1, wherein the first set of scan flip-flops is a first scan chain, and wherein the second set of scan flip-flops is a second scan chain separate from the first scan chain.

[0085] Example 3. The integrated circuit of one of Examples 1 and 2, wherein the circuit under test includes a first-in-first-out (FIFO) circuit, wherein the scan flip-flops of the first scan chain are configured to write to the FIFO circuit, and wherein the scan flip-flops of the second scan chain include shift registers of the FIFO circuit.

[0086] Example 4. The integrated circuit of Example 1, further comprising: a scan chain of scan flip-flops, comprising a subset of the first set and a subset of the second set, wherein scan enable inputs of adjacent scan flip-flops of the scan chain are coupled to different scan enable signals.

[0087] Example 5. The integrated circuit of one of Examples 1 to 4, further comprising: a first test pin coupled to the first scan enable signal; and a second test pin coupled to the second scan enable signal.

[0088] Example 6. An integrated circuit of one of Examples 1 to 4, wherein the controller is configured to simultaneously drive a first scan enable signal and a second scan enable signal to test a logic element, the controller comprising a scan enable input, at least one controller scan trigger, a first OR gate, a first scan enable multiplexer, a second OR gate, and a second scan enable multiplexer, the first OR gate comprising a first input coupled to the scan enable input and a second input coupled to at least one controller scan trigger, the first scan enable multiplexer comprising a first input coupled to the scan enable input, a second input coupled to the first OR gate, and an output coupled to the first scan enable signal, the second OR gate comprising a first input coupled to the scan enable input and a second input coupled to at least one controller scan trigger, the second scan enable multiplexer comprising a first input coupled to the scan enable signal, a second input coupled to the second OR gate, and an output coupled to the second scan enable signal.

[0089] Example 7. The integrated circuit of Example 6, wherein the at least one controller scan flip-flop includes a first controller scan flip-flop coupled to the second input of the first OR gate and a second controller scan flip-flop coupled to the second input of the second OR gate.

[0090] Example 8. An integrated circuit of one of Examples 6 and 7, wherein at least one controller scan trigger is a combination controller scan trigger, which includes an output terminal coupled to the second input terminal of the first OR gate and coupled to an inverter, which is coupled to the second input terminal of the second OR gate.

[0091] Example 9. The integrated circuit of any of Examples 6 to 8, further comprising: a combination test pin coupled to a scan enable input of the controller.

[0092] Example 10. The integrated circuit of any of Examples 6 to 9, further comprising: a logic built-in self-test circuit coupled to a scan enable input of the controller.

[0093] Example 11. The integrated circuit of any of Examples 1 to 10, wherein the test mode is a combination test mode.

[0094] Example 12. The integrated circuit of one of Examples 1 to 11, wherein the shift test mode uses a test clock pulse, and wherein emitting the test mode and capturing the result use two full speed pulses.

[0095] Example 13. An integrated circuit comprising: a circuit under test, including an initiator logic element and a target logic element; a first scan chain of scan triggers, including the initiator logic element, each scan trigger in the first scan chain including a scan enable input terminal coupled to a first scan enable signal; a second scan chain of scan triggers, including the target logic element, each scan trigger in the second scan chain including a scan enable input terminal coupled to a second scan enable signal; and a controller configured to test the circuit under test by shifting a first test mode into the first scan chain while both the initiator logic element and the target logic element are operating in a transmission mode, transmitting the first test mode, and capturing results from the second scan chain while the initiator logic element is operating in the transmission mode and the target logic element is operating in a capture mode.

[0096] Example 14. The integrated circuit of Example 13, wherein the circuit under test includes a first-in, first-out (FIFO) circuit, wherein the initiator logic element is configured to write to the FIFO circuit, and wherein the target logic element includes a shift register of the FIFO circuit.

[0097] Example 15. The integrated circuit of one of Examples 13 and 14, wherein the circuit under test comprises a Joint Test Action Group (JTAG) state machine, wherein the initiator logic element comprises a shared shift data register, and wherein the target logic element comprises a plurality of test data registers.

[0098] Example 16. An integrated circuit of one of Examples 13 to 15, wherein the controller is further configured to test the circuit under test by shifting a second test pattern into the second scan chain while both the initiator logic element and the target logic element operate in a transmit mode, transmitting the second test pattern, and capturing results from the first scan chain while the initiator logic element operates in a capture mode and the target logic element operates in a transmit mode.

[0099] Example 17. The integrated circuit of Example 16, wherein the circuit under test includes a memory circuit, wherein the target logic element includes a memory cell of the memory circuit, and wherein the initiator logic element is configured to write to the memory cell during testing using a first test mode and is configured to read from the memory cell during testing using a second test mode.

[0100] Example 18. The integrated circuit of one of Examples 13 to 17, wherein shifting the first test pattern uses a test clock signal, and wherein transmitting the first test pattern and capturing the result use two full-speed pulses.

[0101] Example 19. A method for testing an integrated circuit, the method comprising: shifting a first test pattern into a first set of scan triggers of an integrated circuit upstream of a first logic element of the integrated circuit while asserting both a first scan enable signal and a second scan enable signal, each scan trigger in the first set including a scan enable input coupled to the first scan enable signal; deasserting the second scan enable signal while continuing to assert the first scan enable signal; emitting the first test pattern; and capturing results from a second set of scan triggers of the integrated circuit downstream of the first logic element while the first scan enable signal is asserted and the second scan enable signal is deasserted, each scan trigger in the second set including a scan enable input coupled to the second scan enable signal.

[0102] Example 20. The method of Example 19, wherein the first set of scan flip-flops is a first scan chain, and wherein the second set of scan flip-flops is a second scan chain separate from the first scan chain.

[0103] Example 21. The method of Example 20, wherein the integrated circuit includes a first-in-first-out (FIFO) circuit, wherein the scan flip-flops of the first scan chain are configured to write to the FIFO circuit, and wherein the scan flip-flops of the second scan chain include shift registers of the FIFO circuit.

[0104] Example 22. The method of Example 19, wherein the integrated circuit includes a scan chain of scan flip-flops, the scan chain of scan flip-flops including a subset of the first set and a subset of the second set, wherein scan enable inputs of adjacent scan flip-flops in the scan chain are coupled to different scan enable signals.

[0105] Example 23. The method of one of Examples 19 to 22, further comprising: shifting a second test pattern into a second set of scan triggers while asserting both the first scan enable signal and the second scan enable signal, the second set of scan triggers being located upstream of a second logic element of the integrated circuit; deasserting the first scan enable signal while continuing to assert the second scan enable signal; emitting the second test pattern and capturing results from the first set of scan triggers while the first scan enable signal is deasserted and the second scan enable signal is asserted, the first set of scan triggers being located downstream of the second logic element.

[0106] Example 24. The method of one of Examples 19 to 23, wherein shifting the first test pattern uses a test clock signal, and wherein transmitting the first test pattern and capturing the result use two full-speed pulses.

[0107] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art after reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An integrated circuit, comprising: a first set of scan flip-flops, each scan flip-flop in the first set comprising a scan enable input coupled to a first scan enable signal; a circuit under test including logic elements downstream of a first set of scan flip-flops; a second set of scan flip-flops, including at least one scan flip-flop downstream of the logic element, each scan flip-flop in the second set including a scan enable input coupled to a second scan enable signal; and The controller is configured to test the logic element by: shifting the test pattern into the first set while asserting both the first scan enable signal and the second scan enable signal, Transmit test mode, and Results are captured from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

2. The integrated circuit of claim 1, wherein: The first set of scan flip-flops is a first scan chain, and wherein the second set of scan flip-flops is a second scan chain separate from the first scan chain.

3. The integrated circuit of claim 1, wherein: The circuit under test includes a first-in-first-out (FIFO) circuit, wherein the scan flip-flops of the first scan chain are configured to write into the FIFO circuit, and wherein the scan flip-flops of the second scan chain include shift registers of the FIFO circuit.

4. The integrated circuit of claim 1 , further comprising: A scan chain of scan flip-flops includes a subset of the first set and a subset of the second set, wherein scan enable inputs of adjacent scan flip-flops in the scan chain are coupled to different scan enable signals.

5. The integrated circuit of claim 1 , further comprising: A first test pin coupled to a first scan enable signal; as well as The second test pin is coupled to a second scan enable signal.

6. The integrated circuit of claim 1, wherein: A controller is configured to simultaneously drive a first scan enable signal and a second scan enable signal to test a logic element, the controller comprising: Scan enable input, at least one controller scan trigger, a first OR gate including a first input terminal coupled to the scan enable input terminal and a second input terminal coupled to at least one controller scan flip-flop, a first scan enable multiplexer including a first input terminal coupled to a scan enable input terminal, a second input terminal coupled to a first OR gate, and an output terminal coupled to a first scan enable signal, a second OR gate including a first input terminal coupled to the scan enable input terminal and a second input terminal coupled to at least one controller scan flip-flop, The second scan enable multiplexer includes a first input terminal coupled to the scan enable signal, a second input terminal coupled to the second OR gate, and an output terminal coupled to the second scan enable signal.

7. The integrated circuit of claim 6, wherein: The at least one controller scan flip-flop includes a first controller scan flip-flop coupled to the second input terminal of the first OR gate and a second controller scan flip-flop coupled to the second input terminal of the second OR gate.

8. The integrated circuit of claim 6, wherein: At least one controller scan flip-flop is a combination controller scan flip-flop including an output terminal coupled to both the second input terminal of the first OR gate and an inverter coupled to the second input terminal of the second OR gate.

9. The integrated circuit of claim 6, further comprising: Combination test pin, coupled to the scan enable input of the controller.

10. The integrated circuit of claim 6, further comprising: The logic has a built-in self-test circuit coupled to the scan enable input of the controller.

11. An integrated circuit comprising: a circuit under test, including an initiator logic element and a target logic element; a first scan chain of scan flip-flops including an enabler logic element, each scan flip-flop in the first scan chain including a scan enable input coupled to a first scan enable signal; a second scan chain of scan flip-flops including a target logic element, each scan flip-flop in the second scan chain including a scan enable input coupled to a second scan enable signal; as well as A controller configured to test the circuit under test by: shifting a first test pattern into a first scan chain while both the initiator logic element and the target logic element are operating in a transmit mode, Transmitting the first test pattern, and Results are captured from the second scan chain while the initiator logic element operates in a transmit mode and the target logic element operates in a capture mode.

12. The integrated circuit of claim 11, wherein: The circuit under test includes a first-in-first-out (FIFO) circuit, wherein the initiator logic element is configured to write to the FIFO circuit, and wherein the target logic element includes a shift register of the FIFO circuit.

13. The integrated circuit of claim 11, wherein: The circuit under test includes a Joint Test Action Group (JTAG) state machine, wherein the initiator logic element includes a common shift data register, and wherein the target logic element includes a plurality of test data registers.

14. The integrated circuit of claim 11, wherein: The controller is also configured to test the circuit under test by: shifting a second test pattern into the second scan chain while both the initiator logic element and the target logic element are operating in the transmit mode, Transmitting a second test pattern, and Results are captured from the first scan chain while the initiator logic element operates in a capture mode and the target logic element operates in a transmit mode.

15. The integrated circuit of claim 14, wherein: The circuit under test includes a memory circuit, wherein the target logic element includes a memory cell of the memory circuit, and wherein the initiator logic element is configured to write to the memory cell during testing using a first test mode and is configured to read from the memory cell during testing using a second test mode.

16. A method for testing an integrated circuit, the method comprising: shifting a first test pattern into a first set of scan flip-flops of the integrated circuit upstream of a first logic element of the integrated circuit while asserting both a first scan enable signal and a second scan enable signal, each scan flip-flop in the first set including a scan enable input coupled to the first scan enable signal; deasserting the second scan enable signal while continuing to assert the first scan enable signal; transmitting a first test pattern; as well as A result is captured from a second set of scan flip-flops of the integrated circuit downstream of the first logic element while the first scan enable signal is asserted and the second scan enable signal is deasserted, each scan flip-flop in the second set including a scan enable input coupled to the second scan enable signal.

17. The method of claim 16, wherein: The first set of scan flip-flops is a first scan chain, and wherein the second set of scan flip-flops is a second scan chain separate from the first scan chain.

18. The method of claim 17, wherein: The integrated circuit comprises a first-in-first-out (FIFO) circuit, wherein the scan flip-flops of the first scan chain are configured to write into the FIFO circuit, and wherein the scan flip-flops of the second scan chain comprise shift registers of the FIFO circuit.

19. The method of claim 16, wherein: The integrated circuit includes a scan chain of scan flip-flops, the scan chain of scan flip-flops including a subset of a first set and a subset of a second set, wherein scan enable inputs of adjacent scan flip-flops of the scan chain are coupled to different scan enable signals.

20. The method of claim 16, further comprising: shifting a second test pattern into a second set of scan flip-flops while asserting both the first scan enable signal and the second scan enable signal, the second set of scan flip-flops being located upstream of a second logic element of the integrated circuit; deasserting the first scan enable signal while continuing to assert the second scan enable signal; A second test pattern is emitted while the first scan enable signal is de-asserted and the second scan enable signal is asserted and results are captured from a first set of scan flip-flops, the first set of scan flip-flops being located downstream of the second logic element.

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