High power supply rejection ratio low noise LDO implementation circuit

Abstract

The application discloses a high-power-supply-suppression-ratio low-noise LDO implementation circuit and belongs to the technical field of integrated circuits. The circuit comprises a voltage reference source, an internal LDO circuit, a voltage follower, a filter circuit and a non-overlapping clock generation circuit. The output end of a first error amplifier EA1 of the internal LDO circuit is connected with the gate of a PMOS tube PM511 in an output stage circuit. The source of a PMOS tube PM303 and the source of a PMOS tube PM301 of the filter circuit are both connected with the drain of the PMOS tube PM511. The gate of the PMOS tube PM303 is connected with the output end of a power-on OK detection circuit. The drain of the PMOS tube PM303 is connected with the drain of a PMOS tube PM302 and the positive pole of a capacitor Cbig. The drain of the PMOS tube PM301 is connected with the source of the PMOS tube PM302 and the positive pole of a capacitor Csmall. The positive input end of a second error amplifier EA2 of the voltage follower is connected with the positive pole of a capacitor CF1. The output end of the second error amplifier EA2 is connected with the gate of a PMOS tube PM622. The application realizes a high-PSRR LDO architecture with low power consumption, reduces the performance requirement and greatly reduces the system overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a high-power-supply-rejection-ratio low-noise LDO implementation circuit. BACKGROUND

[0002] Low-dropout linear voltage regulators (LDOs) have been widely used in various devices, such as various smart phones, personal notebook computers, smart mobile terminals and other mobile portable devices. In order to ensure that the device system works more safely and reliably, high-quality power supply is essential. At present, most mobile portable devices have a large number of sensing sensor precision systems and radio frequency transceiver circuits for transmitting communication information. These precision and noise-sensitive systems require the system to provide low-noise high-power-supply-rejection-ratio (PSRR) power supply.

[0003] In a traditional high-PSRR LDO scheme, in order to reduce the multiplication effect of the output error amplifier on the reference voltage noise, the output stage often adopts a voltage follower scheme, and the first internal LDO multiplies the output voltage. In order to reduce the noise and PSRR influence of the reference voltage, a low-pass filter is used after the first internal LDO to minimize the influence of the previous stage, and the noise and PSRR of the system output are mainly contributed by the voltage follower of the output stage. In the traditional LDO scheme, the noise is mainly composed of four parts: the noise generated by the bandgap reference itself, the noise of the first internal LDO, the noise generated by the reference voltage filter circuit, and the noise generated by the LDO error amplifier. Similarly, the power supply noise coupled into the LDO is also composed of four parts: the path from the power supply to the bandgap reference voltage, the path from the power supply to the first internal LDO, the path from the power supply to the error amplifier output, and the path from the power supply to the output through the power tube. With the increasing requirement of modern devices on system power consumption, lower static current means higher noise, and the fast transient response of the LDO is also a challenge. Therefore, the part of the system generating the reference voltage and the first internal LDO cannot consume too much static power consumption, and more power consumption will be allocated to the error amplifier of the LDO. Therefore, the reference voltage and the first internal LDO will contribute too much noise output to the system. Worse still, in order to achieve high PSRR, the bandgap reference needs a very complex architecture, which will increase the static power consumption and wafer cost.

[0004] Therefore, to improve the noise performance and PSRR of the system reference voltage, a simple RC filter circuit is a viable solution. Implementing a low-bandwidth low-pass filter requires relatively large resistors and capacitors, which necessitates a considerable chip area. However, due to cost or packaging considerations, the chip area cannot be increased indefinitely, and the resistors and capacitors cannot be too large. Therefore, a large off-chip capacitor, CBP, is needed to simply implement a low-cutoff frequency low-pass filter. This can significantly improve the system's noise performance and PSRR. However, using an external capacitor raises the issue of ESD. Introducing ESD devices increases the area and makes them sensitive to high-temperature leakage, which also increases the user's overall system cost.

[0005] Therefore, a circuit LDO is needed to avoid ESD problems and solve the problem of unstable power supply. Summary of the Invention

[0006] In order to solve some existing problems, the present invention aims to provide a high power supply rejection ratio and low noise LDO implementation circuit to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A high power supply rejection ratio and low noise LDO implementation circuit includes a voltage reference source, an internal LDO circuit, a voltage follower, a filtering circuit and a non-overlapping clock generation circuit;

[0009] The internal LDO circuit includes a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit, and a power-on OK detection circuit; the input VREF of the voltage reference source is connected to the positive input terminal of the first error amplifier EA1, the output terminal of the first error amplifier EA1 is connected to the gate of the PMOS transistor PM511 in the output stage circuit, the source of the PMOS transistor PM511 in the output stage circuit is connected to the power supply VIN, the drain of the PMOS transistor PM511 in the output stage circuit is connected to one end of the resistor divider R501, the other end of the resistor divider R501 is simultaneously connected to the negative input terminal of the first error amplifier EA1 and one end of the resistor R502, and the other end of the resistor R502 is grounded; the drain of the PMOS transistor PM511 is connected to one input terminal of the power-on OK detection circuit, and the other input terminal of the power-on OK detection circuit is connected to the power supply VIN;

[0010] The phase compensation network circuit is connected to the gate of the PMOS tube PM511 in the output stage circuit;

[0011] The first bias circuit is electrically connected to the first error amplifier EA1 and the power-on OK detection circuit;

[0012] The filter circuit comprises a PMOS PM301, a PMOS PM302, a PMOS PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1, the source of the PMOS PM303 and the source of the PMOS PM301 are connected with the drain of a PMOS PM511, the gate of the PMOS PM303 is connected with the output end of the power-on OK detection circuit, the gate of the PMOS PM301 is connected with the output signal PH1b of the non-overlapping clock generation circuit, the drain of the PMOS PM303 is connected with the drain of the PMOS PM302 and the positive pole of the capacitor Cbig, and the negative pole of the capacitor Cbig is grounded; the drain of the PMOS PM301 is connected with the source of the PMOS PM302 and the positive pole of the capacitor Csmall, and the negative pole of the capacitor Csmall is grounded; the gate of the PMOS PM302 is connected with the output signal PH2b of the non-overlapping clock generation circuit, the positive pole of the capacitor Cbig is connected with one end of the resistor RF1, the other end of the resistor RF1 is connected with the positive pole of the capacitor CF1, and the negative pole of the capacitor CF1 is grounded.

[0013] The voltage follower comprises a second error amplifier EA2 and a PMOS PM622, the positive input end of the second error amplifier EA2 is connected with the positive pole of the capacitor CF1, the negative input end of the second error amplifier EA2 is connected with the power supply VOUT, the output end of the second error amplifier EA2 is connected with the gate of the PMOS PM622, the source of the PMOS PM622 is connected with the power supply VIN, and the drain of the PMOS PM622 is connected with the power supply VOUT.

[0014] As a further scheme of the application, the non-overlapping clock generation circuit comprises a NAND gate NAND1, a NAND gate NAND2, a NOT gate INV0, a NOT gate INV1, a NOT gate INV2, a NOT gate INV3, a NOT gate INV4, a NOT gate INV5, a NOT gate INV6, a NOT gate INV7, a NOT gate INV8, a NOT gate INV9, a NOT gate INV10, a NOT gate INV11, a NOT gate INV12, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2.

[0015] The CLK signal is connected with one input end of the NAND gate NAND1 and the input end of the NOT gate INV0, and the other input end of the NAND gate NAND1 and the output end of the NOT gate INV10.

[0016] The output end of the NOT gate INV0 is connected with one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 and the output end of the NOT gate INV4.

[0017] The output end of the NAND gate NAND1 is connected with the input end of the NOT gate INV1, the output end of the NOT gate INV1 is connected with the input end of the NOT gate INV2, the output end of the NOT gate INV2 is connected with one end of the resistor R11, the other end of the resistor R11 is connected with the positive pole of the capacitor C1 and the input end of the NOT gate INV3, the output end of the NOT gate INV3 is connected with the input end of the NOT gate INV4, the output end of the NOT gate INV4 is connected with the input end of the NOT gate INV5, the output end of the NOT gate INV5 is connected with the input end of the NOT gate INV6, and the output end of the NOT gate INV6 outputs the signal PH1b; the negative pole of the capacitor C1 is grounded.

[0018] The output end of the NAND gate NAND2 is connected with the input end of the NOT gate INV7, the output end of the NOT gate INV7 is connected with the input end of the NOT gate INV8, the output end of the NOT gate INV8 is connected with one end of the resistor R12, the other end of the resistor R12 is connected with the positive pole of the capacitor C2 and the input end of the NOT gate INV9, the output end of the NOT gate INV9 is connected with the input end of the NOT gate INV10, the output end of the NOT gate INV10 is connected with the input end of the NOT gate INV11, the output end of the NOT gate INV11 is connected with the input end of the NOT gate INV12, and the output end of the NOT gate INV12 outputs the signal PH2b; the negative pole of the capacitor C2 is grounded.

[0019] As a further scheme of the application: the first error amplifier EA1 in the internal LDO circuit comprises NMOS tubes NM501, NMOS tube NM502, NMOS tube NM506, NMOS tube NM507, NMOS tube NM508, NMOS tube NM509, NMOS tube NM513, NMOS tube NM514, PMOS tube PM503, PMOS tube PM504, PMOS tube PM501 and PMOS tube PM502.

[0020] The source of the PMOS tube PM503 and the source of the PMOS tube PM504 are connected with the power supply VIN; the gate of the PMOS tube PM503 is connected with the drain of the PMOS tube PM503, the gate of the PMOS tube PM504 and the drain of the NMOS tube NM513; the drain of the PMOS tube PM504 is connected with the drain of the NMOS tube NM514;

[0021] The gate of the NMOS tube NM513 is connected with the gate of the NMOS tube NM514, the source of the NMOS tube NM513 is connected with the drain of the NMOS tube NM501 and the drain of the NMOS tube NM506; the source of the NMOS tube NM514 is connected with the drain of the NMOS tube NM502 and the drain of the NMOS tube NM509;

[0022] The gate of the NMOS tube NM501 is connected with the gate of the PMOS tube PM502; the gate of the NMOS tube NM502 is connected with the gate of the PMOS tube PM501 and the output VREF of the voltage reference source; the gate of the NMOS tube NM501 is the input negative pole of the first error amplifier EA1; the gate of the NMOS tube NM502 is the input positive pole of the first error amplifier EA1; the drain of the NMOS tube NM514 is the output terminal of the first error amplifier EA1;

[0023] The drain of the PMOS tube PM501 is connected with the gate of the NMOS tube NM506, the gate of the NMOS tube NM507 and the drain of the NMOS tube NM507; the source of the NMOS tube NM506 and the source of the NMOS tube NM507 are grounded; the drain of the PMOS tube PM502 is connected with the gate of the NMOS tube NM508, the gate of the NMOS tube NM509 and the drain of the NMOS tube NM508; the source of the NMOS tube NM508 and the source of the NMOS tube NM509 are grounded.

[0024] As a further scheme of the application, the power-on OK detection circuit in the internal LDO circuit comprises a PMOS tube PM507, a PMOS tube PM508, an NMOS tube NM510 and an NMOS tube NM511; the source of the PMOS tube PM507 and the source of the PMOS tube PM508 are connected with the power supply VIN; the drain of the PMOS tube PM507 is connected with the gate of the PMOS tube PM508, the drain of the NMOS tube NM510 and the gate of the NMOS tube NM511; the drain of the NMOS tube NM511 is connected with the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit;

[0025] The gate of the NMOS tube NM510 is connected with the drain of the NMOS tube NM514 and the gate of the PMOS tube PM511 in the output stage circuit; the source of the NMOS tube NM510 and the source of the NMOS tube NM511 are grounded.

[0026] As a further scheme of the application, the first bias circuit in the internal LDO circuit comprises an NMOS tube NM503, an NMOS tube NM504, an NMOS tube NM505, an NMOS tube NM512, a PMOS tube PM505, a PMOS tube PM506, a current source I501 and a current source I502;

[0027] The input end of the current source I501 and the input end of the current source I502 are connected with the power supply VIN; the output end of the current source I501 is connected with the gate of the NMOS tube NM512, the drain of the NMOS tube NM512 and the gate of the NMOS tube NM513; the source of the NMOS tube NM512 is grounded; the output end of the current source I502 is connected with the gate of the NMOS tube NM503, the drain of the NMOS tube NM503, the gate of the NMOS tube NM504 and the gate of the NMOS tube NM505;

[0028] The drain of the NMOS tube NM504 is connected with the source of the NMOS tube NM501; the drain of the NMOS tube NM505 is connected with the drain of the PMOS tube PM505, the gate of the PMOS tube PM505, the gate of the PMOS tube PM506 and the gate of the PMOS tube PM507; the source of the PMOS tube PM505 and the source of the PMOS tube PM506 are connected with the power supply VIN; the source of the NMOS tube NM503, the source of the NMOS tube NM504 and the source of the NMOS tube NM505 are grounded.

[0029] As a further scheme of the application, the phase compensation network circuit in the internal LDO circuit comprises a resistor R503 and a capacitor C503; one end of the capacitor C503 is connected with the power supply VIN; the other end of the capacitor C503 is connected with one end of the resistor R503, and the other end of the resistor R503 is connected with the gate of the PMOS tube PM511.

[0030] The output stage circuit in the internal LDO circuit comprises the PMOS tube PM511, a resistor R501, a resistor R502, a capacitor C501 and a capacitor C502; the drain of the PMOS tube PM511 is connected with one end of the resistor R501 and one end of the capacitor C502; the capacitor C502 is connected in parallel across the resistor R501; the other end of the resistor R501 is connected with one end of the resistor R502; the other end of the resistor R502 and the other end of the capacitor C502 are grounded.

[0031] As a further scheme of the application, the voltage follower comprises a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit.

[0032] The second bias circuit in the voltage follower comprises a current source I601, an NMOS tube NM605, an NMOS tube NM606, an NMOS tube NM607, an NMOS tube NM614, a PMOS tube PM606, a PMOS tube PM607 and a PMOS tube PM608.

[0033] The input end of the current source I601 is connected with the power supply VIN; the output end of the current source I601 is connected with the drain of the NMOS tube NM605, the gate of the NMOS tube NM605 and the gate of the NMOS tube NM606; the drain of the NMOS tube NM606 is connected with the drain of the PMOS tube PM606, the gate of the PMOS tube PM606, the gate of the PMOS tube PM607 and the gate of the PMOS tube PM608;

[0034] The drain of the PMOS tube PM607 is connected with the drain of the NMOS tube NM614 and the gate of the NMOS tube NM614; the drain of the PMOS tube PM608 is connected with the drain of the NMOS tube NM607 and the gate of the NMOS tube NM607;

[0035] The source of the PMOS tube PM606, the source of the PMOS tube PM607 and the source of the PMOS tube PM608 are connected with the power supply VIN;

[0036] The source of the NMOS tube NM605, the source of the NMOS tube NM606, the source of the NMOS tube NM614 and the source of the NMOS tube NM607 are grounded.

[0037] As a further scheme of the application, the second error amplifier EA2 in the voltage follower comprises a first-stage amplification circuit, a second-stage amplification circuit and a current detection circuit;

[0038] The first-stage amplification circuit comprises the NMOS tubes NM601, NM602, NM603, NM604, NM608, NM609, NM610, NM615, NM616, the PMOS tubes PM601, PM602, PM603 and PM604;

[0039] The gate of the NMOS tube NM601 is connected with the positive pole of the capacitor CF1 in the filter circuit, and the gate of the NMOS tube NM602 is connected with the drain of the PMOS tube PM622; the gate of the NMOS tube NM601 is the positive input pole of the second error amplifier EA2, and the gate of the NMOS tube NM602 is the negative input pole of the second error amplifier EA2;

[0040] The source of the NMOS tube NM601 is connected with the source of the NMOS tube NM602 and the drain of the NMOS tube NM608; the gate of the NMOS tube NM608 is connected with the gate of the NMOS tube NM609, the gate of the NMOS tube NM610 and the gate of the NMOS tube NM607 in the second bias circuit;

[0041] The drain of the NMOS tube NM601 is connected with the source of the NMOS tube NM603, the drain of the NMOS tube NM602 is connected with the source of the NMOS tube NM604, and the gate of the NMOS tube NM603 is connected with the gate of the NMOS tube NM604;

[0042] The drain of the NMOS tube NM603 is connected with the drain of the PMOS tube PM601 and the source of the PMOS tube PM603, and the drain of the NMOS tube NM604 is connected with the drain of the PMOS tube PM602 and the source of the PMOS tube PM604, and the source of the PMOS tube PM601 and the source of the PMOS tube PM602 are connected with the power supply VIN;

[0043] The gate of the PMOS tube PM601 is connected with the gate of the PMOS tube PM602, the gate of the PMOS tube PM603, the drain of the PMOS tube PM603 and the drain of the NMOS tube NM615, and the gate of the PMOS tube PM604 is connected with the drain of the PMOS tube PM604 and the drain of the NMOS tube NM616;

[0044] The gate of the NMOS tube NM615 is connected with the gate of the NMOS tube NM616 and the gate of the NMOS tube NM614 in the second bias circuit, the source of the NMOS tube NM615 is connected with the drain of the NMOS tube NM609, and the source of the NMOS tube NM616 is connected with the drain of the NMOS tube NM610;

[0045] The source of the NMOS tube NM608, the source of the NMOS tube NM609 and the source of the NMOS tube NM610 are grounded;

[0046] The second-stage amplification circuit comprises the NMOS tube NM611, the NMOS tube NM617, the NMOS tube NM625, the NMOS tube NM626, the PMOS tube PM605 and the PMOS tube PM609;

[0047] The source of the PMOS tube PM609 and the source of the PMOS tube PM605 are connected with the power supply VIN, the gate of the PMOS tube PM609 is connected with the gate of the PMOS tube PM608 in the second bias circuit, the gate of the PMOS tube PM605 is connected with the gate of the PMOS tube PM604 in the first-stage amplification circuit, the drain of the PMOS tube PM609 is connected with the drain of the PMOS tube PM605, the drain of the NMOS tube NM617 and the drain of the NMOS tube NM625, and the drain of the PMOS tube PM609 is the output terminal of the second error amplifier EA2;

[0048] The gate of the NMOS tube NM617 is connected with the gate of the NMOS tube NM625 and the gate of the NMOS tube NM616 in the first-stage amplification circuit; the source of the NMOS tube NM617 is connected with the drain of the NMOS tube NM611, the source of the NMOS tube NM625 is connected with the drain of the NMOS tube NM626, and the gate of the NMOS tube NM611 is connected with the gate of the NMOS tube NM610 in the first-stage amplification circuit;

[0049] The source of the NMOS tube NM611 and the source of the NMOS tube NM626 are grounded.

[0050] The current detection circuit comprises a PMOS tube PM621, a PMOS tube PM622, a PMOS tube PM625, a PMOS tube PM626, an NMOS tube NM618 and an NMOS tube NM619.

[0051] The source of the PMOS tube PM621 and the source of the PMOS tube PM622 are connected with the power supply VIN.

[0052] The gate of the PMOS tube PM622 is connected with the gate of the PMOS tube PM621 and the drain of the PMOS tube PM609 in the second-stage amplification circuit; the drain of the PMOS tube PM622 is connected with the source of the PMOS tube PM626 and the gate of the NMOS tube NM602 in the first-stage amplification circuit.

[0053] The drain of the PMOS tube PM621 is connected with the source of the PMOS tube PM625; the gate of the PMOS tube PM625 is connected with the gate of the PMOS tube PM626, the drain of the PMOS tube PM626 and the drain of the NMOS tube NM619; and the drain of the PMOS tube PM625 is connected with the drain of the NMOS tube NM618, the gate of the NMOS tube NM618 and the gate of the NMOS tube NM619.

[0054] The source of the NMOS tube NM618 and the source of the NMOS tube NM619 are grounded.

[0055] As a further scheme of the application, the load adaptive current bias circuit in the voltage follower comprises an NMOS tube NM612, an NMOS tube NM620, an NMOS tube NM621, an NMOS tube NM622, an NMOS tube NM623, a PMOS tube PM610, a PMOS tube PM611, a PMOS tube PM612, a PMOS tube PM613, a resistor R601 and a capacitor C601.

[0056] The source of the PMOS tube PM610, the source of the PMOS tube PM611, the source of the PMOS tube PM612 and the source of the PMOS tube PM613 are connected with the power supply VIN.

[0057] The gate of the PMOS tube PM610 is connected with the drain of the PMOS tube PM610, the gate of the PMOS tube PM611 and the drain of the NMOS tube NM620; the drain of the PMOS tube PM611 is connected with the gate of the NMOS tube NM612 and the gate of the NMOS tube NM611 in the second-stage amplification circuit;

[0058] The gate of the PMOS tube PM612 is connected with the drain of the PMOS tube PM612, the gate of the PMOS tube PM613 and the drain of the NMOS tube NM612; the source of the NMOS tube NM612 is connected with the drain of the NMOS tube NM621; the gate of the NMOS tube NM620 is connected with the gate of the NMOS tube NM621 and the gate of the NMOS tube NM619 in the current detection circuit;

[0059] The drain of the PMOS tube PM613 is connected with the gate of the NMOS tube NM622, the drain of the NMOS tube NM622 and one end of the resistor R601; the other end of the resistor R601 is connected with the other end of the capacitor C601, the gate of the NMOS tube NM623 and the gate of the NMOS tube NM626 in the second-stage amplification circuit; the other end of the capacitor C601 is grounded; the drain of the NMOS tube NM623 is connected with the source of the NMOS tube NM601 in the first-stage amplification circuit;

[0060] The source of the NMOS tube NM620, the source of the NMOS tube NM621, the source of the NMOS tube NM622 and the source of the NMOS tube NM623 are grounded.

[0061] As a further scheme of the application, the compensation circuit in the voltage follower comprises the NMOS tube NM613, the NMOS tube NM624, the PMOS tube PM614, the PMOS tube PM615, the PMOS tube PM616, the PMOS tube PM617, the PMOS tube PM623, the PMOS tube PM624, the resistor R602, the resistor R603, the resistor R604 and the capacitor C602.

[0062] The source of the PMOS tube PM614 and the source of the PMOS tube PM616 are connected with the power supply VIN;

[0063] The gate of the PMOS tube PM614 is connected with the drain of the PMOS tube PM614, the gate of the PMOS tube PM615 and the drain of the NMOS tube NM624; the gate of the NMOS tube NM624 is connected with the gate of the NMOS tube NM623 in the load adaptive current bias circuit;

[0064] The source of the PMOS PM615 is connected with one end of the resistor R602, one end of the resistor R603 and the source of the PMOS PM623; the other end of the resistor R602 is connected with the drain of the PMOS PM602 in the first stage amplification circuit; the other end of the resistor R603 is connected with the source of the PMOS PM624 and one end of the resistor R604, and the other end of the resistor R604 is connected with the drain of the PMOS PM617;

[0065] The drain of the PMOS PM615 is connected with one end of the capacitor C602, the drain of the PMOS PM623, the drain of the PMOS PM624 and the source of the PMOS PM617; the other end of the capacitor C602 is connected with the gate of the PMOS PM623 and the gate of the PMOS PM624;

[0066] The gate of the PMOS PM617 is connected with the gate of the PMOS PM616, the drain of the PMOS PM616 and the drain of the NMOS NM613; the gate of the NMOS NM613 is connected with the gate of the NMOS NM612 in the load adaptive current bias circuit;

[0067] The source of the NMOS NM624 and the source of the NMOS NM613 are grounded.

[0068] Compared with the prior art, the present application has the beneficial effects that:

[0069] The present application solves the technical problem that the conventional architecture must use a large off-chip capacitor to realize a low-pass filter circuit with a low cut-off frequency in the conventional high-PSRR LDO architecture, and realizes a high-PSRR LDO architecture with low power consumption without increasing too much area by using on-chip devices, the reference voltage VREF is amplified to a normal output voltage by the first internal LDO, the noise and PSRR of the voltage reference source and the first internal LDO are all filtered out by the third low-pass filter, and a stable and clean output reference voltage is provided for the second voltage follower, so that the performance requirements of the voltage reference source and the first internal LDO can be reduced, and the system overhead is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0070] Figure 1 It is a circuit architecture schematic diagram of a high-power-suppression-ratio low-noise LDO implementation circuit.

[0071] Figure 2 It is a circuit structure schematic diagram of a non-overlapping clock generation circuit in a high-power-suppression-ratio low-noise LDO implementation circuit.

[0072] Figure 3It is a high power supply rejection ratio low noise LDO implementation circuit internal LDO circuit structure schematic diagram.

[0073] Figure 4 It is a high power supply rejection ratio low noise LDO implementation circuit voltage follower circuit structure schematic diagram.

[0074] Figure 5 It is a high power supply rejection ratio low noise LDO implementation circuit low pass filter implementation high PSRR principle schematic diagram.

[0075] In the figure: 1, internal LDO circuit; 2, voltage follower; 3, filter circuit. DETAILED DESCRIPTION

[0076] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0077] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "provided with", "connected", "connected" should be understood broadly; for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected, or it can be mechanically connected, or it can be electrically connected, or it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0078] Please refer to Figures 1-5 A high power supply rejection ratio low noise LDO implementation circuit, comprising a voltage reference source, an internal LDO circuit 1, a voltage follower 2, a filter circuit 3 and a non-overlapping clock generation circuit;

[0079] The internal LDO circuit 1 comprises a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit and a power-on OK detection circuit; an input VREF of a voltage reference source is connected with a positive input terminal of the first error amplifier EA1, an output terminal of the first error amplifier EA1 is connected with a gate of a PMOS transistor PM511 in the output stage circuit, a source of the PMOS transistor PM511 in the output stage circuit is connected with a power supply VIN, a drain of the PMOS transistor PM511 in the output stage circuit is connected with one end of a resistor divider R501, the other end of the resistor divider R501 is connected with a negative input terminal of the first error amplifier EA1 and one end of a resistor R502 at the same time, the other end of the resistor R502 is grounded; the drain of the PMOS transistor PM511 is connected with one input terminal of the power-on OK detection circuit, the other input terminal of the power-on OK detection circuit is connected with the power supply VIN;

[0080] The phase compensation network circuit is connected with the gate of the PMOS transistor PM511 in the output stage circuit;

[0081] The first bias circuit is electrically connected with the first error amplifier EA1 and the power-on OK detection circuit;

[0082] The filter circuit 3 comprises a PMOS transistor PM301, a PMOS transistor PM302, a PMOS transistor PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1, the source of the PMOS transistor PM303 and the source of the PMOS transistor PM301 are both connected with the drain of the PMOS transistor PM511, the gate of the PMOS transistor PM303 is connected with the output terminal of the power-on OK detection circuit, the gate of the PMOS transistor PM301 is connected with an output signal PH1b of the non-overlapping clock generation circuit, the drain of the PMOS transistor PM303 is connected with the drain of the PMOS transistor PM302 and the positive pole of the capacitor Cbig, the negative pole of the capacitor Cbig is grounded; the drain of the PMOS transistor PM301 is connected with the source of the PMOS transistor PM302 and the positive pole of the capacitor Csmall, the negative pole of the capacitor Csmall is grounded; the gate of the PMOS transistor PM302 is connected with an output signal PH2b of the non-overlapping clock generation circuit, the positive pole of the capacitor Cbig is connected with one end of the resistor RF1, the other end of the resistor RF1 is connected with the positive pole of the capacitor CF1, the negative pole of the capacitor CF1 is grounded;

[0083] The voltage follower 2 comprises a second error amplifier EA2 and a PMOS transistor PM622, the positive input terminal of the second error amplifier EA2 is connected with the positive pole of the capacitor CF1, the negative input terminal of the second error amplifier EA2 is connected with a power supply VOUT, the output terminal of the second error amplifier EA2 is connected with the gate of the PMOS transistor PM622, the source of the PMOS transistor PM622 is connected with the power supply VIN, the drain of the PMOS transistor PM622 is connected with the power supply VOUT.

[0084] As shown in Figure 2 , the non-overlapping clock generation circuit includes NAND gate NAND1, NAND gate NAND2, NOT gate INV0, NOT gate INV1, NOT gate INV2, NOT gate INV3, NOT gate INV4, NOT gate INV5, NOT gate INV6, NOT gate INV7, NOT gate INV8, NOT gate INV9, NOT gate INV10, NOT gate INV11, NOT gate INV12, resistor R11, resistor R12, capacitor C1 and capacitor C2;

[0085] The CLK signal is connected to one input end of the NAND gate NAND1 and the input end of the NOT gate INV0, and is connected to the other input end of the NAND gate NAND1 and the output end of the NAND gate INV10;

[0086] The output end of the NOT gate INV0 is connected to one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 is connected to the output end of the NAND gate INV4;

[0087] The output end of the NAND gate NAND1 is connected to the input end of the NOT gate INV1, the output end of the NOT gate INV1 is connected to the input end of the NOT gate INV2, the output end of the NOT gate INV2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the positive electrode of the capacitor C1 and the input end of the NOT gate INV3 at the same time, the output end of the NOT gate INV3 is connected to the input end of the NOT gate INV4, the output end of the NOT gate INV4 is connected to the input end of the NOT gate INV5, the output end of the NOT gate INV5 is connected to the input end of the NOT gate INV6, the output end of the NOT gate INV6 outputs the signal PH1b; the negative electrode of the capacitor C1 is grounded;

[0088] The output end of the NAND gate NAND2 is connected to the input end of the NOT gate INV7, the output end of the NOT gate INV7 is connected to the input end of the NOT gate INV8, the output end of the NOT gate INV8 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the positive electrode of the capacitor C2 and the input end of the NOT gate INV9 at the same time, the output end of the NOT gate INV9 is connected to the input end of the NOT gate INV10, the output end of the NOT gate INV10 is connected to the input end of the NOT gate INV11, the output end of the NOT gate INV11 is connected to the input end of the NOT gate INV12, the output end of the NOT gate INV12 outputs the signal PH2b; the negative electrode of the capacitor C2 is grounded;

[0089] Figure 1 The voltage reference source and the first internal LDO in the Figure 5 have relatively low PSRR bandwidth due to low power consumption, and the principle of enhancing PSRR through low-pass RC is as shown in Figure 5 The PSRR wave pattern of VOUT_PRIM is shown in Figure 5(b) shows the VOUT CLEAN wave pattern after a first-order low-pass filter (solid line), from which it can be seen that the PSRR enhancement frequency range is from the low-pass filter cutoff frequency (fc) to the first internal LDO PSRR bandwidth (f-3dB), if f-3dB is 100 times fc, VOUT CLEAN can be improved by 40dB, assuming that the first internal LDO dc PSRR is 50dB, f-3dB is 100Hz, fc=1Hz, VOUT CLEAN can achieve 90dB PSRR in the medium and high frequency (greater than 1kHz) range; Figure 5 (c) shows the principle of using a second-order low-pass filter circuit to enhance the PSRR of VOUT CLEAN in a higher frequency range (greater than 100kHz).

[0090] In order to achieve better PSRR enhancement effect, the cutoff frequency of the third low-pass filter needs to be very low (generally below 1Hz), and the filter uses an on-chip capacitor CF, and the on-chip capacitor is generally used in the range of 10pF-100pF. In order to achieve a low cutoff frequency, a relatively large filter resistor RF needs to be implemented, for example, to achieve a 1s time constant, the resistance needs to be 10GΩ-100GΩ, which is impossible to achieve with an on-chip resistor. Based on this problem, the present application innovatively uses a switched capacitor to achieve a large resistance, thereby implementing such a low-pass filter. The third low-pass filter implemented using a switched capacitor uses PMOS tubes PM1 and PM2, the gates of the two PMOS tubes are connected to non-overlapping edge clocks, PH1b and PH2b respectively. PM1 and PM2 act as switches and are divided into two parts in each cycle, the first half cycle charges Csmall, and the second half cycle transfers the charge of Csmall to Cbig. Using the principle of charge transfer to equivalent a larger resistance, the equivalent resistance value and the cutoff frequency of the low-pass filter are determined by the following formula:

[0091]

[0092]

[0093] In order to achieve a lower cutoff frequency, it is necessary to increase the ratio of Cbig and Csmall, and at the same time reduce the clock frequency. Assuming that Cbig=100pF, Csmall=0.1pF, to achieve a 1s equivalent time constant, a clock frequency of 1kHz is required, which realizes an equivalent resistance of up to 10GΩ. Figure 1 The switched capacitor low-pass filter circuit in the present application combines RF1 and CF1 to form a second-order low-pass filter, which achieves the PSRR enhancement effect of VOUT PRIM in a higher frequency range.

[0094] The switch capacitor low pass filter scheme mentioned in the application, when the system is powered on, due to the low frequency of the clock, the ratio of Cbig and Csmall is large, if only relying on the switch capacitor to carry the charge to realize the power-on climbing of VOUT_CLEAN, the climbing time will be very long (related to the cutoff frequency of the filter), which is unacceptable in application, therefore, by short-circuiting VOUT_PRIM and VOUT_CLEAN through a switch during power-on, the power-on speed can be realized faster; for the low dropout LDO, if the system power is lower than the output voltage of the LDO, the LDO will enter the dropout mode, at this time, VOUT_PRIM and VOUT_CLEAN are equal to the input voltage, if the input is quickly restored, VOUT_PRIM can quickly respond, due to the low pass filter, VOUT_CLEAN still cannot quickly recover, therefore, a first internal LDO dropout mode detection circuit is used, so that when the system exits the dropout mode, there is a short enough time to charge VOUT_CLEAN to the voltage of VOUT_PRIM by using the PMOS PM3 as a switch.

[0095] As shown in Figure 3 the first error amplifier EA1 includes NMOS NM501, NMOS NM502, NMOS NM506, NMOS NM507, NMOS NM508, NMOS NM509, NMOS NM513, NMOS NM514, PMOS PM503, PMOS PM504, PMOS PM501 and PMOS PM502;

[0096] The source of PMOS PM503 and the source of PMOS PM504 are connected with the power supply VIN; the gate of PMOS PM503 is connected with the drain of PMOS PM503, the gate of PMOS PM504 and the drain of NMOS NM513; the drain of PMOS PM504 is connected with the drain of NMOS NM514;

[0097] The gate of NMOS NM513 is connected with the gate of NMOS NM514, the source of NMOS NM513 is connected with the drain of NMOS NM501 and the drain of NMOS NM506; the source of NMOS NM514 is connected with the drain of NMOS NM502 and the drain of NMOS NM509;

[0098] The gate of the NMOS tube NM501 is connected with the gate of the PMOS tube PM502; the gate of the NMOS tube NM502 is connected with the gate of the PMOS tube PM501 and the output VREF of the voltage reference source; the gate of the NMOS tube NM501 is the input negative pole of the first error amplifier EA1; the gate of the NMOS tube NM502 is the input positive pole of the first error amplifier EA1; the drain of the NMOS tube NM514 is the output terminal of the first error amplifier EA1;

[0099] The drain of the PMOS tube PM501 is connected with the gate of the NMOS tube NM506, the gate of the NMOS tube NM507 and the drain of the NMOS tube NM507; the source of the NMOS tube NM506 and the source of the NMOS tube NM507 are grounded; the drain of the PMOS tube PM502 is connected with the gate of the NMOS tube NM508, the gate of the NMOS tube NM509 and the drain of the NMOS tube NM508; the source of the NMOS tube NM508 and the source of the NMOS tube NM509 are grounded;

[0100] The power-on OK detection circuit comprises the PMOS tube PM507, the PMOS tube PM508, the NMOS tube NM510 and the NMOS tube NM511; the source of the PMOS tube PM507 and the source of the PMOS tube PM508 are connected with the power supply VIN; the drain of the PMOS tube PM507 is connected with the gate of the PMOS tube PM508, the drain of the NMOS tube NM510 and the gate of the NMOS tube NM511; the drain of the NMOS tube NM511 is connected with the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit 3;

[0101] The gate of the NMOS tube NM510 is connected with the drain of the NMOS tube NM514 and the gate of the PMOS tube PM511 in the output stage circuit; the source of the NMOS tube NM510 and the source of the NMOS tube NM511 are grounded;

[0102] The first bias circuit comprises the NMOS tube NM503, the NMOS tube NM504, the NMOS tube NM505, the NMOS tube NM512, the PMOS tube PM505, the PMOS tube PM506, the current source I501 and the current source I502;

[0103] The input end of current source I501 and the input end of current source I502 are both connected to power supply VIN; the output end of current source I501 is simultaneously connected to the gate of NMOS transistor NM512, the drain of NMOS transistor NM512, and the gate of NMOS transistor NM513; the source of NMOS transistor NM512 is grounded; the output end of current source I502 is simultaneously connected to the gate of NMOS transistor NM503, the drain of NMOS transistor NM503, the gate of NMOS transistor NM504, and the gate of NMOS transistor NM505;

[0104] The drain of NMOS transistor NM504 is connected to the source of NMOS transistor NM501; the drain of NMOS transistor NM505 ​​is connected to the drain of PMOS transistor PM505, the gate of PMOS transistor PM505, the gate of PMOS transistor PM506, and the gate of PMOS transistor PM507; the source of PMOS transistor PM505 and the source of PMOS transistor PM506 are both connected to the power supply VIN; the source of MOS transistor NM503, the source of NMOS transistor NM504, and the source of NMOS transistor NM505 ​​are grounded;

[0105] The phase compensation network circuit includes a resistor R503 and a capacitor C503. One end of the capacitor C503 is connected to the power supply VIN; the other end of the capacitor C503 is connected to one end of the resistor R503, and the other end of the resistor R503 is connected to the gate of the PMOS transistor PM511.

[0106] The output stage circuit includes a PMOS transistor PM511, a resistor R501, a resistor R502, a capacitor C501, and a capacitor C502; the drain of the PMOS transistor PM511 is connected to one end of the resistor R501 and one end of the capacitor C502, the capacitor C502 is connected in parallel to both ends of the resistor R501, the other end of the resistor R501 is connected to one end of the resistor R502, and the other end of the resistor R502 and the other end of the capacitor C502 are both grounded.

[0107] The high PSRR first internal LDO circuit structure proposed in the present invention is as follows Figure 3 As shown, taking into account the normal operation during the reference voltage creepage process, the first internal LDO input stage adopts a dual input stage design, namely NM501, NM502, PM501, PM502, which can widen the common mode range of the input stage; the compensation network adopts type-2 and feedforward compensation, respectively R503, C503, R501, C501, R502; the power-on OK detection part can detect whether this buffer enters the voltage difference mode. When VIN is lower than the VOUT_PRIM design value, VFB will be lower than VREF, thereby making the input stage current unbalanced, which will cause vo1 to drop to 0 and turn off NM10, FAST becomes high, and thus FASTb becomes low, and vice versa.

[0108] As shown in Figure 4 the voltage follower 2 comprises a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit;

[0109] The second bias circuit comprises a current source I601, an NMOS tube NM605, an NMOS tube NM606, an NMOS tube NM607, an NMOS tube NM614, a PMOS tube PM606, a PMOS tube PM607 and a PMOS tube PM608;

[0110] The input end of the current source I601 is connected with the power supply VIN; the output end of the current source I601 is connected with the drain of the NMOS tube NM605, the gate of the NMOS tube NM605 and the gate of the NMOS tube NM606 at the same time, the drain of the NMOS tube NM606 is connected with the drain of the PMOS tube PM606, the gate of the PMOS tube PM606, the gate of the PMOS tube PM607 and the gate of the PMOS tube PM608 at the same time;

[0111] The drain of the PMOS tube PM607 is connected with the drain of the NMOS tube NM614 and the gate of the NMOS tube NM614 at the same time; the drain of the PMOS tube PM608 is connected with the drain of the NMOS tube NM607 and the gate of the NMOS tube NM607 at the same time;

[0112] The source of the PMOS tube PM606, the source of the PMOS tube PM607 and the source of the PMOS tube PM608 are connected with the power supply VIN;

[0113] The source of the NMOS tube NM605, the source of the NMOS tube NM606, the source of the NMOS tube NM614 and the source of the NMOS tube NM607 are grounded;

[0114] The second error amplifier EA2 comprises a first stage amplification circuit, a second stage amplification circuit and a current detection circuit;

[0115] The first stage amplification circuit comprises an NMOS tube NM601, an NMOS tube NM602, an NMOS tube NM603, an NMOS tube NM604, an NMOS tube NM608, an NMOS tube NM609, an NMOS tube NM610, an NMOS tube NM615, an NMOS tube NM616, a PMOS tube PM601, a PMOS tube PM602, a PMOS tube PM603 and a PMOS tube PM604;

[0116] The gate of the NMOS tube NM601 is connected with the positive pole of the capacitor CF1 in the filter circuit 3, and the gate of the NMOS tube NM602 is connected with the drain of the PMOS tube PM622; the gate of the NMOS tube NM601 is the positive input pole of the second error amplifier EA2, and the gate of the NMOS tube NM602 is the negative input pole of the second error amplifier EA2;

[0117] The source of the NMOS tube NM601 is connected with the source of the NMOS tube NM602 and the drain of the NMOS tube NM608, the gate of the NMOS tube NM608 is connected with the gate of the NMOS tube NM609, the gate of the NMOS tube NM610 and the gate of the NMOS tube NM607 in the second bias circuit;

[0118] The drain of the NMOS tube NM601 is connected with the source of the NMOS tube NM603, the drain of the NMOS tube NM602 is connected with the source of the NMOS tube NM604, and the gate of the NMOS tube NM603 is connected with the gate of the NMOS tube NM604;

[0119] The drain of the NMOS tube NM603 is connected with the drain of the PMOS tube PM601 and the source of the PMOS tube PM603, the drain of the NMOS tube NM604 is connected with the drain of the PMOS tube PM602 and the source of the PMOS tube PM604, and the source of the PMOS tube PM601 and the source of the PMOS tube PM602 are connected with the power supply VIN;

[0120] The gate of the PMOS tube PM601 is connected with the gate of the PMOS tube PM602, the gate of the PMOS tube PM603, the drain of the PMOS tube PM603 and the drain of the NMOS tube NM615; the gate of the PMOS tube PM604 is connected with the drain of the PMOS tube PM604 and the drain of the NMOS tube NM616;

[0121] The gate of the NMOS tube NM615 is connected with the gate of the NMOS tube NM616 and the gate of the NMOS tube NM614 in the second bias circuit; the source of the NMOS tube NM615 is connected with the drain of the NMOS tube NM609, and the source of the NMOS tube NM616 is connected with the drain of the NMOS tube NM610;

[0122] The source of the NMOS tube NM608, the source of the NMOS tube NM609 and the source of the NMOS tube NM610 are grounded;

[0123] The second-stage amplification circuit comprises the NMOS tube NM611, the NMOS tube NM617, the NMOS tube NM625, the NMOS tube NM626, the PMOS tube PM605 and the PMOS tube PM609;

[0124] The source of the PMOS PM609 and the source of the PMOS PM605 are connected with the power supply VIN; the gate of the PMOS PM609 is connected with the gate of the PMOS PM608 in the second bias circuit; the gate of the PMOS PM605 is connected with the gate of the PMOS PM604 in the first stage amplification circuit; the drain of the PMOS PM609 is connected with the drain of the PMOS PM605, the drain of the NMOS NM617 and the drain of the NMOS NM625; the drain of the PMOS PM609 is the output terminal of the second error amplifier EA2;

[0125] The gate of the NMOS NM617 is connected with the gate of the NMOS NM625 and the gate of the NMOS NM616 in the first stage amplification circuit; the source of the NMOS NM617 is connected with the drain of the NMOS NM611, and the source of the NMOS NM625 is connected with the drain of the NMOS NM626; the gate of the NMOS NM611 is connected with the gate of the NMOS NM610 in the first stage amplification circuit;

[0126] The source of the NMOS NM611 and the source of the NMOS NM626 are grounded;

[0127] The current detection circuit comprises the PMOS PM621, the PMOS PM622, the PMOS PM625, the PMOS PM626, the NMOS NM618 and the NMOS NM619;

[0128] The source of the PMOS PM621 and the source of the PMOS PM622 are connected with the power supply VIN;

[0129] The gate of the PMOS PM622 is connected with the gate of the PMOS PM621 and the drain of the PMOS PM609 in the second stage amplification circuit; the drain of the PMOS PM622 is connected with the source of the PMOS PM626 and the gate of the NMOS NM602 in the first stage amplification circuit;

[0130] The drain of the PMOS PM621 is connected with the source of the PMOS PM625; the gate of the PMOS PM625 is connected with the gate of the PMOS PM626, the drain of the PMOS PM626 and the drain of the NMOS NM619; the drain of the PMOS PM625 is connected with the drain of the NMOS NM618, the gate of the NMOS NM618 and the gate of the NMOS NM619;

[0131] The source of the NMOS NM618 and the source of the NMOS NM619 are grounded;

[0132] The load adaptive current bias circuit comprises NMOS NM612, NMOS NM620, NMOS NM621, NMOS NM622, NMOS NM623, PMOS PM610, PMOS PM611, PMOS PM612, PMOS PM613, resistor R601 and capacitor C601;

[0133] The source of PMOS PM610, the source of PMOS PM611, the source of PMOS PM612 and the source of PMOS PM613 are connected with power supply VIN;

[0134] The gate of PMOS PM610 is connected with the drain of PMOS PM610, the gate of PMOS PM611 and the drain of NMOS NM620; the drain of PMOS PM611 is connected with the gate of NMOS NM612 and the gate of NMOS NM611 in the second-stage amplification circuit;

[0135] The gate of PMOS PM612 is connected with the drain of PMOS PM612, the gate of PMOS PM613 and the drain of NMOS NM612; the source of NMOS NM612 is connected with the drain of NMOS NM621; the gate of NMOS NM620 is connected with the gate of NMOS NM621 and the gate of NMOS NM619 in the current detection circuit;

[0136] The drain of PMOS PM613 is connected with the gate of NMOS NM622, the drain of NMOS NM622 and one end of resistor R601; the other end of resistor R601 is connected with the other end of capacitor C601, the gate of NMOS NM623 and the gate of NMOS NM626 in the second-stage amplification circuit; the other end of capacitor C601 is grounded; the drain of NMOS NM623 is connected with the source of NMOS NM601 in the first-stage amplification circuit;

[0137] The source of NMOS NM620, the source of NMOS NM621, the source of NMOS NM622 and the source of NMOS NM623 are grounded;

[0138] The compensation circuit comprises NMOS NM613, NMOS NM624, PMOS PM614, PMOS PM615, PMOS PM616, PMOS PM617, PMOS PM623, PMOS PM624, resistor R602, resistor R603, resistor R604 and capacitor C602;

[0139] The source of the PMOS transistor PM614 and the source of the PMOS transistor PM616 are connected with the power supply VIN;

[0140] The gate of the PMOS transistor PM614 is connected with the drain of the PMOS transistor PM614, the gate of the PMOS transistor PM615 and the drain of the NMOS transistor NM624, and the gate of the NMOS transistor NM624 is connected with the gate of the NMOS transistor NM623 in the load adaptive current bias circuit;

[0141] The source of the PMOS transistor PM615 is connected with one end of the resistor R602, one end of the resistor R603 and the source of the PMOS transistor PM623; the other end of the resistor R602 is connected with the drain of the PMOS transistor PM602 in the first-stage amplification circuit; the other end of the resistor R603 is connected with the source of the PMOS transistor PM624 and one end of the resistor R604, and the other end of the resistor R604 is connected with the drain of the PMOS transistor PM617;

[0142] The drain of the PMOS transistor PM615 is connected with one end of the capacitor C602, the drain of the PMOS transistor PM623, the drain of the PMOS transistor PM624 and the source of the PMOS transistor PM617; the other end of the capacitor C602 is connected with the gate of the PMOS transistor PM623 and the gate of the PMOS transistor PM624;

[0143] The gate of the PMOS transistor PM617 is connected with the gate of the PMOS transistor PM616, the drain of the PMOS transistor PM616 and the drain of the NMOS transistor NM613, and the gate of the NMOS transistor NM613 is connected with the gate of the NMOS transistor NM612 in the load adaptive current bias circuit;

[0144] The source of the NMOS transistor NM624 and the source of the NMOS transistor NM613 are grounded;

[0145] The high PSRR voltage follower circuit structure provided in the application adopts a three-stage structure to improve the PSRR, and the common-mode voltage of the input stage can work normally at the power supply, so that the first amplification stage adopts an NMOS differential pair input stage quasi-folded cascode structure; the second amplification stage adopts a common-source amplification circuit structure; and the third stage is an output amplification stage. The static current of the voltage follower is adaptively increased with the increase of the load current, and the purpose is to gradually improve the system bandwidth with the increase of the load, thereby widening the PSRR bandwidth, and realizing the consideration of low static power consumption and high PSRR. The specific design idea is that the input differential pair tail current is gradually increased and quickly reaches an upper limit value with the increase of the load, and the second-stage static bias current changes linearly with the load. The phase compensation network adopts a cross-connection mode between the output end with a certain driving capability of the first stage and the output of the second stage, and the Miller compensation with a dynamic zero resistance makes the system stable, and the zero point position of the compensation scheme is adaptively adjusted with the change of the load to match the requirements of the loop characteristics under different loads, so as to realize the system loop stability under full load.

[0146] The application solves the technical problem that a large off-chip capacitor must be used to realize a low-pass filter circuit with a low cutoff frequency in the conventional high-PSRR LDO architecture, and realizes the high-PSRR LDO architecture with low power consumption without increasing too much area by using on-chip devices, wherein a reference voltage VREF is generated by a voltage reference source, the reference voltage VREF is amplified to a normal output voltage (VOUT_PRIM) by a first internal LDO (Internal LDO), the noise and PSRR of the voltage reference source and the first internal LDO are filtered out by a third low-pass filter, and a stable and clean output reference voltage (VOUT_CLEAN) is provided for a second voltage follower, so that the performance requirements of the voltage reference source and the first internal LDO can be reduced, and the system overhead is greatly reduced.

[0147] For those skilled in the art, it is obvious that the application is not limited to the details of the above exemplary embodiments, and the application can be implemented in other specific forms without departing from the spirit or essential characteristics of the application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0148] Furthermore, it should be understood that, although the description is made according to the embodiments, not every embodiment contains only one independent technical solution; the description is made in this way only for the sake of clarity; a person skilled in the art should understand the description as a whole; the technical solutions in each embodiment can also be combined appropriately; to form other embodiments that can be understood by a person skilled in the art.

Claims

1. A high power supply rejection ratio low noise LDO implementation circuit, characterized in that: It includes a voltage reference source, an internal LDO circuit (1), a voltage follower (2), a filter circuit (3) and a non-overlapping clock generation circuit; The internal LDO circuit (1) includes a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit and a power-on OK detection circuit; the input VREF of the voltage reference source is connected to the positive input terminal of the first error amplifier EA1, the output terminal of the first error amplifier EA1 is connected to the gate of the PMOS transistor PM511 in the output stage circuit, the source of the PMOS transistor PM511 in the output stage circuit is connected to the power supply VIN, the drain of the PMOS transistor PM511 in the output stage circuit is connected to one end of the resistor divider R501, the other end of the resistor divider R501 is simultaneously connected to the negative input terminal of the first error amplifier EA1 and one end of the resistor R502, and the other end of the resistor R502 is grounded; the drain of the PMOS transistor PM511 is connected to one input terminal of the power-on OK detection circuit, and the other input terminal of the power-on OK detection circuit is connected to the power supply VIN; The phase compensation network circuit is connected to the gate of the PMOS tube PM511 in the output stage circuit; The first bias circuit is electrically connected to the first error amplifier EA1 and the power-on OK detection circuit; The filter circuit (3) includes a PMOS transistor PM301, a PMOS transistor PM302, a PMOS transistor PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1. The source of the PMOS transistor PM303 and the source of the PMOS transistor PM301 are both connected to the drain of the PMOS transistor PM511. The gate of the PMOS transistor PM303 is connected to the output end of the power-on OK detection circuit. The gate of the PMOS transistor PM301 is connected to the output signal PH1b of the non-overlapping clock generation circuit. The drain of PMOS transistor PM301 is connected to the drain of PMOS transistor PM302 and the positive electrode of capacitor Cbig, and the negative electrode of capacitor Cbig is grounded. The drain of PMOS transistor PM301 is connected to the source of PMOS transistor PM302 and the positive electrode of capacitor Csmall, and the negative electrode of capacitor Csmall is grounded. The gate of PMOS transistor PM302 is connected to the output signal PH2b of the non-overlapping clock generation circuit, the positive electrode of capacitor Cbig is connected to one end of resistor RF1, the other end of resistor RF1 is connected to the positive electrode of capacitor CF1, and the negative electrode of capacitor CF1 is grounded. The voltage follower (2) includes a second error amplifier EA2 and a PMOS transistor PM622, wherein the positive input terminal of the second error amplifier EA2 is connected to the positive electrode of the capacitor CF1, the negative input terminal of the second error amplifier EA2 is connected to the power supply VOUT, the output terminal of the second error amplifier EA2 is connected to the gate of the PMOS transistor PM622, the source of the PMOS transistor PM622 is connected to the power supply VIN, and the drain of the PMOS transistor PM622 is connected to the power supply VOUT.

2. A high power supply rejection ratio low noise LDO implementation circuit according to claim 1, characterized in that: The non-overlapping clock generating circuit includes a NAND gate NAND1, a NAND gate NAND2, a NOT gate INV0, a ​​NOT gate INV1, a NOT gate INV2, a NOT gate INV3, a NOT gate INV4, a NOT gate INV5, a NOT gate INV6, a NOT gate INV7, a NOT gate INV8, a NOT gate INV9, a NOT gate INV10, a NOT gate INV11, a NOT gate INV12, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2; The CLK signal is connected to one input terminal of the NAND gate NAND1 and the input terminal of the NAND gate INV0 at the same time, and the other input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate INV10; The output end of the NOT gate INV0 is connected to one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 is connected to the output end of the NAND gate INV4; The output end of the NAND gate NAND1 is connected to the input end of the NAND gate INV1, the output end of the NAND gate INV1 is connected to the input end of the NAND gate INV2, the output end of the NAND gate INV2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the positive electrode of the capacitor C1 and the input end of the NAND gate INV3, the output end of the NAND gate INV3 is connected to the input end of the NAND gate INV4, the output end of the NAND gate INV4 is connected to the input end of the NAND gate INV5, the output end of the NAND gate INV5 is connected to the input end of the NAND gate INV6, and the output end of the NAND gate INV6 outputs the signal PH1b; the negative electrode of the capacitor C1 is grounded; The output end of the NAND gate NAND2 is connected to the input end of the NAND gate INV7, the output end of the NAND gate INV7 is connected to the input end of the NAND gate INV8, the output end of the NAND gate INV8 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the positive electrode of the capacitor C2 and the input end of the NAND gate INV9, the output end of the NAND gate INV9 is connected to the input end of the NAND gate INV10, the output end of the NAND gate INV10 is connected to the input end of the NAND gate INV11, the output end of the NAND gate INV11 is connected to the input end of the NAND gate INV12, and the output end of the NAND gate INV12 outputs the signal PH2b; the negative electrode of the capacitor C2 is grounded.

3. A high power supply rejection ratio low noise LDO implementation circuit according to claim 2, characterized in that: The first error amplifier EA1 in the internal LDO circuit (1) includes an NMOS transistor NM501, an NMOS transistor NM502, an NMOS transistor NM506, an NMOS transistor NM507, an NMOS transistor NM508, an NMOS transistor NM509, an NMOS transistor NM513, an NMOS transistor NM514, a PMOS transistor PM503, a PMOS transistor PM504, a PMOS transistor PM501 and a PMOS transistor PM502; The source of the PMOS transistor PM503 and the source of the PMOS transistor PM504 are connected to the power supply VIN; the gate of the PMOS transistor PM503 is connected to the drain of the PMOS transistor PM503, the gate of the PMOS transistor PM504, and the drain of the NMOS transistor NM513; the drain of the PMOS transistor PM504 is connected to the drain of the NMOS transistor NM514; The gate of NMOS transistor NM513 is connected to the gate of NMOS transistor NM514. The source of NMOS transistor NM513 is connected to the drain of NMOS transistor NM501 and the drain of NMOS transistor NM506. The source of NMOS transistor NM514 is connected to the drain of NMOS transistor NM502 and the drain of NMOS transistor NM509. The gate of the NMOS transistor NM501 is connected to the gate of the PMOS transistor PM502; the gate of the NMOS transistor NM502 is connected to the gate of the PMOS transistor PM501 and the output VREF of the voltage reference source; the gate of the NMOS transistor NM501 is the negative input of the first error amplifier EA1; the gate of the NMOS transistor NM502 is the positive input of the first error amplifier EA1; the drain of the NMOS transistor NM514 is the output terminal of the first error amplifier EA1; The drain of the PMOS transistor PM501 is simultaneously connected to the gate of the NMOS transistor NM506, the gate of the NMOS transistor NM507, and the drain of the NMOS transistor NM507; the source of the NMOS transistor NM506 and the source of the NMOS transistor NM507 are both grounded; the drain of the PMOS transistor PM502 is simultaneously connected to the gate of the NMOS transistor NM508, the gate of the NMOS transistor NM509, and the drain of the NMOS transistor NM508; the source of the NMOS transistor NM508 and the source of the NMOS transistor NM509 are both grounded.

4. A high power supply rejection ratio low noise LDO implementation circuit according to claim 3, characterized in that: The power-on OK detection circuit in the internal LDO circuit (1) includes a PMOS tube PM507, a PMOS tube PM508, an NMOS tube NM510, and an NMOS tube NM511. The source of the PMOS tube PM507 ​​and the source of the PMOS tube PM508 are both connected to the power supply VIN. The drain of the PMOS tube PM507 ​​is simultaneously connected to the gate of the PMOS tube PM508, the drain of the NMOS tube NM510, and the gate of the NMOS tube NM511. The drain of the NMOS tube NM511 is simultaneously connected to the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit (3). The gate of the NMOS transistor NM510 is connected to the drain of the NMOS transistor NM514 and the gate of the PMOS transistor PM511 in the output stage circuit; the source of the NMOS transistor NM510 and the source of the NMOS transistor NM511 are both grounded.

5. A high power supply rejection ratio low noise LDO implementation circuit according to claim 4, characterized in that: The first bias circuit in the internal LDO circuit (1) includes an NMOS transistor NM503, an NMOS transistor NM504, an NMOS transistor NM505, an NMOS transistor NM512, a PMOS transistor PM505, a PMOS transistor PM506, a current source I501, and a current source I502; The input end of current source I501 and the input end of current source I502 are both connected to power supply VIN; the output end of current source I501 is simultaneously connected to the gate of NMOS transistor NM512, the drain of NMOS transistor NM512, and the gate of NMOS transistor NM513; the source of NMOS transistor NM512 is grounded; the output end of current source I502 is simultaneously connected to the gate of NMOS transistor NM503, the drain of NMOS transistor NM503, the gate of NMOS transistor NM504, and the gate of NMOS transistor NM505; The drain of NMOS transistor NM504 is connected to the source of NMOS transistor NM501; the drain of NMOS transistor NM505 ​​is connected to the drain of PMOS transistor PM505, the gate of PMOS transistor PM505, the gate of PMOS transistor PM506, and the gate of PMOS transistor PM507; the source of PMOS transistor PM505 and the source of PMOS transistor PM506 are both connected to the power supply VIN; the source of MOS transistor NM503, the source of NMOS transistor NM504, and the source of NMOS transistor NM505 ​​are grounded.

6. A high power supply rejection ratio low noise LDO implementation circuit according to claim 5, characterized in that: The phase compensation network circuit in the internal LDO circuit (1) includes a resistor R503 and a capacitor C503, one end of the capacitor C503 is connected to the power supply VIN; the other end of the capacitor C503 is connected to one end of the resistor R503, and the other end of the resistor R503 is connected to the gate of the PMOS tube PM511; The output stage circuit in the internal LDO circuit (1) includes a PMOS transistor PM511, a resistor R501, a resistor R502, a capacitor C501 and a capacitor C502; the drain of the PMOS transistor PM511 is connected to one end of the resistor R501 and one end of the capacitor C502, the capacitor C502 is connected in parallel to both ends of the resistor R501, the other end of the resistor R501 is connected to one end of the resistor R502, and the other end of the resistor R502 and the other end of the capacitor C502 are both grounded.

7. A high power supply rejection ratio low noise LDO implementation circuit according to claim 6, characterized in that: The voltage follower (2) comprises a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit; The second bias circuit in the voltage follower (2) includes a current source I601, an NMOS transistor NM605, an NMOS transistor NM606, an NMOS transistor NM607, an NMOS transistor NM614, a PMOS transistor PM606, a PMOS transistor PM607 and a PMOS transistor PM608; The input end of the current source I601 is connected to the power supply VIN; the output end of the current source I601 is simultaneously connected to the drain of the NMOS transistor NM605, the gate of the NMOS transistor NM605, and the gate of the NMOS transistor NM606; the drain of the NMOS transistor NM606 is simultaneously connected to the drain of the PMOS transistor PM606, the gate of the PMOS transistor PM606, the gate of the PMOS transistor PM607, and the gate of the PMOS transistor PM608; The drain of the PMOS transistor PM607 is connected to the drain of the NMOS transistor NM614 and the gate of the NMOS transistor NM614; the drain of the PMOS transistor PM608 is connected to the drain of the NMOS transistor NM607 and the gate of the NMOS transistor NM607; The source of the PMOS transistor PM606, the source of the PMOS transistor PM607, and the source of the PMOS transistor PM608 are connected to the power supply VIN; The source of the NMOS transistor NM605 , the source of the NMOS transistor NM606 , the source of the NMOS transistor NM614 , and the source of the NMOS transistor NM607 are grounded.

8. The high power supply rejection ratio low noise LDO implementation circuit according to claim 7, characterized in that: The second error amplifier EA2 in the voltage follower (2) includes a first-stage amplifier circuit / a second-stage amplifier circuit and a current detection circuit; The first-stage amplifier circuit includes NMOS transistors NM601, NMOS transistors NM602, NMOS transistors NM603, NMOS transistors NM604, NMOS transistors NM608, NMOS transistors NM609, NMOS transistors NM610, NMOS transistors NM615, NMOS transistors NM616, PMOS transistors PM601, PMOS transistors PM602, PMOS transistors PM603, and PMOS transistors PM604; The gate of the NMOS transistor NM601 is connected to the positive electrode of the capacitor CF1 in the filter circuit (3), and the gate of the MOS transistor NM602 is connected to the drain of the PMOS transistor PM622; the gate of the NMOS transistor NM601 is the positive input electrode of the second error amplifier EA2, and the gate of the NMOS transistor NM602 is the negative input electrode of the second error amplifier EA2; The source of the NMOS transistor NM601 is connected to the source of the NMOS transistor NM602 and the drain of the NMOS transistor NM608. The gate of the NMOS transistor NM608 is connected to the gate of the NMOS transistor NM609, the gate of the NMOS transistor NM610, and the gate of the NMOS transistor NM607 in the second bias circuit. The drain of the NMOS transistor NM601 is connected to the source of the NMOS transistor NM603, the drain of the NMOS transistor NM602 is connected to the source of the NMOS transistor NM604, and the gate of the NMOS transistor NM603 is connected to the gate of the NMOS transistor NM604; The drain of the NMOS transistor NM603 is connected to the drain of the PMOS transistor PM601 and the source of the PMOS transistor PM603. The drain of the NMOS transistor NM604 is connected to the drain of the PMOS transistor PM602 and the source of the PMOS transistor PM604. The source of the PMOS transistor PM601 and the source of the PMOS transistor PM602 are connected to the power supply VIN. The gate of the PMOS transistor PM601 is simultaneously connected to the gate of the PMOS transistor PM602, the gate of the PMOS transistor PM603, the drain of the PMOS transistor PM603, and the drain of the NMOS transistor NM615; the gate of the PMOS transistor PM604 is simultaneously connected to the drain of the PMOS transistor PM604 and the drain of the NMOS transistor NM616; The gate of NMOS transistor NM615 is connected to the gate of NMOS transistor NM616 and the gate of NMOS transistor NM614 in the second bias circuit. The source of NMOS transistor NM615 is connected to the drain of NMOS transistor NM609, and the source of NMOS transistor NM616 is connected to the drain of NMOS transistor NM610. The source of the NMOS transistor NM608, the source of the NMOS transistor NM609, and the source of the NMOS transistor NM610 are grounded; The second-stage amplifier circuit includes NMOS transistor NM611, NMOS transistor NM617, NMOS transistor NM625, NMOS transistor NM626, PMOS transistor PM605 and PMOS transistor PM609; The source of the PMOS transistor PM609 and the source of the PMOS transistor PM605 are connected to the power supply VIN; the gate of the PMOS transistor PM609 is connected to the gate of the PMOS transistor PM608 in the second bias circuit; the gate of the PMOS transistor PM605 is connected to the gate of the PMOS transistor PM604 in the first-stage amplifier circuit; the drain of the PMOS transistor PM609 is simultaneously connected to the drain of the PMOS transistor PM605, the drain of the NMOS transistor NM617, and the drain of the NMOS transistor NM625; the drain of the PMOS transistor PM609 is the output end of the second error amplifier EA2; The gate of NMOS transistor NM617 is connected to the gate of NMOS transistor NM625 and the gate of NMOS transistor NM616 in the first-stage amplifier circuit. The source of NMOS transistor NM617 is connected to the drain of NMOS transistor NM611. The source of NMOS transistor NM625 is connected to the drain of NMOS transistor NM626. The gate of NMOS transistor NM611 is connected to the gate of NMOS transistor NM610 in the first-stage amplifier circuit. The source of the NMOS transistor NM611 and the source of the NMOS transistor NM626 are grounded; The current detection circuit includes a PMOS transistor PM621, a PMOS transistor PM622, a PMOS transistor PM625, a PMOS transistor PM626, an NMOS transistor NM618, and an NMOS transistor NM619; The source of the PMOS transistor PM621 and the source of the PMOS transistor PM622 are connected to the power supply VIN; The gate of the PMOS transistor PM622 is connected to the gate of the PMOS transistor PM621 and the drain of the PMOS transistor PM609 in the second-stage amplifier circuit; the drain of the PMOS transistor PM622 is connected to the source of the PMOS transistor PM626 and the gate of the NMOS transistor NM602 in the first-stage amplifier circuit; The drain of the PMOS transistor PM621 is connected to the source of the PMOS transistor PM625. The gate of the PMOS transistor PM625 is connected to the gate of the PMOS transistor PM626, the drain of the PMOS transistor PM626, and the drain of the NMOS transistor NM619. The drain of the PMOS transistor PM625 is connected to the drain of the NMOS transistor NM618, the gate of the NMOS transistor NM618, and the gate of the NMOS transistor NM619. The source of the NMOS transistor NM618 and the source of the NMOS transistor NM619 are grounded.

9. A high power supply rejection ratio low noise LDO implementation circuit according to claim 8, characterized in that: The load adaptive current bias circuit in the voltage follower (2) includes an NMOS transistor NM612, an NMOS transistor NM620, an NMOS transistor NM621, an NMOS transistor NM622, an NMOS transistor NM623, a PMOS transistor PM610, a PMOS transistor PM611, a PMOS transistor PM612, a PMOS transistor PM613, a resistor R601, and a capacitor C601; The source of the PMOS transistor PM610, the source of the PMOS transistor PM611, the source of the PMOS transistor PM612, and the source of the PMOS transistor PM613 are connected to the power supply VIN; The gate of the PMOS transistor PM610 is connected to the drain of the PMOS transistor PM610, the gate of the PMOS transistor PM611, and the drain of the NMOS transistor NM620. The drain of the PMOS transistor PM611 is connected to the gate of the NMOS transistor NM612 and the gate of the NMOS transistor NM611 in the second-stage amplifier circuit. The gate of the PMOS transistor PM612 is simultaneously connected to the drain of the PMOS transistor PM612, the gate of the PMOS transistor PM613, and the drain of the NMOS transistor NM612; the source of the NMOS transistor NM612 is connected to the drain of the NMOS transistor NM621; the gate of the NMOS transistor NM620 is simultaneously connected to the gate of the NMOS transistor NM621 and the gate of the NMOS transistor NM619 in the current detection circuit; The drain of the PMOS transistor PM613 is connected to the gate of the NMOS transistor NM622, the drain of the NMOS transistor NM622, and one end of the resistor R601. The other end of the resistor R601 is also connected to one end of the capacitor C601, the gate of the NMOS transistor NM623, and the gate of the NMOS transistor NM626 in the second-stage amplifier circuit. The other end of the capacitor C601 is grounded. The drain of the NMOS transistor NM623 is connected to the source of the NMOS transistor NM601 in the first-stage amplifier circuit. The source of the NMOS transistor NM620 , the source of the NMOS transistor NM621 , the source of the NMOS transistor NM622 , and the source of the NMOS transistor NM623 are all grounded.

10. The high power supply rejection ratio low noise LDO implementation circuit according to claim 9, characterized in that: The compensation circuit in the voltage follower (2) includes an NMOS transistor NM613, an NMOS transistor NM624, a PMOS transistor PM614, a PMOS transistor PM615, a PMOS transistor PM616, a PMOS transistor PM617, a PMOS transistor PM623, a PMOS transistor PM624, a resistor R602, a resistor R603, a resistor R604 and a capacitor C602; The source of the PMOS transistor PM614 and the source of the PMOS transistor PM616 are connected to the power supply VIN; The gate of the PMOS transistor PM614 is connected to the drain of the PMOS transistor PM614, the gate of the PMOS transistor PM615, and the drain of the NMOS transistor NM624. The gate of the NMOS transistor NM624 is connected to the gate of the NMOS transistor NM623 in the load adaptive current bias circuit. The source of the PMOS transistor PM615 is connected to one end of the resistor R602, one end of the resistor R603, and the source of the PMOS transistor PM623; the other end of the resistor R602 is connected to the drain of the PMOS transistor PM602 in the first-stage amplifier circuit; the other end of the resistor R603 is connected to the source of the PMOS transistor PM624 and one end of the resistor R604; the other end of the resistor R604 is connected to the drain of the PMOS transistor PM617; The drain of the PMOS transistor PM615 is simultaneously connected to one end of the capacitor C602, the drain of the PMOS transistor PM623, the drain of the PMOS transistor PM624, and the source of the PMOS transistor PM617; the other end of the capacitor C602 is simultaneously connected to the gate of the PMOS transistor PM623 and the gate of the PMOS transistor PM624; The gate of the PMOS transistor PM617 is connected to the gate of the PMOS transistor PM616, the drain of the PMOS transistor PM616, and the drain of the NMOS transistor NM613. The gate of the NMOS transistor NM613 is connected to the gate of the NMOS transistor NM612 in the load adaptive current bias circuit. The source of the NMOS transistor NM624 and the source of the NMOS transistor NM613 are grounded.

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