Synchronization signal generating circuit and synchronization method among multiple devices

Abstract

The invention provides a synchronization signal generating circuit and a synchronization method among a plurality of devices. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a main end device, and generates a plurality of clock signals to be selected through a plurality of counting actions based on a reference clock signal. The controller selectively transmits one of the clock signals to be selected to each peripheral device according to the demand information corresponding to each peripheral device. Wherein the clock signal to be selected and the input clock signal have mutually aligned starting time points in each frame period.

Description

Technical Field

[0001] The present invention relates to a synchronization signal generating circuit and a synchronization method between multiple devices, and in particular to a synchronization signal generating circuit and a synchronization method between multiple devices used in an augmented actual display system. Background Art

[0002] In the known technical field, the display device of augmented reality includes a display and a plurality of sensing devices. The display and the sensing devices can perform various object tracking actions. The display can be used as an output device and the sensing device can be used as an input device. Since the display and the sensing device may perform actions according to different frame rates, it is difficult to synchronize the display and the plurality of sensing devices. Summary of the invention

[0003] The present invention is directed to a synchronization signal generating circuit and a synchronization method between multiple devices, which can synchronize multiple devices working at different frame rates.

[0004] According to an embodiment of the present invention, a synchronization signal generating circuit includes a clock signal generator and a first controller. The clock signal generator generates a reference clock signal. The first controller is coupled between a master device and a plurality of first peripheral devices, and receives an input clock signal from the master device. The first controller, based on the reference clock signal, generates a plurality of selected clock signals respectively through a plurality of counting actions. The first controller selects one of the selected clock signals to be transmitted to each first peripheral device according to the demand information corresponding to each first peripheral device. The selected clock signal and the input clock signal have mutually aligned starting time points in each frame period.

[0005] According to an embodiment of the present invention, a synchronization method between multiple devices includes: enabling a clock signal generator to generate a reference clock signal; setting a first controller between a main-end device and multiple first peripheral devices; enabling the first controller to receive an input clock signal from the main-end device, and based on the reference clock signal, enabling the first controller to respectively generate multiple selected clock signals through multiple counting actions; and, based on demand information corresponding to each first peripheral device, enabling the first controller to select and transmit one of the selected clock signals to each first peripheral device, wherein the selected clock signal and the input clock signal have mutually aligned starting time points in each frame period.

[0006] Based on the above, in the synchronization signal generating circuit of the present invention, a first controller is used to perform multiple counting actions based on a reference clock signal to generate multiple clock signals to be selected respectively, and one of the clock signals to be selected is selected according to the frame rate requirements of each peripheral device to be transmitted to each peripheral device and used as a synchronization signal of the peripheral device. The controller is used to make the clock signal to be selected and the input clock signal of the master device have a mutually aligned starting time point in each frame cycle, thereby synchronizing the actions between the master device and the multiple peripheral devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a synchronization signal generating circuit according to an embodiment of the present invention is shown.

[0008] Figure 2 A schematic diagram showing a synchronization signal generating circuit according to another embodiment of the present invention is shown.

[0009] Figure 3 A schematic diagram showing an implementation of a controller in a synchronization signal generating circuit according to an embodiment of the present invention.

[0010] Figure 4 The waveform diagram of the input clock signal and the output clock signal according to the embodiment of the present invention is shown.

[0011] Figure 5 A schematic diagram showing a partial circuit of a controller in a synchronization signal generating circuit according to an embodiment of the present invention.

[0012] Figure 6 A schematic diagram showing a synchronization signal generating circuit according to another embodiment of the present invention is shown.

[0013] Figure 7 A schematic diagram showing a synchronization signal generating circuit according to another embodiment of the present invention is shown.

[0014] Figure 8 A flow chart showing a synchronization method among multiple devices according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Please refer to Figure 1 , Figure 1Schematic diagram of a synchronization signal generating circuit according to an embodiment of the present invention is shown. The synchronization signal generating circuit 100 includes a controller 110 and a clock signal generator 120. The controller 110 is coupled to the clock signal generator 120. The clock signal generator 120 is used to generate a reference clock signal CLK and transmit the reference clock signal CLK to the controller 110. In this embodiment, the clock signal generator 120 is externally mounted outside the controller 110.

[0017] On the other hand, the controller 110 is coupled to the master device 101 and to a plurality of peripheral devices 130-1 to 130-3. The controller 110 receives an input clock signal INCK transmitted by the master device 101, wherein the input clock signal INCK may be a synchronization signal sent by the master device 101. The controller 110 may generate a plurality of selected clock signals respectively through a plurality of counting actions based on the received reference clock signal CLK. Further, the controller 110 may select one of the selected clock signals to be transmitted to generate an output clock signal OUTCK1 according to the requirement information of the peripheral devices 130-1 and 130-2, and transmit the output clock signal OUTCK1 to the peripheral devices 130-1 and 130-2. The controller 110 may also select one of the selected clock signals to be transmitted to generate an output clock signal OUTCK2 according to the requirement information of the peripheral device 130-3, and transmit the output clock signal OUTCK2 to the peripheral device 130-3.

[0018] The demand information of the peripheral devices 130-1, 130-2, and 130-3 is the frame rate at which the peripheral devices 130-1, 130-2, and 130-3 perform their work. In this embodiment, the peripheral devices 130-1 and 130-2 may have the same working frame rate and may receive the same output clock signal OUTCK1. The peripheral devices 130-1 and 130-2 receive the output clock signal OUTCK1 as a synchronization signal. In contrast, the working frame rate of the peripheral device 130-3 may be different from the working frame rate of the peripheral device 130-1, and may receive the output clock signal OUTCK2 as a synchronization signal. The output clock signal OUTCK2 and OUTCK1 may have different frequencies.

[0019] Since the output clock signals OUTCK1 and OUTCK2 are both selected from a plurality of clock signals to be selected generated internally by the controller 110, the output clock signal OUTCK1 can be one of the clock signals to be selected, and the output clock signal OUTCK2 can be another of the clock signals to be selected. In addition, the demand information of the peripheral devices 130-1 to 130-3 does not need to be fixed, but can be adjusted dynamically. Taking the peripheral device 130-1 as an example, when the demand information of the peripheral device 130-1 changes, the controller 110 can correspondingly select another clock signal to be selected (having a frequency different from the output clock signal OUTCK1) other than the output clock signal OUTCK1 as the output clock signal, and transmit this output clock signal to the peripheral device 130-1 as a synchronization signal of the peripheral device 130-1.

[0020] It is worth mentioning that in order to synchronize the operations of the host device 101 and the peripheral devices 130-1 to 130-3, the controller 110 can align the starting time points of the generated clock signals to be selected with the starting time point of the input clock signal INCK in each frame period.

[0021] Incidentally, in this embodiment, the host device 101 may be an electronic device having a display. In addition, the host device 101 may have a processor. The input clock signal INCK provided by the host device 101 may be a synchronization signal for the display to perform a display action, such as a vertical synchronization signal. Each of the peripheral devices 130-1 to 130-3 may be a sensing component, such as a light sensor array and a light emitter array and / or a microelectromechanical system (MEMS).

[0022] Please refer to the following Figure 2 , Figure 2A schematic diagram of a synchronization signal generating circuit according to another embodiment of the present invention is shown. The synchronization signal generating circuit 200 includes a controller 210 and a clock signal generator 220. The controller 210 is coupled to the clock signal generator 220, wherein the clock signal generator 220 is embedded in the controller 210. The clock signal generator 220 is used to generate a reference clock signal CLK inside the controller 210. In this embodiment, the controller 210 is coupled to the host device 201, and is also coupled to the peripheral devices 230-1 to 230-3, and the peripheral device 230-4 can be directly coupled to the host device 201. The controller 210 is the same as the controller 110 of the aforementioned embodiment, and can generate and transmit the output clock signal OUTCK1 to the peripheral devices 230-1 and 230-2 according to the demand information of the peripheral devices 230-1 to 230-3, and generate and transmit the output clock signal OUTCK2 to the peripheral device 230-3. The peripheral devices 230 - 1 to 230 - 3 can perform synchronization actions according to the received output clock signal OUTCK1 or OUTCK2 .

[0023] Regarding the synchronization action of the peripheral device 230-4, the host device 201 can directly send the synchronization signal SYNC to the peripheral device 230-4, and the peripheral device 230-4 can perform the synchronization action according to the synchronization signal SYNC. Further, in this embodiment, the peripheral device 230-1 can also generate a post-synchronization signal PSYNC according to the received output clock signal OUTCK1. The peripheral device 230-1 can transmit the post-synchronization signal PSYNC to the peripheral device 230-4. In this way, the peripheral device 230-4 can perform the synchronization action according to the post-synchronization signal PSYNC and the synchronization signal SYNC.

[0024] Regarding the above Figure 1 , Figure 2 For details on the generation of the selected clock signal and the output clock signals OUTCK1 and OUTCK2 in the embodiment, please refer to the following embodiment.

[0025] Please refer to Figure 3 , Figure 3 A schematic diagram showing an implementation of a controller in a synchronization signal generating circuit according to an embodiment of the present invention. The controller 300 includes a frequency generator 301. The frequency generator 301 includes an arbitrator 310, counters 321, 322, and a selector 330. It is worth mentioning that one frequency generator 301 may correspond to at least one peripheral device. When the controller 300 corresponds to controlling multiple peripheral devices with different demand information, multiple frequency generators 301 may be provided in the controller 300.

[0026] In this embodiment, the arbiter 310 is coupled to the counters 321, 322 and the selector 330. The arbiter 310 receives the request information RQI of the corresponding peripheral device and generates the selection signal SEL according to the request information RQI. The counters 321, 322 receive the reference clock signal CLK generated by the frequency generator 301, perform counting based on the reference clock signal CLK, and generate the selected clock signals dCK1 and dCK2 respectively. The selector 330 is coupled to the counters 321, 322 and the arbiter 310, and the selector 330 selects one of the selected clock signals dCK1 and dCK2 according to the selection signal SEL to generate the output clock signal OUTCKx.

[0027] In terms of operation details, the arbitrator 310 is used to decode the received requirement information RQI. The requirement information RQI includes the possible operating frame rate of the corresponding peripheral device and the currently required operating frame rate. In this embodiment, the arbitrator 310 can decode the possible operating frame rate in the requirement information RQI to generate the first target frequency GF1 and the second target frequency GF2. The arbitrator 310 can also decode the currently required operating frame rate in the requirement information RQI to generate the selection signal SEL.

[0028] The counters 321 and 322 receive the first target frequency GF1 and the second target frequency GF2, respectively. The counter 321 performs a counting operation based on the reference clock signal CLK according to the first target frequency GF1, and thereby generates a clock signal dCK1 to be selected whose frequency is equal to the first target frequency GF1. It is worth mentioning that the reference clock signal CLK can be a signal with a relatively high frequency, such as millions or tens of megahertz (Hz). The first target frequency GF1 can be a relatively low frequency, such as tens of Hz. The counter 321 can generate the clock signal dCK1 to be selected by counting according to the multiple relationship between the frequency of the reference clock signal CLK and the first target frequency GF1. In the present embodiment, the counter 321 may include a frequency dividing circuit.

[0029] The counter 322 performs counting based on the reference clock signal INCK according to the second target frequency GF2, and generates a candidate clock signal dCK2 having a frequency equal to the second target frequency GF2. The counter 322 has similar circuit characteristics to the counter 321, and will not be described in detail.

[0030] In this embodiment, the arbiter 310 may be a digital circuit. The counters 321 and 322 may be any form of counting circuits known to those skilled in the art without any particular limitation. The selector 330 may be any form of multitasking circuit known to those skilled in the art without any particular limitation.

[0031] Please refer to the following Figure 4 ,in Figure 4 The waveform diagram of the input clock signal and the output clock signal of the embodiment of the present invention is shown. Figure 4 In the example, taking the frame rate of the host device as 30 Hz, the controller can obtain the starting time points ST1 and ST2 of the next frame periods FP2 and FP3 by counting the pulse numbers of the input clock signal INCK provided by the host device in the frame periods FP1 and FP2 respectively.

[0032] On the other hand, in the frame period FP1, the controller selects the selected clock signal dCK1 to generate the output clock signal OUTCK1, and selects the selected clock signal dCK2 to generate the output clock signal OUTCK2. For example, the frequencies of the selected clock signals dCK1 and dCK2 are 30 Hz and 20 Hz respectively. The counter in the controller (e.g. Figure 3 The counters 321 and 322 in the circuit 321 can count the pulse numbers of the clock signals dCK1 and dCK2 to be selected. When the pulse number of the clock signal dCK1 to be selected reaches the first target value, the counter 321 can enter the reset interval RST1 and maintain the output clock signal OUTCK1 (equivalent to the clock signal dCK1 to be selected) at a set logic value (e.g., logic value 0). Similarly, when the pulse number of the clock signal dCK2 to be selected reaches the second target value, the counter 322 can enter the reset interval RST1 and maintain the output clock signal OUTCK2 (equivalent to the clock signal dCK2 to be selected) at a set logic value (e.g., logic value 0).

[0033] The first target value and the second target value can be determined according to the frequencies of the selected clock signals dCK1 and dCK2 and the length of the frame period FP1. For example, when the frame period FP1 is 1 second, the first target value corresponding to the selected clock signal dCK1 can be 20, and the second target value corresponding to the selected clock signal dCK2 can be 30.

[0034] The controller maintains the output clock signals OUTCK1 and OUTCK2 at logic value 0 in the reset interval RST1, and synchronously releases the reset state of the output clock signals OUTCK1 and OUTCK2 at the start time point ST1 of the frame period FP2, and synchronously starts the oscillation action of the output clock signals OUTCK1 and OUTCK2. In this way, the output clock signals OUTCK1 and OUTCK2 can achieve synchronization with the input clock signal INCK.

[0035] In the frame period FP2, based on the information required by the peripheral device, the controller switches to select the selected clock signal dCK2 to generate the output clock signal OUTCK1, and selects the selected clock signal dCK1 to generate the output clock signal OUTCK2. Similarly, in the frame period FP2, the counters 321 and 322 respectively count the pulse numbers of the selected clock signals dCK1 and dCK2 to generate a reset interval RST2, and maintain the output clock signals OUTCK1 and OUTCK2 at a logic value of 0 in the reset interval RST2. In addition, at the starting time point ST2 of the frame period FP3, the output clock signals OUTCK1 and OUTCK2 can start the oscillation action synchronously.

[0036] Please refer to the following Figure 5 , Figure 5 FIG. 5 is a schematic diagram showing a partial circuit of a controller in a synchronization signal generating circuit according to an embodiment of the present invention. The counter 510 in the controller may be coupled to the comparator 520. The counter 510 may be Figure 3 The counter 510 can count the pulse number NP of the generated clock signal to be selected, and the comparator 520 is used to compare the pulse number NP with the corresponding target value TV. When the pulse number NP is equal to the corresponding target value TV, the comparator 520 can generate a reset signal RST to reset the counter 510 and maintain the clock signal to be selected at a set logic value (e.g., logic value 0).

[0037] Please refer to Figure 6 , Figure 6 A schematic diagram of a synchronization signal generating circuit according to another embodiment of the present invention is shown. The synchronization signal generating circuit 600 includes controllers 610 and 620. The controllers 610 and 620 can receive a reference clock signal CLK generated by a clock signal generator (not shown). The controller 610 is coupled between a display device 601 as a master device and a peripheral device 631-1. The controller 620 is coupled between the display device 601, the controller 610, and the peripheral devices 631-2 and 631-3.

[0038] The controller 610 can perform the sending and receiving actions of the input and output data IO1 with the display device 601. The controller 610 can also receive the input clock signal INCK from the display device 610. The controller 610 can be used to generate a plurality of selected clock signals respectively through a plurality of counting actions based on the reference clock signal CLK, and select one of the plurality of selected clock signals to be transmitted as the output clock signal OUTCK1 according to the requirement information of the corresponding peripheral device 631-1, and transmit the output clock signal OUTCK1 to the peripheral device 631-1.

[0039] On the other hand, the controller 610 can select another one of the multiple clock signals to be selected as the output clock signal OUTCK2, and transmit the output clock signal OUTCK2 to the controller 620. The controller 620 can have a circuit architecture similar to that of the controller 610. The controller 620 receives the output clock signal OUTCK2 as its input clock signal, and performs operations similar to those of the controller 610 to generate the output clock signal OUTCK3 and the output clock signal OUTCK4, and provides the output clock signal OUTCK3 and the output clock signal OUTCK4 to the corresponding peripheral devices 631-2 and 431-3, respectively.

[0040] In this embodiment, the controller 620 can serve as a relay circuit between multiple peripheral devices 631-2, 631-3 and the controller 610, and by providing output clock signals OUTCK3 and output clock signals OUTCK4 to corresponding peripheral devices 631-2 and 631-3 respectively, the peripheral devices 631-2 and 631-3 can perform synchronous actions according to the output clock signals OUTCK3 and output clock signals OUTCK4 respectively.

[0041] In this embodiment, the operation details of the controllers 610 and 620 have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0042] It is worth mentioning that, in this embodiment, the controller 620 may be directly coupled to the display device 601 , and may directly send and receive input and output data IO2 with the display device 601 .

[0043] Please refer to Figure 7 , Figure 7 A schematic diagram of a synchronization signal generating circuit according to another embodiment of the present invention is shown. The synchronization signal generating circuit 700 includes a controller 710. In this embodiment, the master device may be one of a plurality of peripheral devices. The controller 710 is coupled between the peripheral device 701 and the peripheral devices 730-1 and 730-2. The controller 710 may receive a synchronization signal provided by the peripheral device 701 as an input clock signal INCK, and generate output clock signals OUTCK1 and OUTCK2 based on the reference clock signal CLK. The controller 710 also provides output clock signals OUTCK1 and OUTCK2 to the peripheral devices 730-1 and 730-2, respectively, as synchronization signals. In this way, the synchronization signal generating circuit 700 may perform synchronization actions between the peripheral devices 701, 730-1, and 730-2.

[0044] In this embodiment, the operation details of the controller 710 have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0045] Please refer to Figure 8 , Figure 8 The flowchart of the synchronization method between multiple devices according to an embodiment of the present invention is shown. In step S810, a clock signal generator generates a reference clock signal; in step S820, a first controller is set between a master device and multiple first peripheral devices; in step S830, the first controller receives an input clock signal from the master device, and based on the reference clock signal, the first controller generates multiple clock signals to be selected through multiple counting operations; in step S840, according to the demand information corresponding to each first peripheral device, the first controller selects one of the clock signals to be selected and transmits it to each first peripheral device, wherein the clock signal to be selected and the input clock signal have mutually aligned starting time points in each frame period.

[0046] The implementation details of the above steps have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0047] In summary, the synchronization signal generating circuit of the present invention performs multiple counting actions through the first controller, and then selects and transmits one of the multiple clock signals to each first peripheral device according to the demand information of the corresponding peripheral device, so as to serve as the synchronization signal of each first peripheral device. The key point is that the controller of the present invention enables the selected clock signal and the input clock signal provided by the host device to have mutually aligned starting time points in each frame cycle. In this way, the synchronization action between the host device and multiple peripheral devices can be effectively executed, effectively improving the overall efficiency of the system.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A synchronization signal generating circuit, comprising: A clock signal generator, generating a reference clock signal; as well as A first controller is coupled between a master device and a plurality of first peripheral devices, and receives an input clock signal from the master device. The first controller generates a plurality of selected clock signals through a plurality of counting operations based on the reference clock signal. The first controller selects and transmits one of the plurality of selected clock signals to each of the first peripheral devices according to the demand information corresponding to each of the first peripheral devices. The plurality of to-be-selected clock signals and the input clock signal have mutually aligned starting time points in each frame period. 2 . The synchronization signal generating circuit according to claim 1 , wherein the frequencies of the plurality of clock signals to be selected are different. 3 . The synchronization signal generating circuit according to claim 1 , wherein each of the first peripheral devices receives one of the plurality of selectable clock signals as a synchronization signal.

4. The synchronization signal generating circuit according to claim 1, wherein the first controller comprises: A plurality of frequency generators respectively correspond to the plurality of first peripheral devices, each of the frequency generators respectively generates the plurality of selected clock signals of different frequencies according to the reference clock signal, each of the frequency generators parses the respective demand information to generate a selection signal, and selects one of the plurality of selected clock signals according to the selection signal to generate a corresponding output clock signal.

5. The synchronization signal generating circuit according to claim 4, wherein each of the frequency generators comprises: An arbitrator receives each of the demand information and analyzes each of the demand information to generate each of the selection signals; A first counter receives the reference clock signal and generates a first selected clock signal having a first frequency by performing a first counting operation based on the reference clock signal; A second counter receives the reference clock signal and generates a second selected clock signal having a second frequency by performing a second counting operation based on the reference clock signal, wherein the first frequency is different from the second frequency; as well as The selector is coupled to the first counter, the second counter and the arbitrator, and selects the first to-be-selected clock signal or the second to-be-selected clock signal as the output clock signal according to the selection signal.

6. The synchronization signal generating circuit according to claim 5, wherein the frequency generator further comprises: a first comparator, for comparing a first target value with a first count value of the first counter, and generating a first reset signal to reset the first counter and maintain the first selected clock signal at a set logic value when the first target value is equal to the first count value in each frame period; as well as The second comparator compares the second target value with the second count value of the second counter, and in each frame period, when the second target value is equal to the second count value, generates a second reset signal to reset the second counter and maintains the second selected clock signal at the set logic value.

7. The synchronization signal generating circuit according to claim 1 further comprises: A second controller is coupled to the first controller, wherein the first controller transmits a first clock signal, one of the multiple selected clock signals, to the second controller, and the second controller selects to transmit one of the multiple secondary selected clock signals to the at least one second peripheral device based on the first clock signal and the demand information corresponding to the at least one second peripheral device. 8 . The synchronization signal generating circuit according to claim 1 , wherein the master device is an electronic device or a sensing component having a display. 9 . The synchronization signal generating circuit according to claim 1 , wherein the master device directly transmits the synchronization signal to the second peripheral device. 10 . The synchronization signal generating circuit according to claim 1 , wherein the first controller obtains the starting time point of each frame period by counting the input clock signal. 11 . The synchronization signal generating circuit according to claim 1 , wherein the clock signal generator is embedded in the first controller, or the clock signal generator is externally mounted outside the first controller.

12. A method for synchronizing multiple devices, comprising: Enable the clock signal generator to generate a reference clock signal; A first controller is arranged between the host device and the plurality of first peripheral devices; The first controller receives an input clock signal from the master device, and based on the reference clock signal, the first controller generates a plurality of clock signals to be selected respectively through a plurality of counting actions; as well as According to the demand information corresponding to each of the first peripheral devices, the first controller selects to transmit one of the plurality of selected clock signals to each of the first peripheral devices, The plurality of to-be-selected clock signals and the input clock signal have mutually aligned starting time points in each frame period. The synchronization method according to claim 12 , wherein the frequencies of the plurality of clock signals to be selected are different.

14. The synchronization method according to claim 12, further comprising: Each of the first peripheral devices receives one of the plurality of selected clock signals as a synchronization signal.

15. The synchronization method according to claim 12, further comprising: A second controller is arranged after the first controller; Enable the first controller to transmit a first clock signal among the plurality of clock signals to be selected to the second controller; as well as The second controller is enabled to select and transmit one of a plurality of secondary selected clock signals to the at least one second peripheral device based on the first clock signal and according to the requirement information corresponding to the at least one second peripheral device.

16. The synchronization method according to claim 12, further comprising: The host device directly transmits a synchronization signal to a second peripheral device.

17. The synchronization method according to claim 12, further comprising: The first controller is enabled to obtain a starting time point of each frame period by counting the input clock signal.

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