Method and device for generating control signal based on timing interruption of pulse per second

Abstract

The invention belongs to the field of interruption control, and particularly discloses a method and a device for generating a control signal of timing interruption based on pulse per second. According to the invention, the receiving of the second pulse signal, the optimization shaping of the second pulse single-ended signal, the output of the second pulse effective indication signal and the output of the second pulse absence indication signal are realized, and the precise second pulse-based control signal for controlling the timing interruption realization circuit is generated. The method can eliminate the influence of ringing, noise, jitter and the like on a second pulse single-ended signal in an application occasion with more signal flaws, and can meet the requirement of an external second pulse signal on the precise control of the timing interruption realization circuit, so that the timing interruption realization circuit can adapt to the mismatching of the local clock precision and the external clock precision, and the reliability of the timing interruption realization circuit is improved. And the time sequence problem caused by mismatching can be avoided, the robustness is good, and the operation is stable and reliable.

Description

Technical Field

[0001] The present application belongs to the field of interrupt control, and more specifically, to a method and device for generating a control signal based on a timed interrupt of a second pulse. Background Art

[0002] In complex application environments, circuit stability and accuracy issues caused by the instability of the local power supply, signal glitches caused by high-frequency interference sources in space, and signal ringing caused by impedance changes during signal transmission will have varying degrees of impact on the pulse-per-second single-ended signal.

[0003] In addition, after receiving the second pulse, under normal circumstances, the timing interrupt implementation circuit uses the local clock beat count within one second, and generates a regular interrupt signal to the CPU. The precision mismatch between the external clock and the local clock will make it difficult for the time counted by the local clock beat to be completely consistent with the time of one second on the external clock. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of this application is to provide a control signal generation method and device based on second pulse timing interruption, aiming to solve the influence of ringing, noise, jitter, etc. on the second pulse single-ended signal, and the mismatch between the local clock accuracy and the external second pulse signal time accuracy.

[0005] To achieve the above objectives, in a first aspect, the present application provides a control signal generation method based on a timed interrupt of a second pulse, comprising:

[0006] Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to the first threshold, the second pulse valid indication signal is at a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to the second threshold, the second pulse valid indication signal is at a high level; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is at a low level;

[0007] Under the beat of the local clock, the number of clock cycles is counted with the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to the third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again.

[0008] The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interruption implementation circuit to control the timing interruption implementation circuit;

[0009] Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0010] Preferably, the pulse-per-second differential signal is converted to obtain a pulse-per-second single-ended signal.

[0011] Preferably, the pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

[0012] To achieve the above-mentioned purpose, in a second aspect, the present application provides a control signal generating device based on a timed interrupt of a second pulse, comprising:

[0013] A second pulse effective indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of an input unipolar rectangular pulse signal under the beat of a local clock. If the positive pulse width count value is less than or equal to a first threshold, the second pulse effective indication signal is a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse effective indication signal is a high level; if the positive pulse width count value is greater than the second threshold, the second pulse effective indication signal is a low level; the first threshold is the product of the jitter signal width to be eliminated and the local clock frequency; the second threshold is the sum of the first threshold and the product of the pulse width of the effective indication signal and the local clock frequency;

[0014] The second pulse absence indication circuit is used to count the number of clock cycles under the beat of the local clock, using the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to a third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again. The third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0015] Preferably, the second pulse effective indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse effective indication signal output unit;

[0016] The first counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock;

[0017] The first counter enabling unit is used to enable counting of the first counter;

[0018] The pulse-per-second valid indication signal output unit is used to compare the count value of the first counter with the first threshold value and the second threshold value, and generate a pulse-per-second valid indication signal according to the comparison result.

[0019] Preferably, the first counter enabling unit is used to compare the count value of the first counter with a second threshold, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold.

[0020] Preferably, the second pulse absence indication circuit comprises: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit;

[0021] The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock with the second pulse valid indication signal as the clearing signal;

[0022] The second counter enabling unit is used to enable counting of the second counter;

[0023] The second pulse absence indication signal output unit is used to compare the count value of the second counter with the third threshold value, and generate a second pulse absence indication signal according to the comparison result.

[0024] Preferably, the second counter enabling unit is used to compare the count value of the second counter with a third threshold, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold.

[0025] Preferably, it also includes:

[0026] A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal;

[0027] The pulse-per-second single-ended signal optimization and shaping circuit is used to optimize and shape the pulse-per-second single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the pulse-per-second single-ended signal, and generate an optimized and shaped pulse-per-second access signal.

[0028] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0029] The present application provides a control signal generation method and device based on a timed interrupt of a second pulse, which generates a precise control signal based on a second pulse for controlling a timed interrupt implementation circuit by receiving a second pulse signal, optimizing and shaping a second pulse single-ended signal, outputting a second pulse valid indication signal, and outputting a second pulse absent indication signal. The method can be independent of an external second pulse signal generation device and a timed interrupt implementation circuit, and can eliminate the influence of ringing, noise, jitter, etc. on the second pulse single-ended signal in applications with many signal defects, and can meet the requirements of the external second pulse signal for precise control of the timed interrupt implementation circuit, so that the timed interrupt implementation circuit can adapt to the mismatch between the local clock accuracy and the external clock accuracy, and can avoid the timing problems caused by such mismatch, and can effectively prevent the timed interrupt implementation circuit from performing unnecessary work and bringing additional hardware overhead, and can meet the requirements of the external second pulse signal for precise control of the timed interrupt implementation circuit, with good robustness and stable and reliable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flow chart of a control signal generation method based on second pulse timing interruption provided in an embodiment of the present application.

[0031] Figure 2 It is a circuit connection relationship diagram of a second pulse receiving circuit, a second pulse access signal optimization shaping circuit, and a second pulse effective indication circuit provided in an embodiment of the present application.

[0032] Figure 3 It is a circuit connection diagram of the pulse-per-second absence indication circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0035] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0036] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0037] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0038] First, the technical terms involved in the embodiments of the present application are introduced.

[0039] "Pulse per second" refers to the number of pulses generated per second, that is, a pulse signal with a time interval of 1 second, which is used to indicate the whole second.

[0040] "Interrupt" means that when the CPU is executing the current program, due to some emergency situation that needs to be handled in the system, the CPU needs to pause the program being executed and execute another special program to handle the emergency. After the processing is completed, the CPU automatically returns to the originally paused program to continue execution. This situation where the execution process is interrupted due to external reasons is called an interruption.

[0041] When this execution process is caused by an interrupt issued to the CPU according to a certain rule within the whole second time period indicated by the second pulse, this interrupt is called a "timed interrupt based on the second pulse".

[0042] The "local clock" refers to a clock signal of the same frequency and phase provided to a control signal generating method and device for a timing interrupt and a timing interrupt implementation circuit.

[0043] "External clock" refers to the clock signal used by an external device that generates an external second pulse signal.

[0044] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0045] like Figure 1 As shown, the present application provides a control signal generation method based on a timed interrupt of a second pulse, comprising:

[0046] Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to the first threshold, the second pulse valid indication signal is at a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to the second threshold, the second pulse valid indication signal is at a high level; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is at a low level;

[0047] Under the beat of the local clock, the number of clock cycles is counted with the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to the third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again.

[0048] The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interruption implementation circuit to control the timing interruption implementation circuit;

[0049] Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0050] The first threshold = the jitter signal width that needs to be eliminated * the local clock frequency.

[0051] The second threshold value=the first threshold value+the pulse width of the valid indication signal*the local clock frequency.

[0052] The third threshold value=local clock frequency-the number of clock cycles corresponding to the positive pulse width of the pulse-per-second valid indication signal.

[0053] Preferably, the pulse-per-second differential signal is converted to obtain a pulse-per-second single-ended signal.

[0054] Preferably, the pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

[0055] Correspondingly, the present application provides a control signal generating device based on timed interruption of second pulse, comprising:

[0056] A second pulse effective indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of an input unipolar rectangular pulse signal under the beat of a local clock. If the positive pulse width count value is less than or equal to a first threshold, the second pulse effective indication signal is a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse effective indication signal is a high level; if the positive pulse width count value is greater than the second threshold, the second pulse effective indication signal is a low level; the first threshold is the product of the jitter signal width to be eliminated and the local clock frequency; the second threshold is the sum of the first threshold and the product of the pulse width of the effective indication signal and the local clock frequency;

[0057] The second pulse absence indication circuit is used to count the number of clock cycles under the beat of the local clock, using the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to a third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again. The third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0058] Preferably, the second pulse effective indication circuit is used to further eliminate the influence of jitter on control accuracy that is not eliminated by the second pulse single-ended signal optimization shaping circuit due to the large level fluctuation range, and generate a second pulse effective indication signal according to the second pulse access signal to realize control of the timing interrupt implementation circuit.

[0059] Preferably, the second pulse absence indication circuit is used to generate a second pulse absence indication signal according to the second pulse valid indication signal, so as to realize the control of the timing interruption realization circuit.

[0060] Preferably, the second pulse effective indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse effective indication signal output unit;

[0061] The first counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock;

[0062] The first counter enabling unit is used to enable counting of the first counter;

[0063] The pulse-per-second valid indication signal output unit is used to compare the count value of the first counter with the first threshold value and the second threshold value, and generate a pulse-per-second valid indication signal according to the comparison result.

[0064] Preferably, the first counter enabling unit is used to compare the count value of the first counter with a second threshold, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold.

[0065] The pulse-per-second valid indication circuit includes not only a NOT gate, a first counter, a first counter enabling unit, and a pulse-per-second valid indication signal output unit, but may also include logic gate circuits such as an OR gate according to the needs of reset control.

[0066] The first threshold is determined by the local clock frequency and the width of the jitter signal whose influence needs to be eliminated. By setting the first threshold, the pulse-per-second valid indication circuit ignores the positive pulse jitter signal that is less than or equal to the set positive pulse width in the pulse-per-second access signal optimized by the Schmitt trigger buffer circuit, and regards the positive pulse signal that is greater than the set positive pulse width as a "valid" positive pulse signal.

[0067] The second threshold is determined by the local clock frequency, the first threshold and the positive pulse width of the pulse-per-second effective indication signal, wherein the positive pulse width of the pulse-per-second effective indication signal is determined by the input requirement of the timing interruption implementation circuit.

[0068] The first counter should at least have a clock input port (clk), a count clear port (CLR), a count enable port (EN), and a count value output port (Q). The clock input port (clk) is connected to a local clock. The count clear port (CLR) is controlled by a second pulse access signal output from a second pulse single-ended signal optimization shaping circuit and a global reset signal. The count enable port (EN) is controlled by the first counter enable unit.

[0069] The second pulse valid indication signal output unit generates a second pulse valid indication signal according to the comparison result between the count value of the first counter and the first threshold value and the second threshold value. When the count value of the first counter is less than or equal to the first threshold value, the second pulse valid indication signal is at a low level. When the count value of the first counter is greater than the first threshold value and less than or equal to the second threshold value, the second pulse valid indication signal is at a high level. When the count value of the first counter is greater than the second threshold value, the positive pulse width of the second pulse valid indication signal has reached the input requirement of the timing interruption realization circuit, and the second pulse valid indication signal output unit controls the second pulse valid indication signal to be at a low level.

[0070] Preferably, the second pulse absence indication circuit comprises: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit;

[0071] The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock with the second pulse valid indication signal as the clearing signal;

[0072] The second counter enabling unit is used to enable counting of the second counter;

[0073] The second pulse absence indication signal output unit is used to compare the count value of the second counter with the third threshold value, and generate a second pulse absence indication signal according to the comparison result.

[0074] Preferably, the second counter enabling unit is used to compare the count value of the second counter with a third threshold, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold.

[0075] The third threshold is determined by the local clock frequency and the positive pulse width of the pulse-per-second valid indication signal. The third threshold is equal to the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the pulse-per-second valid indication signal.

[0076] The second counter should at least include a clock input port (clk), a count clear port (CLR), a count enable port (EN), and a count value output port (Q). The clock input port (clk) is connected to a local clock. The count clear port (CLR) is controlled by a second pulse valid indication signal. The count enable port (EN) is controlled by the second counter enable unit.

[0077] The second pulse absence indication signal output unit generates a second pulse absence indication signal according to the comparison result of the count value of the second counter and the third threshold value. When the count value of the second counter is less than or equal to the third threshold value, the second pulse absence indication signal is at a low level. When the count value of the second counter is greater than the third threshold value, the second pulse absence indication signal is at a high level. Until the count value of the second counter is cleared by the next second pulse valid indication signal, the second pulse absence indication signal returns to a low level again.

[0078] The timing interruption implementation circuit performs the work of each second cycle under the joint control of a second pulse valid indication signal and a second pulse absence indication signal output by a control signal generation method and device for timing interruption based on second pulse. For the timing interruption implementation circuit, the second pulse valid indication signal indicates the arrival of a new external second cycle. The second pulse valid indication signal is used to control the clearing of relevant counters, register variables, etc. in the timing interruption implementation circuit. After the clearing is completed, the timing interruption implementation circuit can regularly generate interrupts to the CPU by controlling the relevant counters, register variables, etc. under the action of the local clock. When all the interrupts that should be generated by the timing interruption implementation circuit within 1 second are completed, and the positive pulse of the next second pulse valid indication signal does not arrive, in order to avoid the timing interruption implementation circuit from starting the work of the next second cycle, the present application also uses the second pulse absence indication signal to control the clearing of relevant counters, register variables, etc. of the timing interruption implementation circuit, which can effectively prevent the timing interruption implementation circuit from performing unnecessary work and bringing additional hardware overhead. Only when the positive pulse of the next second pulse valid indication signal arrives, the timing interruption implementation circuit will start the work of a new second cycle.

[0079] Preferably, it also includes:

[0080] A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal;

[0081] The pulse-per-second single-ended signal optimization and shaping circuit is used to optimize and shape the pulse-per-second single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the pulse-per-second single-ended signal, and generate an optimized and shaped pulse-per-second access signal.

[0082] The second pulse receiving circuit mainly includes the RS485 receiving unit and its peripheral power supply and grounding circuits.

[0083] The RS485 receiving unit receives a pair of differential signals and outputs a CMOS digital signal, and the interface level meets the TIA / EIA-485 protocol specification. The RS485 receiving unit should at least include a receiver in-phase input interface (A), a receiver inverting input interface (B), a receiver output interface (RO), and a receiver output enable (RE#). A and B are a pair of differential signals for receiving external second pulse signals. The receiver output interface (RO) outputs a second pulse single-ended signal. When RE# is connected to a low level (zero level), the RO output is valid; when RE# is connected to a high level, RO is in a high impedance state. When RE# is at a low level (zero level), if the difference between the A and B levels is higher than the input high level threshold, the RO output is a high level; if the difference between the A and B levels is lower than the input low level threshold, the RO output is a low level (zero level).

[0084] The pulse-per-second single-ended signal optimization shaping circuit mainly includes a Schmitt trigger buffer unit.

[0085] The Schmitt trigger buffer unit converts the level of the CMOS digital signal output by the pulse-per-second receiving circuit into a level signal that matches the input level of the pulse-per-second effective indication circuit, eliminates ringing, noise, slight jitter, etc. on the pulse-per-second single-ended signal, and generates an optimized and shaped pulse-per-second access signal.

[0086] Example

[0087] In this embodiment, if Figure 2 As shown, the pulse-per-second receiving circuit is implemented by the RS-485 transceiver chip (BL1590), which is powered by 3.3V. The pulse-per-second single-ended signal optimization and shaping circuit in the device is implemented by the Schmitt trigger buffer chip (RS1G17). The pulse-per-second valid indication circuit includes two NOT gates, one OR gate, a first counter, a first counter enable unit, and a pulse-per-second valid indication signal output unit. The pulse-per-second valid indication circuit and the pulse-per-second absent indication circuit are both implemented by FPGA. The BL1590 chip receives a pair of differential level signals and outputs a 3.3V level CMOS digital pulse signal. The CMOS level digital pulse signal is a pulse-per-second single-ended signal (RO1). The pulse-per-second single-ended signal (RO1) is optimized and shaped by the Schmitt trigger buffer unit (RS1G17) to generate a pulse-per-second access signal (RO2). RS1G17 is used to eliminate ringing, noise, slight jitter, etc. on the pulse-per-second single-ended signal (RO1) to complete the optimization of the pulse-per-second single-ended signal. When the level of the pulse-per-second single-ended signal (RO1) rises above the upper threshold voltage of 2.1V, the trigger circuit in RS1G17 causes the pulse-per-second access signal (RO2) to change state. When the level of the pulse-per-second single-ended signal (RO1) drops below the lower threshold voltage of 0.45V, the trigger circuit in RS1G17 causes RO2 to change state. As long as the disturbance caused by ringing, noise, and slight jitter causes the level of the pulse-per-second single-ended signal (RO1) to be within the hysteresis voltage range formed by two critical voltages (upper threshold voltage and lower threshold voltage), RS1G17 can avoid false triggering of the circuit caused by disturbance. The pulse-per-second access signal (RO2) is introduced into the FPGA through the IO pin of the FPGA. The global reset signal (RSTn) with a low-level reset valid is also introduced into the FPGA through the IO pin of the FPGA. The local clock clk frequency connected to the FPGA is 125MHz.

[0088] Under ideal conditions without the influence of ringing, noise, jitter, etc., the pulse-per-second single-ended signal (RO1) output by BL1590 and the pulse-per-second access signal (RO2) output by RS1G17 are both unipolar rectangular pulse signals, and the pulse width of the positive pulse in RO2 is 100ms. However, in actual application scenarios, the pulse-per-second access signal (RO2) generated after the pulse-per-second single-ended signal (RO1) is optimized and shaped by RS1G17 may still contain jitter signals that are not eliminated by RS1G17, such as positive pulse jitter signals with a width of about 20μs. Inside the FPGA, the first counter in the pulse-per-second valid indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of the pulse-per-second access signal (RO2). By setting the first threshold, under the action of the pulse-per-second valid indication signal output unit, this embodiment can further eliminate the influence of jitter in the pulse-per-second access signal (RO2) that has a large signal level disturbance but is not eliminated by RS1G17 on the control accuracy. In the second pulse access signal (RO2) output by RS1G17, when the positive pulse width is less than or equal to 20μs, the pulse is considered to be a jitter signal that needs to be eliminated; when the positive pulse width is greater than 20μs, the positive pulse is considered to be a "real" positive pulse. A positive pulse width of 20μs corresponds to 2500 clk clock cycles. The input requirement of the timing interrupt implementation circuit for the high level width of the second pulse valid indication signal (Sp_clr) is 24ns. 24ns corresponds to 3 local clock cycles. Therefore, the first threshold is 2500. Set the second threshold to 2503.

[0089] In this embodiment, the inverted signal (RO3) of the second pulse access signal (RO2) and the inverted signal (RST) of the global reset signal (RSTn) are used as inputs of the OR gate. After the global reset is completed, the first counter actually counts the number of clock cycles corresponding to the positive pulse width of the second pulse access signal (RO2), that is, the number of clock cycles corresponding to the low level (zero level) width of the inverted signal (RO3) of the second pulse access signal (RO2) is counted. The first counter receives the local clock clk as input and receives the output signal (CLR1) of the OR gate as input. The counting bit width of the first counter is set to 12 bits. The output of the first counter is Q1[11:0]. The input of the first counter enable unit is the count value Q1[11:0] of the first counter and the second threshold. The output of the first counter enable unit provides input for the enable signal input terminal of the first counter. The input of the second pulse valid indication signal output unit is the count value Q1[11:0] of the first counter, the first threshold and the second threshold. The output of the second pulse valid indication signal output unit is the pulse valid indication signal (Sp_clr).

[0090] The low level of the second pulse access signal (RO2) corresponds to the high level of the RO3 signal. The high level of the RO3 signal, or the high level of the inverted signal (RST) of the global reset signal (RSTn), clears the first counter. After the global reset is completed, when the second pulse access signal (RO2) is at a low level, the RO3 signal is at a high level, and the clear signal of the first counter is valid. When the clear signal of the first counter is valid, under the beat of the local clock, even if the enable signal of the first counter is allowed to count by adding 1, the count value of the first counter is always 0, and the Sp_clr ​​signal remains at a low level. After the global reset is completed, when the second pulse access signal (RO2) is at a high level, the RO3 signal is at a low level, and the clear signal of the first counter is invalid. When the clear signal of the first counter is invalid and the first counter is allowed to count by adding 1, the first counter is incremented by 1 once at each clk clock beat. The first counter outputs its count value to the first counter enable unit and the second pulse valid indication signal output unit at the same time. The first counter enabling unit compares the first count value with the second threshold value: when the first count value is less than or equal to the second threshold value 2503, the first counter is allowed to count by 1; when the first count value is greater than the second threshold value 2503, the first counter is not allowed to count by 1. The second pulse valid indication signal output unit compares the count value of the first counter with the first threshold value and the second threshold value to determine whether the "real" second pulse is coming, and then determines whether the Sp_clr ​​signal is low or high and the duration of the high level. When the count value of the first counter is less than or equal to 2500, the Sp_clr ​​signal is low. When the count value of the first counter is greater than 2500 and less than or equal to 2503, the Sp_clr ​​signal is high. When the count value of the first counter is greater than 2503, the Sp_clr ​​signal is low. Therefore, the width of the positive pulse in the Sp_clr ​​signal generated by the second pulse valid indication signal output unit in the second pulse valid indication circuit is 24ns.

[0091] In the first application scenario with the influence of ringing, noise and slight jitter, after the second pulse single-ended signal (RO1) is optimized and shaped by the Schmitt trigger buffer unit (RS1G17), a positive pulse with a width of 100ms appears every 1 second on the second pulse access signal (RO2), but a positive pulse jitter signal with a width of 18μs appears 30ns before the positive pulse. After the global reset is completed, before the positive pulse jitter comes, the RO3 signal is high, the CLR1 signal is high, and the count value of the first counter is always 0. When the positive pulse jitter comes, the RO3 signal becomes low, the CLR1 signal becomes low, and the first counter starts counting from zero. When the first count value is less than or equal to 2503, it is always allowed to count by the first counting enable unit. When the first counter counts to 2250, a falling edge appears on the second pulse access signal (RO2), and the positive pulse jitter ends. During the positive pulse of the jitter signal, the count value of the first counter is less than 2500, and it is considered that the "real" second pulse has not arrived, and the Sp_clr ​​signal remains at a low level. Subsequently, the count value of the first counter is cleared due to the low level of the second pulse access signal (RO2), and the Sp_clr ​​signal remains at a low level until the second pulse access signal (RO2) has a positive pulse again. After the positive pulse ends, the first counter starts counting from zero again.

[0092] In the second application scenario without the influence of ringing, noise and slight jitter, after the second pulse single-ended signal (RO1) is optimized and shaped by the Schmitt trigger buffer unit (RS1G17), a positive pulse with a width of 100ms appears every 1 second on the second pulse access signal (RO2). After the global reset is completed, before the positive pulse of the second pulse access signal (RO2) arrives, the RO3 signal is high, the CLR1 signal is high, and the count value of the first counter remains 0. When the positive pulse of the second pulse single-ended signal (RO1) arrives, the RO3 signal becomes low, the CLR1 signal becomes low, and the first counter starts counting from zero under the beat of the local clock. The first count value is always allowed to count by the first count enable unit when it is less than or equal to 2503. When the count value of the first counter is less than 2501, Sp_clr ​​is low. When the count value of the first counter is equal to 2501, it is determined that the "real" second pulse has arrived, and the Sp_clr ​​signal becomes high. When the count value of the first counter is equal to 2501, 2502 or 2503, Sp_clr ​​is at a high level. When the count value of the first counter is greater than 2503, Sp_clr ​​becomes a low level. Therefore, the second pulse valid indication signal output unit in the second pulse valid indication circuit generates a Sp_clr ​​signal with a positive pulse width of 24ns.

[0093] The high level of the pulse valid indication signal (Sp_clr) lasts for 3 local clock cycles, which is 24ns. At a local clock frequency of 125MHz, the count value of the second counter is kept at 0 within the 3 local clock cycles when Sp_clr ​​is at a high level, and it takes exactly 1 second for the second counter to count from 0 to 124999997 after Sp_clr ​​becomes a low level. Therefore, the third threshold is set to 124999997.

[0094] like Figure 3 As shown, the second counter receives the local clock clk input and receives the pulse valid indication signal (Sp_clr) output by the second pulse valid indication circuit as input. The counting bit width of the second counter is set to 27 bits. The output of the second counter is Q2[26:0]. The input of the second counter enable unit is the count value Q2[26:0] of the second counter and the third threshold. The output of the second counter enable unit provides input for the enable signal input terminal of the second counter. The input of the second pulse absence indication signal output unit is the count value Q2[26:0] of the second counter and the third threshold. The output of the second pulse absence indication signal output unit is the pulse absence indication signal (Sp_absent).

[0095] The high level of the pulse valid indication signal (Sp_clr) clears the second counter. When the pulse valid indication signal (Sp_clr) is at a high level, the clear signal of the second counter is valid. When the clear signal of the second counter is valid, under the beat of the local clock, even if the enable signal of the second counter is allowed to count by adding 1, the count value of the second counter is always kept at 0, and the Sp_absent signal remains at a low level. When the pulse valid indication signal (Sp_clr) is at a low level, the clear signal of the second counter is invalid. When the clear signal of the second counter is invalid and the second counter is allowed to count by adding 1, the second counter is incremented once at each clk clock beat. The second counter outputs its count value to the second counter enable unit and the second pulse absence indication signal output unit at the same time. The second counter enable unit compares the second count value with the third threshold value: when the second count value is less than or equal to the third threshold value 124999997, the second counter is allowed to count by adding 1; when the second count value is greater than the third threshold value 124999997, the second counter is not allowed to count by adding 1. The second pulse absence indication signal output unit compares the count value of the second counter with the third threshold value to determine whether the time taken to count from 0 to the current value reaches 1 second, and then determines whether the Sp_absent signal is low or high. When the count value of the second counter is less than 124999997, the Sp_absent signal is low. When the second count value is equal to 124999997, the time taken to count from 0 to the current value reaches 1 second, and the Sp_absent signal is low. When the count value of the second counter is equal to 124999998, it indicates that although the counting time has reached 1 second under the local clock beat, Sp_clr ​​is low, the second counter is not cleared, and Sp_absent is high. If the 1 second of the external clock is exactly equal to the 1 second counted under the local clock beat, then the count value of the second counter reaches 124999997 in the next clock beat, the second pulse valid indication signal (Sp_clr) will become high level to clear the second counter, and Sp_absent will not appear high level. When the 1 second of the external clock is longer than the 1 second under the local clock beat, the positive pulse of the second pulse valid indication signal (Sp_clr) will be "delayed", causing the second pulse absence indication signal (Sp_absent) to remain high for a period of time.

[0096] The second pulse absence indication signal (Sp_absent) and the second pulse valid indication signal (Sp_clr) are used to control the relevant counter (third counter, non Figure 2 and Figure 3When the 1 second counted according to the local clock frequency is shorter than the 1 second count of the external second pulse, the 1 second counted under the local clock beat count has been reached, but the positive pulse of the second pulse valid indication signal (Sp_clr) has not arrived, then the pulse absence indication signal (Sp_absent) changes from low level to high level. When the second pulse absence indication signal (Sp_absent) is at a high level, the related counters, register variables, etc. in the timing interrupt implementation circuit are cleared, and the timing interrupt implementation circuit will not generate an interrupt signal to the CPU at this time. When the positive pulse of the second pulse valid indication signal (Sp_clr) arrives, the high level of the second pulse valid indication signal (Sp_clr) will last for 3 clk cycles, and the Sp_absent signal will also change from high level to low level. The period of time that the Sp_absent signal continues to be at a high level is actually the time that the timing interrupt implementation circuit needs to wait for the positive pulse of the second pulse valid indication signal (Sp_clr) to arrive. By waiting for this period of time, the time point at which the relevant counters, register variables, etc. in the timing interruption implementation circuit are finished being cleared can be synchronized with the positive pulse signal of the relatively delayed second pulse valid indication signal (Sp_clr). When the second pulse absence indication signal (Sp_absent) and the second pulse valid indication signal (Sp_clr) are both at a low level, the clearing of the relevant counters, register variables, etc. in the timing interruption implementation circuit is completed, and the timing interruption implementation circuit can start to generate an interrupt signal according to a certain rule and provide it to the CPU. Therefore, the introduction of the second pulse valid indication signal (Sp_clr) and the second pulse absence indication signal (Sp_absent) enables the timing interruption implementation circuit to avoid the timing problem caused by the mismatch between the local clock accuracy and the time accuracy of the external second pulse signal. At the same time, the second pulse absence indication signal (Sp_absent) is used as one of the clearing signals of the timing interruption implementation circuit to clear the relevant counters, register variables, etc. in the timing interruption implementation circuit, which can effectively prevent the timing interruption implementation circuit from performing unnecessary work and causing no additional hardware overhead.

[0097] On the contrary, there is no waiting for the pulse absence indication signal (Sp_absent) to change from low level to high level and remain at a high level during this period of time. When the 1 second time counted according to the local clock frequency is shorter than the 1 second time of the external second pulse, the timing interrupt implementation circuit calculates that 1 second time has arrived according to the local clock frequency, but the positive pulse of the second pulse valid indication signal (Sp_clr) has not arrived. The timing interrupt implementation circuit will ignore the difference between the local clock accuracy and the external second pulse accuracy, and start to generate interrupt signals according to a certain rule under the local clock beat and provide them to the CPU, resulting in a certain error in the control of the timing interrupt implementation circuit by the external second pulse, which may bring adverse consequences.

[0098] In the application scenario where the 1 second counted according to the local clock frequency is longer than the 1 second counted according to the external second pulse, when the 1 second counted according to the local clock frequency is not reached, the positive pulse of the second pulse valid indication signal (Sp_clr) arrives, and the high level of the second pulse valid indication signal (Sp_clr) will last for 3 clk cycles, and the Sp_absent signal remains at a low level. After the clearing of the relevant counters, register variables, etc. in the timing interrupt implementation circuit brought by the positive pulse of the Sp_clr ​​signal is completed, the timing interrupt implementation circuit begins to generate an interrupt signal according to a certain rule and provides it to the CPU, so that the time point when the relevant counters, register variables, etc. in the timing interrupt implementation circuit end clearing can be synchronized with the relatively advanced positive pulse signal of the second pulse valid indication signal (Sp_clr). Therefore, this embodiment enables the timing interrupt implementation circuit to adapt to the application scenario where the second period of the local clock is longer than the second period of the external second pulse.

[0099] In summary, the control signal for the timing interruption implementation circuit generated by this embodiment enables the timing interruption implementation circuit to adapt to the mismatch between the local clock accuracy and the external clock accuracy, and can avoid the timing problem caused by such mismatch.

[0100] It can be understood that the detailed functional implementation of each of the above-mentioned units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0101] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.

[0102] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0103] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0104] It is understandable that the processor in the embodiment of the present application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0105] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0106] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0107] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0108] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A control signal generation method based on timed interruption of second pulse, characterized in that: include: Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to the first threshold, the second pulse valid indication signal is at a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to the second threshold, the second pulse valid indication signal is at a high level; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is at a low level; Under the beat of the local clock, the number of clock cycles is counted with the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to the third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again. The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interruption implementation circuit to control the timing interruption implementation circuit; Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

2. The control signal generating method according to claim 1, characterized in that: The pulse-per-second differential signal is converted to obtain a pulse-per-second single-ended signal.

3. The control signal generating method according to claim 1, characterized in that: The pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

4. A control signal generating device based on timed interrupt of second pulse, characterized in that: include: A pulse-per-second valid indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of an input unipolar rectangular pulse signal under the beat of a local clock. If the positive pulse width count value is less than or equal to a first threshold, the pulse-per-second valid indication signal is at a low level; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the pulse-per-second valid indication signal is at a high level; if the positive pulse width count value is greater than the second threshold, the pulse-per-second valid indication signal is at a low level; the first threshold is the product of the jitter signal width to be eliminated and the local clock frequency; The second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency; The second pulse absence indication circuit is used to count the number of clock cycles under the beat of the local clock, using the second pulse valid indication signal as the count reset signal. If the count value of the clock cycle number is less than or equal to a third threshold, the second pulse absence indication signal is at a low level. Otherwise, the second pulse absence indication signal is at a high level until the count value of the clock cycle number is reset by the next second pulse valid indication signal, and the second pulse absence indication signal returns to a low level again. The third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

5. The control signal generating device according to claim 4, characterized in that: The second pulse effective indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse effective indication signal output unit; The first counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock; The first counter enabling unit is used to enable counting of the first counter; The pulse-per-second valid indication signal output unit is used to compare the count value of the first counter with the first threshold value and the second threshold value, and generate a pulse-per-second valid indication signal according to the comparison result.

6. The control signal generating device according to claim 4, characterized in that: The first counter enabling unit is used to compare the count value of the first counter with the second threshold, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold.

7. The control signal generating device according to claim 4, characterized in that: The second pulse absence indication circuit comprises: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit; The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the counting value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock with the second pulse valid indication signal as the clearing signal; The second counter enabling unit is used to enable counting of the second counter; The second pulse absence indication signal output unit is used to compare the count value of the second counter with the third threshold value, and generate a second pulse absence indication signal according to the comparison result.

8. The control signal generating device according to claim 4, characterized in that: The second counter enabling unit is used to compare the count value of the second counter with a third threshold value, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold value.

9. The control signal generating device according to claim 4, characterized in that: Also includes: A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal; The pulse-per-second single-ended signal optimization and shaping circuit is used to optimize and shape the pulse-per-second single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the pulse-per-second single-ended signal, and generate an optimized and shaped pulse-per-second access signal.

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