Power supply management circuit, management method thereof and embedded system

Abstract

The invention relates to the technical field of embedded systems, and discloses a power supply management circuit, a management method thereof and an embedded system, and the power supply management circuit comprises a single-chip microcomputer, a main control chip, a primary power supply management module and a switch module. The management method is applied to a single-chip microcomputer and comprises the following steps: when a board-level power supply is switched on, enabling a switch module to be in a cut-off state according to a first state of an enabling control end, enabling the enabling of a primary power supply management module to be effective, and reducing the voltage of the board-level power supply into a primary power supply; the enabling control end is controlled to be in a second state, so that the switch module is continuously in a cut-off state, and enabling of the first-stage power management module is kept effective; a reset signal is output to the main control chip, so that the main control chip works normally; and the processor is used for receiving the pulse signal of the main control chip, judging the working state of the main control chip according to the detection result of the pulse signal, and determining whether the enabling of the primary power management module is invalid or not. According to the invention, the master control chip with disordered functions can be recovered to be normal, and the reliability of the embedded system is improved.

Description

Technical Field

[0001] The present application relates to the technical field of embedded systems, and in particular to a power supply management circuit and a management method thereof, and an embedded system. Background Art

[0002] Embedded systems, composed of hardware and software that work together to perform specific functions, have been widely used in various industries across national production. Some application scenarios require complex embedded system functions, necessitating the use of highly integrated master control chips. Highly integrated chips feature advanced technology, abundant on-chip resources, and complex power supply branches, which increases the risk of interference with the chip. For example, problems such as abnormal power supply in any branch of the chip, electrostatic interference, and latch-up effects can disrupt chip functionality or even cause the chip to fail, thereby locking up the entire embedded system. Improving the reliability of complex embedded systems is a critical issue we need to address, especially in harsh industrial environments where complex embedded systems are prone to lockup, such as unstable power supplies, severe electromagnetic interference, and severe mechanical vibration. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a power supply management circuit, a management method thereof, and an embedded system, which can effectively restore a main control chip with chaotic functions to normal, prevent the embedded system from being locked, and thus improve the reliability of the embedded system.

[0004] In a first aspect, an embodiment of the present application provides a management method for a power management circuit, wherein the power management circuit includes a single-chip microcomputer, a main control chip, a primary power management module, and a switch module; the management method is applied to the single-chip microcomputer, including:

[0005] When the board-level power supply is turned on, the switch module is in a cut-off state according to the first state of the enable control terminal of the single-chip microcomputer, so that the enable of the first-level power management module is effective, and the board-level power supply is stepped down to a first-level power supply, and the first-level power supply is used as a second-level power supply for multiple subsequent power supplies;

[0006] Controlling the enable control terminal to be in a second state so that the switch module is continuously in a cut-off state and the enable of the primary power management module is kept valid;

[0007] Outputting a reset signal to the main control chip to put the main control chip into a normal working state;

[0008] A pulse signal sent by the main control chip is received, and according to a detection result of the pulse signal, a working state of the main control chip is judged to determine whether to disable the enabling of the first-level power management module.

[0009] In a first possible embodiment of the first aspect, the further comprising:

[0010] If it is determined that the main control chip cannot work normally, the enable control terminal is controlled to be in the third state, so that the switch module is in the on state, so as to invalidate the enable of the first-level power management module and make the first-level power supply have no output;

[0011] The enable control terminal is placed in the first state to control the switch module to be in the cut-off state again, so that the primary power supply is output again.

[0012] In a second possible embodiment of the first aspect, judging the working state of the main control chip according to the detection result of the pulse signal includes:

[0013] If the periodic pulse signal is detected, it is determined that the main control chip is in a normal working state;

[0014] If the periodic pulse signal is not detected, it is determined that the main control chip is not in a normal working state.

[0015] In a third possible embodiment of the first aspect, the first state of the enable control terminal is a high-impedance state; the second state of the enable control terminal is to output a level signal of a first level state; and the third state of the enable control terminal is to output a level signal of a second level state.

[0016] In a second aspect, an embodiment of the present application provides a power supply management circuit, including a single-chip microcomputer, a main control chip, a first-level power management module and a switch module, and the single-chip microcomputer adopts the management method described above.

[0017] In a first possible embodiment of the second aspect, the switching module includes a current limiting resistor and a switching tube, the first end of the current limiting resistor is connected to the output end of the first-level power management module, and the second end of the current limiting resistor is connected to the switching tube; the switching tube is a photoelectric coupling chip, a transistor or a field effect tube.

[0018] In a second possible embodiment of the second aspect, the single-chip microcomputer includes a power enable control pin, a hardware reset pin, and a diagnostic input pin;

[0019] The power enable control pin is used to connect the first input end of the optocoupler chip, the base of the transistor or the gate of the field effect transistor, the hardware reset pin and the diagnostic input pin are respectively used to connect the main control chip, and the single-chip microcomputer is connected to the output end of the primary power management module.

[0020] In a third possible embodiment of the second aspect, when the switching tube is the optocoupler chip, a first input end of the optocoupler chip is connected to a power enable control pin of the single-chip microcomputer, a second input end of the optocoupler chip is connected to the second end of the current-limiting resistor, a first output end of the optocoupler chip is connected to the enable pin of the primary power management module, and a second output end of the optocoupler chip is grounded;

[0021] When the switch tube is the triode, the base of the triode is respectively connected to the second end of the current limiting resistor and the power enable control pin of the single chip microcomputer, the collector of the triode is connected to the enable pin of the primary power management module, and the emitter of the triode is grounded;

[0022] When the switching tube is the field effect tube, the gate of the field effect tube is respectively connected to the second end of the current limiting resistor and the power enable control pin of the microcontroller, the drain of the field effect tube is connected to the enable pin of the first-level power management module, and the source of the field effect tube is grounded.

[0023] In a fourth possible embodiment of the second aspect, the primary power management module includes a pull-up resistor, an input capacitor, a DC-DC chip, a bootstrap capacitor, an inductor, a first feedback resistor, a second feedback resistor, and an output capacitor;

[0024] The first end of the pull-up resistor is connected to the board-level power supply, the second end of the pull-up resistor is connected to the enable pins of the switch module and the DC-DC chip respectively, the first end of the input capacitor is connected to the board-level power supply, and the second end of the input capacitor is grounded;

[0025] An input voltage pin of the DC-DC chip is connected to the board-level power supply, an output voltage pin of the DC-DC chip is connected to a first end of the inductor, a second end of the inductor is connected to a first end of the first feedback resistor, a second end of the first feedback resistor is connected to a first end of the second feedback resistor, and a second end of the second feedback resistor is grounded;

[0026] The feedback pin of the DC-DC chip is connected to the series node of the first feedback resistor and the second feedback resistor, the output voltage pin and the start pin of the DC-DC chip are connected in parallel with the bootstrap capacitor, and the ground pin of the DC-DC chip is grounded;

[0027] A first end of the output capacitor is connected to a series node of the inductor and the first feedback resistor and a primary power supply, respectively, and a second end of the output capacitor is grounded.

[0028] In a third aspect, an embodiment of the present application provides an embedded system, comprising the power supply management circuit described above.

[0029] The embodiments of the present application have the following beneficial effects:

[0030] The present embodiment provides a management method for a power supply management circuit, wherein the power supply management circuit includes a single-chip microcomputer, a main control chip, a first-level power management module and a switch module; the management method is applied to the single-chip microcomputer, including: when the board-level power supply is turned on, according to the first state of the enable control terminal of the single-chip microcomputer, the switch module is in a cut-off state, so that the enable of the first-level power management module is effective, and the board-level power supply is reduced to a first-level power supply, and the first-level power supply is used as a second-level power supply for multiple subsequent power supplies; the enable control terminal is controlled to be in a second state, so that the switch module is continuously in a cut-off state, and the enable of the first-level power management module is kept effective; a reset signal is output to the main control chip, so that the main control chip enters a normal working state; a pulse signal sent by the main control chip is received, and according to the detection result of the pulse signal, the working state of the main control chip is judged to determine whether to invalidate the enable of the first-level power management module. Based on the above scheme, the present application uses a single-chip microcomputer to detect the pulse signal periodically output by the main control chip to determine whether the main control chip is locked. If locked, the board-level power supply is cut off by prohibiting the output of the first-level power supply, and the main control chip is powered on again. This management method can effectively restore the main control chip from functional confusion or even malfunction caused by interference such as abnormal branch power supply, static electricity, and latch-up effects, preventing the embedded system from locking up, thereby improving the reliability of the embedded system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic structural diagram of a power supply management circuit according to an embodiment of the present application is shown;

[0033] Figure 2 A power supply branch and power-on timing diagram of the main control chip in an embodiment of the present application are shown;

[0034] Figure 3 A circuit diagram of a power supply management circuit according to an embodiment of the present application is shown;

[0035] Figure 4 A flow chart of a management method of a power supply management circuit according to an embodiment of the present application is shown.

[0036] Description of main component symbols:

[0037] 100 - power supply management circuit; 110 - single chip microcomputer; 120 - main control chip; 130 - first level power management module; 140 - switch module. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0039] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0040] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0042] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0043] Typically, a reset chip with a watchdog function is used to ensure stable operation of an embedded system. The reset chip's reset output is connected to the hardware reset pin of the main control chip, while the watchdog input is connected to a general-purpose input / output (GPIO) port on the main control chip. The watchdog output can be connected to a non-maskable interrupt input pin on the main control chip or to the reset chip's manual reset input. During normal operation of the embedded system, the main control chip, in a pre-set program, periodically sends a pulse signal to the reset chip's watchdog input via its output port. If the watchdog input fails to detect a pulse signal within a predetermined time period, the watchdog determines that the embedded system has failed. In this case, the watchdog output sends a non-maskable interrupt signal to the main control chip. The main control chip then performs a software reset by reading and writing a reset register in its interrupt service routine. Alternatively, the watchdog output triggers the reset chip's manual reset input, causing the reset chip's reset output to provide a hardware reset pulse to the main control chip, restoring normal operation.

[0044] However, in some cases, if the main control chip is locked, it will directly cause the main control chip to be unable to read and write registers normally and cannot correctly judge the level of the hardware reset pin. At this time, whether it is a software reset or a hardware reset, it will not be able to restore the main control chip to normal working state. In this case, a more complex recovery strategy is required.

[0045] This application uses a single-chip microcomputer to control the enabling of the primary power management system, enabling the primary power output, which then serves as the secondary power supply for the subsequent power supply. This application also uses the single-chip microcomputer to manage the hardware reset of the main control chip and detect whether the embedded system is operating normally. If the single-chip microcomputer detects an abnormality in the main control chip, it disables the output of the primary power supply. This application also uses the single-chip microcomputer to enable the embedded system to power on again, restoring the normal operating state of the main control chip.

[0046] Before describing the management method of the power supply management circuit, the structures of the embedded system and the power supply management circuit are first introduced accordingly.

[0047] Please refer to Figure 1, is a structural diagram of the power supply management circuit 100 proposed in an embodiment of the present application. Exemplarily, the embedded system includes a power supply management circuit 100, which includes a single-chip microcomputer 110, a main control chip 120, a first-level power management module 130 and a switch module 140; the first-level power management module 130 is used to connect to the board-level power supply Vin, and to reduce the voltage of the board-level power supply Vin to obtain a first-level power supply, which can be used as a second-level power supply for multiple subsequent power supplies. The single-chip microcomputer 110, the switch module 140 and the first-level power management module 130 are connected in sequence, and the single-chip microcomputer 110 is used to enable or disable the first-level power management module 130 by controlling the cutoff or conduction of the switch module 140, thereby controlling the output of the first-level power supply or prohibiting the output of the first-level power supply. The single-chip microcomputer 110 is also connected to the main control chip 120 and is used to receive the pulse signal sent by the main control chip 120. The single-chip microcomputer 110 is also used to detect the periodic pulse signal, determine whether the main control chip 120 is abnormal, and control the main control chip 120 to power on again when the main control chip 120 is abnormal, so that the main control chip 120 returns to normal.

[0048] Alternatively, as Figure 2 As shown, the embedded system is powered by the board-level power supply Vin input, and the main control chip 120 is powered by a two-stage power supply, which includes a primary power supply and multiple subsequent power supplies; wherein, the primary power supply is obtained by reducing the voltage of the board-level power supply Vin through the primary power management module 130, and the primary power supply can also be reduced to different degrees to obtain multiple subsequent power supplies of different voltage sizes.

[0049] like Figure 3 As shown, in one embodiment, the microcontroller 110 includes a power enable control pin GPIO1, a hardware reset pin GPIO2, and a diagnostic input pin GPIO3; the power enable control pin GPIO1 is used to connect to the first input end of the optocoupler chip U2, the base of the transistor or the gate of the field effect transistor, the hardware reset pin GPIO2 and the diagnostic input pin GPIO3 are respectively used to connect to the main control chip 120, and the microcontroller 110 is connected to the output end of the first-level power management module 130.

[0050] Exemplarily, the power enable control pin GPIO1 of the microcontroller 110 is connected to the switch module 140 to control the on and off state of the switch module 140. The hardware reset pin GPIO2 of the microcontroller 110 is connected to the hardware terminal of the main control chip 120. When the embedded system completes all power supply voltages, the hardware reset pin GPIO2 of the microcontroller 110 outputs a reset signal to the main control chip 120, causing the embedded system to complete the reset and enter normal operation. The diagnostic input pin GPIO3 of the microcontroller 110 is connected to the timing pulse output pin of the main control chip 120 to receive the periodic pulse signal output by the main control chip 120.

[0051] In one embodiment, Figure 3 As shown, the switch module 140 includes a current limiting resistor R1 and a switch tube. The first end of the current limiting resistor R1 is connected to the output end of the first-level power management module 130, and the second end of the current limiting resistor R1 is connected to the switch tube; the switch tube is a photoelectric coupling chip, a transistor or a field effect tube.

[0052] For example, the optocoupler chip U2 can be replaced by a transistor or a field-effect transistor. The second input terminal of the optocoupler chip U2 can correspond to the base of the transistor or the gate of the field-effect transistor. The first output terminal of the optocoupler chip U2 can correspond to the collector of the transistor or the drain of the field-effect transistor. The second output terminal of the optocoupler chip U2 can correspond to the emitter of the transistor or the source of the field-effect transistor. The transistor, field-effect transistor, and optocoupler chip U2 can achieve the same effect.

[0053] For example, in one embodiment, Figure 3 As shown, when the switch tube is a photoelectric coupling chip U2, the first input terminal of the photoelectric coupling chip U2 is connected to the power enable control pin GPIO1 of the single-chip microcomputer 110, the second input terminal of the photoelectric coupling chip U2 is connected to the second end of the current limiting resistor R1, the first output terminal of the photoelectric coupling chip U2 is connected to the enable pin of the first-level power management module 130, and the second output terminal of the photoelectric coupling chip U2 is grounded GND. It can be understood that Figure 3 The switching tube shown as the optocoupler chip U2 is only an example, and the switching tube is not limited to the optocoupler chip U2.

[0054] For example, in one embodiment, when the switching tube is a transistor, the base of the transistor is respectively connected to the second end of the current limiting resistor R1 and the power enable control pin GPIO1 of the microcontroller 110, the collector of the transistor is connected to the enable pin of the first-level power management module 130, and the emitter of the transistor is grounded.

[0055] For example, in one embodiment, when the switching tube is a field-effect tube, the gate of the field-effect tube is respectively connected to the second end of the current-limiting resistor R1 and the power enable control pin GPIO1 of the microcontroller 110, the drain of the field-effect tube is connected to the enable pin of the first-level power management module 130, and the source of the field-effect tube is grounded GND.

[0056] In one embodiment, Figure 3As shown, the first-level power management module 130 includes a pull-up resistor R2, an input capacitor C1, a DC-DC chip U1, a bootstrap capacitor C2, an inductor L1, a first feedback resistor R3, a second feedback resistor R4 and an output capacitor C3; the first end of the pull-up resistor R2 is connected to the board-level power supply, the second end of the pull-up resistor R2 is connected to the enable pin EN of the switch module 140 and the DC-DC chip U1 respectively, the first end of the input capacitor C1 is connected to the board-level power supply Vin, and the second end of the input capacitor C1 is grounded; the input voltage pin VIN of the DC-DC chip U1 is connected to the board-level power supply Vin, and the output voltage pin SW of the DC-DC chip U1 is connected The first end of the inductor L1 and the second end of the inductor L1 are connected to the first end of the first feedback resistor R3, the second end of the first feedback resistor R3 is connected to the first end of the second feedback resistor R4, and the second end of the second feedback resistor R4 is grounded; the feedback pin FB of the DC-DC chip U1 is connected to the series node of the first feedback resistor R3 and the second feedback resistor R4, the output voltage pin and the start pin of the DC-DC chip U1 are connected in parallel with the bootstrap capacitor C2, and the ground pin of the DC-DC chip U1 is grounded GND; the first end of the output capacitor C3 is respectively connected to the series node of the inductor L1 and the first feedback resistor R3 and the primary power supply, and the second end of the output capacitor C3 is grounded.

[0057] The management method of the power supply management circuit 100 of the present application is described in detail below in conjunction with the above circuit structure.

[0058] Please refer to Figure 4 , is a flow chart of a management method of the power supply management circuit 100 proposed in an embodiment of the present application. Exemplarily, the management method is applied to the single-chip microcomputer 110, and the management method includes the following steps:

[0059] S210, when the board-level power supply Vin is turned on, the switch module 140 is in the cut-off state according to the first state of the enable control terminal of the single-chip microcomputer 110, so that the enable of the first-level power management module 130 is effective, and the board-level power supply Vin is stepped down to a first-level power supply, which is used as a second-level power supply for multiple subsequent power supplies.

[0060] Exemplarily, when the primary power supply is not output, the single-chip microcomputer 110 is not powered on. At this time, the power enable control pin GPIO1 of the enable control end of the single-chip microcomputer 110 is in a high-impedance state, so that the switch module 140 is in a cut-off state. When the board-level power supply Vin is connected, the primary power management module 130 can be enabled to be effective, and the board-level power supply Vin is stepped down to obtain the primary power supply.

[0061] S220 , controlling the enable control terminal to be in the second state, so that the switch module 140 is continuously in the cut-off state, and the enable of the first-level power management module 130 is kept valid.

[0062] For example, when the primary power supply is output, the microcontroller 110 is powered on. The microcontroller 110 controls the enable control terminal to output a first-level signal, turning off the switch module 140. This enables the primary power management module 130, ensuring continuous output of the primary power supply. Simultaneously, the primary power supply can be further stepped down to produce multiple subsequent power supplies of varying magnitudes. When all subsequent power supplies are output, the embedded system is powered on.

[0063] S230 , outputting a reset signal to the main control chip 120 , so that the main control chip 120 enters a normal working state.

[0064] Exemplarily, the single chip microcomputer 110 outputs a reset signal to the main control chip 120 by setting the state of the hardware reset pin GPIO2 to control the reset of the main control chip 120, thereby completing the reset of the entire embedded system.

[0065] S240 , receiving the pulse signal sent by the main control chip 120 , and judging the working state of the main control chip 120 according to the detection result of the pulse signal, and determining whether to disable the enabling of the first-level power management module 130 .

[0066] Exemplarily, after the main control chip 120 completes the reset, it is programmed to periodically output a pulse signal through the timing pulse output pin. The pulse signal is received and detected by the diagnostic input pin GPIO3 of the microcontroller 110. If the microcontroller 110 detects the pulse signal within this period, it is determined that the main control chip 120 is operating normally. If the microcontroller 110 does not detect the pulse signal within this period, it is determined that the main control chip 120 is operating abnormally.

[0067] For example, in one embodiment, the single-chip microcomputer 110 determines the working status of the main control chip 120 based on the detection result of the pulse signal, including: if a periodic pulse signal is detected, it is determined that the main control chip 120 is in a normal working state; if no periodic pulse signal is detected, it is determined that the main control chip 120 is not in a normal working state.

[0068] For example, when the main control chip 120 malfunctions, the power enable control pin GPIO1 of the microcontroller 110's enable control terminal outputs a second-level signal, thereby disabling the first-stage power supply. Once the first-stage power supply is disabled, all subsequent power supplies are then further disabled, effectively powering off the entire embedded system. At this point, the microcontroller 110 is powered off, and the power enable control pin GPIO1 of the microcontroller 110 enters a high-impedance state. The first-stage power management module 130 is enabled, and the first-stage power supply resumes output. After the first-stage power supply is reduced in voltage, the subsequent power supplies are enabled, thereby powering the embedded system back on.

[0069] For example, in one embodiment, the management method further includes the following steps: if it is determined that the main control chip 120 cannot work normally, the enable control terminal is controlled to be in the third state, so that the switch module 140 is in the on state, so that the enable of the first-level power management module 130 is invalid, so that the first-level power supply has no output; the enable control terminal is placed in the first state to control the switch module 140 to be in the off state again, so that the first-level power supply is output again.

[0070] For example, in one embodiment, the first state of the enable control terminal is a high impedance state; the second state of the enable control terminal is to output a level signal of a first level state; and the third state of the enable control terminal is to output a level signal of a second level state.

[0071] It is understood that factors such as abnormal branch power supply, electrostatic interference, and latch-up can cause the main control chip 120 to become malfunctioning or even inoperable, thereby locking up the entire embedded system. Such faults can be recovered by powering on again. The above management method can resolve embedded system lockups caused by malfunction or complete failure of the main control chip 120, allowing the embedded system to resume normal operation and significantly improving the reliability of the embedded system in harsh environments.

[0072] The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of the present application.

Claims

1. A management method for a power supply management circuit, It is characterized in that The power supply management circuit includes a single chip microcomputer, a main control chip, a primary power management module and a switch module; The management method is applied to a single chip microcomputer and includes: When the board-level power supply is turned on, the switch module is in a cut-off state according to the first state of the enable control terminal of the single-chip microcomputer, so that the enable of the primary power management module is effective, and the board-level power supply is stepped down to a primary power supply, and the primary power supply is used as a secondary power supply for multiple subsequent power supplies; Controlling the enable control terminal to be in a second state, so that the switch module is continuously in a cut-off state, and keeping the enable of the primary power management module valid; Outputting a reset signal to the main control chip to enable the main control chip to enter a normal working state; A pulse signal sent by the main control chip is received, and according to a detection result of the pulse signal, a working state of the main control chip is judged to determine whether to invalidate the enabling of the primary power management module.

2. The management method of the power supply management circuit according to claim 1, It is characterized in that Also includes: If it is determined that the main control chip cannot work normally, the enable control terminal is controlled to be in the third state, so that the switch module is in the on state, so that the enable of the primary power management module is invalid, so that the primary power supply has no output; The enable control terminal is placed in the first state to control the switch module to be in the cut-off state again, so that the primary power supply is output again.

3. The management method of the power supply management circuit according to claim 1, It is characterized in that The step of judging the working state of the main control chip according to the detection result of the pulse signal includes: If the periodic pulse signal is detected, it is determined that the main control chip is in a normal working state; If the periodic pulse signal is not detected, it is determined that the main control chip is not in a normal working state.

4. The management method of the power supply management circuit according to claim 1, It is characterized in that Also includes: The first state of the enable control terminal is a high impedance state; the second state of the enable control terminal is to output a level signal of a first level state; The third state of the enable control terminal is to output a level signal of the second level state.

5. A power supply management circuit, It is characterized in that It comprises a single chip microcomputer, a main control chip, a primary power management module and a switch module, and the single chip microcomputer adopts the management method as claimed in any one of claims 1 to 4.

6. The power supply management circuit according to claim 5, It is characterized in that The switch module includes a current limiting resistor and a switch tube, wherein the first end of the current limiting resistor is connected to the output end of the primary power management module, and the second end of the current limiting resistor is connected to the switch tube; the switch tube is a photoelectric coupling chip, a triode or a field effect tube.

7. The power supply management circuit according to claim 6, It is characterized in that The single chip microcomputer includes a power enable control pin, a hardware reset pin and a diagnostic input pin; The power enable control pin is used to connect the first input end of the photoelectric coupling chip, the base of the transistor or the gate of the field effect transistor, the hardware reset pin and the diagnostic input pin are respectively used to connect the main control chip, and the single-chip microcomputer is connected to the output end of the primary power management module.

8. The power supply management circuit according to claim 6, It is characterized in that When the switch tube is the photoelectric coupling chip, the first input end of the photoelectric coupling chip is connected to the power enable control pin of the single-chip microcomputer, the second input end of the photoelectric coupling chip is connected to the second end of the current limiting resistor, the first output end of the photoelectric coupling chip is connected to the enable pin of the primary power management module, and the second output end of the photoelectric coupling chip is grounded; When the switch tube is the triode, the base of the triode is respectively connected to the second end of the current limiting resistor and the power enable control pin of the single chip microcomputer, the collector of the triode is connected to the enable pin of the primary power management module, and the emitter of the triode is grounded; When the switching tube is the field effect tube, the gate of the field effect tube is respectively connected to the second end of the current limiting resistor and the power enable control pin of the single chip microcomputer, the drain of the field effect tube is connected to the enable pin of the primary power management module, and the source of the field effect tube is grounded.

9. The power supply management circuit according to claim 5, It is characterized in that The primary power management module includes a pull-up resistor, an input capacitor, a DC-DC chip, a bootstrap capacitor, an inductor, a first feedback resistor, a second feedback resistor and an output capacitor; The first end of the pull-up resistor is connected to the board-level power supply, the second end of the pull-up resistor is respectively connected to the switch module and the enable pin of the DC-DC chip, the first end of the input capacitor is connected to the board-level power supply, and the second end of the input capacitor is grounded; The input voltage pin of the DC-DC chip is connected to the board-level power supply, the output voltage pin of the DC-DC chip is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the first feedback resistor, the second end of the first feedback resistor is connected to the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded; The feedback pin of the DC-DC chip is connected to the series node of the first feedback resistor and the second feedback resistor, the output voltage pin and the start pin of the DC-DC chip are connected in parallel with the bootstrap capacitor, and the ground pin of the DC-DC chip is grounded; The first end of the output capacitor is respectively connected to the series node of the inductor and the first feedback resistor and a primary power supply, and the second end of the output capacitor is grounded.

10. An embedded system, It is characterized in that The method comprises a power supply management circuit as claimed in any one of claims 5 to 9.

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