Data storage device and non-volatile memory control method

Abstract

The invention relates to a data storage device adaptively adjusted according to sensing temperature and a non-volatile memory control method. The data storage device is provided with a first clock pulse generator and a second clock pulse generator which respectively generate a first clock pulse and a second clock pulse which are selected by a controller to operate a non-volatile memory. The frequency of the second clock pulse is lower than that of the first clock pulse. When the sensed temperature does not exceed a first critical temperature, the controller selects the first clock pulse to operate the non-volatile memory, and when the sensed temperature exceeds the first critical temperature, the controller alternately selects the first clock pulse and the second clock pulse to operate the non-volatile memory.

Description

Technical Field

[0001] The invention relates to a control technology of a non-volatile memory. Background Art

[0002] There are many forms of non-volatile memory, such as flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, spin transfer torque RAM (STT-RAM), etc., which are used for long-term data storage and can be used as storage media to implement a data storage device.

[0003] How to efficiently control non-volatile memory is an important issue in the technical field. Summary of the invention

[0004] The present invention controls the non-volatile memory in an adaptive manner according to the sensed temperature.

[0005] A data storage device implemented according to one embodiment of the present invention includes a non-volatile memory, a controller, a first clock generator, and a second clock generator. The controller is coupled to the non-volatile memory and is constructed to operate the non-volatile memory in response to host requirements. The first clock generator and the second clock generator respectively generate a first clock and a second clock for the controller to select to operate the non-volatile memory. When a sensed temperature does not exceed a first critical temperature, the controller selects the first clock to operate the non-volatile memory. When the sensed temperature exceeds the first critical temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.

[0006] The above concepts are further used to implement a control method of a non-volatile memory.

[0007] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A data storage device 100 according to one embodiment of the present invention is illustrated;

[0009] Figure 2 A graphical representation of the timing of the adaptive cooling strategy, showing how the adaptive cooling strategy is fine-tuned under various temperature conditions;

[0010] Figure 3 An embodiment of the temperature modulation control of the present invention is illustrated; and

[0011] Figure 4 According to one embodiment of the present invention, temperature control of the data storage device 100 is illustrated.

[0012]

Explanation of symbols

[0013] 100: Data storage device

[0014] 102: Flash memory

[0015] 104: Controller

[0016] 106: First clock generator

[0017] 108: Second clock generator

[0018] 110: Multiplexer

[0019] 112: Host side

[0020] 114: Signal for enabling / disabling the first clock generator 106

[0021] CD1…CD4, DT1…DT3: Value

[0022] Clk, Clk1, Clk2: clock

[0023] S402…S414: Steps

[0024] Sc: Cooling state

[0025] Sel: Select signal

[0026] St: Normal transmission status

[0027] TMTU, TM_L, TM_H: first, second, third critical temperature

[0028] Ts: Sensing temperature

[0029] ΔT: Temperature difference DETAILED DESCRIPTION

[0030] The following description lists various embodiments of the present invention to introduce the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims. The various functional blocks mentioned below can be implemented by a combination of hardware, software, and firmware, and can also include special circuits. The various functional blocks are not limited to being implemented separately, but can also be combined together to share certain functions.

[0031] Non-volatile memory can be Flash Memory, Magnetoresistive RAM, Ferroelectric RAM, Resistive RAM (RRAM), Spin Transfer Torque RAM (STT-RAM), etc., which provide storage media for long-term data preservation. The following discussion specifically takes Flash Memory as an example, but the technology described can also be used on other types of non-volatile memory.

[0032] Nowadays, data storage devices often use flash memory as storage media to realize products such as memory cards, USB flash devices, solid-state drives (SSDs), etc. One application is to use multi-chip packaging to package flash memory and its controller together, which is called an embedded flash memory module (such as eMMC).

[0033] Data storage devices using flash memory as storage media can be applied to a variety of electronic devices, including smart phones, wearable devices, tablet computers, virtual reality devices, etc. The processor of the electronic device can be regarded as a host, operating the data storage device configured in the electronic device to access the flash memory therein.

[0034] Data storage devices using flash memory as storage media can also be used to build data centers. For example, servers can operate solid-state drive (SSD) arrays to form data centers. The server can be regarded as a host and operate the connected solid-state drive to access the flash memory therein.

[0035] The vehicle-mounted system can also use flash memory to implement data storage devices. Various sensors in the vehicle-mounted system can be regarded as hosts and have the need to access flash memory.

[0036] As technology advances, flash memory is getting smaller and smaller, faster and faster, and the temperature is also prone to overheating. For example, the Secure Digital Card (SD) Association has proposed a variety of specifications (such as SD Express Card, Macro SD Express Card) to implement small memory devices, using a high-speed peripheral component interconnect (PCIe) interface for high-speed data transmission, but it also has to face the problem of heat energy. The present invention controls the flash memory adaptively based on the sensed temperature, effectively reducing the temperature while taking into account performance.

[0037] Figure 1A data storage device 100 implemented according to an embodiment of the present invention is illustrated, comprising a flash memory 102, a controller 104, a first clock generator (e.g., a phase locked loop circuit, English phase locked loop, abbreviated PLL) 106, a second clock generator (e.g., an oscillator, such as a quartz oscillator) 108, and a multiplexer 110. The controller 104 is coupled to the flash memory 102, and is configured to operate the flash memory 102 in response to a request from a host 112. The first clock generator 106 and the second clock generator 108 respectively generate a first clock Clk1 and a second clock Clk2, which are used by the controller 104 to switch the multiplexer 110 to select (Clk) to operate the flash memory 102 with a selection signal Sel. The frequency of the second clock Clk2 is lower than that of the first clock Clk1; for example, the first clock Clk1 may be as high as 1000 MHz or more, while the second clock Clk2 may be only tens of MHz. The controller 104 can disable the first clock generator 106 through a signal 114 according to a sensed temperature Ts, for example, stopping the high-speed operation of the phase-locked loop (PLL), thereby achieving a cooling effect. At this time, the controller 104 selects the low-speed second clock Clk2 (for example, an oscillation signal generated by an oscillator) generated by the second clock generator 108, so that it can be awakened at any time to cope with interrupt requests (interrupts) from the host end 112.

[0038] The present invention proposes an adaptive cooling strategy. In one embodiment, when the sensed temperature Ts does not exceed a first critical temperature (hereinafter referred to as TMTU), the controller 104 selects the first clock Clk1 to operate the flash memory 102. When the sensed temperature Ts exceeds the first critical temperature TMTU, the controller 104 alternately selects the first clock Clk1 and the second clock Clk2 to operate the non-volatile memory.

[0039] When the controller 104 enables the first clock generator 106, the first clock Clk1 is selected to operate the flash memory 102 to respond to the access request of the host end 112; this state is called the normal transmission state (hereinafter indicated by St). When the controller 104 disables the first clock generator 106, the second clock Clk2 is selected to operate the non-volatile memory 102 in standby mode; this state is called the cooling state (hereinafter indicated by Sc). In one embodiment, when the sensed temperature Ts exceeds the first critical temperature TMTU, the controller 104 activates an adaptive cooling strategy: cyclically enabling and disabling the first clock generator 106, repeatedly switching between the normal transmission state St and the cooling state Sc. This design can effectively reduce the temperature without excessively lowering the device performance.

[0040] Figure 2 The timing diagram of the adaptive cooling strategy is shown, which shows how the adaptive cooling strategy is fine-tuned under various temperature conditions. Once the sensed temperature Ts exceeds the first critical temperature TMTU, the controller 104 implements the adaptive cooling strategy, repeatedly switching between the normal transmission state St and the cooling state Sc. In particular, the illustrated embodiment further shows that as the magnitude of the sensed temperature Ts exceeding the first critical temperature TMTU increases, the controller 104 enables the first clock generator 106 for a longer time length.

[0041] In the figure, DT1, DT2, and DT3 are numerical values representing temperature differences, CD1, CD2, CD3, and CD4 are numerical values for time ratios, and CD1 < CD2 < CD3 < CD4. When the temperature difference ΔT by which the sensed temperature Ts exceeds the first critical temperature TMTU is less than DT1 degrees, the controller 104 repeatedly enables (St) and disables (Sc) the first clock generator 106 at a time ratio of 1:CD1. When the temperature difference ΔT reaches DT1 degrees but is less than DT2 degrees, the controller 104 repeatedly enables (St) and disables (Sc) the first clock generator 106 at a time ratio of 1:CD2. When the temperature difference ΔT reaches DT2 degrees but is less than DT3 degrees, the controller 104 repeatedly enables (St) and disables (Sc) the first clock generator 106 at a time ratio of 1:CD3. After the temperature difference ΔT reaches DT3 degrees, the controller 104 repeatedly enables (St) and disables (Sc) the first clock generator 106 at a time ratio of 1:CD4. For example, let DT1 be 5, DT2 be 10, and DT3 be 15, and let CD1 be 2, CD2 be 4, CD3 be 6, and CD4 be 8. The figure shows that the adaptive cooling strategy is divided into four-stage control. Other embodiments may adopt other numbers of stages.

[0042] In summary, when the sensed temperature Ts exceeds the first critical temperature TMTU, the controller 104 adjusts a selected time ratio of the first clock Clk1 and the second clock Clk2 according to the magnitude of the sensed temperature Ts exceeding the first critical temperature TMTU.

[0043] In one embodiment, when the sensed temperature Ts does not exceed the first critical temperature TMTU, the controller 104 down-clocks the flash memory 102 based on the first clock Clk1 generated by the enabled first clock generator 106. The down-clocking is different from the standby operation of the aforementioned second clock Clk2, but rather accesses the flash memory 102 required by the host 112 at a lower frequency.

[0044] In one embodiment, as the sensed temperature Ts approaches the first critical temperature TMTU, the controller 104 increasingly reduces the operating frequency of the flash memory 102.

[0045] Figure 3 FIG. 1 illustrates an embodiment of the temperature modulation control of the present invention. In addition to the first critical temperature TMTU for initiating the adaptive cooling strategy described above, this example further provides a second critical temperature TM_L and a third critical temperature TM_H; TM_L < TM_H < TMTU. When the sensed temperature Ts exceeds the second critical temperature TM_L but does not exceed the third critical temperature TM_H, the controller 104 performs a first-order frequency reduction based on the first clock Clk1 generated by the first clock generator 106, and operates the flash memory 102 with a frequency reduction of N1 percentage, where N1 is a number less than 100. For example, a third clock Clk3 is generated at a frequency of (100 - N1)% of the first clock Clk1 to operate the access of the flash memory 102. In particular, the third clock Clk3 can be designed to be higher than the second clock Clk2. When the sensed temperature Ts exceeds the third critical temperature TM_H but does not exceed the first critical temperature TMTU, the controller 104 performs a second-order frequency reduction based on the first clock Clk1 generated by the first clock generator 106, and operates the flash memory 102 with a frequency reduction of N2 percentage, where N2 is a number less than 100 but greater than N1. For example, a fourth clock Clk4 is generated at a frequency of (100 - N2)% of the first clock Clk1 to operate the access of the flash memory 102; the fourth clock Clk4 is lower than the third clock Clk3. In one embodiment, N1 is 30 and N2 is 70; the third clock Clk3 used for the first-order frequency reduction is at 70% of the frequency of the first clock Clk1, and the fourth clock Clk4 used for the second-order frequency reduction is at 30% of the frequency of the first clock Clk1.

[0046] Figure 3 FIG. 2 shows that when the temperature gradually rises, the controller 104 first performs a first-order frequency reduction based on the first clock Clk1 generated by the first clock generator 106, and then performs a second-order frequency reduction. When the temperature reaches the first critical temperature TMTU, the adaptive cooling strategy is initiated, and the controller 104 enables and disables the first clock generator 106 in a dynamic ratio, switching between the normal transmission state St and the cooling state Sc. This embodiment achieves effective cooling while taking into account performance.

[0047] Figure 4According to one embodiment of the present invention, the temperature control of the data storage device 100 is illustrated. Step S402 senses the temperature Ts. Step S404 determines the temperature value. When the sensed temperature Ts exceeds the first critical temperature TMTU, the process proceeds to step S406 to implement the adaptive cooling strategy of the present invention; the controller 104 repeatedly enables and disables the first clock generator 106 in a dynamic ratio, switching between the normal transmission state St and the cooling state Sc. When the sensed temperature Ts does not exceed the first critical temperature TMTU, the process proceeds to step S408, and is further compared with the second critical temperature TM_L and the third critical temperature TM_H. If the sensed temperature Ts does not exceed the second critical temperature TM_L, the process proceeds to step S410, and the controller 104 operates the flash memory 102 at high speed based on the first clock Clk1 generated by the first clock generator 106. If the sensed temperature Ts exceeds the second critical temperature TM_L but does not exceed the third critical temperature TM_H, the process proceeds to step S412, the controller 104 performs a first-order frequency reduction based on the first clock Clk1 generated by the first clock generator 106, and operates the flash memory 102 at 70% of the frequency of the first clock Clk1 (third clock Clk3) to respond to the access request of the host end 112. If the sensed temperature Ts exceeds the third critical temperature TM_H but does not exceed the first critical temperature TMTU, the process proceeds to step S414, the controller 104 performs a second-order frequency reduction based on the first clock Clk1 generated by the first clock generator 106, and operates the flash memory 102 at 30% of the frequency of the first clock Clk1 (fourth clock Clk4) to respond to the access request of the host end 112.

[0048] The above concept can be further used to implement a non-volatile memory control method, including: providing a first clock generator 106 and a second clock generator 108, respectively generating a first clock Clk1 and a second clock Clk2 for selection to operate a flash memory 102, wherein the frequency of the second clock Clk2 is lower than the first clock Clk1, wherein when a sensed temperature Ts does not exceed a first critical temperature TMTU, the first clock Clk1 is selected to operate the flash memory 102, and when the sensed temperature Ts exceeds the first critical temperature TMTU, the first clock Clk1 and the second clock Clk2 are alternately selected to operate the flash memory 102. Any architecture involving this adaptive cooling strategy falls within the scope of protection of the present invention.

[0049] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this technology can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A data storage device, comprising: a non-volatile memory; a controller coupled to the non-volatile memory and configured to operate the non-volatile memory in response to a host request; as well as A first clock generator and a second clock generator, generating a first clock and a second clock respectively, for the controller to select to operate the non-volatile memory, wherein the frequency of the second clock is lower than that of the first clock; When a sensed temperature does not exceed a first critical temperature, the controller selects the first clock to operate the non-volatile memory. When the sensed temperature exceeds the first critical temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.

2. The data storage device according to claim 1, wherein: The first clock generator is a phase-locked loop, and the second clock generator is an oscillator.

3. The data storage device according to claim 1, wherein: When the sensed temperature exceeds the first critical temperature, the controller adjusts a selected time ratio of the first clock and the second clock according to the magnitude by which the sensed temperature exceeds the first critical temperature.

4. The data storage device according to claim 3, wherein: When the sensed temperature exceeds the first critical temperature by a temperature difference less than DT degrees, the controller selects the first clock and the second clock respectively at the selection time ratio of 1:CD1; When the temperature difference reaches DT degrees, the controller selects the first clock and the second clock respectively at the selection time ratio of 1:CD2; wherein, DT, CD1 and CD2 are numerical values, and CD1 <CD2。 5. The data storage device according to claim 1, wherein: When the sensed temperature exceeds a second critical temperature but does not exceed a third critical temperature which is lower than the first critical temperature, the controller selects a third clock to operate the non-volatile memory.

6. The data storage device according to claim 5, wherein: The third clock is generated by down-converting the first clock.

7. The data storage device according to claim 6, wherein: The third clock is higher than the second clock.

8. The data storage device according to claim 2, wherein: Also includes: a multiplexer, an input end of which is coupled to the first clock generated by the phase-locked loop circuit and the second clock generated by the oscillator, The multiplexer is controlled by the controller to output one of the first clock and the second clock for the controller to operate the non-volatile memory.

9. A non-volatile memory control method, comprising: Generate a first clock and a second clock for selectively operating a non-volatile memory, wherein the frequency of the second clock is lower than that of the first clock; Sensing - sensing temperature; When the sensed temperature does not exceed a first critical temperature, the first clock is selected to operate the non-volatile memory; and When the sensed temperature exceeds the first critical temperature, the first clock and the second clock are alternately selected to operate the non-volatile memory.

10. The non-volatile memory control method according to claim 9, wherein Also includes: operating a phase-locked loop to generate the first clock; and An oscillator is operated to generate the second clock.

11. The non-volatile memory control method according to claim 9, wherein Also includes: When the sensed temperature exceeds the first critical temperature, a selected time ratio of one of the first clock and the second clock is adjusted according to the extent to which the sensed temperature exceeds the first critical temperature.

12. The non-volatile memory control method according to claim 11, wherein Also includes: When the sensed temperature exceeds the first critical temperature by a temperature difference less than DT degrees, the first clock and the second clock are respectively selected at the selection time ratio of 1:CD1; and When the temperature difference reaches DT degrees, the first clock and the second clock are respectively selected at the selection time ratio of 1:CD2; Among them, DT, CD1 and CD2 are numerical values, and CD1 <CD2。 13. The non-volatile memory control method according to claim 9, wherein Also includes: When the sensed temperature exceeds a second critical temperature but does not exceed a third critical temperature which is lower than the first critical temperature, a third clock is selected to operate the non-volatile memory.

14. The non-volatile memory control method according to claim 13, wherein: The third clock is generated by down-converting the first clock.

15. The non-volatile memory control method according to claim 14, wherein: The third clock is higher than the second clock.

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