Multi-level ECC (Error Correction Code) method in storage equipment
By adopting a multi-level ECC method in a solid-state hard disk, the storage device is divided into single ECC and multi-ECC codeword areas, and using short and long ECC codewords, the problem of read amplification and high power consumption of SSD when accessing small data blocks is solved. Achieve performance improvement and hardware efficiency optimization.
Patent Information
- Application Number
- CN202410989201.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2024-12-20
AI Technical Summary
Existing solid-state drives (SSDs) have read-amplification problems and high power consumption of ECC codec engines when handling small data blocks, resulting in reduced performance and increased power consumption.
Using the multi-level ECC method, the memory device is divided into a single ECC codeword area and a multi-ECC codeword area. According to the mapping unit particle size of the data block, the code of the short ECC codeword and the long ECC codeword are used. The rate is lower than the long ECC codeword. The length of the long ECC codeword is the same as the ECC codeword in the single ECC codeword area. Multiple short ECC codewords form a long ECC codeword to reduce the power consumption of read, amplification and encoding and codec engines.
It reduces the read amplification problem during access to small data blocks and the power consumption generated by ECC encoding and codec, reduces hardware overhead, ensures ECC error correction capabilities, and improves the performance and efficiency of storage devices.
Smart Images
Figure CN119166039A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of storage technology, in particular to a multi-level ECC method in a storage device. Background Art
[0002] With the advancement of storage technology, solid-state drives (SSDs) have gradually become the main medium for data storage for individuals, enterprises, and data centers. Compared with traditional mechanical disks (HDDs), they have greatly alleviated the pressure on the storage end and released the performance potential of the overall system. In recent years, transparent compression solutions have also begun to be used in solid-state drives. By integrating data compression functions in hard drives, the data occupancy of physical storage space is further reduced.
[0003] The main storage medium of SSD is NAND. Normally, the data blocks written to NAND generally correspond to one or more logical block addresses (LBA), and each logical block address corresponds to a fixed size, such as 512B or 4KB. The size of LBA is specified by the host when the SSD is formatted. Since NAND cannot be updated in situ, the mapping between its LBA and physical block address (PBA) is not fixed after the data is written to NAND, so a flash translation layer (FTL) is required in the SSD to record and maintain the mapping relationship between LBA and PBA.
[0004] In the current SSD design, the mapping of LBA and PBA generally adopts a fixed-size mapping unit, such as 4KB. In order to maximize the performance of the SSD, the mapping table is generally stored in the DDR inside the SSD. When the size of the LBA is smaller than the size of the mapping unit and the write request from the host is unaligned (that is, the initial LBA or the ending LBA of the write request is not aligned with the mapping unit), a read-modify-write (RMW) operation needs to be performed inside the SSD to solve the mismatch between the LBA and the mapping unit. For example, when the LBA size is 512B and the mapping unit size is 4KB, if the host performs a 512B write operation, the SSD needs to first find the 4KB PBA corresponding to the LBA where the 512B data is located in the mapping table, then read the 4KB data from the PBA, and use the 512B data written by the host to replace the 512B data in the original corresponding position, and finally write the entire 4KB data to NAND and update the mapping table. In addition, SSDs generally use fixed-length ECC (error correction coding) codewords to protect data, such as using LDPC codewords of (4KB original data + 0.5KB check data) to protect 4KB of user data. At this time, if you want to read 512B of data, you need to read the entire 4.5KB LDPC codeword from NAND, and return the required 512B data after decoding. This will cause read amplification problems, and the LDPC decoding engine will also bring more power consumption; when writing 512B data, the SSD also needs to read the corresponding 4KB user data from NAND, replace the old 512B data with the new 512B data after LDPC decoding, and then re-write it to NAND after LDPC encoding. This will also cause write amplification problems and power consumption problems of the LDPC encoding and decoding engine.
[0005] In some actual scenarios, most of the read and write accesses of applications to SSDs are small data blocks, such as 200B or 400B, which often involve a large number of read, modify and write operations, thereby reducing the performance of the SSD and applications. One method to solve the problem of small data block access performance is to use mapping units of different granularities in different partitions of the hard disk, so that the granularity of the mapping unit is as close as possible to the granularity of the host accessing data. However, since the ECC encoding engine still has a large granularity, there are still problems with read amplification and power consumption of the ECC encoding and decoding engine. Summary of the invention
[0006] In order to overcome the deficiencies of the prior art, the present invention provides a multi-level ECC method in a storage device, which uses shorter code words to reduce the read amplification problem and the power consumption of the ECC encoding and decoding engine.
[0007] To achieve the above objectives, a multi-level ECC method in a storage device is designed to divide the storage device into a single ECC codeword area and a multi-ECC codeword area, and divide the multi-ECC codeword area into short ECC codewords and long ECC codewords.
[0008] The division condition for dividing the single ECC codeword area and the multiple ECC codeword area is the mapping unit granularity of the data block LBA address; when the mapping unit granularity of the data block LBA address is large, it is divided into a single ECC codeword area, and when the mapping unit granularity of the data block LBA address is small, it is divided into multiple ECC codeword areas.
[0009] The data blocks in the single ECC codeword area have ECC codewords of a single length and the ECC codewords are relatively long; the data blocks in the multi-ECC codeword area have ECC codewords of different lengths.
[0010] In the multi-ECC codeword area, the length of user data in the short ECC codeword adopts the minimum address mapping unit in the storage device.
[0011] In the multi-ECC codeword area, multiple complete short ECC codewords constitute the user data part of the long ECC codeword.
[0012] In the multi-ECC codeword area, the code rate of the short ECC codeword is lower than the code rate of the long ECC codeword, and the length of the long ECC codeword is the same as the length of the ECC codeword in the single ECC codeword area.
[0013] When the host writes data, the following steps are included: S1, obtain the size of the data block, determine whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, encode the data block into a long ECC codeword and write it into a storage medium; if it is divided into a multi-codeword ECC area, proceed to step S2, S2, determining the long ECC codeword corresponding to the LBA of the data block in the write request and the PBA corresponding to the long ECC codeword, reading the long ECC codeword and decoding it; S3, encode the data in the write request LBA with a short ECC codeword, and replace the corresponding short ECC codeword in the long ECC codeword after encoding; S4, re-encode the long ECC codeword, and write the encoded long ECC codeword into a storage medium; S5, updating the address mapping table according to the physical location where the data is written.
[0014] When the host reads data, the following steps are included: S1, obtaining the size of the data block, determining whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, decoding the long ECC codeword of the data block; if it is divided into a multi-codeword ECC area, proceeding to step S2; S2, determining the short ECC codeword contained in the LBA of the data block in the read request and its corresponding PBA; S3, read the corresponding short ECC codeword and decode it. If the decoding is correct, the corresponding user data is returned; if the decoding fails, proceed to step S4, S4, reading the long ECC codeword including the short ECC codeword that failed to be decoded, and decoding the long ECC codeword; S5, returning user data corresponding to the short ECC codeword that failed to be decoded from the decoded long ECC codeword.
[0015] When the host reads data, if the decoding engine of the short ECC codeword is fully saturated, that is, the data reading speed has reached the upper limit of the decoding engine of the short ECC codeword, it can be assisted by the decoding engine of the long ECC codeword to further improve the decoding throughput.
[0016] When the host reads data in a multi-ECC codeword area, if the proportion of data read once in a long ECC codeword is high, the long ECC codeword can be directly read for decoding.
[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. When accessing small data blocks, the data read amplification problem and the power consumption generated by ECC encoding and decoding are reduced.
[0018] 2. Use the long and short two-level ECC method to reduce the hardware overhead caused by longer ECC codeword lengths.
[0019] 3. By using the same long ECC codeword in the multi-ECC codeword area as in the single-ECC codeword area, it is ensured that the final error correction capability of ECC is not affected by the short ECC codeword. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of a single ECC codeword area and a multi-ECC codeword area in Embodiment 1 of the present invention.
[0021] Figure 2 It is a schematic diagram of a long ECC codeword in a single ECC codeword area in the first embodiment of the present invention.
[0022] Figure 3 It is a schematic diagram of a multi-ECC codeword area in the first embodiment of the present invention, in which a long ECC codeword includes multiple short ECC codewords.
[0023] Figure 4 The figure is a flow chart of a process of writing data into a multi-ECC codeword area in the first embodiment of the present invention.
[0024] Figure 5 The flowchart of the multi-ECC codeword area data reading process in the first embodiment of the present invention. DETAILED DESCRIPTION
[0025] The present invention will be further described below with reference to the accompanying drawings.
[0026] like Figure 1 As shown, this embodiment divides the interior of the storage device into a single ECC codeword area and a multi-ECC codeword area.
[0027] The division condition for dividing the single ECC codeword area and the multiple ECC codeword area is the mapping unit granularity of the data block LBA address; when the mapping unit granularity of the data block LBA address is large, it is divided into a single ECC codeword area, and when the mapping unit granularity of the data block LBA address is small, it is divided into multiple ECC codeword areas.
[0028] In this embodiment, when the mapping unit granularity of the data block LBA address is ≥4KB, it is divided into a single ECC codeword area, and when the mapping unit granularity of the data block LBA address is <4KB, it is divided into multiple ECC codeword areas.
[0029] See also Figure 1 In this embodiment, partition 0 to partition 2 correspond to address mapping units of 512B, 1KB and 2KB respectively, and adopt a multi-ECC codeword data storage method to reduce the read-write amplification problem and the power consumption of the ECC encoding and decoding engine; partition 3 corresponds to an address mapping unit of 4KB, and adopts a single ECC codeword data storage method.
[0030] For a multi-ECC codeword area, the multi-ECC codeword area is divided into short ECC codewords and long ECC codewords according to the size of the data block accessed by the host side.
[0031] In the multi-ECC codeword area, multiple complete short ECC codewords constitute the user data part of the long ECC codeword.
[0032] The data block in the single ECC codeword area has an ECC codeword of a single length and the ECC codeword is relatively long. Figure 1 The single ECC codeword area of the middle partition 3 has an address mapping unit of 4KB, so a long ECC codeword of 4KB user data + check data can be used, such as Figure 2 shown.
[0033] Data blocks in a multi-ECC codeword area correspond to areas with smaller address mapping unit granularity and have different ECC codeword lengths. In a multi-ECC codeword area, the length of user data in a short ECC codeword adopts the smallest address mapping unit in the storage device. Figure 1 For partition 0 to partition 2 in the , the address mapping units are 512B, 1KB and 2KB respectively, so a short ECC codeword of 512B user data + check data can be used. If there is a 256B address mapping unit, the user data length in the short ECC codeword can be 256B. Here, for the 1KB and 2KB mapping units, the short ECC codeword of 512B user data + check data is still used, because in this way, 1KB or 2KB can be stored using multiple short ECC codewords, thereby avoiding the use of more ECC codec engines with different code lengths, and thus avoiding the hardware implementation overhead of multiple ECC codec engines.
[0034] The multi-ECC codeword area includes short ECC codewords and long ECC codewords. The code rate of the short ECC codeword is lower than the code rate of the long ECC codeword. The long ECC codeword is used to encode and protect multiple short ECC codewords. The length of the long ECC codeword is the same as the length of the ECC codeword in the single ECC codeword area. Figure 3 As shown, a long ECC codeword is still 4KB of user data + check data in length, and contains multiple short ECC codewords of 512B of user data + check data, and the total length of multiple short ECC codewords does not exceed the length of 4KB of user data in the long ECC codeword. Since the error correction capability of ECC is related to the code length, that is, the longer the code length is at the same code rate, the stronger the error correction capability is, because short ECC codewords need to use a smaller code rate, that is, the ratio of the check data length to the user data length in the short ECC codeword is larger than that of the long ECC codeword, so as to ensure a higher success rate of decoding short ECC codewords.
[0035] At the same code rate, the longer the code length, the better the data protection effect. In the multi-ECC codeword area, the proportion of check data in the short ECC codeword is larger, that is, the code rate of the short ECC codeword is lower, because we hope that the success rate of decoding the short ECC codeword is also high, that is, the long ECC codeword does not need to participate in the decoding, so as to effectively reduce the read amplification problem. The number of short ECC codewords contained in a long ECC codeword is fixed. For example, a long ECC codeword containing 4KB user data + 400B check data may be composed of 6 short ECC codewords containing 512B valid data + 170B check data. At this time, the composition of a long ECC codeword is: (512B valid data + 170B check data) * 6 (and aligned to 4096B) + 400B check data. In this case, one long ECC codeword corresponds to 6 short ECC codewords with fixed LBA, and the 4KB user data in the long ECC codeword is actually 6 complete short ECC codewords, and the 400B check data in the long ECC codeword is an additional protection for the 6 short ECC codewords. When the decoding of the short ECC codeword fails, its corresponding long ECC codeword can be read for decoding; when the long ECC codeword is successfully decoded, the corresponding 6 short ECC codewords are all available, and only the user data in the required short ECC codeword needs to be intercepted.
[0036] The ECC codewords in the single ECC codeword area are also long ECC codewords. The long ECC codewords in the multi-ECC codewords and the ECC codewords in the single ECC codewords have the same code length, so that the long ECC encoding and decoding engines in the two areas can be reused, reducing the complexity of hardware design, and at the same time will not increase the probability of overall data decoding failure.
[0037] When the host writes data, the following steps are included: S1, obtain the size of the data block, determine whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, encode the data block into a long ECC codeword and write it into a storage medium; if it is divided into a multi-codeword ECC area, proceed to step S2, S2, determining the long ECC codeword corresponding to the LBA of the data block in the write request and the PBA corresponding to the long ECC codeword, reading the long ECC codeword and decoding it; S3, encode the data in the write request LBA with a short ECC codeword, and replace the corresponding short ECC codeword in the long ECC codeword after encoding; S4, re-encode the long ECC codeword, and write the encoded long ECC codeword into a storage medium; S5, updating the address mapping table according to the physical location where the data is written.
[0038] When the host reads data, the following steps are included: S1, obtaining the size of the data block, determining whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, decoding the long ECC codeword of the data block; if it is divided into a multi-codeword ECC area, proceeding to step S2; S2, determining the short ECC codeword contained in the LBA of the data block in the read request and its corresponding PBA; S3, read the corresponding short ECC codeword and decode it. If the decoding is correct, the corresponding user data is returned; if the decoding fails, proceed to step S4, S4, reading the long ECC codeword including the short ECC codeword that failed to be decoded, and decoding the long ECC codeword; S5, returning user data corresponding to the short ECC codeword that failed to be decoded from the decoded long ECC codeword.
[0039] When the host reads data, if the decoding engine of the short ECC codeword is fully saturated, that is, the data reading speed has reached the upper limit of the decoding engine of the short ECC codeword, it can be assisted by the decoding engine of the long ECC codeword to further improve the decoding throughput.
[0040] When the host reads data in a multi-ECC codeword area, if the proportion of data read in a long ECC codeword is high, the long ECC codeword can be directly read for decoding. For example, when a long ECC codeword contains 6 short ECC codewords, and a read operation needs to read 5 or more of the short ECC codewords, the long ECC codeword can be directly read for decoding.
[0041] In the present invention, when accessing small data blocks, the problem of data read amplification and the power consumption generated by ECC encoding and decoding are reduced. The use of a long and short two-level ECC method reduces the hardware overhead caused by more ECC codeword lengths. By using the same long ECC codeword as the single ECC codeword area in the multi-ECC codeword area, it is ensured that the final error correction capability of ECC is not affected by the short ECC codeword.
Claims
1. A multi-level ECC method in a storage device, characterized in that: The storage device is internally divided into a single ECC codeword area and a multi-ECC codeword area, wherein the multi-ECC codeword area is divided into short ECC codewords and long ECC codewords.
2. The multi-level ECC method in a storage device according to claim 1, characterized in that: The division condition for dividing the single ECC codeword area and the multiple ECC codeword area is the mapping unit granularity of the data block LBA address; when the mapping unit granularity of the data block LBA address is large, it is divided into a single ECC codeword area, and when the mapping unit granularity of the data block LBA address is small, it is divided into multiple ECC codeword areas.
3. The multi-level ECC method in a storage device according to claim 1, characterized in that: The data blocks in the single ECC codeword area have ECC codewords of a single length and the ECC codewords are relatively long, and the data blocks in the multiple ECC codeword areas have ECC codewords of different lengths.
4. The multi-level ECC method in a storage device according to claim 1, characterized in that: In the multi-ECC codeword area, the length of user data in the short ECC codeword adopts the minimum address mapping unit in the storage device.
5. The multi-level ECC method in a storage device according to claim 1, characterized in that: In the multi-ECC codeword area, multiple complete short ECC codewords constitute the user data part of the long ECC codeword.
6. The multi-level ECC method in a storage device according to claim 1, characterized in that: In the multi-ECC codeword area, the code rate of the short ECC codeword is lower than the code rate of the long ECC codeword, and the length of the long ECC codeword is the same as the length of the ECC codeword in the single ECC codeword area.
7. The multi-level ECC method in a storage device according to claim 1, characterized in that: When the host writes data, the following steps are included: S1, obtain the size of the data block, determine whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, encode the data block into a long ECC codeword and write it into a storage medium; if it is divided into a multi-codeword ECC area, proceed to step S2, S2, determining the long ECC codeword corresponding to the LBA of the data block in the write request and the PBA corresponding to the long ECC codeword, reading the long ECC codeword and decoding it; S3, encode the data in the write request LBA with a short ECC codeword, and replace the corresponding short ECC codeword in the long ECC codeword after encoding; S4, re-encode the long ECC codeword, and write the encoded long ECC codeword into a storage medium; S5, updating the address mapping table according to the physical location where the data is written.
8. The multi-level ECC method in a storage device according to claim 1, characterized in that: When the host reads data, the following steps are included: S1, obtaining the size of the data block, determining whether the data block is divided into a single ECC codeword area or a multi-ECC codeword area, if it is divided into a single ECC codeword area, decoding the long ECC codeword of the data block; if it is divided into a multi-codeword ECC area, proceeding to step S2; S2, determining the short ECC codeword contained in the LBA of the data block in the read request and its corresponding PBA; S3, read the corresponding short ECC codeword and decode it. If the decoding is correct, the corresponding user data is returned; if the decoding fails, proceed to step S4, S4, reading the long ECC codeword including the short ECC codeword that failed to be decoded, and decoding the long ECC codeword; S5, returning user data corresponding to the short ECC codeword that failed to be decoded from the decoded long ECC codeword.
9. The multi-level ECC method in a storage device according to claim 1, characterized in that: When the host reads data, if the decoding engine of the short ECC codeword is fully saturated, that is, the data reading speed has reached the upper limit of the decoding engine of the short ECC codeword, it can be assisted by the decoding engine of the long ECC codeword to further improve the decoding throughput.
10. The multi-level ECC method in a storage device according to claim 1, characterized in that: When the host reads data in a multi-ECC codeword area, if the proportion of data read once in a long ECC codeword is high, the long ECC codeword can be directly read for decoding.